bq2013H

Gas Gauge IC for Power-

Assist Applications
Features General Description Nominal available charge may be
➤ Accurate measurement of available The bq2013H Gas Gauge IC is in- directly indicated using a five-seg-
charge in rechargeable batteries tended for battery-pack installation to ment LED display. These segments
➤ Designed for electric assist bicycles maintain an accurate record of a bat- are used to graphically indicate
and other applications tery’s available charge. The IC moni- nominal available charge.
tors a voltage drop across a sense resis-
➤ Measures a wide dynamic current tor connected in series between the The bq2013H supports a simple
range negative battery terminal and ground single-line bi-directional serial link to
to determine charge and discharge ac- an external processor (common
➤ Supports NiCd, NiMH or lead acid ground). The bq2013H outputs bat-
tivity of the battery. The bq2013H is
➤ Designed for battery pack inte- designed for high cpaacity battery tery information in response to exter-
gration packs used in high-discharge rate sys- nal commands over the serial link. To
support battery pack testing, the
- 120µA typical standby current tems.
outputs may also be controlled by
(self-discharge estimation mode)
Battery self-discharge is estimated command. The external processor
- Small size enables imple- based on an internal timer and tem- may also overwrite some of the
mentations in as little as 1 2 perature sensor. Compensations for bq2013H gas gauge data registers.
square inch of PCB
battery temperature, rate of charge,
➤ Direct drive of LEDs for capacity and self-discharge are applied to the The bq2013H may operate directly
display charge counter to provide available from four nickel cells or three lead
capacity information across a wide acid. With the REF output and an
➤ A u t o m a ti c char g e and s e l f - external transistor, a simple, inexpen-
discharge compensation using in- range of operating conditions. Initial
battery capacity, self-discharge rate, sive regulator can be built to provide
ternal temperature sensor VCC from a greater number of cells.
display mode, and charge compensa-
➤ Simple single-wire serial commu- tion are set using the PROG1-6 pins.
nications port for subassembly Internal registers include available
Actual battery capacity is automati- charge, temperature, capacity, battery
testing cally “learned” in the course of a dis- ID, and battery status.
➤ 16-pin narrow SOIC charge cycle from full to empty.

Pin Connections Pin Names

LCOM LED common output REF Voltage reference output

LCOM 1 16 VCC
SEG1/PROG1 LED segment 1/ Program DONE Fast charge complete
SEG1/PROG1 2 15 REF
1 input input
SEG2/PROG2 3 14 DONE
SEG2/PROG2 LED segment 2 / Program HDQ Serial communications
SEG3/PROG3 4 13 HDQ 2 input input/output
SEG4/PROG4 5 12 RBI
SEG3/PROG3 LED segment 3/ Program RBI Register backup input
SEG5PROG5 6 11 SB 3 input
SB Battery sense input
PROG6 7 10 DISP SEG4/PROG4 LED segment 4/ Program
VSS 8 9 SR
4 input DISP Display control input

SEG5/PROG5 LED segment 5/ Program SR Sense resistor input

16-Pin Narrow SOIC 5 input
PN2013.eps VCC Supply voltage
PROG6 Program 6 input

SLUS120B–MAY 1999 - REVISED - JANUARY 2014

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bq2013H

Pin Descriptions DISP Display control input

LCOM LED common DISP pulled high disables the display.

DISP floating allows the LED display to
This open-drain output switches VCC to source be active during certain charge and dis-
current for the LEDs. The switch is off during charge conditions. Transitioning DISP
initialization to allow reading of PROG1-5 low activates the display.
pull-up or pull-down program resistors. LCOM
is also high impedance when the display is off. SB Secondary battery input

SEG1– LED display segment outputs (dual func- This input monitors the scaled battery volt-
SEG5 tion with PROG1–PROG5 age through a high-impedance resistive di-
vider network for the end-of-discharge volt-
Each output may activate an LED to sink age (EDV) thresholds.
the current sourced from LCOM.
RBI Register backup input
PROG1– Programmed full count selection inputs
PROG6 (dual function with SEG1 - SEG5) This input is used to provide backup poten-
tial to the bq2013H registers during periods
These three-level input pins define the pro- when VCC < 3V. A storage capacitor can be
grammed full-count (PFC), display mode, connected to RBI.
self-discharge rate, offset compensation,
overload threshold, and charge compensa- HDQ Serial I/O pin
tion.
This is an open-drain bidirectional commu-
SR Sense resistor input nications port.

The voltage drop (VSR) across the sense re- REF Voltage reference output for regulator
sistor RS is monitored and integrated over
time to interpret charge and discharge activ- REF provides a voltage reference output for
ity. The SR input (see Figure 1) is connected an optional micro-regulator.
between the negative terminal of the battery VCC Supply voltage input
and ground. VSR > VSS indicates charge, and
VSR < VSS indicates discharge. The effective VSS Ground
voltage drop, VSRO, as seen by the bq2013H
is VSR + VOS.

DONE Charge complete input

This input/output is used to communicate

the status of an external charge controller to
the bq2013H.

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 bq2013H

Figure 1 shows a typical battery pack application of the

Functional Description bq2013H using the LED display. The bq2013H can be
configured to display capacity in either a relative or an
General Operation absolute display mode. The relative display mode uses
the last measured discharge capacity of the battery as
The bq2013H determines battery capacity by monitoring the battery “full” reference. The absolute display mode
the amount of charge input to or removed from a recharge- uses the programmed full count (PFC) as the full refer-
able battery. The bq2013H measures discharge and charge ence, forcing each segment of the display to represent a
currents, estimates self-discharge, monitors the battery for fixed amount of charge. A push-button display feature
low-battery voltage thresholds, and compensates for tem- is available for enabling the LED display.
perature and charge rates. The charge measurement is
made by monitoring the voltage across a small-value se- The bq2013H monitors the charge and discharge cur-
ries sense resistor between the battery’s negative terminal rents as a voltage across a sense resistor (see RS in Fig-
and ground. The available battery charge is determined ure 1). A filter between the negative battery terminal
by monitoring this voltage over time and correcting the and the SR pin is required.
measurement for the environmental and operating condi-
tions.

R1

bq2013H Q1
Gas Gauge IC ZVNL110A
REF
C1
VCC RB1
LCOM

SEG1/PROG1 SB
SEG2/PROG2 RB2
SEG3/PROG3 DISP

SEG4/PROG4
100K
SR
SEG5/PROG5 0.1µF RS
VSS
H, Z, or L PROG6
To µC HDQ RBI
DONE
To µC or
Fast Charger

Notes: Charger
1. Indicates optional.
Load
2. The battery stack voltage can be directly connect to VCC across 4 nickel cells
(4.8V nominal and should not exceed 6.5V) with a resistor and a zener diode
to limit voltage during charge. Otherwise, R1and Q1 are needed for
regulation of > 4 nickel cells.

3. Programming resistors and ESD-protection diodes are not shown.

FG2013H1.eps
4. R-C on SR is required.

Figure 1. Application Diagram: LED Display

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bq2013H

Register Backup Temperature

The bq2013H RBI input pin is intended to be used with The bq2013H internally determines the temperature in
a storage capacitor to provide backup potential to the in- 10°C steps centered from -35°C to +85°C. The tempera-
ternal bq2013H registers when VCC momentarily drops be- ture steps are used to adapt charge rate compensations
low 3.0V. VCC is output on RBI when VCC is above 3.0V. and self-discharge counting. The temperature range is
available over the serial port in 10°C increments as
After VCC rises above 3.0V, the bq2013H checks the internal shown in the following table:
registers for data loss or corruption. If data has changed,
then the NAC register is cleared, and the LMD register is
loaded with the initial PFC. TMPGG (hex) Temperature Range
0x < -30°C
Voltage Thresholds 1x -30°C to -20°C
In conjunction with monitoring VSR for charge/discharge 2x -20°C to -10°C
currents, the bq2013H monitors the battery potential
through the SB pin for the end-of-discharge voltage (EDV) 3x -10°C to 0°C
thresholds. 4x 0°C to 10°C
The EDV threshold levels are used to determine when 5x 10°C to 20°C
the battery has reached an “empty” state. 6x 20°C to 30°C
The EDV thresholds for the bq2013H are set as follows: 7x 30°C to 40°C
EDV1 (first) = 1.00V 8x 40°C to 50°C

EDVF (final) = EDV1 - 100mV 9x 50°C to 60°C

Ax 60°C to 70°C
The battery voltage divider (RB1 and RB2 in Figure 1) is
used to scale these values to the desired threshold. Bx 70°C to 80°C

If VSB is below either of the two EDV thresholds for the Cx > 80°C
specified delay times in Table 1, the associated flag is
latched and remains latched, independent of VSB, until Layout Considerations
the next valid charge. EDV monitoring is disabled if the
OVLD bit in FLGS2 is set. The bq2013H measures the voltage differential between
the SR and VSS pins. VOS (the offset voltage at the SR
pin) is greatly affected by PC board layout. For optimal
results, the PC board layout should follow the strict rule of
Table 1. Delay Time in Seconds a single-point ground return. Sharing high-current
ground with small signal ground causes undesirable noise
Temperature on the small signal nodes. Additionally:
Capacity
< 10°C 10°C to 30°C > 30°C ■ The capacitors should be placed as close as possible
> 40% 7 6 5 to the SB and VCC pins and their paths to VSS should
be as short as possible. A high-quality ceramic
20% to 40% 4 3 2 capacitor of 0.1µf is recommended for VCC.
< 20% 2 2 2
■ The sense resistor (RS) should be as close as possible
to the bq2013H.
Reset
■ The R-C on the SR pin should be located as close as
The bq2013H can be reset by removing VCC and ground- possible to the SR pin. The maximum R should not
ing the RBI pin for 15 seconds or with a command over exceed 100K.
the serial port. The serial port reset command sequence
requires writing 00h to register PPFC (address = leh)
and the writing 00h to register LMD (address = 05h.)
Gas Gauge Operation
The operational overview diagram in Figure 2 illus-
trates the operation of the bq2013H. The bq2013H ac-
cumulates a measure of charge and discharge currents,
as well as an estimation of self-discharge. The bq2013H
compensates charge current for charge rate and tem-

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 bq2013H

perature. Discharge current is load compensated based 1. Last Measured Discharge (LMD) or learned
on the value stored in location LCOMP (address = 0eh). battery capacity:
LCOMP allows the bq2013H to automatically adjust for
continuous small discharge currents. The bq2013H com- LMD is the last measured discharge capacity of the
pensates self discharge for the load value as well as tem- battery. On initialization (application of VCC or bat-
perature. tery replacement), LMD = PFC. During subsequent
discharges, the LMD is updated with the latest
The main counter, Nominal Available Capacity (NAC), measured capacity in the Discharge Count Register
represents the available battery capacity at any given (DCR) representing a discharge from full to below
time. Battery charging increments the NAC register, EDV. The maximum decrease in LMD because of a
while battery discharging, self-discharge decrement the DCR update is 25% of LMD. A qualified discharge
NAC register and increment the DCR (Discharge Count is necessary for a capacity transfer from the DCR
Register). NAC is also corrected automatically for offset to the LMD register. The LMD also serves as the
error based on the value in the offset location OFFSET 100% reference threshold used by the relative dis-
(address = 0bh.) play mode.
The Discharge Count Register (DCR) is used to update 2. Programmed Full Count (PFC) or initial bat-
the Last Measured Discharge (LMD) register only if a tery capacity:
complete battery discharge from full to empty occurs
without any partial battery charges. Therefore, the The initial LMD and gas gauge rate values are pro-
bq2013H adapts its capacity determination based on the grammed by using PFC. The PFC also provides the
actual conditions of discharge. 100% reference for the absolute display mode. The
bq2013H is configured for a given application by se-
The battery’s initial capacity is equal to the Pro- lecting a PFC value from Table 2. The correct PFC
grammed Full Count (PFC) shown in Table 2. Until may be determined by multiplying the rated bat-
LMD is updated, NAC counts up to but not beyond this tery capacity in mAh by the sense resistor value:
threshold during subsequent charges. This approach al-
lows the gas gauge to be charger-independent and com- Battery capacity (mAh) * sense resistor (Ω) =
patible with any type of charge regime.
PFC (mVh)
Selecting a PFC slightly less than the rated capac-
ity for absolute mode provides capacity above the
full reference for much of the battery’s life.

Inputs Charge Discharge Self-Discharge

Current Current Timer

Rate and Load Load and

Temperature Compensation Temperature
Compensation Compensation

- - + +

+ Nominal Last Discharge

Main Counters
and Capacity
Available
Charge
< Measured
Discharged
Count
Qualified Register
Reference (LMD) (NAC) (LMD) Transfer (DCR)
(offset corrected)

Temperature Temperature Step,

Translation Other Data

Chip-Controlled Serial
Outputs Available Charge Port
LED Display
FG2013H2.eps

Figure 2. Operational Overview

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bq2013H

Example: Selecting a PFC Value Therefore:

Given: 5000mAh * 0.0075Ω = 37.5mVh
Sense resistor = 0.0075Ω Select:
Number of cells = 14
Capacity = 5000mAh, NiCd cells PFC = 44,800 counts or 35mVh
Current range = 1A to 30A PROG1, PROG2 = Z, L
Relative display mode with 4 second timer PROG3 = Z
Self-discharge = 1% per day PROG4 = H
Trickle charge compensation = 0.85 PROG5 = L
Typical offset = -75µV PROG6 = Z
Voltage drop across sense resistor = 5mV to 225 mV

Table 2. bq2013H Programmed Full Count mVh Selections

Programmed
Full Count (PFC) mVh Scale PROG1 PROG2

27136 84.8 1
320 H H

24064 75.2 1
320 H Z

41472 64.8 1
640 H L

35072 54.8 1
640 Z H

28672 44.8 1
640 Z Z

44800 35 1
1280 Z L

30720 24 1
1280 L H

38400 15 1
2560 L Z

12800 5 1
2560 L L

Table 3. Programmed Self-Discharge

PROG3 Self-Discharge

H 1.6% per day

Z 0.8% per day

L 0.2% per day

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 bq2013H

Table 4. Programmed Display Mode

PROG4 Overload Threshold Display Mode

H VOVLD = -75mV Relative/4s timer after push-button release

Z VOVLD = -75mV Relative/4s timer after push-button release

L VOVLD = -25mV Absolute/4s timer after push-button release

Table 5. Programmed Charge Compensation

Trickle Fast
PROG5
<30°C 30°C—50°C >50°C <30°C 30°C—50°C >50°C

H 0.80 0.75 0.70 0.95 0.90 0.85

Z 1.00 1.00 1.00 1.00 1.00 1.00

L 0.85 0.80 0.75 0.95 0.90 0.85

Table 6. Programmed Discharge Offset Adjustment

PROG6 Offset

H -150µV

Z -75µV

L 0µV

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bq2013H

The initial full battery capacity is 35mVh (4667mAh) until Discharge Counting
the bq2013H “learns” a new capacity with a qualified dis-
charge from full to EDV1. All discharge counts where VSRO < -250µV cause the
NAC register to decrement and the DCR to increment. If
3. Nominal Available Capacity (NAC): enabled, the display is activated when VSRO < -2mV.
NAC counts up during charge to a maximum value The display remains active for 10 seconds after VSRO
of LMD and down during discharge and self dis- rises above - 2mV.
charge to 0. NAC is reset to 0 on initialization and
on the first valid charge following discharge to Self-Discharge Estimation
EDV1. To prevent overstatement of charge during The bq2013H decrements NAC and increments DCR for
periods of overcharge, NAC stops incrementing self-discharge based on time and temperature. The self-
when NAC = LMD. When the DONE input is as- discharge count rate is programmed per Table 3. This is
serted high, indicating full charge completion, NAC the rate for a battery temperature between 20–30°C.
is set to LMD. The NAC register cannot be decremented below 0.
4. Discharge Count Register (DCR):
The DCR counts up during discharge independent
Count Compensations
of NAC and could continue increasing after NAC The bq2013H determines fast charge when the NAC up-
has decremented to 0. Prior to NAC = 0 (empty dates at a rate of ≥ 2 counts/s. Charge activity is com-
battery), both discharge and self-discharge incre- pensated for temperature and rate before updating
ment the DCR. After NAC = 0, only discharge in- NAC. Self-discharge estimation is compensated for tem-
crements the DCR. The DCR resets to 0 when NAC perature before updating NAC or DCR.
= LMD. The DCR does not roll over but stops
counting when it reaches FFFFh. Charge Compensation
The DCR value becomes the new LMD value on the Charge efficiency factors are selected using Table 5 for
first charge after a valid discharge to EDV1 if all of trickle charge and fast charge. Fast charge is defined as
the following conditions are met: a rate of charge resulting in ≥ 2 NAC counts/s (0.16C to
0.6C, depending on PFC selections; see Table 2).
■ No valid charge initiations (charges greater than
2 NAC updates) occurred during the period be- Temperature adapts the charge rate compensation
tween NAC = LMD and EDV1. factors over three ranges between nominal, warm, and
hot temperatures. Program pin 5 is used to select one of
■ The self-discharge count is less than 6% of NAC. three compensation programs. These values are shown
■ The temperature is ≥ 0°C when the EDV1 level in Table 5.
is reached during discharge.
■ VDQ is set.

Charge Counting
Charge activity is detected based on a positive voltage
on the VSR input. If charge activity is detected, the
bq2013H increments NAC at a rate proportional to VSRO
(VSR + VOS) and, if enabled, activates an LED display
if VSRO > 500µV. Charge actions increment the NAC af-
ter compensation for charge rate and temperature.
The bq2013H detects charge activity with VSRO > 250µV.
A valid charge equates to a sustained charge activity
greater than 2 NAC updates. Once a valid charge is de-
tected, charge counting continues until VSRO drops be-
low 250µV.

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 bq2013H

Self-Discharge Compensation fast-charge completion, the bq2013H sets NAC = LMD.

The DONE input should be maintained high as long as
The self-discharge compensation can be programmed for the fast-charge controller or microcontroller keeps the
three different rates. The rates vary across 8 ranges batteries full; otherwise, the pin should be held low.
from <10°C to >70°C, doubling with each higher tem-
perature step (10°C). See Table 7.
Communicating With the bq2013
Table 7. Self-Discharge Compensation The bq2013H includes a simple single-pin (HDQ plus re-
turn) serial data interface. A host processor uses the inter-
Self-Discharge Compensation face to access various bq2013H registers. Battery character-
Typical Rate/Day istics may be easily monitored by adding a single contact to
Temperature the battery pack. The open-drain HDQ pin on the bq2013H
Range PROG3 = H PROG3 = Z PROG3 = L should be pulled up by the host system, or may be left float-
< 10°C NAC NAC NAC ing if the serial interface is not used.
256 512 2048

10–20°C NAC
128
NAC
256
NAC
1024
The interface uses a command-based protocol, where the
host processor sends a command byte to the bq2013H.
20–30°C NAC
64
NAC
128
NAC
512 The command directs the bq2013H to either store the
next eight bits of data received to a register specified by
30–40°C NAC
32
NAC
64
NAC
256
the command byte or output the eight bits of data speci-
40–50°C NAC
16
NAC
32
NAC
128
fied by the command byte. (See Figure 3.)
50–60°C NAC
8
NAC
16
NAC
64
The communication protocol is asynchronous re-
turn-to-one. Command and data bytes consist of a
60–70°C NAC
4
NAC
8
NAC
32 stream of eight bits that have a maximum transmission
> 70°C NAC NAC NAC rate of 5K bits/s. The least-significant bit of a command
2 4 16
or data byte is transmitted first. The protocol is simple
enough that it can be implemented by most host proces-
sors using either polled or interrupt processing. Data
Offset Compensation input from the bq2013H may be sampled using the
pulse-width capture timers available on some microcon-
The bq2013H uses a voltage to frequency converter to trollers.
measure the voltage across a resistor used to monitor
the current into and out of the battery. This converter If a communication error occurs, e.g., tCYCB > 250µs, the
has an offset value that can be influenced by the VCC bq2013H should be sent a BREAK to reinitiate the se-
supply and the bypassing of this supply. The typical rial interface. A BREAK is detected when the HDQ pin
value found on a well designed PCB is about -75µV. Pro- is driven to a logic-low state for a time, tB or greater.
gram pin 6 can be used to compensate for this offset, re- The HDQ pin should then be returned to its normal
ducing the effective VOS. Offset compensation occurs ready-high logic state for a time, tBR. The bq2013H is
when VSRO < -250µV or VSRO > 250µV. now ready to receive a command from the host proces-
sor.
Error Summary The return-to-one data bit frame consists of three dis-
tinct sections. The first section is used to start the trans-
The LMD is susceptible to error on initialization or if no
mission by either the host or the bq2013H taking the
updates occur. On initialization, the LMD value includes
HDQ pin to a logic-low state for a period, tSTRH;B. The
the error between the programmed full capacity and the
next section is the actual data transmission, where the
actual capacity. This error is present until a valid dis-
data should be valid by a period, tDSU;B, after the nega-
charge occurs and LMD is updated (see the DCR de-
tive edge used to start communication. The data should
scription in the “Layout Considerations” section). The
be held for a period, tDH;DV, to allow the host or bq2013H
other cause of LMD error is battery wear-out. As the
to sample the data bit.
battery ages, the measured capacity must be adjusted to
account for changes in actual battery capacity. The final section is used to stop the transmission by re-
turning the HDQ pin to a logic-high state by at least a
DONE Input period, tSSU;B, after the negative edge used to start com-
munication. The final logic-high state should be until a
A fast-charge controller IC or micro-controller uses the period tCYCH;B, to allow time to ensure that the bit
DONE input to communicate charge status to the transmission was stopped properly. The timings for data
bq2013H. When the DONE input is asserted high on and break communication are given in the serial com-

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bq2013H

Table 8. bq2013H Current-Sensing Errors

Symbol Parameter Typical Maximum Units Notes

Integrated non-linearity Add 0.1% per °C above or below 25°C
INL ±2 ±4 %
error and 1% per volt above or below 4.25V.
Integrated non- Measurement repeatability given
INR ±1 ±2 %
repeatability error similar operating conditions.

munication timing specification and illustration sec- The W/R location is:
tions.
Communication with the bq2013H is always performed Command Code Bits
with the least-significant bit being transmitted first. Fig- 7 6 5 4 3 2 1 0
ure 3 shows an example of a communication sequence to
read the bq2013H NACH register. W/R - - - - - - -

Where W/R is:

bq2013H Command Code and
0 The bq2013H outputs the requested regis-
Registers ter contents specified by the address por-
tion of command code.
The bq2013H status registers are listed in Table 9 and
described below. 1 The following eight bits should be written
to the register specified by the address por-
Command Code tion of command code.
The bq2013H latches the command code when eight The lower seven-bit field of command code contains the
valid command bits have been received by the bq2013H. address portion of the register to be accessed. Attempts
The command code register contains two fields: to write to invalid addresses are ignored.
■ W/R bit
Command Code Bits
■ Command address
7 6 5 4 3 2 1 0
The W/R bit of the command code is used to select AD0
whether the received command is for a read or a write - AD6 AD5 AD4 AD3 AD2 AD1
(LSB)
function.

Written by Host to bq2013H Received by Host from bq2013H

CMDR = 03h NAC = 65h

LSB MSB LSB MSB

Break 1 1 0 0 0 0 0 0 1 0 1 0 0 11 0

DQ

tRSPS
TD2013H.eps

Figure 3. Typical Communication With the bq2013H

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 bq2013H

Table 9. bq2013H Command and Status Registers

Control Field
Loc. Read/
Symbol Register Name (hex) Write 7(MSB) 6 5 4 3 2 1 0(LSB)
Primary status
FLGS1 flags register 01h R CHGS BRP RSVD RSVD VDQ RSVD EDV1 EDVF

Temperature and
TMPGG 02h R TMP3 TMP2 TMP1 TMP0 GG3 GG2 GG1 GG0
gas gauge register
Nominal available
NACH capacity high byte 03h R/W NACH7 NACH6 NACH5 NACH4 NACH3 NACH2 NACH1 NACH0
register
Nominal available
NACL capacity low byte 17h R/W NACL7 NACL6 NACL5 NACL4 NACL3 NACL2 NACL1 NACL0
register
Battery
BATID identification 04h R/W BATID7 BATID6 BATID5 BATID4 BATID3 BATID2 BATID1 BATID0
register

LMD Last measured 05h R/W LMD7 LMD6 LMD5 LMD4 LMD3 LMD2 LMD1 LMD0
discharge register

FLGS2 Secondary
status
flags register 06h R CR RSVD RSVD RSVD RSVD RSVD RSVD OVLD

Program pull
PPD 07h R RSVD RSVD PPD6 PPD5 PPD4 PPD3 PPD2 PPD1
down register
Program pull up
PPU 08h R RSVD RSVD PPU6 PPU5 PPU4 PPU3 PPU2 PPU1
register
Output control
OCTL 0ah R/W OC6 OC5 OC4 OC3 OC2 OC1 OCE OCC
register

OFFSET Offset
adjustment
regisiter 0bh R/W OFS7 OFS6 OFS5 OFS4 OFS3 OFS2 OFS1 OFS0

SDR Self discharge rate 0ch R/W SDR7 SDR6 SDR5 SDR4 SDR3 SDR2 SDR1 SDR0

DMF Digital magnitude 0dh R/W DMF7 DMF6 DMF5 DMF4 DMF3 DMF2 DMF1 DMF0
filter

LCOMP Load
compensa-
0eh R/W LC7 LC6 LC5 LC4 LC3 LC2 LC1 LC0
tion
Fast charge
CCOMP 0fh R/W CC7 CC6 CC5 CC4 CC3 CC2 CC1 CC0
compensation
PPFC Program pin data leh R/W RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD
Battery voltage
VSB 7eh R VSB7 VSB6 VSB5 VSB4 VSB3 VSB2 VSB1 VSB0
register

Notes: RSVD = reserved.

All other registers not documented are reserved.

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bq2013H

Primary Status Flags Register (FLGS1) The VDQ location is:

The FLGS1 register (address=01h) contains the primary

FLGS1 Bits
bq2013H flags.
7 6 5 4 3 2 1 0
The charge status flag (CHGS) is asserted when a
valid charge rate is detected. The bq2013H deems the - - - - VDQ - - -
charge valid if it results in two NAC updates with VSRO
> 250µV. A VSRO of less than 250µV or discharge activity where VDQ is
clears CHGS. 0 Self-discharge reduces NAC by 6%, valid
The CHGS location is: charge action detected, EDV1 asserted with
the temperature less than 0°C, or reset
FLGS1 Bits 1 On first discharge after NAC = LMD
7 6 5 4 3 2 1 0 The first end-of-discharge warning flag (EDV1)
CHGS - - - - - - - warns the user that the battery is empty. SEG1 blinks
at a 4Hz rate and DONE is asserted low. EDV1 detec-
where CHGS is tion is disabled if OVLD = 1. The EDV flag is latched
until a valid charge has been detected.
0 Either discharge activity detected or
VSRO < 250µV The EDV1 location is:

1 Two NAC updates with VSRO > 250µV FLGS1 Bits

The battery replaced flag (BRP) is asserted whenever 7 6 5 4 3 2 1 0
the bq2013H is reset by application of VCC or by a serial
port command. BRP is reset when either a valid charge - - - - - - EDV1 -
action increments NAC to be equal to LMD, or when a
valid charge action is detected after the EDV1 flag is where EDV1 is
asserted. BRP = 1 signifies that the device has been re- 0 Valid charge action detected or VSB ≥ VEDV1
set.
1 VSB < VEDV1 for the delay time, provided
The BRP location is: that the OVLD bit is not set

FLGS1 Bits The final end-of-discharge warning flag (EDVF) flag

is used to warn that battery power is at a failure condi-
7 6 5 4 3 2 1 0 tion. All segment drivers are turned off. The EDVF flag
is latched until a valid charge has been detected. The
- BRP - - - - - -
EDVF threshold is set 100mV below the EDV1 thresh-
where BRP is old.

0 bq2013H is charged until NAC = LMD or The EDVF location is:

on the first charge after or a discharge
which sets the EDV1 flag FLGS1 Bits
1 bq2013H is reset 7 6 5 4 3 2 1 0

The valid discharge flag (VDQ) is asserted when the - - - - - - - EDVF

bq2013H is discharged from NAC=LMD. The flag re-
mains set until either LMD is updated or until one of Where EDVF is:
three actions that can clear VDQ occurs: 0 Valid charge action detected or VSB ≥ VEDVF
■ NAC has been reduced by more than 6% during 1 VSB < VEDVF, providing the OVLD bit is not
because of self-discharge since VDQ was set set
■ A valid charge action sustained at VSRO > VSRQ for at
least two NAC updates
■ The EDV1 flag was set at a temperature below 0°C.

12
 bq2013H

TMPGG Gas Gauge Bits

Table 10. Temperature Register Contents
7 6 5 4 3 2 1 0
TMP3 TMP2 TMP1 TMP0 Temperature - - - - GG3 GG2 GG1 GG0
0 0 0 0 T < -30°C
Nominal Available Charge Register (NAC)
0 0 0 1 -30°C < T < -20°C The NACH register (address=03h) and the NACL regis-
ter (address=17h) are the main gas gauging registers for
0 0 1 0 -20°C < T < -10°C the bq2013H. The NAC registers are incremented dur-
ing charge actions and decremented during discharge
0 0 1 1 -10°C < T < 0°C
and self-discharge actions. The correction factors for
charge/discharge efficiency are applied automatically to
0 1 0 0 0°C < T < 10°C
NAC. NACH and NACL are set to 0 during a bq2013H
reset.
0 1 0 1 10°C < T < 20°C

0 1 1 0 20°C < T < 30°C Battery Identification Register (BATID)

The read/write BATID register (address=04h) is avail-
0 1 1 1 30°C < T < 40°C able for use by the system to determine the type of bat-
tery pack. The BATID contents are retained as long as
1 0 0 0 40°C < T < 50°C VRBI is greater than 2V. The contents of BATID have no
effect on the operation of the bq2013H. There is no de-
1 0 0 1 50°C < T < 60°C fault setting for this register.
1 0 1 0 60°C < T < 70°C
Last Measured Discharge Register (LMD)
1 0 1 1 70°C < T < 80°C LMD is a read/write register (address=05h) that the
bq2013H uses as a measured full reference. The
1 1 0 0 T > 80°C bq2013H adjusts LMD based on the measured discharge
capacity of the battery from full to empty. In this way
the bq2013H updates the capacity of the battery. LMD
Temperature and Gas Gauge Register is set to PFC during a bq2013H reset.
(TMPGG)
Secondary Status Flags Register (FLGS2)
TMPGG Temperature Bits The read-only FLGS2 register (address=06h) contains
7 6 5 4 3 2 1 0 the secondary bq2013H flags.

TMP3 TMP2 TMP1 TMP0 - - - The charge rate flag (CR) is used to denote the fast
charge regime. Fast charge is assumed whenever a
The read-only TMPGG register (address=02h) contains charge action is initiated. The CR flag remains asserted
two data fields. The first field contains the battery tem- if the charge rate does not fall below 2 NAC counts/s.
perature. The second field contains the available charge
from the battery. The CR location is:

The bq2013H contains an internal temperature sensor. FLGS2 Bits

The temperature is used to set charge efficiency factors
as well as to adjust the self-discharge coefficient. The 7 6 5 4 3 2 1 0
temperature register contents may be translated as CR - - - - - - -
shown in Table 10.
The bq2013H calculates the available charge as a func- Where CR is:
tion of NAC and a full reference, either LMD or PFC. 0 When charge rate falls below 2 counts/sec
The results of the calculation are available via the dis-
play port or the gas gauge field of the TMPGG register. 1 When charge rate is above 2 counts/sec
The register is used to give available capacity in 1 16 in-
crements from 0 to 15 16. The fast charge regime efficiency factors are used when
CR = 1. When CR = 0, the trickle charge efficiency fac-

13
bq2013H

tors are used. The time to change CR varies due to the tion. OCE may be cleared by either writing the bit to a
user-selectable count rates. logic zero via the serial port or by resetting the bq2013H.
The overload flag (OVLD) is asserted when a discharge Offset Adjustment Register
overload is detected. PROG4 defines the overload
threshold, as defined in Table 4. OVLD remains as- The value in this register (address = 0bh) is used to cor-
serted as long as the condition is valid. rect NAC for the offset of the VFC. This register is ini-
tialized from the state of PROG6. The following are the
The OVLD location is: initial values:

FLGS2 Bits ■ 0 = no offset correction

7 6 5 4 3 2 1 0 ■ 46 = -75µV correction
- - - - - - - OVLD ■ 23 = -150µV correcton

Where OVLD is: The value is set by the equation:

0 If VSRO > VOVLD 1

Offset =
289∗ VCOS
1 If VSRO < VOVLD
where VCOS is the desired offset correction in volts.
Program Pin Pull-Down Register (PPD)
Self-Discharge Rate Compensation
The PPD register (address=07h) contains some of the pro-
gramming pin information for the bq2013H. The program This register contains the value used to correct for the
pins have a corresponding PPD bit location, PPD1–6. A self-discharge compensation. This value is initialized
given location is set if a pull-down resistor has been de- from the state of PROG3. The following are the initial
tected on its corresponding segment driver. For example, if values:
PROG1 and PROG4 have pull-down resistors, the con-
235 = 1.6% per day  
1
tents of PPD are xx001001. ■
 64 

214 = 0.8% per day 

PPD/PPU Bits 1 
■ 
 128 
7 6 5 4 3 2 1 0
88 = 0.2% per day 
1 
RSVD RSVD PPU6 PPU5 PPU4 PPU3 PPU2 PPU1 ■ 
 512 
RSVD RSVD PPD6 PPD5 PPD4 PPD3 PPD2 PPD1
The value is set by the equation:
Program Pin Pull-Up Register (PPU) SDR = 256 − 
0.3296 

 CSD 
The PPU register (address=08h) contains the rest of the
programming pin information for the bq2013H. The pro- where CSD is the self-discharge rate per day.
gram pins have a corresponding PPU bit location, PPU1–6.
A given location is set if a pull-up resistor has been de-
tected on its corresponding segment driver. For example, if
Digital Magnitude Filter (DMF)
PROG3 and PROG5 have pull-up resistors, the contents of The read-write DMF register (address=0dh) provides
PPU are xx010100. the system with a means to change the default settings
of the digital magnitude filter. By writing different val-
Output Control Register (OCTL) ues into this register, the limits of VSRD and VSRQ can be
adjusted. The default value for the DMF is 250µV. The
The write-only OCTL register (address=0ah) provides the
value is set by the equation:
system with a means to check the display connections for
the bq2013H. The segment drivers may be overwritten by 45
DMF =
data from OCTL when bit 1 of OCTL, OCE, is set. The VSRD, Q
data in bits OC5–1 of the OCTL register (see Table 9 for de-
tails) is output onto the segment pins, SEG5–1, respectively where VSRD,Q is the desired filter threshold in mV.
if OCE=1. Whenever OCE is written to 1, the MSB of
OCTL should be set to a 1. The OCE register location Note: Care should be taken when writing to this regis-
must be cleared to return the bq2013H to normal opera- ter. A VSRD and VSRQ below the specified VOS may ad-
versely affect the accuracy of the bq2013H.

14
 bq2013H

VSB = 1.2V ∗ 
Load Compensation VSB 

 256 
The load compensation value (address = 0eh) allows the
bq2013H to compensate for small discharge loads that
are below the digital filter. Each increment in the Display
LCOMP register represents 2µVh. The value in LCOMP The bq2013H can directly display capacity information
represents the additional amount of discharge applied to using low-power LEDs. If LEDs are used, the segment
NAC and DCR at a constant rate when VSRO < VSRQ. pins should be tied to VCC, the battery, or the LCOM pin
LCOMP compensation is applied in addition to self- through resistors for programming the bq2013H.
discharge. LCOMP is set to 0 on a full reset. The value
is set by the equation: The bq2013H displays the battery charge state in either
1 absolute or relative mode. In relative mode, the battery
LCOMP = charge is represented as a percentage of the LMD. Each
289∗ VCLD LED segment represents 20% of the LMD.
where VCLD is the desired load correction in volts. In absolute mode, each segment represents a fixed
amount of charge, based on the initial PFC. In absolute
Charge Compensation mode, each segment represents 20% of the PFC. As the
battery wears out over time, it is possible for the LMD
The charge-compensation value (address = 0fh) allows
to be below the initial PFC. In this case, all of the LEDs
the bq2013H to compensate for battery charge ineffi-
may not turn on, representing the reduction in the ac-
ciencies. This value is initialized from the state of
tual battery capacity.
PROG5 and represents the fast-charge compensation
factor for < 30°C. The value can be overwritten via the When DISP is tied to VCC, the SEG1–5 outputs are inac-
serial port and is stored in percent. The bq2013H scales tive. When DISP is left floating, the display becomes ac-
the value in 0fh to determine the compensation at other tive during charge if the NAC registers are counting at a
rates and temperatures. For example, if PROG5 = H, rate equivalent to VSRO > 500µV or fast discharge if the
the applied efficiency drops by 5% for each temperature NAC registers are counting at a rate equivalent to VSRO
range, and the trickle rates are 15% below the fast- < -2mV. When DISP is pulled low and held, the segment
charge rates. If the value 55h (85%) is written to outputs become active continuously. When released to
CCOMP, the compensation for trickle charge at > 50°C high Z, the segment outputs will remain active for 4 sec-
is 60%. onds.

Program Pin Data (PPFC) The segment outputs are modulated as two banks, with
segments 1, 3, and 5 alternating with segments 2 and 4.
The PPFC register provides the means to perform a soft- The segment outputs are modulated at approximately
ware controlled reset of the device. The recommended 320Hz, with each bank active for 30% of the period.
reset method for the bq2013H is:
SEG1 blinks at a 4Hz rate whenever VSB has been de-
■ Write PPFC to zero tected to be below VEDV1 to indicate a low-battery condi-
tion or NAC is less than 10% of the LMD or PFC, de-
■ Write LMD to zero pending on the display mode.
After these operations, a software reset occurs.
Resetting the bq2013H sets the following:
Microregulator
The bq2013H can operate directly from 4 nickel or 3
■ LMD = PFC lead acid cells. To facilitate the power supply require-
■ VDQ, OCE, LCOMP, and NAC = 0 ments of the bq2013H, an REF output is provided to
regulate an external low-threshold n-FET. A micropower
■ BRP = 1 source for the bq2013H can be inexpensively built using
the FET and an external resistor.
Battery Voltage Register (VSB)
The battery voltage register is used to read the battery
voltage on the SB pin. The VSB register (address = 7eh)
is updated approximately once per second with the pres-
ent value of the battery voltage. The battery voltage on
the SB pin is determined by the equation:

15
bq2013H

Absolute Maximum Ratings

Symbol Parameter Minimum Maximum Unit Notes

VCC Relative to VSS -0.3 +7.0 V
All other pins Relative to VSS -0.3 +7.0 V
REF Relative to VSS -0.3 +8.5 V Current limited by R1 (see Figure 1)
100kΩ series resistor should be used to
VSR Relative to VSS -0.3 Vcc+0.7 V
protect SR in case of a shorted battery.
TOPR Operating temperature 0 +70 °C Commercial

Note: Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional
operation should be limited to the Recommended DC Operating Conditions detailed in this data sheet.
Exposure to conditions beyond the operational limits for extended periods of time may affect device reli-
ability.

DC Voltage Thresholds (TA = TOPR; V = 3.0 to 6.5V)

Symbol Parameter Minimum Typical Maximum Unit Notes

VEDV End-of-discharge warning 0.96 ∗ VEDV VEDV 1.04 ∗ VEDV V SB

VSRO SR sense range -300 - +500 mV SR, VSR + VOS

VSRQ Valid charge 250 - - µV VSR + VOS

VSRD Valid discharge - - -250 µV VSR + VOS

Note: VOS is affected by PC board layout. Proper layout guidelines should be followed for optimal performance.
See “LayoutConsiderations.”

16
 bq2013H

DC Electrical Characteristics (TA = TOPR)

Symbol Parameter Minimum Typical Maximum Unit Notes
VCC excursion from < 2.0V to ≥
VCC Supply voltage 3.0 4.25 6.5 V
3.0V initializes the unit.
VOS Offset referred to VSR - ±50 ±150 µV DISP = VCC
Reference at 25°C 5.7 6.0 6.3 V IREF = 5µA
VREF
Reference at -40°C to +85°C 4.5 - 7.5 V IREF = 5µA
RREF Reference input impedance 2.0 5.0 - MΩ VREF = 3V
- 90 135 µA VCC = 3.0V, HDQ = 0
ICC Normal operation - 120 180 µA VCC = 4.25V, HDQ = 0
- 170 250 µA VCC = 6.5V, HDQ = 0
VSB Battery input 0 - VCC V
RSBmax SB input impedance 10 - - MΩ 0 < VSB < VCC
IDISP DISP input leakage - - 5 µA VDISP = VSS
ILCOM LCOM input leakage -0.2 - 0.2 µA DISP = VCC
IRBI RBI data-retention current - - 100 nA VRBI > VCC < 3V
RHDQ Internal pulldown 500 - - KΩ
RSR SR input impedance 10 - - MΩ -200mV < VSR < VCC
VIHPFC PROG logic input high VCC - 0.2 - - V PROG1-6
VILPFC PROG logic input low - - VSS + 0.2 V PROG1-6
VIZPFC PROG logic input Z float - float V PROG1-6
VCC = 3V, IOLS ≤ 1.75mA
VOLSL SEG output low, low VCC - 0.1 - V
SEG1–SEG5, DONE
VCC = 6.5V, IOLS ≤ 11.0mA
VOLSH SEG output low, high VCC - 0.4 - V
SEG1–SEG5, DONE
VOHML LCOM output high, low VCC VCC - 0.3 - - V VCC = 3V, IOHLCOM = -5.25mA
VOHMH LCOM output high, high VCC VCC - 0.6 - - V VCC > 3.5V, IOHLCOM = -33.0mA
IOLS SEG sink current 11.0 - - mA At VOLSH = 0.4V, VCC = 6.5V
IOL Open-drain sink current 5.0 - - mA At VOL = VSS + 0.3V, HDQ
VOL Open-drain output low - - 0.3 V IOL ≤ 5mA, HDQ
VIHDQ HDQ input high 2.5 - - V HDQ
VILDQ HDQ input low - - 0.8 V HDQ
VIH DONE input high 2.5 - - V DONE
VIL DONE input low - - 0.5 V DONE
Soft pull-up or pull-down resis-
RPROG - - 200 kΩ PROG1–6
tor value (for programming)
RFLOAT Float state external impedance - 5 - MΩ PROG1-6

Note: All voltages relative to VSS.

17
bq2013H

High-Speed Serial Communication Timing Specification (TA = TOPR)

Symbol Parameter Minimum Typical Maximum Unit Notes
tCYCH Cycle time, host to bq2013H (write) 190 - - µs See note
tCYCB Cycle time, bq2013H to host (read) 190 205 250 µs
tSTRH Start hold, host to bq2013H (write) 5 - - ns
tSTRB Start hold, bq2013H to host (read) 32 - - µs
tDSU Data setup - - 50 µs
tDSUB Data setup - - 50 µs
tDH Data hold 100 - - µs
tDV Data valid 80 - - µs
tSSU Stop setup - - 145 µs
tSSUB Stop setup - - 145 µs
tRSPS Response time, bq2013H to host 190 - 320 µs
tB Break 190 - - µs
tBR Break recovery 40 - - µs

Note: The open-drain HDQ pin should be pulled to at least VCC by the host system for proper HDQ operation.
HDQ may be left floating if the serial interface is not used.

18
 bq2013H

Break Timing

tB tBR

TD201803.eps

Host to bq2013H

Write "1"

Write "0"
tSTRH
tDSU
tDH
tSSU
tCYCH

bq2013H to Host

Read "1"

Read "0"

tSTRB
tDSUB
tDV
tSSUB
tCYCB

19
bq2013H

16-Pin SOIC Narrow (SN)

16-Pin SN (SOIC Narrow)

Dimension Minimum Maximum
A 0.060 0.070
D B A1 0.004 0.010
e B 0.013 0.020
C 0.007 0.010
D 0.385 0.400
E E 0.150 0.160
e 0.045 0.055
H H 0.225 0.245
L 0.015 0.035
All dimensions are in inches.
A
C A1

.004
L

20
 bq2013H

Data Sheet Revision History

ChangeNo. Page No. Description of Change

1 All “Final” changes from “Preliminary” version

2 3 Updated application diagram
2 8 Changed charge/discharge default threshold from 200µV to 250µV.
2 9 Changed offset compensation window range from ±200µV to ±250µV
2 11 Designated appropriate locations from “R/W” to “R”
2 12 Changed charge threshold from 200µV to 250µV
2 14 Changed default DMF from 200µV to 250µV
2 16 Added REF absolute maximum rating
2 16 Changed charge/discharge default threshold from 200µV to 250µV
2 16 Added VSRO parameter
2 17 Changed DQ designation to HDQ
2 17 Changed VOL from 0.5V to 0.3V (max.)
2 17 Added RPROG
3 9 Changed the DONE Input section

Note: Change 1 = Dec. 1998 changes from July 1998 “Preliminary.”

Change 2 = May 1999 A changes from Dec. 1998.
Change 3 = December 2013 B changes from May 1999

21
bq2013H

Ordering Information

bq2013H

Temperature Range:
blank = Commercial (0 to +70°C)

Package Option:
SN = 16-pin narrow SOIC

Device:
bq2013H Gas Gauge IC

22
 PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

BQ2013HSN-A514 ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-2-260C-1 YEAR 0 to 70 2013H
A514
BQ2013HSN-A514G4 ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-2-260C-1 YEAR 0 to 70 2013H
A514
BQ2013HSN-A514TR NRND SOIC D 16 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR 0 to 70 2013H
A514
BQ2013HSN-A514TRG4 NRND SOIC D 16 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR 0 to 70 2013H
A514

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 30-Dec-2020

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
BQ2013HSN-A514TR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 30-Dec-2020

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
BQ2013HSN-A514TR SOIC D 16 2500 853.0 449.0 35.0

Pack Materials-Page 2
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