dra829j-q1
dra829j-q1
dra829j-q1
DRA829 Processors
• Full-HD video, one (1920 × 1080p, 60 fps), or up to
1 Features three (1920 × 1080p, 30 fps) H.264 encode
Processor cores:
Functional Safety:
• Dual 64-bit Arm® Cortex®-A72 microprocessor • Functional Safety-Compliant targeted (on select
subsystem at up to 2.0GHz part numbers)
– 1MB shared L2 cache per dual-core Arm® – Developed for functional safety applications
Cortex®-A72 cluster – Documentation available to aid ISO 26262/IEC
– 32KB L1 DCache and 48KB L1 ICache per 61508 functional safety system design up to
Cortex®-A72 Core ASIL-D/SIL-3 targeted
• Six Arm® Cortex®-R5F MCUs at up to 1.0GHz – Systematic capability up to ASIL-D/SC-3
– 16K I-Cache, 16K D-Cache, 64K L2 TCM targeted
– Two Arm® Cortex®-R5F MCUs in isolated MCU – Hardware integrity up to ASIL-D/SIL-3 targeted
subsystem for MCU Domain
– Four Arm® Cortex®-R5F MCUs in general – Hardware integrity up to ASIL-B/SIL-2 targeted
compute partition for Main Domain
• Deep-learning Matrix Multiply Accelerator (MMA), – Safety-related certification
up to 8 TOPS (8b) at 1.0 GHz • ISO 26262 certification up to ASIL-D by TÜV
• C7x floating point, vector DSP, up to 1.0 GHz, SÜD planned
80 GFLOPS, 256 GOPS • IEC 61508 certification up to SIL-3 by TÜV
• Two C66x floating point DSP, up to 1.35 GHz, SÜD planned
40 GFLOPS, 160 GOPS • AEC-Q100 qualified on part number variants
• 3D GPU PowerVR® Rogue 8XE GE8430, up to ending in Q1
750 MHz, 96 GFLOPS, 6 Gpix/sec • Device security (on select part numbers):
• Secure boot with secure run-time support
Memory subsystem:
• Customer programmable root key, up to RSA-4K
• Up to 8MB of on-chip L3 RAM with ECC and
or ECC-512
coherency
• Embedded hardware security module
– ECC error protection • Crypto hardware accelerators – PKA with ECC,
– Shared coherent cache AES, SHA, RNG, DES and 3DES
– Supports internal DMA engine
• External Memory Interface (EMIF) module with High speed serial interfaces:
ECC • Two CSI2.0 4L RX plus one CSI2.0 4L TX
– Supports LPDDR4 memory types • Integrated Ethernet switch supporting up to 8
– Supports speeds up to 4266 MT/s external ports
– 32-bit data bus with inline ECC up to 14.9GB/s – All ports support 2.5Gb SGMII
• General-Purpose Memory Controller (GPMC) – All ports support 1Gb SGMII/RGMII
• 512KB on-chip SRAM in MAIN domain, protected – All ports support 100Mb RMII
by ECC – Any two ports support QSGMII (using 4 internal
ports per QSGMII)
Display subsystem: • Up to four PCI-Express® (PCIe) Gen3 controllers
• One eDP/DP interface with Multi-Display Support
– Gen1 (2.5GT/s), Gen2 (5.0GT/s), and Gen3
(MST)
(8.0GT/s) operation with auto-negotiation
– HDCP1.4/HDCP2.2 high-bandwidth digital – Up to two lanes per controller
content protection • Two USB 3.0 dual-role device (DRD) subsystem
• One DSI TX (up to 2.5K)
– Two enhanced SuperSpeed Gen1 ports
• Up to two DPI
– Each port supports Type-C switching
Video acceleration: – Each port independently configurable as USB
• Ultra-HD video, one (3840 × 2160p, 60 fps), or two host, USB peripheral, or USB DRD
(3840 × 2160p, 30 fps) H.264/H.265 decode
Automotive interfaces:
• Full-HD video, four (1920 × 1080p, 60 fps), or eight
• Sixteen Modular Controller Area Network (MCAN)
(1920 × 1080p, 30 fps) H.264/H.265 decode
modules with full CAN-FD support
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1
SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com
(1) For more information, see Mechanical, Packaging, and Orderable Information.
(2) The package size (length × width) is a nominal value and includes pins, where applicable.
Note
To understand what device features are currently supported by TI Software Development Kits (SDKs),
see the DRA829 and TDA4VM Software Build Sheet (PROCESSOR-SDK-J721E).
DRA829
Navigator Subsystem
Dual Arm ® ® C7x DSP 2×
4× Arm UDMA SecProxy PVU CPTS
Cortex ®-A72 Cortex ®-R5F w/ MMA C66x DSP
Proxy/RA MCRC INTR Mailbox
Memory Subsystem Ethernet Subsystem Display Subsystem System Services Capture Subsystem
Interconnect
Media and Data Storage Control Interfaces General Connectivity High-Speed Serial Interfaces
(B)
2× SD/SDIO 3× eCAP 8× GPIO 8× MCSPI 2× USB 3.0 DRD
14× CAN-FD 12× MCASP 7× I2C 10× UART 10/100/1000 Ethernet (A)
(A) (A)
2× CAN-FD (A) 3× I2C 2× UART
intro_001
(A)
2× I3C I3C
A. This interface is located on the MCU Island but is available for the full system to access.
B. DP, SGMII, USB3.0, and PCIE[3:0] share total of twelve SerDes lanes.
C. Two simultaneous flash interfaces configured as OSPI0 and OSPI1, or HyperBus™ and OSPI1.
Table of Contents
1 Features............................................................................1 7 Detailed Description....................................................291
2 Applications..................................................................... 2 7.1 Overview................................................................. 291
3 Description.......................................................................2 7.2 Processor Subsystems........................................... 292
3.1 Functional Block Diagram........................................... 3 7.3 Accelerators and Coprocessors..............................293
4 Device Comparison......................................................... 6 7.4 Other Subsystems.................................................. 294
4.1 Related Products........................................................ 8 8 Applications and Implementation.............................. 303
5 Terminal Configuration and Functions..........................9 8.1 Power Supply Mapping........................................... 303
5.1 Pin Diagram................................................................ 9 8.2 Device Connection and Layout Fundamentals....... 306
5.2 Pin Attributes.............................................................10 8.3 Peripheral- and Interface-Specific Design
5.3 Signal Descriptions................................................... 76 Information................................................................ 308
5.4 Pin Multiplexing.......................................................132 9 Device and Documentation Support..........................313
5.5 Pin Connectivity Requirements...............................147 9.1 Device Nomenclature..............................................313
6 Specifications.............................................................. 150 9.2 Tools and Software................................................. 315
6.1 Absolute Maximum Ratings.................................... 150 9.3 Documentation Support.......................................... 316
6.2 ESD Ratings........................................................... 153 9.4 Support Resources................................................. 316
6.3 Power-On-Hour (POH) Limits................................. 153 9.5 Trademarks............................................................. 316
6.4 Recommended Operating Conditions.....................153 9.6 Electrostatic Discharge Caution..............................316
6.5 Operating Performance Points................................156 9.7 Glossary..................................................................316
6.6 Electrical Characteristics.........................................157 10 Revision History........................................................ 317
6.7 VPP Specifications for One-Time Programmable 11 Mechanical, Packaging, and Orderable
(OTP) eFuses............................................................165 Information.................................................................. 320
6.8 Thermal Resistance Characteristics....................... 167 11.1 Packaging Information.......................................... 320
6.9 Timing and Switching Characteristics..................... 168
4 Device Comparison
Table 4-1 shows the features of the SoC, highlighting the differences.
Note
To understand what device features are currently supported by TI Software Development Kits (SDKs),
see the DRA829 and TDA4VM Software Build Sheet (PROCESSOR-SDK-J721E).
(1) Safety features including R5F Lockstep and SIL/ASIL ratings are only applicable to select part number variants as indicated by the
Device Type (Y) identifier in the Table 9-1, Nomenclature Description table.
(2) Device security features including Secure Boot and Customer Programmable Keys are applicable to select part number variants as
indicated by the Device Type (Y) identifier in the Table 9-1, Nomenclature Description table.
(3) AEC-Q100 qualification is applicable to select part number variants as indicated by the Automotive Designator (Q1) identifier in the
Table 9-1, Nomenclature Description table.
(4) DP, SGMII, USB3.0, and PCIE[3:0] share total of twelve SerDes lanes.
(5) Two simultaneous flash interfaces configured as OSPI0 and OSPI1, or HyperBus and OSPI1.
(6) Software should constrain the features used to match the intended production device.
(7) OSPI1 module only pins out 4 pins and is referred to as QSPI in some contexts.
Figure 5-1 shows the ball locations for the 827-ball flip chip ball grid array (FCBGA) package that are used in
conjunction with Table 5-1 through Figure 5-1 to locate signal names and ball grid numbers.
AJ
AH
AG
AF
AE
AD
AC
AB
AA
Y
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29
2 4 6 8 10 12 14 16 18 20 22 24 26 28
Note
Media Local Bus (MLB) is not available on this device. The following balls must be left unconnected if not used in GPIO mode: AE2, AD2, AD3,
AC3, AC1, AD1.
Note
PRU_ICSSG0 and PRU_ICSSG1 are not available on this device. The prg* signals should not be used. Those pins can be used for other
functions.
USB0_SSRX2N I
AJ18 SERDES0_RX0_P SERDES0_RX0_P I OFF 0.8 V VDDA_0P8_SE 2-L-PHY
RDES0_1 / VDD
SGMII1_RXP0 I A_1P8_SERDE
PCIE0_RXP0 I S0_1
USB0_SSRX2P I
USB0_SSRX1N I
AJ17 SERDES0_RX1_P SERDES0_RX1_P I OFF 0.8 V VDDA_0P8_SE 2-L-PHY
RDES0_1 / VDD
SGMII2_RXP0 I A_1P8_SERDE
PCIE0_RXP1 I S0_1
USB0_SSRX1P I
AF19 SERDES0_TX0_N SERDES0_TX0_N O OFF 0.8 V VDDA_0P8_SE 2-L-PHY
RDES0_1 / VDD
SGMII1_TXN0 O A_1P8_SERDE
PCIE0_TXN0 O S0_1
USB0_SSTX2N O
AG18 SERDES0_TX0_P SERDES0_TX0_P O OFF 0.8 V VDDA_0P8_SE 2-L-PHY
RDES0_1 / VDD
SGMII1_TXP0 O A_1P8_SERDE
PCIE0_TXP0 O S0_1
USB0_SSTX2P O
AF18 SERDES0_TX1_N SERDES0_TX1_N O OFF 0.8 V VDDA_0P8_SE 2-L-PHY
RDES0_1 / VDD
SGMII2_TXN0 O A_1P8_SERDE
PCIE0_TXN1 O S0_1
USB0_SSTX1N O
AG17 SERDES0_TX1_P SERDES0_TX1_P O OFF 0.8 V VDDA_0P8_SE 2-L-PHY
RDES0_1 / VDD
SGMII2_TXP0 O A_1P8_SERDE
PCIE0_TXP1 O S0_1
USB0_SSTX1P O
AH15 SERDES1_RX0_N SERDES1_RX0_N I OFF 0.8 V VDDA_0P8_SE 2-L-PHY
RDES0_1 / VDD
SGMII3_RXN0 I A_1P8_SERDE
PCIE1_RXN0 I S0_1
USB1_SSRX2N I
PRG1_SGMII0_RXN0 I
AJ14 SERDES1_RX0_P SERDES1_RX0_P I OFF 0.8 V VDDA_0P8_SE 2-L-PHY
RDES0_1 / VDD
SGMII3_RXP0 I A_1P8_SERDE
PCIE1_RXP0 I S0_1
USB1_SSRX2P I
PRG1_SGMII0_RXP0 I
USB1_SSRX1N I
PRG1_SGMII1_RXN0 I
AJ15 SERDES1_RX1_P SERDES1_RX1_P I OFF 0.8 V VDDA_0P8_SE 2-L-PHY
RDES0_1 / VDD
SGMII4_RXP0 I A_1P8_SERDE
PCIE1_RXP1 I S0_1
USB1_SSRX1P I
PRG1_SGMII1_RXP0 I
AF15 SERDES1_TX0_N SERDES1_TX0_N O OFF 0.8 V VDDA_0P8_SE 2-L-PHY
RDES0_1 / VDD
SGMII3_TXN0 O A_1P8_SERDE
PCIE1_TXN0 O S0_1
USB1_SSTX2N O
PRG1_SGMII0_TXN0 O
AG14 SERDES1_TX0_P SERDES1_TX0_P O OFF 0.8 V VDDA_0P8_SE 2-L-PHY
RDES0_1 / VDD
SGMII3_TXP0 O A_1P8_SERDE
PCIE1_TXP0 O S0_1
USB1_SSTX2P O
PRG1_SGMII0_TXP0 O
AF16 SERDES1_TX1_N SERDES1_TX1_N O OFF 0.8 V VDDA_0P8_SE 2-L-PHY
RDES0_1 / VDD
SGMII4_TXN0 O A_1P8_SERDE
PCIE1_TXN1 O S0_1
USB1_SSTX1N O
PRG1_SGMII1_TXN0 O
AG15 SERDES1_TX1_P SERDES1_TX1_P O OFF 0.8 V VDDA_0P8_SE 2-L-PHY
RDES0_1 / VDD
SGMII4_TXP0 O A_1P8_SERDE
PCIE1_TXP1 O S0_1
USB1_SSTX1P O
PRG1_SGMII1_TXP0 O
AH13 SERDES2_RX0_N SERDES2_RX0_N I OFF 0.8 V VDDA_0P8_SE 2-L-PHY
RDES2_3 / VDD
PCIE2_RXN0 I A_1P8_SERDE
USB1_SSRX2N I S2_3
PRG1_SGMII0_RXN0
PRG1_SGMII0_RXP0
AH12 SERDES2_RX1_N SERDES2_RX1_N I OFF 0.8 V VDDA_0P8_SE 2-L-PHY
RDES2_3 / VDD
PCIE2_RXN1 I A_1P8_SERDE
USB1_SSRX1N I S2_3
PRG1_SGMII1_RXN0
AJ11 SERDES2_RX1_P SERDES2_RX1_P I OFF 0.8 V VDDA_0P8_SE 2-L-PHY
RDES2_3 / VDD
PCIE2_RXP1 I A_1P8_SERDE
USB1_SSRX1P I S2_3
PRG1_SGMII1_RXP0
AF13 SERDES2_TX0_N SERDES2_TX0_N O OFF 0.8 V VDDA_0P8_SE 2-L-PHY
RDES2_3 / VDD
PCIE2_TXN0 O A_1P8_SERDE
USB1_SSTX2N O S2_3
PRG1_SGMII0_TXN0
AG12 SERDES2_TX0_P SERDES2_TX0_P O OFF 0.8 V VDDA_0P8_SE 2-L-PHY
RDES2_3 / VDD
PCIE2_TXP0 O A_1P8_SERDE
USB1_SSTX2P O S2_3
PRG1_SGMII0_TXP0
AF12 SERDES2_TX1_N SERDES2_TX1_N O OFF 0.8 V VDDA_0P8_SE 2-L-PHY
RDES2_3 / VDD
PCIE2_TXN1 O A_1P8_SERDE
USB1_SSTX1N O S2_3
PRG1_SGMII1_TXN0
AG11 SERDES2_TX1_P SERDES2_TX1_P O OFF 0.8 V VDDA_0P8_SE 2-L-PHY
RDES2_3 / VDD
PCIE2_TXP1 O A_1P8_SERDE
USB1_SSTX1P O S2_3
PRG1_SGMII1_TXP0
AH9 SERDES3_RX0_N SERDES3_RX0_N I OFF 0.8 V VDDA_0P8_SE 2-L-PHY
RDES2_3 / VDD
PCIE3_RXN0 I A_1P8_SERDE
USB0_SSRX2N I S2_3
1. The MUXMODE field is not used to select the multiplexed signal function for this pin. For more information, see ADC Integration Details section in
Device Configuration chapter of the device TRM.
The following list describes the table column headers:
1. BALL NUMBER: Ball numbers on the bottom side associated with each signal on the bottom.
2. BALL NAME: Mechanical name from package device (name is taken from muxmode 0).
3. SIGNAL NAME: Names of signals multiplexed on each ball (also notice that the name of the ball is the signal name in muxmode 0).
Note
Table 5-1, Pin Attributes, does not take into account the subsystem multiplexing signals. Subsystem multiplexing signals are described in
Section 5.3, Signal Descriptions.
4. MUXMODE: Multiplexing mode number:
a. MUXMODE 0 is the primary muxmode. The primary muxmode is not necessarily the default muxmode.
Note
The default muxmode is the mode at the release of the reset; also see the BALL RESET REL. MUXMODE column.
b. MUXMODE 1 through 7 are possible muxmodes for alternate functions. On each pin, some muxmodes are effectively used for alternate
functions, while some muxmodes are not used. Only MUXMODE values which correspond to defined functions should be used.
c. MCU_BOOTMODE pins are latched on the rising edge of MCU_PORz_OUT. BOOTMODE pins are latched on the rising edge of PORz_OUT.
d. An empty box means Not Applicable.
5. TYPE: Signal type and direction:
• I = Input
• O = Output
• IO = Input or Output
• IOD = Open drain terminal - Input or Output
• IOZ = Input, Output or Three-state terminal
• OZ = Output or Three-state terminal
• A = Analog
• PWR = Power
• GND = Ground
• CAP = LDO Capacitor.
6. BALL RESET STATE: The state of the terminal at power-on reset:
• DRIVE 0 (OFF): The buffer drives VOL (pulldown or pullup resistor not activated).
• DRIVE 1 (OFF): The buffer drives VOH (pulldown or pullup resistor not activated).
• OFF: High-impedance
• PD: High-impedance with an active pulldown resistor
• PU: High-impedance with an active pullup resistor
• An empty box means Not Applicable.
7. BALL RESET REL. MUXMODE: This muxmode is automatically configured at the release of the rstoutn signal.
An empty box means Not Applicable.
8. I/O VOLTAGE VALUE: This column describes the IO voltage value (the corresponding power supply).
An empty box means Not Applicable.
9. POWER: The voltage supply that powers the terminal IO buffers.
An empty box means Not Applicable.
10. HYS: Indicates if the input buffer has hysteresis:
• Yes: With hysteresis
• No: Without hysteresis
An empty box means No.
For more information, see the hysteresis values in, Electrical Characteristics.
11. BUFFER TYPE: This column describes the associated output buffer type
Note
Configuring two pins to the same input signal is not supported as it can yield unexpected results. This can be easily prevented with the
proper software configuration (HiZ mode is not an input signal).
Note
When a pad is set into a multiplexing mode which is not defined by pin multiplexing, that pad’s behavior is undefined. This should be
avoided.
Note
In Pin Attributes and Pin Multiplexing are not described the subsystem multiplexing signals.
2. DESCRIPTION: Description of the signal
3. PIN TYPE: Signal direction and type:
• I = Input
• O = Output
• IO = Input or Output
• IOD = Open drain terminal - Input or Output
• IOZ = Input, Output or Three-state terminal
• OZ = Output or Three-state terminal
• A = Analog
• PWR = Power
• GND = Ground
• CAP = LDO Capacitor
4. BALL: Associated balls bottom
For more information on the I/O cell configurations, see Pad Configuration Registers section of Device
Configuration chapter in the MAIN.
5.3.1 ADC
Note
The ADC can be configured to be used as a GPI. For more information, see Analog-to-Digital
Converter (ADC) section in Peripherals chapter in the device TRM.
5.3.2 DDRSS
5.3.2.1 MAIN Domain
Table 5-5. DDRSS Signal Descriptions
PIN TYPE
SIGNAL NAME [1] DESCRIPTION [2] BALL [4]
[3]
DDR_RET External IO Retention Enable I P6
(1) An external 240 Ω ±1% resistor must be connected between this pin and VSS. No external voltage should be applied to this pin.
5.3.3 GPIO
5.3.3.1 MAIN Domain
Table 5-7. GPIO0 Signal Descriptions
PIN TYPE
SIGNAL NAME [1] DESCRIPTION [2] BALL [4]
[3]
GPIO0_0 General Purpose Input/Output IO AC18
GPIO0_1 General Purpose Input/Output IO AC23
GPIO0_2 General Purpose Input/Output IO AG22
GPIO0_3 General Purpose Input/Output IO AF22
GPIO0_4 General Purpose Input/Output IO AJ23
5.3.4 I2C
5.3.4.1 MAIN Domain
Table 5-10. I2C0 Signal Descriptions
PIN TYPE
SIGNAL NAME [1] DESCRIPTION [2] BALL [4]
[3]
I2C0_SCL I2C Clock IOD AC5
I2C0_SDA I2C Data IOD AA5
5.3.5 I3C
5.3.5.1 MAIN Domain
Table 5-20. I3C0 Signal Descriptions
PIN TYPE
SIGNAL NAME [1] DESCRIPTION [2] BALL [4]
[3]
I3C0_SCL I3C Clock IO W2
I3C0_SDA I3C Data IO W1
I3C0_SDAPULLEN MAIN domain I3C Data Pull Enable O AB4, U2
5.3.6 MCAN
5.3.6.1 MAIN Domain
Table 5-23. MCAN0 Signal Descriptions
PIN TYPE
SIGNAL NAME [1] DESCRIPTION [2] BALL [4]
[3]
MCAN0_RX MCAN Receive Data I W5
MCAN0_TX MCAN Transmit Data O W6
5.3.7 MCSPI
5.3.7.1 MAIN Domain
Table 5-39. MCSPI0 Signal Descriptions
PIN TYPE
SIGNAL NAME [1] DESCRIPTION [2] BALL [4]
[3]
SPI0_CLK SPI Clock IO AA1
SPI0_CS0 SPI Chip Select 0 IO AA2
SPI0_CS1 SPI Chip Select 1 IO Y4
SPI0_CS2 SPI Chip Select 2 IO AC2
SPI0_CS3 SPI Chip Select 3 IO AB1
SPI0_D0 SPI Data 0 IO AB5
SPI0_D1 SPI Data 1 IO AA3
5.3.8 UART
5.3.8.1 MAIN Domain
Table 5-48. UART0 Signal Descriptions
PIN TYPE
SIGNAL NAME [1] DESCRIPTION [2] BALL [4]
[3]
UART0_CTSn UART Clear to Send (active low) I AC2, Y3
UART0_DCDn UART Data Carrier Detect (active low) I P23
UART0_DSRn UART Data Set Ready (active low) I R28
UART0_DTRn UART Data Terminal Ready (active low) O T27
UART0_RIn UART Ring Indicator I T24
UART0_RTSn UART Request to Send (active low) O AA2, AB1
UART0_RXD UART Receive Data I AB2, AC23
UART0_TXD UART Transmit Data O AB3, AG22
5.3.9 MDIO
5.3.9.1 MCU Domain
Table 5-60. MDIO0 Signal Descriptions
PIN TYPE
SIGNAL NAME [1] DESCRIPTION [2] BALL [4]
[3]
MCU_MDIO0_MDC MDIO Clock O F23
MCU_MDIO0_MDIO MDIO Data IO E23
5.3.10 CPSW2G
Note
The subsystem (SS) applies to both CPSW2G and the CPTS. For more details about CPTS signal
characteristics, see the Section 5.3.21, CPTS signal descriptions.
5.3.11 CPSW9G
5.3.11.1 MAIN Domain
Table 5-62. CPSW9G0 Signal Descriptions
PIN TYPE
SIGNAL NAME [1] DESCRIPTION [2] BALL [4]
[3]
RMII Clock Output (50 MHz). This pin is used for clock
CLKOUT source to the external PHY and must be routed back to OZ AA25, AJ28, Y29
the RMII_REF_CLK pin for proper device operation.
MDIO0_MDC MDIO Clock O V24
MDIO0_MDIO MDIO Data IO V26
RGMII1_RXC RGMII Receive Clock I AD22
RGMII1_RX_CTL RGMII Receive Control I AH23
RGMII1_TXC RGMII Transmit Clock O AE24
RGMII1_TX_CTL RGMII Transmit Control O AC24
RGMII2_RXC RGMII Receive Clock I AE23
RGMII2_RX_CTL RGMII Receive Control I AH24
RGMII2_TXC RGMII Transmit Clock O AJ26
RGMII2_TX_CTL RGMII Transmit Control O AJ27
RGMII3_RXC RGMII Receive Clock I AE26
RGMII3_RX_CTL RGMII Receive Control I AD25
RGMII3_TXC RGMII Transmit Clock O AH28
RGMII3_TX_CTL RGMII Transmit Control O AG27
RGMII4_RXC RGMII Receive Clock I AC26
RGMII4_RX_CTL RGMII Receive Control I AD29
RGMII4_TXC RGMII Transmit Clock O AG29
RGMII4_TX_CTL RGMII Transmit Control O AF29
RGMII5_RXC RGMII Receive Clock I U25
RGMII5_RX_CTL RGMII Receive Control I U26
RGMII5_TXC RGMII Transmit Clock O U29
RGMII5_TX_CTL RGMII Transmit Control O U23
RGMII6_RXC RGMII Receive Clock I W26
RGMII6_RX_CTL RGMII Receive Control I V23
RGMII6_TXC RGMII Transmit Clock O W29
RGMII6_TX_CTL RGMII Transmit Control O Y28
RGMII7_RXC RGMII Receive Clock I AD22
RGMII7_RX_CTL RGMII Receive Control I AH23
RGMII7_TXC RGMII Transmit Clock O AE24
RGMII7_TX_CTL RGMII Transmit Control O AC24
RGMII8_RXC RGMII Receive Clock I AE23
5.3.12 ECAP
5.3.12.1 MAIN Domain
Table 5-63. ECAP0 Signal Descriptions
PIN TYPE
SIGNAL NAME [1] DESCRIPTION [2] BALL [4]
[3]
Enhanced Capture (ECAP) Input or Auxiliary PWM
ECAP0_IN_APWM_OUT IO P24, U2
(APWM) Ouput
5.3.13 EQEP
5.3.13.1 MAIN Domain
Table 5-66. EQEP0 Signal Descriptions
PIN TYPE
SIGNAL NAME [1] DESCRIPTION [2] BALL [4]
[3]
EQEP0_A EQEP Quadrature Input A I AC2
EQEP0_B EQEP Quadrature Input B I AB1
EQEP0_I EQEP Index IO AD5
EQEP0_S EQEP Strobe IO AC4
5.3.14 EHRPWM
5.3.14.1 MAIN Domain
Table 5-69. EHRPWM Signal Descriptions
PIN TYPE
SIGNAL NAME [1] DESCRIPTION [2] BALL [4]
[3]
EHRPWM_SOCA EHRPWM Start of Conversion A O U25
EHRPWM_SOCB EHRPWM Start of Conversion B O R23
5.3.15 USB
5.3.15.1 MAIN Domain
Note
USB3 functionality is available on the SERDES pins. For more information, refer to Section 5.3.16,
SERDES.
(1) An external resistor divider is required to limit the voltage applied to the device pin. For more information, see Section 8.3.4, USB
Design Guidelines.
(2) An external 500 Ω ±1% resistor must be connected between this pin and VSS, even when the pin is unused.
(1) An external resistor divider is required to limit the voltage applied to the device pin. For more information, see Section 8.3.4, USB
Design Guidelines.
(2) An external 500 Ω ±1% resistor must be connected between this pin and VSS, even when the pin is unused.
5.3.16 SERDES
5.3.16.1 MAIN Domain
Table 5-78. SERDES0 Signal Descriptions
(2) PIN TYPE
SIGNAL NAME [1] DESCRIPTION [2] BALL [4]
[3]
PCIE0_CLKREQn PCIE Clock Request Signal IO W2
PCIE_REFCLK0N PCIE Reference Clock Input/Output (negative) IO AE17
PCIE_REFCLK0P PCIE Reference Clock Input/Output (positive) IO AD16
(1)
SERDES0_REXT External Calibration Resistor A AE18
SERDES0_RX0_N SERDES Differential Receive Data (negative) I AH19
SERDES0_RX0_P SERDES Differential Receive Data (positive) I AJ18
SERDES0_RX1_N SERDES Differential Receive Data (negative) I AH18
SERDES0_RX1_P SERDES Differential Receive Data (positive) I AJ17
(1) An external 3.01 kΩ ±1% resistor must be connected between this pin and VSS, even when the pin is unused.
(2) The functionality of these pins is controlled by SERDES0_LN[1:0]_CTRL LANE_FUNC_SEL.
(1) The external 3.01 kΩ ±1% resistor must be connected between this pin and VSS, even when the pin is unused.
(2) The functionality of these pins is controlled by SERDES1_LN[1:0]_CTRL LANE_FUNC_SEL.
(1) The external 3.01 kΩ ±1% resistor must be connected between this pin and VSS, even when the pin is unused.
(2) The functionality of these pins is controlled by SERDES2_LN[1:0]_CTRL LANE_FUNC_SEL.
(1) The external 3.01 kΩ ±1% resistor must be connected between this pin and VSS, even when the pin is unused.
(2) The functionality of these pins is controlled by SERDES3_LN[1:0]_CTRL LANE_FUNC_SEL.
(1) The external 3.01 kΩ ±1% resistor must be connected between this pin and VSS, even when the pin is unused.
(2) The functionality of these pins is controlled by SERDES4_LN[4:0]_CTRL LANE_FUNC_SEL.
5.3.17 OSPI
5.3.17.1 MCU Domain
Table 5-83. OSPI0 Signal Descriptions
PIN TYPE
SIGNAL NAME [1] DESCRIPTION [2] BALL [4]
[3]
MCU_OSPI0_CLK OSPI Clock O E20
MCU_OSPI0_DQS OSPI Data Strobe (DQS) or Loopback Clock Input I D21
(1) An external pull-up resistor to corresponting power supply is recommended on this signal.
5.3.18 Hyperbus
5.3.18.1 MCU Domain
Table 5-85. HYPERBUS0 Signal Descriptions
PIN TYPE
SIGNAL NAME [1] DESCRIPTION [2] BALL [4]
[3]
MCU_HYPERBUS0_CK Hyperbus Differential Clock (positive) O E20
MCU_HYPERBUS0_CKn Hyperbus Differential Clock (negative) O C21
MCU_HYPERBUS0_INTn Hyperbus Interrupt (active low) I B23
MCU_HYPERBUS0_RESETn Hyperbus Reset (active low) Output O E19
Hyperbus Reset Status Indicator (active low) from
MCU_HYPERBUS0_RESETOn I A23
Hyperbus Memory
MCU_HYPERBUS0_RWDS Hyperbus Read-Write Data Strobe IO D21
MCU_HYPERBUS0_WPn Hyperbus Write Protect (not in use) O E22
MCU_HYPERBUS0_CSn0 Hyperbus Chip Select 0 O F19
MCU_HYPERBUS0_CSn1 Hyperbus Chip Select 1 O E22
5.3.19 GPMC
5.3.19.1 MAIN Domain
Table 5-86. GPMC0 Signal Descriptions
PIN TYPE
SIGNAL NAME [1] DESCRIPTION [2] BALL [4]
[3]
GPMC functional clock output selected through a mux
GPMC0_FCLK_MUX O AB23
logic
GPMC Address Valid (active low) or Address Latch
GPMC0_ADVn_ALE O AG20
Enable
GPMC0_CLKOUT GPMC clock generated for external synchronization O AB23
GPMC0_DIR GPMC Data Bus Signal Direction Control O AJ23, W25
GPMC Output Enable (active low) or Read Enable
GPMC0_OEn_REn O AJ20
(active low)
GPMC0_WEn GPMC Write Enable (active low) O AD20
GPMC0_WPn GPMC Flash Write Protect (active low) O AG21
GPMC Address 0 Output. Only used to effectively
GPMC0_A0 OZ AA27
address 8-bit data non-multiplexed memories
GPMC address 1 Output in A/D non-multiplexed mode
GPMC0_A1 OZ U23
and Address 17 in A/D multiplexed mode
GPMC address 2 Output in A/D non-multiplexed mode
GPMC0_A2 OZ U26
and Address 18 in A/D multiplexed mode
GPMC address 3 Output in A/D non-multiplexed mode
GPMC0_A3 OZ V28
and Address 19 in A/D multiplexed mode
GPMC address 4 Output in A/D non-multiplexed mode
GPMC0_A4 OZ V29
and Address 20 in A/D multiplexed mode
GPMC address 5 Output in A/D non-multiplexed mode
GPMC0_A5 OZ V27
and Address 21 in A/D multiplexed mode
GPMC address 6 Output in A/D non-multiplexed mode
GPMC0_A6 OZ U28
and Address 22 in A/D multiplexed mode
GPMC address 7 Output in A/D non-multiplexed mode
GPMC0_A7 OZ U29
and Address 23 in A/D multiplexed mode
GPMC address 8 Output in A/D non-multiplexed mode
GPMC0_A8 OZ U25
and Address 24 in A/D multiplexed mode
GPMC address 9 Output in A/D non-multiplexed mode
GPMC0_A9 OZ U27
and Address 25 in A/D multiplexed mode
GPMC address 10 Output in A/D non-multiplexed mode
GPMC0_A10 OZ U24
and Address 26 in A/D multiplexed mode
GPMC address 11 Output in A/D non-multiplexed mode
GPMC0_A11 OZ R23
and unused in A/D multiplexed mode
GPMC address 12 Output in A/D non-multiplexed mode
GPMC0_A12 OZ T23
and unused in A/D multiplexed mode
5.3.20 MMC
5.3.20.1 MAIN Domain
Table 5-87. MMC0 Signal Descriptions
PIN TYPE
SIGNAL NAME [1] DESCRIPTION [2] BALL [4]
[3]
(1)
MMC0_CALPAD MMC/SD/SDIO Calibration Resistor A AE1
MMC0_CLK MMC/SD/SDIO Clock O AF1
(2)
MMC0_CMD MMC/SD/SDIO Command IO AE3
MMC0_DS MMC Data Strobe IO AE4
(2)
MMC0_DAT0 MMC/SD/SDIO Data IO AG2
(2)
MMC0_DAT1 MMC/SD/SDIO Data IO AH1
(2)
MMC0_DAT2 MMC/SD/SDIO Data IO AG3
(2)
MMC0_DAT3 MMC/SD/SDIO Data IO AF4
(2)
MMC0_DAT4 MMC/SD/SDIO Data IO AE5
(1) An external 10 kΩ ±1% resistor must be connected between this pin and VSS. No external voltage should be applied to this pin.
(2) An external pull-up of 10 kΩ ~ 50 kΩ ±1% resistor, as specified in the specification, must be connected to this ball to ensure proper
operation.
(1) For MMC1_CLK signal to work properly, the RXACTIVE bit of the CTRLMMR_PADCONFIG171 register should be set to 0x1 because
of retiming purposes.
(2) For ROM boot from MMC1 interface to work properly, the MMC1_SDCD pin should be pulled low externally with a resistor to indicate
an SD Card/Memory device is present.
(1) For MMC2_CLK signal to work properly, the RXACTIVE bit of the CTRLMMR_PADCONFIG172 register should be set to 0x1 because
of retiming purposes.
(2) For MMC2 module to work properly, the MMC2_SDCD pin should be pulled low to indicate an SD Card/Memory device is present.
5.3.21 CPTS
Note
Some CPTS signals are connected directly to CPTS modules within the device. Other CPTS signals
are connected to the Time Sync Router and fanned out to peripherals linked to the router. Input
signals are sent to the peripherals while output signals are sourced from the peripherals. For more
information, see the Time Sync and Compare Events section in the Time Sync chapter in the device
TRM.
5.3.22 UFS
5.3.22.1 MAIN Domain
Table 5-92. UFS0 Signal Descriptions
PIN TYPE
SIGNAL NAME [1] DESCRIPTION [2] BALL [4]
[3]
UFS0_REF_CLK UFS Reference Clock O AE6
UFS0_RSTn UFS Reset Out O AD6
UFS0_RX_DN0 UFS Lane 0 Differential Receive Data (negative) I AH3
UFS0_RX_DP0 UFS Lane 0 Differential Receive Data (positive) I AJ2
UFS0_RX_DN1 UFS Lane 1 Differential Receive Data (negative) I AH4
UFS0_RX_DP1 UFS Lane 1 Differential Receive Data (positive) I AJ3
UFS0_TX_DN0 UFS Lane 0 Differential Transmit Data (negative) O AG6
UFS0_TX_DP0 UFS Lane 0 Differential Transmit Data (positive) O AF7
UFS0_TX_DN1 UFS Lane 1 Differential Transmit Data (negative) O AG5
UFS0_TX_DP1 UFS Lane 1 Differential Transmit Data (positive) O AF6
5.3.24 MCASP
5.3.24.1 MAIN Domain
Table 5-95. MCASP0 Signal Descriptions
PIN TYPE
SIGNAL NAME [1] DESCRIPTION [2] BALL [4]
[3]
MCASP0_ACLKR MCASP Receive Bit Clock IO AE27
MCASP0_ACLKX MCASP Transmit Bit Clock IO AB26
MCASP0_AFSR MCASP Receive Frame Sync IO AD26
MCASP0_AFSX MCASP Transmit Frame Sync IO AB25
MCASP0_AXR0 MCASP Serial Data (Input/Output) IO AF28
MCASP0_AXR1 MCASP Serial Data (Input/Output) IO AE28
MCASP0_AXR2 MCASP Serial Data (Input/Output) IO AD25
MCASP0_AXR3 MCASP Serial Data (Input/Output) IO AC29
MCASP0_AXR4 MCASP Serial Data (Input/Output) IO AE26
5.3.25 DSS
5.3.25.1 MAIN Domain
Table 5-107. DSS0 Signal Descriptions
PIN TYPE
SIGNAL NAME [1] DESCRIPTION [2] BALL [4]
[3]
DSS_FSYNC0 Video Output Frame Sync 0 O AH27, Y26
DSS_FSYNC1 Video Output Frame Sync 1 O AD19, AH28
DSS_FSYNC2 Video Output Frame Sync 2 O AA27, AH29
DSS_FSYNC3 Video Output Frame Sync 3 O AG27, Y24
VOUT0_DE Video Output Data Enable O AC22
VOUT0_EXTPCLKIN Video Output External Pixel Clock Input I AH21
VOUT0_HSYNC Video Output Horizontal Sync O AJ26
VOUT0_PCLK Video Output Pixel Clock Output O AH22
VOUT0_VSYNC Video Output Vertical Sync O AJ22
VOUT0_DATA0 Video Output Data 0 O AE22
VOUT0_DATA1 Video Output Data 1 O AG23
VOUT0_DATA2 Video Output Data 2 O AF23
VOUT0_DATA3 Video Output Data 3 O AD23
VOUT0_DATA4 Video Output Data 4 O AH24
VOUT0_DATA5 Video Output Data 5 O AG21
VOUT0_DATA6 Video Output Data 6 O AE23
VOUT0_DATA7 Video Output Data 7 O AC21
VOUT0_DATA8 Video Output Data 8 O Y23
VOUT0_DATA9 Video Output Data 9 O AF21
VOUT0_DATA10 Video Output Data 10 O AB23
VOUT0_DATA11 Video Output Data 11 O AJ25
VOUT0_DATA12 Video Output Data 12 O AH25
5.3.26 DP
5.3.26.1 MAIN Domain
Note
DP0_TX functionality is available on the SERDES pins. For more information, refer to Section 5.3.16,
SERDES.
(1) An external 500 Ω ±1% resistor must be connected between this pin and VSS, even when the pin is unused.
(2) CSI TX functionally is available on the DSI pins. For more information, refer to Section 5.3.28, DSI_TX.
(1) An external 500 Ω ±1% resistor must be connected between this pin and VSS, even when the pin is unused.
5.3.28 DSI_TX
5.3.28.1 MAIN Domain
Table 5-111. DSI_TX0 Signal Descriptions
(1) PIN TYPE
SIGNAL NAME [1] DESCRIPTION [2] BALL [4]
[3]
DSI_TXCLKN DSI Differential Transmit Clock Output (positive) O E10
DSI_TXCLKP DSI Differential Transmit Clock Output (negative) O E11
DSI_TXN0 DSI Differential Transmit Output (negative) IO D11
DSI_TXP0 DSI Differential Transmit Output (positive) IO C12
DSI_TXN1 DSI Differential Transmit Output (negative) O D12
DSI_TXP1 DSI Differential Transmit Output (positive) O C13
DSI_TXN2 DSI Differential Transmit Output (negative) O B13
DSI_TXP2 DSI Differential Transmit Output (positive) O A14
DSI_TXN3 DSI Differential Transmit Output (negative) O B14
DSI_TXP3 DSI Differential Transmit Output (positive) O A15
(2) DSI pin connected to external resistor for on-chip resistor
DSI_TXRCALIB A F12
calibration
(1) The functionality of these pins is controlled by CTRLMMR_DPHY_TX0_CTRL[1:0] LANE_FUNC_SEL. 0x0 = DSI PPI, 0x1 = CSI0 TX.
(2) An external 500 Ω ±1% resistor must be connected between this pin and VSS, even when the pin is unused.
5.3.29 VPFE
5.3.29.1 MAIN Domain
Table 5-112. VPFE0 Signal Descriptions
PIN TYPE
SIGNAL NAME [1] DESCRIPTION [2] BALL [4]
[3]
VPFE0_FIELD Video Input Field Indicator I AG23
VPFE0_HD Video Input Horizontal Sync I AE22
VPFE0_PCLK Video Input Pixel Clock I AH21
VPFE0_VD Video Input Vertical Sync I AF23
VPFE0_WEN Video Input Write Enable I AD23
VPFE0_DATA0 Video Input Data I AF24
VPFE0_DATA1 Video Input Data I AJ24
VPFE0_DATA2 Video Input Data I AG24
VPFE0_DATA3 Video Input Data I AD24
VPFE0_DATA4 Video Input Data I AC24
VPFE0_DATA5 Video Input Data I AE24
VPFE0_DATA6 Video Input Data I AJ21
VPFE0_DATA7 Video Input Data I AE21
VPFE0_DATA8 Video Input Data I AG25
VPFE0_DATA9 Video Input Data I AJ27
VPFE0_DATA10 Video Input Data I AC22
VPFE0_DATA11 Video Input Data I AD19
VPFE0_DATA12 Video Input Data I AD18
5.3.30 DMTIMER
5.3.30.1 MAIN Domain
Table 5-113. DMTIMER Signal Descriptions
PIN TYPE
SIGNAL NAME [1] DESCRIPTION [2] BALL [4]
[3]
Timer Inputs and Outputs (not tied to single timer
TIMER_IO0 IO P24, V6
instance)
Timer Inputs and Outputs (not tied to single timer
TIMER_IO1 IO R24, V5
instance)
Timer Inputs and Outputs (not tied to single timer
TIMER_IO2 IO AD23, P23
instance)
Timer Inputs and Outputs (not tied to single timer
TIMER_IO3 IO AH24, R28
instance)
Timer Inputs and Outputs (not tied to single timer
TIMER_IO4 IO AG21, T27
instance)
Timer Inputs and Outputs (not tied to single timer
TIMER_IO5 IO AE23, T24
instance)
Timer Inputs and Outputs (not tied to single timer
TIMER_IO6 IO AC2, T26
instance)
Timer Inputs and Outputs (not tied to single timer
TIMER_IO7 IO AB1, T25
instance)
Note
BOOTMODE pins are latched on the rising edge of PORz_OUT.
(1) These signals must be connected to VSS through a separate external pull resistor to ensure these balls are held to a valid logic low
level.
Note
MCU_BOOTMODE pins are latched on the rising edge of MCU_PORz_OUT.
5.3.32.2 Clock
5.3.32.2.1 MAIN Domain
Table 5-119. Clock1 Signal Descriptions
PIN TYPE
SIGNAL NAME [1] DESCRIPTION [2] BALL [4]
[3]
OSC1_XI High frequency oscillator input I P29
OSC1_XO High frequency oscillator output O P27
5.3.32.3 System
5.3.32.3.1 MAIN Domain
Table 5-121. System0 Signal Descriptions
PIN TYPE
SIGNAL NAME [1] DESCRIPTION [2] BALL [4]
[3]
External clock routed to ATL or MCASP as one of the
AUDIO_EXT_REFCLK0 selectable input clock sources, or as a output clock IO AD22
output for ATL or MCASP
External clock routed to ATL or MCASP as one of the
AUDIO_EXT_REFCLK1 selectable input clock sources, or as a output clock IO AE20
output for ATL or MCASP
External clock routed to ATL or MCASP as one of the
AUDIO_EXT_REFCLK2 selectable input clock sources, or as a output clock IO W26
output for ATL or MCASP
External clock routed to ATL or MCASP as one of the
AUDIO_EXT_REFCLK3 selectable input clock sources, or as a output clock IO W25
output for ATL or MCASP
EXTINTn External Interrupt I AC18
External clock input to MAIN domain, routed to Timer
clock muxes as one of the selectable input clock
EXT_REFCLK1 I U3
sources for Timer/WDT modules, or as reference clock
to MAIN_PLL2 (PER1 PLL)
Observation clock output for test and debug purposes
OBSCLK0 O V5
only
Observation clock output for test and debug purposes
OBSCLK1 O AB24
only
Observation clock output for test and debug purposes
OBSCLK2 O AD21
only
PORz_OUT MAIN domain POR status output O U1
RESETSTATz MAIN domain warm reset status output O T6
SOC_SAFETY_ERRORn Error signal output from MAIN domain ESM IO U4
SYSCLK0 output from MAIN PLL controller (divided by 6)
SYSCLKOUT0 O V6
for test and debug purposes only
Voltage Monitor for System supply, requires External
VMON_ER_VSYS A M26
Resistor divider
Voltage Monitor for External 1.8V supply, uses Internal
VMON_IR_VEXT A V19
Resistor divider
5.3.32.4 EFUSE
Table 5-123. EFUSE Signal Description
PIN TYPE
SIGNAL NAME [1] DESCRIPTION [2] BALL [4]
[3]
(1)
VPP_CORE Programming voltage for MAIN Domain efuses PWR AB11
(1)
VPP_MCU Programming voltage for MCU Domain efuses PWR F17
(1) This signal is valid only for High-Security devices. For more details, see Section 6.7, VPP Specification for One-Time Programmable
(OTP) eFUSEs. For General-Purpose devices do not connect any signal, test point, or board trace to this signal.
Note
All power balls must be supplied with the voltages specified in Section 6.4, Recommended Operating
Conditions, unless otherwise specified in Section 5.3, Signal Descriptions.
(1) This pin must always be connected via a 1-μF ±10% capacitor to VSS.
Note
When a pad is set into a pin multiplexing mode which is not defined, that pad’s behavior is undefined. This should be avoided.
Note
Table 5-125, Pin Multiplexing does not include SerDes signal functions. For more information, refer to the Serializer/Deserializer (SerDes)
chapter in the device TRM.
Note
Table 5-125, Pin Multiplexing does not include DPHY_TX signal functions. For more information, refer to the Shared D-PHY Transmitter
(DPHY_TX) chapter in the device TRM.
For more information on the I/O cell configurations, see Pad Configuration Registers section in Device Configuration chapter in the device TRM.
Table 5-125. Pin Multiplexing
BALL MUXMODE[14:0] SETTINGS
REGISTER
ADDRESS NUMB
NAME 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Bootstrap
ER
0x00011C2 PADCONFIG165 AD1 MLB0_ML GPIO1_30
94 BSP
0x00011C2 PADCONFIG167 AC3 MLB0_ML GPIO1_32
9C BDP
0x00011C2 PADCONFIG164 U6 USB0_DR USB1_DR GPIO1_29
90 VVBUS VVBUS
0x00011C2 PADCONFIG166 AC1 MLB0_ML GPIO1_31
98 BSN
0x00011C2 PADCONFIG168 AD3 MLB0_ML GPIO1_33
A0 BDN
0x00011C2 PADCONFIG169 AD2 MLB0_ML GPIO1_34
A4 BCP
Note
All power balls must be supplied with the voltages specified in Section 6.4, Recommended Operating
Conditions, unless otherwise specified in Section 5.3, Signal Descriptions.
Note
MMC1_SDCD and MMC2_SDCD must be pulled down for respective MMC modules to work properly
as a boot source.
(1) To determine which power supply is associated with any IO refer to Table 5-1, Pin Attributes.
Note
All other unused signal balls without Pad Configuration Register can be left unconnected.
Note
All other unused signal balls with a Pad Configuration Register can be left unconnected with their
multiplexing mode set to GPIO input and internal pulldown resistor enabled.
Unused balls are defined as those which only connect to a PCB solder pad. This is the only use case
where internal pull resistors are allowed as the only source/sink to hold a valid logic level.
Any balls connected to a via, test point, or PCB trace are considered used and must not depend on
the internal pull resistor to hold a valid logic level.
Internal pull resistors are weak and may not source enough current to maintain a valid logic level for
some operating conditions. This may be the case when connected to components with leakage to the
opposite logic level, or when external noise sources couple to signal traces attached to balls which
are only pulled to a valid logic level by the internal resistor. Therefore, external pull resistors may be
required to hold a valid logic level on balls with external connections.
If balls are allowed to float between valid logic levels, the input buffer may enter a high-current state
which could damage the IO cell.
6 Specifications
IO supply voltage +
Steady State Max. Voltage at all other IO pins(3) All other IO pins –0.3 V
0.3
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Section 6.4, Recommended
Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to their associated VSS or VSSA_x, unless otherwise noted.
(3) This parameter applies to all IO pins which are not fail-safe and the requirement applies to all values of IO supply voltage. For
example, if the voltage applied to a specific IO supply is 0 volts the valid input voltage range for any IO powered by that supply will be
–0.3 to +0.3 volts. Special attention should be applied anytime peripheral devices are not powered from the same power sources used
to power the respective IO supply. It is important the attached peripheral never sources a voltage outside the valid input voltage range,
including power supply ramp-up and ramp-down sequences.
(4) For current pulse injection:
Pins stressed per JEDEC JESD78E (Class II) and passed with specified I/O pin injection current and clamp voltage of 1.5 times
maximum recommended I/O voltage and negative 0.5 times maximum recommended I/O voltage.
For overvoltage performance:
Supplies stressed per JEDEC JESD78E (Class II) and passed specified voltage injection.
(5) For tape and reel the storage temperature range is [–10°C; +50°C] with a maximum relative humidity of 70%. TI recommends returning
to ambient room temperature before usage.
(6) VDD is the voltage on the corresponding power-supply pin(s) for the IO.
(7) An external resistor divider is required to create the VMON input value that triggers with VTH = 0.45 when the VSYS level reaches the
minimum allowed threshold. A series resistor R2 (VMON_ER_VSYS = VSYS × R1 / (R1 + R2)) of at least 10kΩ is recommended to limit
current.
(8) The VMON_ER_VSYS pin provides a way to monitor the system power supply. For more information, see Section 8.3.5 System Power
Supply Monitor Design Guidelines.
(9) An external resistor divider is required to limit the voltage applied to this device pin. For more information, see Section 8.3.4, USB
VBUS Design Guidelines.
Fail-safe IO terminals are designed such they do not have dependencies on the respective IO power supply
voltage. This allows external voltage sources to be connected to these IO terminals when the respective IO
power supplies are turned off. The I2C0_SCL, I2C0_SDA, I2C1_SCL, I2C1_SDA, DDR_FS_RESETn, NMIn,
VMON_ER_VSYS, and VMON_IR_VEXT are the only fail-safe IO terminals. All other IO terminals are not
fail-safe and the voltage applied to them should be limited to the value defined by the Steady State Max. Voltage
at all IO pins parameter in Section 6.1.
Tperiod
Tundershoot
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
(1) This information is provided solely for your convenience and does not extend or modify the warranty provided under TI's standard
terms and conditions for TI semiconductor products.
(2) Unless specified in the table above, all voltage domains and operating conditions are supported in the device at the noted
temperatures.
(3) POH is a function of voltage, temperature and time. Usage at higher voltages and temperatures will result in a reduction in POH.
(4) Automotive profile is defined as 20000 power on hours with a junction temperature as follows: 5%@-40°C, 65%@70°C, 20%@110°C,
and 10%@125°C.
(1) The voltage at the device ball must never be below the MIN voltage or above the MAX voltage for any amount of time. This
requirement includes dynamic voltage events such as AC ripple, voltage transients, voltage dips, and so forth.
(2) VDDS_DDR is required to still be powered with LPDDR4 voltage ranges, even If DDR interface is unused.
(3) This terminal is connected to analog circuits in the respective USB PHY. The circuit sources a known current while measuring the
voltage to determine if the terminal is connected to VSS with a resistance less than 10 Ω or greater than 100 kΩ. The terminal should
be connected to ground for USB host operation or open-circuit for USB peripheral operation, and should never be connected to any
external voltage source.
(4) The AVS Voltages are device-dependent, voltage domain-dependent, and OPP-dependent. They must be read from the
VTM_DEVINFO_VDn. For information about VTM_DEVINFO_VDn Registers address, please refer to Voltage and Thermal Manager
section in the device TRM. The power supply should be adjustable over the ranges shown in the VDD_CPU AVS Range entry.
(5) An external resistor divider is required to limit the voltage applied to this device pin. For more information, see Section 8.3.4, USB
VBUS Design Guidelines.
(1) Maximum DDR Frequency is limited based on the specific memory type (vendor) used in a system and by PCB implementation. TI
strongly recommends that all designs follow the TI LPDDR4 EVM PCB layout exactly in every detail (routing, spacing, vias/backdrill,
PCB material, and so forth) in order to achieve the full specified clock frequency. For details, see the Jacinto 7 LPDDR4 Board Design
and Layout Guidelines.
(1) VDDSHV stands for corresponding power supply. For more information on the power supply name and the corresponding ball, see
Section 5.2, Pin Attributes, POWER column.
(2) The IOL parameter defines the minimum Low Level Output Current for which the device is able to maintain the specified VOL value.
The value defined by this parameter should be considered the maximum current available to a system implementation which needs to
maintain the specified VOL value for attached components.
(3) f = toggle frequency of the input signal in Hz.
(4) This MIN parameter only applies to input signal functions which are not defined in their respective Timing and Switching
Characteristics sections. Select the MIN parameter which results in the largest value.
(5) I2C Hs-mode is not supported, when operating the IO in 3.3-V mode.
(1) VDDSHV stands for corresponding power supply. For more information on the power supply name and the corresponding ball, see
Section 5.2, Pin Attributes, POWER column.
(1) VDDSHV stands for corresponding power supply. For WKUP_OSC0, the corresponding power supply is VDDA_WKUP. For OSC1_XI,
the corresponding power supply is VDDS_OSC1.
(1) VDDSHV stands for corresponding power supply (vddshv8). For more information on the power supply name and the corresponding
ball, see Section 5.2, Pin Attributes, POWER column.
(1) VDDSHV stands for corresponding power supply (vddshv8). For more information on the power supply name and the corresponding
ball, see Section 5.2, Pin Attributes, POWER column.
(2) f = toggle frequency of the input signal in Hz.
(3) This MIN parameter only applies to input signal functions which are not defined in their respective Timing and Switching
Characteristics sections. Select the MIN parameter which results in the largest value.
Note
CSI-2/DSI (D-PHY) interfaces are compliant with MIPI D-PHY specifications v1.2 dated August 1,
2014, including ECNs and Errata as applicable.
(1) MCU_ADC0/1 can be configured to operate in General Purpose Input mode, where all MCU_ADC0/1_AIN[7:0] inputs are globally
enabled to operate as digital inputs via the ADC0/1_CTRL register (gpi_mode_en = 1).
Only GPIO mode supported. Over operating free-air temperature range (unless otherwise noted)
TEST
PARAMETER MIN TYP MAX UNIT
CONDITIONS
VIH Input High Voltage 0.7 × VDD(1) V
VIHSS Input High Voltage Steady State 0.75 × VDD(1) V
VHYS Input Hysteresis Voltage 80 mV
IIN Input Leakage Current VI = 1.8 V or 0 V ±10 µA
RPD Pull-down Resistor 20 53 130 kΩ
VOL Output Low Voltage 0.2 V
VOH Output High Voltage VDD(1) - 0.2 V
IOL Low Level Output Current VOL(MAX) 6 mA
IOH High Level Output Current VOH(MIN) 6 mA
fop > 100 MHz 1 V/ns
SRI Input Slew Rate(2)
fop < 1 MHz 10 V/ns
(1) VDD stands for corresponding power supply. For more information on the power supply name and the corresponding ball, see Section
5.2, Pin Attributes, POWER column.
(2) Slew rate may be further limited, reference Section 6.9 for actual slew rate during operation.
(1) VDD stands for corresponding power supply. For more information on the power supply name and the corresponding ball, see Section
5.2, Pin Attributes , POWER column.
(2) The IOL and IOH parameters define the minimum Low Level Output Current and High Level Output Current for which the device is
able to maintain the specified VOL and VOH values. Values defined by these parameters should be considered the maximum current
available to a system implementation which needs to maintain the specified VOL and VOH values for attached components.
(3) f = toggle frequency of the input signal in Hz.
(4) This MIN parameter only applies to input signal functions which are not defined in their respective Timing and Switching
Characteristics sections. Select the MIN parameter which results in the largest value.
Note
USB0 and USB1 Electrical Characteristics are compliant with Universal Serial Bus Revision 2.0
Specification dated April 27, 2000 including ECNs and Errata as applicable.
Note
The PCIe interfaces are compliant with the electrical parameters specified in PCI Express® Base
Specification Revision 4.0, September 27, 2017.
This Device imposes an additional limit on SERDES REFCLK when used in Input mode with internal
termination enabled, as described by parameter VREFCLK_TERM in Table 6-2, 4-L-PHY SERDES
REFCLK Electrical Characteristics. Internal termination is enabled by default and must be disabled
before applying a reference clock signal that exceeds the limits defined by VREFCLK_TERM. External
termination should always be enabled on the source side.
Note
The SerDes USB interfaces are compliant with the USB3.1 SuperSpeed Transmitter and Receiver
Normative Electrical Parameters as defined in the Universal Serial Bus 3.1 Specification, Revision
1.0 , July 26, 2013.
Note
The SGMII interfaces electrical characteristics are compliant with 1000BASE-KX per IEEE802.3
Clause 70.
Note
The SGMII 2.5G / XAUI interfaces electrical characteristics are compliant with IEEE802.3 Clause 47.
Note
The QSGMII interface electrical characteristics are compliant with QSGMII Specification revision 1.2.
This Device imposes an additional limit on the 2-L-PHY SERDES REFCLK, as described by parameters VIDTH
and VIDTL in Table 6-3, 2-L-PHY SERDES REFCLK Electrical Characteristics.
Note
The UFS interface electrical characteristics are compliant with MIPI M-PHY Specification v3.1,
February 17, 2014.
Note
The DP interface electrical characteristics are compliant with the VESA DisplayPort (DP) Standard v
1.4 February 23, 2016.
Note
The eDP interface electrical characteristics are compliant with the VESA Embedded DisplayPort
(eDP) Standard v1.4b October 23, 2015.
Note
The DDR interface is compatible with JESD209-4B standard compliant LPDDR4 SDRAM devices.
(1) Supply voltage range includes DC errors and peak-to-peak noise. TI power management solutions TLV70018-Q1 from the TLV707x
family meet the supply voltage range needed for VPP_CORE and VPP_MCU.
(1) These values are based on a JEDEC defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on
a JEDEC defined 1S0P system) and will change based on environment as well as application. For more information, see these
EIA/JEDEC standards:
• JESD51-2, Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air)
• JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-6, Integrated Circuit Thermal Test Method Environmental Conditions - Forced Convection (Moving Air)
• JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-9, Test Boards for Area Array Surface Mount Packages
(2) m/s = meters per second.
(3) °C/W = degrees Celsius per watt.
Supply value
t
Slew Rate = ∆V / ∆T
Max Slew Rate < 100 mV / µs or 0.1 V / 1E(-6)s = 1E(+5) V / s
SPRSP08_ELCH_06
VDD_CPU
(10)
VDDA_0P8_PLL_DDR, VDDA_0P8_DLL_MMC0, VDDA_0P8_PLL_MLB
(8)
VDD_MCU , VDD_CORE, (VDDA_0P8_SERDES0_1,
VDDA_0P8_SERDES2_3, VDDA_0P8_SERDES_C0_1,
VDDA_0P8_SERDES_C2_3, VDDA_0P8_DP, VDDA_0P8_DP_C,
VDDA_0P8_CSIRX, VDDA_0P8_UFS, VDDA_0P8_USB,
(9)
VDDA_0P8_DSITX, VDDA_0P8_DSITX_C)
(8)
VDD_MCU , VDDAR_CORE, VDDAR_CPU, VDDAR_MCU
WKUP_OSC0_XI, WKUP_OSC1_XO
WKUP_LFOSC0_XI, WKUP_LFOSC0_XO
(optional)
OSC1_XI, OSC1_XO
(optional)
MCU_BOOTMODE[9:0], BOOTMODE[7:0]
(11) Valid Configuration
(11)(12)
PORz, MCU_PORz
J7ES_ELCH_01
Figure 6-3. Combined MCU and Main Domains, Primary Power-Up Sequence
rates with fixed 3.3V operation is acceptable, then domain can be grouped with digital IO 3.3V power rail. If a
SD card is capable of operating with fixed 1.8V, then domain can be grouped with digital IO 1.8V power rail.
5. VDDA_3P3_USB is 3.3V analog domain used for USB 2.0 differential interface signaling. A low noise,
analog supply is recommended to provide best signal integrity for USB data eye mask compliance. The start
of ramp-up to 3.3V will be same as other 3.3V domains as shown. If USB interface is not needed or data bit
errors can be tolerated, then domain can be grouped with 3.3V digital IO power rail either directly or through
a supply filter.
6. VDDA_1P8_<phy> are 1.8V analog domains supporting multiple serial PHY interfaces. A low noise, analog
supply is recommended to provide best signal integrity, interface performance and spec compliance. If any of
these interfaces are not needed, data bit errors or non-compliant operation can be tolerated, then domains
can be grouped with digital IO 1.8V power rail either directly or through an in-line supply filter is allowed.
7. VDD_MMC0 is 1.8V digital supply supporting MMC0 signaling for eMMC interface. If MMC0 or eMMC0
interface is not needed, then domain can be grouped with digital IO 1.8V power rail with power up time
stamp at T1. However, if MMC0 interface is needed, then VDD_MMC0 must not start ramp-up until time
stamp T3 after VDD_CORE has reached VOPR MIN. Any MCU or Main dual voltage IO operating at 1.8V can
be grouped with VDD_MMC0 into a common power rail with power up time stamp T3.
8. VDD_MCU is a digital voltage supply with a wide operational voltage range and power sequencing flexibility,
enabling it to be grouped and ramped-up with either 0.8V VDD_CORE at time stamp T2 or 0.85V RAM array
domains (VDDAR_xxx) at time stamp T3.
9. VDDA_1P8_<clk/pll/ana> are 1.8V analog domains supporting clock oscillator, PLL and analog circuitry
needing a low noise supply for optimal performance. It is not recommended to combine analog
VDDA_1P8_<phy> domains or digital VDDSHVn_MCU and VDDSHVn IO domains since high frequency
switching noise could negatively impact jitter performance of clock, PLL and DLL signals.
10. VDDA_0P8_<dll/pll> are 0.8V analog domains supporting PLL and DLL circuitry needing a low noise supply
for optimal performance. It is not recommended to combine these domains with any other 0.8V domains
since high frequency switching noise could negatively impact jitter performance of PLL and DLL signals.
11. Minimum set-up and hold times shown with respect to MCU_PORz and PORz asserting high to latch
MCU_BOOTMODEn (referenced to MCU_VDDSHV0) and BOOTMODEn (reference to VDDSHV2) settings
into registers during power up sequence.
12. Minimum elapsed time from crystal oscillator circuitry being energized (VDDS_OSC1 at T1) until stable clock
frequency is reached depends upon on crystal oscillator, capacitor parameters and PCB parasitic values.
A conservative 10ms elapsed time defined by (T4 – T1) time stamps is shown. This could be reduced
depending upon customer’s clock circuit (that is, crystal oscillator or clock generator) and PCB designs.
6.9.2.3 Combined MCU and Main Domains Power- Down Sequencing
Figure 6-4 describes the device power-down sequencing.
T0 T1 T2 T3 T4
VDD_CPU
(8)
VDD_MCU ,VDDAR_CORE, VDDAR_MCU, VDDAR_CPU
OSC1_XI, OSC1_XO
WKUP_OSC0_XI, WKUP_OSC0_XO
(optional)
WKUP_LFOSC0_XI, WKUP_LFOSC0_XO
(optional)
MCU_BOOTMODE[9:0], BOOTMODE[7:0]
(10)
PORz, MCU_PORz TΔ1
J7ES_ELCH_02
Figure 6-4. Combined MCU and Main Domains, Primary Power-Down Sequence
4. VDDSHV5 supports MMC1 signaling for SD memory cards. A dual voltage (3.3V/1.8V) power rail is required
for compliant, high-speed SD card operations. If compliant highspeed SD card operation is needed, then
an independent, dual voltage (3.3V/1.8V) power source and rail are required. The start of ramp-down from
3.3V/1.8V will be same as other 3.3V domains as shown. If SD card is not needed or standard data rates
with fixed 3.3V operation is acceptable, then domain can be grouped with digital IO 3.3V power rail. If a SD
card is capable of operating with fixed 1.8V, then domain can be grouped with digital IO 1.8V power rail.
5. VDDA_3P3_USB is 3.3V analog domain used for USB 2.0 differential interface signaling. A low noise,
analog supply is recommended to provide best signal integrity for USB data eye mask compliance. The start
of ramp-down from 3.3V will be same as other 3.3V domains as shown. If USB interface is not needed or
data bit errors can be tolerated, then domain can be grouped with 3.3V digital IO power rail either directly or
through a supply filter.
6. VDDA_1P8_<phy> are 1.8V analog domains supporting multiple serial PHY interfaces. A low noise, analog
supply is recommended to provide best signal integrity, interface performance and spec compliance. If any of
these interfaces are not needed, data bit errors or non-compliant operation can be tolerated, then domains
can be grouped with digital IO 1.8V power rail either directly or through an in-line supply filter is allowed.
7. VDD_MMC0 is 1.8V digital supply supporting MMC0 signaling for eMMC interface and must ramp-down at
time stamp T1 before VDD_CORE starts ramp-down. Any MCU or Main dual voltage IO operating at 1.8V
can be grouped with VDD_MMC0 into a common power rail with power down time stamp T1. If MMC0 or
eMMC0 interface is not needed, then domain can be grouped with digital IO 1.8V power rail and ramp-down
at time stamp T3.
8. VDD_MCU is a digital voltage supply with a wide operational voltage range and power sequencing flexibility,
enabling it to be grouped and ramped-down with either 0.8V VDD_CORE at time stamp T2 or 0.85V RAM
array domains (VDDAR_xxx) at time stamp T1.
9. VDDA_1P8_<clk/pll/ana> are 1.8V analog domains supporting clock oscillator, PLL and analog circuitry
needing a low noise supply for optimal performance. It is not recommended to combine analog
VDDA_1P8_<phy> domains or digital VDDSHVn_MCU and VDDSHVn IO domains since high frequency
switching noise could negatively impact jitter performance of clock, PLL and DLL signals.
10. MCU_PORz and PORz must be asserted low for TΔ1 = 200us min to ensure SoC resources enter into safe
state before any voltage begins to ramp down.
6.9.2.4 Isolated MCU and Main Domains Power- Up Sequencing
Isolated MCU and Main voltage domains enable an SoC’s MCU and Main processor sub-systems to operate
independently. There are 2 reasons an SoC’s PDN design may need to support independent MCU and Main
processor functionality. First is to provide flexibility to enable SoC low power modes that can significant reduce
SoC power dissipation when processor operations are not needed. Second is to enable robustness to gain
freedom from interference (FFI) of a single fault impacting both MCU and Main processor sub-systems which
is especially beneficial if using the SoC’s MCU as the system safety monitoring processor. The number of
additional PDN power rails needed is dependent upon number of different MCU IO signaling voltage levels.
If only 1.8V IO signaling is used, the only 2 additional power rails could be required. If both 1.8 and 3.3V IO
signaling is desired, then 4 additional power rails could be needed. Table 8-2 in Section 8.1, Power Supply
Mapping captures recommended device power supplies to power rail mapping summary.
(3)
(VDDSHV0_MCU, VDDSHV1_MCU, VDDSHV2_MCU)
VDDS_OSC1, VDDA_PLLGRP0,
VDDA_PLLGRP1, VDDA_PLLGRP2,
VDDA_PLLGRP3, VDDA_PLLGRP4, VDDA_PLLGRP5,
VDDA_PLLGRP6, VDDA_TEMP0_1, VDDA_TEMP2_3,
(8)
VDD_MCU , VDDAR_MCU
VDD_CPU
(10)
VDDA_0P8_PLL_DDR, VDDA_0P8_DLL_MMC0, VDDA_0P8_PLL_MLB
VDDAR_CORE, VDDAR_CPU
OSC1_XI, OSC1_XO
WKUP_OSC0_XI, WKUP_OSC0_XO
(optional)
WKUP_LFOSC0_XI, WKUP_LFOSC0_XO
(optional)
MCU_BOOTMODE[9:0],BOOTMODE[7:0]
(10) Valid Configuration
(11)(12)
MCU_PORz
(11)(12)
PORz
J7ES_ELCH_03
Figure 6-5. Isolated MCU and Main Domains, Primary Power-Up Sequence
3. Any MCU or Main dual voltage IO supplies (VDDSHVn_MCU or VDDSHVn) being supplied by 1.8V to
support 1.8V digital interfaces. When eMMC memories are used, Main 1.8V supplies could have delayed
start times that aligns to T3 due to PDN designs grouping supplies with VDD_MMC0.
4. VDDSHV5 supports MMC1 signaling for SD memory cards. If compliant UHS-I SD card operation is needed,
then an independent, dual voltage (3.3V/1.8V) power source and rail are required. The start of ramp-up to
3.3V will be same as other 3.3V domains as shown. If SD card is not needed or standard data rates with
fixed 3.3V operation is acceptable, then supply can be grouped with digital IO 3.3V power rail. If a SD card is
capable of operating with fixed 1.8V, then supply can be grouped with digital IO 1.8V power rail.
5. VDDA_3P3_USB is 3.3V analog supply used for USB 2.0 differential interface signaling. A low noise, analog
supply is recommended to provide best signal integrity for USB data eye mask compliance. The start of
ramp-up to 3.3V will be same as other 3.3V domains as shown. If USB interface is not needed or data bit
errors can be tolerated, then supply can be grouped with 3.3V digital IO power rail either directly or through a
supply filter.
6. VDDA_1P8_<phy> are 1.8V analog supplies supporting multiple serial PHY interfaces. A low noise, analog
supply is recommended to provide best signal integrity, interface performance and spec compliance. If any
of these interfaces are not needed, data bit errors or non-compliant operation can be tolerated, then supplies
can be grouped with digital IO 1.8V power rail either directly or through an in-line supply filter is allowed.
7. VDD_MMC0 is 1.8V digital supply supporting MMC0 signaling for eMMC interface and must ramp up at
time stamp T3. Any MCU or Main dual voltage IO operating at 1.8V can be grouped with VDD_MMC0 into
a common power rail with a ramp-up at time stamp T3. If MMC0 or eMMC0 interface is not needed, then
domain can be grouped with digital IO 1.8V power rail with ramp-up at time stamp T1.
8. VDD_MCU is a digital voltage supply with a wide operational voltage range and power sequencing flexibility,
enabling it to be grouped and ramped-up with either 0.8V VDD_CORE at time stamp T2 or 0.85V RAM array
domains (VDDAR_xxx) at time stamp T3.
9. VDDA_1P8_<clk/pll/ana> are 1.8V analog supplies supporting clock oscillator, PLL and analog circuitry
needing a low noise supply for optimal performance. It is not recommended to combine analog
VDDA_1P8_<phy> domains or digital VDDSHVn_MCU and VDDSHVn IO domains since high frequency
switching noise could negatively impact jitter performance of clock, PLL and DLL signals.
10. VDDA_0P8_<dll/pll> are 0.8V analog supplies supporting PLL and DLL circuitry needing a low noise supply
for optimal performance. It is not recommended to combine these domains with any other 0.8V domains
since high frequency switching noise could negatively impact jitter performance of PLL and DLL signals.
11. Minimum set-up and hold times shown with respect to MCU_PORz and PORz asserting high to latch
MCU_BOOTMODEn (referenced to MCU_VDDSHV0) and BOOTMODEn (reference to VDDSHV2) settings
into registers during power up sequence.
12. Minimum elapsed time from crystal oscillator circuitry being energized (VDDS_OSC1 at T1) until stable clock
frequency is reached depends upon on crystal oscillator, capacitor parameters and PCB parasitic values.
A conservative 10ms elapsed time defined by (T4 – T1) time stamps is shown. This could be reduced
depending upon customer’s clock circuit (that is, crystal oscillator or clock generator) and PCB designs.
6.9.2.5 Isolated MCU and Main Domains, Primary Power- Down Sequencing
Figure 6-6 describes the device power-down sequencing.
T0 T1 T2 T3 T4
(2)
(VDDSHV0_MCU, VDDSHV1_MCU, VDDSHV2_MCU)
(3)
(VDDSHV0_MCU, VDDSHV1_MCU, VDDSHV2_MCU)
(8)
(VDD_MCU , VDDAR_MCU)
VDD_CPU
VDDAR_CORE, VDDAR_CPU
OSC1_XI, OSC1_XO
WKUP_OSC0_XI, WKUP_OSC0_XO
(optional)
WKUP_LFOSC0_XI, WKUP_LFOSC0_XO
(optional)
BOOTMODE[9:0],BOOTMODE[7:0]
(10)
MCU_PORz TΔ1
(10)
PORz
J7ES_ELCH_04
Figure 6-6. Isolated MCU and Main Domains, Primary Power- Down Sequencing
3. Any MCU or Main dual voltage IO supplies (VDDSHVn_MCU or VDDSHVn) being supplied by 1.8V to
support 1.8V digital interfaces. When eMMC memories are used, Main 1.8V supplies could have a ramp-
down aligned to T1 due to PDN designs grouping supplies with VDD_MMC0.
4. VDDSHV5 supports MMC1 signaling for SD memory cards. A dual voltage (3.3V/1.8V) power rail is required
for compliant, high-speed SD card operations. If compliant highspeed SD card operation is needed, then
an independent, dual voltage (3.3V/1.8V) power source and rail are required. The start of ramp-down from
3.3V/1.8V will be same as other 3.3V domains as shown. If SD card is not needed or standard data rates
with fixed 3.3V operation is acceptable, then domain can be grouped with digital IO 3.3V power rail. If a SD
card is capable of operating with fixed 1.8V, then domain can be grouped with digital IO 1.8V power rail.
5. VDDA_3P3_USB is 3.3V analog domain used for USB 2.0 differential interface signaling. A low noise,
analog supply is recommended to provide best signal integrity for USB data eye mask compliance. The start
of ramp-down from 3.3V will be same as other 3.3V domains as shown. If USB interface is not needed or
data bit errors can be tolerated, then domain can be grouped with 3.3V digital IO power rail either directly or
through a supply filter.
6. VDDA_1P8_<phy> are 1.8V analog domains supporting multiple serial PHY interfaces. A low noise, analog
supply is recommended to provide best signal integrity, interface performance and spec compliance. If any of
these interfaces are not needed, data bit errors or non-compliant operation can be tolerated, then domains
can be grouped with digital IO 1.8V power rail either directly or through an in-line supply filter is allowed.
7. VDD_MMC0 is 1.8V digital supply supporting MMC0 signaling for eMMC interface and must ramp-down at
time stamp T1 before VDD_CORE starts ramp-down. Any MCU or Main dual voltage IO operating at 1.8V
can be grouped with VDD_MMC0 into a common power rail with power down time stamp T1. If MMC0 or
eMMC0 interface is not needed, then domain can be grouped with digital IO 1.8V power rail and ramp-down
at time stamp T3.
8. VDD_MCU is a digital voltage supply with a wide operating voltage range and power sequencing flexibility,
enabling it to be grouped and ramped-down with either 0.8V VDD_CORE at time stamp T2 or 0.85V RAM
array domains (VDDAR_xxx) at time stamp T1.
9. VDDA_1P8_<clk/pll/ana> are 1.8V analog domains supporting clock oscillator, PLL & analog circuitry
needing a low noise supply for optimal performance. It is not recommended to combine analog
VDDA_1P8_<phy> domains or digital VDDSHVn_MCU and VDDSHVn IO domains since high frequency
switching noise could negatively impact jitter performance of clock, PLL and DLL signals.
10. MCU_PORz and PORz must be asserted low for TΔ1 = 200us min to ensure SoC resources enter into safe
state before any voltage begins to ramp down.
6.9.2.6 Entry and Exit of MCU Only State
Entry into MCU Only lower power state is accomplished by executing a power down sequence except
for the 4 MCU supply groups (VDDSHVx_MCU at 3.3V, VDDSHVx_MCU at 1.8V, VDDA_MCU_PLLGRP0/
VDDA_MCU_TEMP analog supplies at 1.8V, VDD_MCU/VDDAR_MCU at 0.85V) that remain energized. Exit
from MCU Only state is accomplished by executing a power up sequence with the 4 MCU supply groups
remaining energized throughout the sequence. The example diagram shown is for an Isolated MCU & Main PDN
type with eMMC support.
Active Entry into MCU only MCU only Exit from MCU only Active
T0 T1 T2 T3 T4
T0 T1 T2 T3 T4
(3)(5a)
VDDSHV0_MCU, VDDSHV1_MCU, VDDSHV2_MCU
(4)
VDDSHV0_MCU, VDDSHV1_MCU, VDDSHV2_MCU
VDDS_MMC0
VDDS_OSC1, VDDA_PLLGRP0,
VDDA_PLLGRP1, VDDA_PLLGRP2,
VDDA_PLLGRP3, VDDA_PLLGRP4, VDDA_PLLGRP5,
VDDA_PLLGRP6, VDDA_TEMP0_1, VDDA_TEMP2_3,
(7)
VDD_MCU, VDDAR_MCU
VDD_CPU
(7)
VDDAR_CORE, VDDAR_CPU, VDDAR_MCU
OSC1_XI, OSC1_XO
WKUP_OSC0_XI, WKUP_OSC0_XO
(optional)
WKUP_LFOSC0_XI, WKUP_LFOSC0_XO
(optional)
(9)
SYSBOOT[17:0] Valid Configuration
(9)(10)
MCU_PORz
(9)(10)
PORz
J7ES_ELCH_03
Active Entry into MCU only DDR Retention Exit from MCU only Active
T0 T1 T2 T3 T4
T0 T1 T2 T3 T4
(3)(5a)
VDDSHV0_MCU, VDDSHV1_MCU, VDDSHV2_MCU
(4)
VDDSHV0_MCU, VDDSHV1_MCU, VDDSHV2_MCU
VDDS_MMC0
VDDS_OSC1, VDDA_PLLGRP0,
VDDA_PLLGRP1, VDDA_PLLGRP2,
VDDA_PLLGRP3, VDDA_PLLGRP4, VDDA_PLLGRP5,
VDDA_PLLGRP6, VDDA_TEMP0_1, VDDA_TEMP2_3,
(7)
VDD_MCU, VDDAR_MCU
VDD_CPU
(7)
VDDAR_CORE, VDDAR_CPU, VDDAR_MCU
OSC1_XI, OSC1_XO
WKUP_OSC0_XI, WKUP_OSC0_XO
(optional)
WKUP_LFOSC0_XI, WKUP_LFOSC0_XO
(optional)
(9)
SYSBOOT[17:0] Valid Configuration
(9)(10)
MCU_PORz
(9)(10)
PORz
J7ES_ELCH_03
(1) For definition of the MCU DOMAIN supplies, see the Combined MCU and Main Domains Power-Up sequence.
(2) N = oscillator start-up time
RST1
RST2 RST3
MCU_PORz
MCU DOMAIN
SUPPLIES VALID
MCU_OSC0_XI,
MCU_OSC0_XO
1. For definition of the MAIN DOMAIN supplies, see the Combined MCU and Main Domains Power-Up
sequence.
RST4
RST5
PORz
MAIN DOMAIN
SUPPLIES VALID
RST12
RST13
MCU_PORz
RST6
RST7
RST14
MCU_PORz_OUT
RST10
RST11
RST16
MCU_RESETSTATz
RST8
RST9
RST15
PORz_OUT
RST17
RESETSTATz
RST18
RST19
PORz
PORz_OUT
RST20
RST21
RESETSTATz
(1) Timing for MCU_RESETz is valid only after all supplies are valid and MCU_PORz has been asserted for the specified time.
RST23
RST24
MCU_RESETz
RST22
MCU_RESETSTATz
RST25
RST26
RESETSTATz
Figure 6-13. MCU_RESETz initiates; MCU_RESETSTATz, and RESETSTATz Timing Requirements and
Switching Characteristics
(1) Timing for RESET_REQz is valid only after all supplies are valid and MCU_PORz has been asserted for the specified time.
RST27
RESET_REQz
RST28
RST29
RESETSTATz
Figure 6-14. RESET_REQz initiates; RESETSTATz Timing Requirements and Switching Characteristics
RST30
MCU_PORz
RST31
EMU[1:0]
RST32
MCU_PORz_OUT
MCU_BOOTMODE[09:00]
RST33
RST34
PORz_OUT
BOOTMODE[7:0]
RST35
SFTY1
SFTY2
MCU_SAFETY_ERRORn
(PWM Mode Disabled)
SFTY3
SFTY4
SOC_SAFETY_ERRORn
(PWM Mode Disabled)
CLK1
CLK2 CLK3
EXT_REFCLK1
CLK19
CLK20 CLK21
MCU_EXT_REFCLK0
CLK4
CLK5 CLK6
SYSCLKOUT0
CLK7
CLK8 CLK9
OBSCLK0
CLK10
CLK11 CLK12
CLKOUT0
CLK13
CLK14 CLK15
MCU_SYSCLKOUT0
CLK16
CLK17 CLK18
MCU_OBSCLK0
DEVICE
CLKOUT Reference clock output
WKUP_LFOSC0_XI External Low frequency crystal interface pins connected to internal oscillator
which provides a 32.768 KHz clock for low power operation
WKUP_LFOSC0_XO in deeper sleep modes.
OSC1_XI
External main crystal interface pins connected to internal oscillator
which provides reference clock to PLLs within MCU domain
OSC1_XO and MAIN domain.
MCU_RESETz/ RESET_REQz MCU Warm Reset Input / Device Warm Reset Input
MCU_BOOTMODE[09:00] MCU Boot Mode system clock speed and fail-safe boot device
PCIE_REFCLK[3:0]N/P There are 4 differential clock input/output pins to support PCIe devices
SERDES4_REFCLK_P/N SerDes reference clock input for PCIe or Optional USB3 and SGMII interfaces
MCU_OBSCLK0 / OBSCLK[2:0] Observation clock outputs for MCU Domain clock / MAIN Domain clocks
MCU_EXT_REFCLK0 / EXT_REFCLK1 Optional external System clock inputs - (MCU domain) / (MAIN domain)
J7ES_CLOCK_01
For more information about Input clock interfaces, see Clocking section in Device Configuration chapter in the
device TRM.
6.9.4.1.1 WKUP_OSC0 Internal Oscillator Clock Source
Figure 6-23 shows the recommended crystal circuit. All discrete components used to implement the oscillator
circuit should be placed as close as possible to the WKUP_OSC0_XI and WKUP_OSC0_XO pins.
Device
WKUP_OSC0_XI WKUP_OSC0_XO
Rd
Crystal (Optional)
(Optional) Rbias
Cf1 Cf2
PCB Ground
J7ES_WKUP_OSC_INT_02
The crystal must be in the fundamental mode of operation and parallel resonant. Table 6-21 summarizes the
required electrical constraints.
Table 6-21. WKUP_OSC0 Crystal Electrical Characteristics
PARAMETER MIN TYP MAX UNIT
Fxtal Crystal Parallel Resonance Frequency 19.2, 20, 24, 25, 26, 27 MHz
Fxtal Crystal Frequency Stability and Tolerance Ethernet RGMII and RMII ppm
±100
not used
Ethernet RGMII and RMII
±50
using derived clock
CL1+PCBXI Capacitance of CL1 + CPCBXI 12 24 pF
CL2+PCBXO Capacitance of CL2 + CPCBXO 12 24 pF
CL Crystal Load Capacitance 6 12 pF
Cshunt Crystal Circuit Shunt Capacitance ESRxtal = 30 Ω 19.2 MHz, 20 MHz, pF
24 MHz, 25 MHz, 26 MHz, 7
27 MHz
ESRxtal = 40 Ω 19.2 MHz, 20 MHz, pF
24 MHz, 25 MHz, 26 MHz, 5
27 MHz
ESRxtal = 50 Ω 19.2 MHz, 20 MHz, pF
24 MHz, 25 MHz, 26 MHz, 5
27 MHz
ESRxtal = 60 Ω 19.2 MHz, 20 MHz, 24 MHz 5 pF
ESRxtal = 80 Ω 19.2 MHz, 20 MHz 5 pF
25 MHz 3 pF
ESRxtal = 100 Ω 19.2 MHz, 20 MHz 3 pF
When selecting a crystal, the system design must consider the temperature and aging characteristics of a based
on the worst case environment and expected life expectancy of the system.
Table 6-22 details the switching characteristics of the oscillator and the requirements of the input clock.
Table 6-22. WKUP_OSC0 Switching Characteristics – Crystal Mode
PARAMETER MIN TYP MAX UNIT
CXI XI Capacitance 1.55 pF
CXO XO Capacitance 1.35 pF
CXIXO XI to XO Mutual Capacitance 0.1 pF
ts Maximum Start-up Time 9.5(1) ms
(1) TI strongly encourages each customer to submit samples of the device to the resonator/crystal vendors for validation. The
vendors are equipped to determine what load capacitors will best tune their resonator/crystal to the microcontroller device
for optimum startup and operation over temperature/voltage extremes.
VDD_WKUP (min.)
VDD_WKUP
VSS
Voltage
VSS WKUP_OSC0_XO
tsX
Time
J7ES_WKUP_OSC_STARTUP_04
Device
Crystal Circuit PCB
Components Signal Traces
WKUP_OSC0_XI
WKUP_OSC0_XO
J7ES_WKUP_OSC_CC_05
Load capacitors, CL1 and CL2 in Figure 6-23, should be chosen such that the below equation is satisfied. CL in
the equation is the load specified by the crystal manufacturer.
CL = [(CL1 + CPCBXI + CXI) × (CL2 + CPCBXO + CXO)] / [(CL1 + CPCBXI + CXI) + (CL2 + CPCBXO + CXO)]
To determine the value of CL1 and CL2, multiply the capacitive load value CL by 2. Using this result, subtract the
combined values of CPCBXI + CXI to determine the value of CL1 and the combined values of CPCBXO + CXO to
determine the value of CL2. For example, if CL = 10 pF, CPCBXI = 2.9 pF, CXI = 0.5 pF, CPCBXO = 3.7 pF, CXO =
0.5 pF, the value of CL1 = [(2CL) - (CPCBXI + CXI)] = [(2 × 10 pF) - 2.9 pF - 0.5 pF)] = 16.6 pF and CL2 = [(2CL) -
(CPCBXO + CXO)] = [(2 × 10 pF) - 3.7 pF - 0.5 pF)] = 15.8 pF
6.9.4.1.1.2 Shunt Capacitance
The crystal circuit must also be designed such that it does not exceed the maximum shunt capacitance for
WKUP_OSC0 operating conditions defined in Table 6-21. Shunt capacitance, Cshunt, of the crystal circuit is a
combination of crystal shunt capacitance and parasitic contributions. PCB signal traces which connect crystal
circuit components to WKUP_OSC0 have mutual parasitic capacitance to each other, CPCBXIXO, where the
PCB designer should be able to extract mutual parasitic capacitance between these signal traces. The device
package also has mutual parasitic capacitance, CXIXO, where this mutual parasitic capacitance value is defined
in Table 6-22.
PCB routing should be designed to minimize mutual capacitance between XI and XO signal traces. This is
typically done by keeping signal traces short and not routing them in close proximity. Mutual capacitance can
also be minimized by placing a ground trace between these signals when the layout requires them to be routed
in close proximity. It is important to minimize the mutual capacitance on the PCB to provide as much margin as
possible when selecting a crystal.
Device
Crystal Circuit PCB
Components Signal Traces
WKUP_OSC0_XI
CPCBXIXO CXIXO
CO
WKUP_OSC0_XO
J7ES_WKUP_OSC_SC_06
A crystal should be chosen such that the below equation is satisfied. CO in the equation is the maximum shunt
capacitance specified by the crystal manufacturer.
Cshunt ≥ CO + CPCBXIXO + CXIXO
For example, the equation would be satisfied when the crystal being used is 25 MHz with an ESR = 30 Ω,
CPCBXIXO = 0.04 pF, CXIXO = 0.01 pF, and shunt capacitance of the crystal is less than or equal to 6.95 pF.
6.9.4.1.2 WKUP_OSC0 LVCMOS Digital Clock Source
Figure 6-27 shows the recommended oscillator connections when WKUP_OSC0_XI is connected to a 1.8-V
LVCMOS square-wave digital clock source.
Note
A DC steady-state condition is not allowed on WKUP_OSC0_XI when the oscillator is powered up.
This is not allowed because WKUP_OSC0_XI is internally AC coupled to a comparator that may enter
a unknown state when DC is applied to the input. Therefore, application software should power down
WKUP_OSC0 any time WKUP_OSC0_XI is not toggling between logic states.
Device
WKUP_OSC0_XI WKUP_OSC0_XO
PCB Ground
J7ES_WKUP_OSC_EXT_CLK_05
Device
OSC1_XI OSC1_XO
Rd
Crystal (Optional)
(Optional) Rbias
Cf1 Cf2
PCB Ground
J7ES_AUX_OSC_INT_07
The crystal must be in the fundamental mode of operation and parallel resonant. Table 6-23 summarizes the
required electrical constraints.
Table 6-23. OSC1 Crystal Electrical Characteristics
PARAMETER MIN TYP MAX UNIT
Fxtal Crystal Parallel Resonance Frequency 19.2 27 MHz
Fxtal Crystal Frequency Stability and Tolerance Ethernet RGMII and RMII ±100 ppm
not used
Ethernet RGMII and RMII ±50
using derived clock
CL1+PCBXI Capacitance of CL1 + CPCBXI 12 24 pF
CL2+PCBXO Capacitance of CL2 + CPCBXO 12 24 pF
CL Crystal Load Capacitance 6 12 pF
Cshunt Crystal Circuit Shunt Capacitance ESRxtal = 30 Ω 19.2 MHz, 20 MHz, 7 pF
24 MHz, 25 MHz, 26 MHz,
27 MHz
ESRxtal = 40 Ω 19.2 MHz, 20 MHz, 5 pF
24 MHz, 25 MHz, 26 MHz,
27 MHz
ESRxtal = 50 Ω 19.2 MHz, 20 MHz, 5 pF
24 MHz, 25 MHz, 26 MHz,
27 MHz
ESRxtal = 60 Ω 19.2 MHz, 20 MHz, 24 MHz 5 pF
ESRxtal = 80 Ω 19.2 MHz, 20 MHz 5 pF
25 MHz 3 pF
ESRxtal = 100 Ω 19.2 MHz, 20 MHz 3 pF
ESRxtal Crystal Effective Series Resistance 100 Ω
When selecting a crystal, the system design must consider the temperature and aging characteristics of a based
on the worst case environment and expected life expectancy of the system.
Table 6-24 details the switching characteristics of the oscillator and the requirements of the input clock.
Table 6-24. OSC1 Switching Characteristics – Crystal Mode
PARAMETER MIN TYP MAX UNIT
CXI XI Capacitance 1.55 pF
CXO XO Capacitance 1.35 pF
CXIXO XI to XO Mutual Capacitance 0.9 fF
ts Maximum Start-up Time 9.5(1) ms
(1) TI strongly encourages each customer to submit samples of the device to the resonator/crystal vendors for validation. The
vendors are equipped to determine what load capacitors will best tune their resonator/crystal to the microcontroller device
for optimum startup and operation over temperature/voltage extremes.
VDD_CORE (min.)
VDD_CORE
VSS
Voltage
VSS OSC1_XO
tsX
Time
J7ES_AUX_OSC_STARTUP_08
Device
Crystal Circuit PCB
Components Signal Traces
OSC1_XI
OSC1_XO
J7ES_AUX_OSC_CC_05
Load capacitors, CL1 and CL2 in Figure 6-28, should be chosen such that the below equation is satisfied. CL in
the equation is the load specified by the crystal manufacturer.
CL = [(CL1 + CPCBXI + CXI) × (CL2 + CPCBXO + CXO)] / [(CL1 + CPCBXI + CXI) + (CL2 + CPCBXO + CXO)]
To determine the value of CL1 and CL2, multiply the capacitive load value CL by 2. Using this result, subtract the
combined values of CPCBXI + CXI to determine the value of CL1 and the combined values of CPCBXO + CXO to
determine the value of CL2. For example, if CL = 10 pF, CPCBXI = 2.9 pF, CXI = 0.5 pF, CPCBXO = 3.7 pF, CXO =
0.5 pF, the value of CL1 = [(2CL) - (CPCBXI + CXI)] = [(2 × 10 pF) - 2.9 pF - 0.5 pF)] = 16.6 pF and CL2 = [(2CL) -
(CPCBXO + CXO)] = [(2 × 10 pF) - 3.7 pF - 0.5 pF)] = 15.8 pF
Device
Crystal Circuit PCB
Components Signal Traces
OSC1_XI
CPCBXIXO CXIXO
CO
OSC1_XO
J7ES_AUX_OSC_SC_06
A crystal should be chosen such that the below equation is satisfied. CO in the equation is the maximum shunt
capacitance specified by the crystal manufacturer.
Cshunt ≥ CO + CPCBXIXO + CXIXO
For example, the equation would be satisfied when the crystal being used is 25 MHz with an ESR = 30 Ω,
CPCBXIXO = 0.04 pF, CXIXO = 0.01 pF, and shunt capacitance of the crystal is less than or equal to 6.95 pF.
6.9.4.1.4 Auxiliary OSC1 LVCMOS Digital Clock Source
Figure 6-32 shows the recommended oscillator connections when OSC1 is connected to a 1.8-V LVCMOS
square-wave digital clock source.
Note
A DC steady-state condition is not allowed on OSC1_XI when the oscillator is powered up. This is not
allowed because OSC1_XI is internally AC coupled to a comparator that may enter a unknown state
when DC is applied to the input. Therefore, application software should power down OSC1 any time
OSC1_XI is not toggling between logic states.
Device
OSC1_XI OSC1_XO
PCB Ground
J7ES_AUX_OSC_EXT_09
Device
OSC1_XI OSC1_XO
Rpd NC
Device
WKUP_LFOSC0_XI WKUP_LFOSC0_XO
Rd
Crystal (Optional)
(Optional) Rbias
Cf1 Cf2
PCB Ground
J7ES_LF_OSC_INT_12
Note
User should set CTRLMMR_WKUP_LFXOSC_TRIM[18:16] i_mult = 3b’001 for CL in the range 6pf to
9.5pf. CTRLMMR_WKUP_LFXOSC_TRIM [18:16] i_mult = 3b’010 for CL in the range 8.5pf to 12pf.
Default setting is 3b’010.
Note
The load capacitors, Cf1 and Cf2 in Figure 6-35, should be chosen such that the below equation is
satisfied. CL in the equation is the load specified by the crystal manufacturer. All discrete components
used to implement the oscillator circuit should be placed as close as possible to the associated
oscillator WKUP_LFOSC0_XI, WKUP_LFOSC0_XO, and VSS pins.
Cf1Cf2
CL=
(Cf1+Cf2)
J7ES_CL_MATH_03
The crystal must be in the fundamental mode of operation and parallel resonant. Table 6-26 summarizes the
required electrical constraints.
Table 6-26. WKUP_LFOSC0 Crystal Electrical Characteristics
NAME DESCRIPTION MIN TYP MAX UNIT
fp Parallel resonance crystal frequency 32768 Hz
Cf1 Cf1 load capacitance for crystal parallel resonance with Cf1 = Cf2 12 24 pF
Cf2 Cf2 load capacitance for crystal parallel resonance with Cf1 = Cf2 12 24 pF
ESRxtal – 40 Ω 4 pF
ESRxtal – 60 Ω 3 pF
Cshunt Shunt capacitance
ESRxtal – 80 Ω 2 pF
ESRxtal – 100 Ω 1 pF
ESR Crystal effective series resistance 100 kΩ
When selecting a crystal, the system design must consider the temperature and aging characteristics of a based
on the worst case environment and expected life expectancy of the system.
Table 6-27 details the switching characteristics of the oscillator and the requirements of the input clock.
Table 6-27. WKUP_LFOSC0 Switching Characteristics – Crystal Mode
NAME DESCRIPTION MIN TYP MAX UNIT
fxtal Oscillation frequency 32768 Hz
tsX Start-up time 96.5 ms
VDD_WKUP (min.)
VDD_WKUP
VSS
Voltage
VSS WKUP_LFOSC0_XO
tsX
Time
J7ES_LF_OSC_STARTUP_13
Device
WKUP_LFOSC0_XI WKUP_LFOSC0_XO
NC NC
J7ES_LF_OSC_NOT_USED_14
6.9.4.3 PLLs
Power is supplied to the Phase-Locked Loop circuitries (PLLs) by internal regulators that derive power from the
off-chip power-supply.
There are total of three PLLs in the device in WKUP and MCU domains:
• MCU_PLL0 (MCU R5FSS PLL) with WKUP_PLLCTRL0
• MCU_PLL1 (MCU PERIPHERAL PLL)
• MCU_PLL2 (MCU CPSW PLL)
There are total of twenty PLLs in the device in MAIN domain:
• PLL0 (MAIN PLL) with PLLCTRL0
• PLL1 (PER0 PLL)
• PLL2 (PER1 PLL)
• PLL3 (CPSW9G PLL)
• PLL4 (AUDIO0 PLL)
• PLL5 (VIDEO PLL)
• PLL6 (GPU PLL)
• PLL7 (C7x PLL)
• PLL8 (ARM0 PLL)
• PLL12 (DDR PLL)
• PLL13 (C66 PLL)
• PLL14 (R5F PLL)
• PLL15 (AUDIO1 PLL)
• PLL16 (DSS PLL0)
• PLL17 (DSS PLL1)
• PLL18 (DSS PLL2)
• PLL19 (DSS PLL3)
• PLL23 (DSS PLL7)
• PLL24 (MLB PLL)
• PLL25 (VISION PLL)
Note
For more information, see:
• Device Configuration / Clocking / PLLs section in the device TRM.
• Peripherals / Display Subsystem Overview section in the device TRM.
Note
The input reference clock (OSC1_XI/OSC1_XO) is specified and the lock time is ensured by the PLL
controller, as documented in the Device Configuration chapter in the device TRM.
6.9.5 Peripherals
6.9.5.1 ATL
The device contains ATL module that can be used for asynchronous sample rate conversion of audio. The ATL
calculates the error between two time bases, such as audio syncs, and optionally generates an averaged clock
using cycle stealing via software.
Note
For more information about ATL, see Audio Tracking Logic (ATL) section in Peripherals chapter in the
device TRM.
Section 6.9.5.1.1, Section 6.9.5.1.2, Section 6.9.5.1.3, and Section 6.9.5.1.4 present timing requirements and
switching characteristics for ATL.
6.9.5.1.1 ATL_PCLK Timing Requirements
D10
D12
ATCLK[x]
D11
atl_01
6.9.5.2 VPFE
Table 6-29 represents VPFE timnig conditions.
Table 6-29. VPFE Timing Conditions
PARAMETER MIN MAX UNIT
INPUT CONDITIONS
SRI Input slew rate 1.3 2.64 V/ns
PCB CONNECTIVITY REQUIREMENTS
td(Trace Mismatch Delay) Propagation delay mismatch across 50 ps
all traces
Table 6-30, Figure 6-39, and Figure 6-40 represent timing requirements for VPFE0.
Table 6-30. Timing Requirements for VPFE0
NO.(1) MIN MAX UNIT
V1 tc(pclk) Cycle time, VPFE0_PCLK 6.06(1) ns
V2 tw(pclkH) Pulse duration, VPFE0_PCLK high 0.45 × P(2) ns
V3 tw(pclkL) Pulse duration, VPFE0_PCLK low 0.45 × P(2) ns
Setup time, control signals (VPFE0_HD, VPFE0_VD,
V4 tsu(ctrlV-pclkV) VPFE0_WEN, VPFE0_FIELD) valid before VPFE0_PCLK 2.12 ns
transition
Setup time, VPFE0_DATA[15:0] valid before VPFE0_PCLK
V5 tsu(dataV-pclkV) 2.38 ns
transition
Hold time, control signals (VPFE0_HD, VPFE0_VD, VPFE0_WEN,
V6 th(pclkV-ctrlV/dataV) VPFE0_FIELD) and VPFE0_DATA[15:0] valid after VPFE0_PCLK -0.05 ns
transition
V2 V1 V3
VPFE0_PCLK
VPFE0_TIMING_01
VPFE0_PCLK
(Positive-edge clocking)
VPFE0_PCLK
(Negative-edge clocking)
V4 V6
VPFE0_HD, VPFE0_VD,
VPFE0_WEN, VPFE0_FIELD
V5 V6
VPFE0_DATA[15:0]
VPFE0_TIMING_02
For more information, see Video Processing Front End (VPFE) section in Peripherals chapter in the device TRM.
6.9.5.3 CPSW2G
For more details about features and additional description information on the device Gigabit Ethernet MAC, see
the corresponding sections within , Section 5.3, Signal Descriptions and Section 7, Detailed Description.
6.9.5.3.1 CPSW2G MDIO Interface Timings
Table 6-31 represents CPSW2G timing conditions.
Table 6-31. CPSW2G MDIO Timing Conditions
PARAMETER DESCRIPTION MIN MAX UNIT
INPUT CONDITIONS
SRI Input signal slew rate 0.9 3.6 V/ns
OUTPUT CONDITIONS
CL Output load capacitance 10 470 pF
Table 6-32, Table 6-33, and Figure 6-41 present timing requirements for MDIO.
Table 6-32. CPSW2G MDIO Timing Requirements
NO. MIN MAX UNIT
MDIO1 tsu(mdioV-mdcH) Setup time, MDIO[x]_MDIO valid before MDIO[x]_MDC high 90 ns
MDIO2 th(mdcH-mdioV) Hold time, MDIO[x]_MDIO valid after MDIO[x]_MDC high 0 ns
MDIO3
MDIO4
MDIO5
MDIO[x]_MDC
MDIO1
MDIO2
MDIO[x]_MDIO
(input)
MDIO7
MDIO[x]_MDIO
(output)
CPSW2G_MDIO_TIMING_01
Note
x = 0 in MCU domain
(1) x = 0 - 5, where x indicates the respective IO power rail. Refer to Pin Attributes for more information
on IO power rail assinments.
RMII1
RMII2
RMII[x]_REF_CLK
RMII3
A. x = 1 in MCU domain.
6.9.5.3.2.2 CPSW2G RMII[x]_RXD[1:0], RMII[x]_CRS_DV, and RMII[x]_RX_ER Timing Requirements – RMII Mode
RMII4
RMII5
RMII[x]_REF_CLK
RMII[x]_RXD[1:0], RMII[x]_CRS_DV,
RMII[x]_RX_ER
Section 6.9.5.3.2.3, and Figure 6-44 present switching characteristics for CPSW2G RMII Transmit.
RMII6
RMII[x]_REF_CLK
RMII[x]_TXD[1:0], RMII[x]_TX_EN
6.9.5.3.3.2 CPSW2G Timing Requirements for RGMII[x]_RD[3:0], and RGMII[x]_RCTL – RGMII Mode
see Figure 6-45
NO. MODE MIN MAX UNIT
10Mbps 1 ns
Setup time, RGMII[x]_RD[3:0] valid before RGMII[x]_RXC
tsu(rdV-rxcV) 100Mbps 1 ns
transition
1000Mbps 1 ns
RGMII4
10Mbps 1 ns
Setup time, RGMII[x]_RX_CTL valid before RGMII[x]_RXC
tsu(rx_ctlV-rxcV) 100Mbps 1 ns
transition
1000Mbps 1 ns
10Mbps 1 ns
Hold time, RGMII[x]_RD[3:0] valid after RGMII[x]_RXC
th(rxcV-rdV) 100Mbps 1 ns
transition
1000Mbps 1 ns
RGMII5
10Mbps 1 ns
Hold time, RGMII[x]_RX_CTL valid after RGMII[x]_RXC
th(rxcV-rx_ctlV) 100Mbps 1 ns
transition
1000Mbps 1 ns
RGMII1
RGMII2
RGMII3
(A)
RGMII[x]_RXC
RGMII4
RGMII5
(B)
RGMII[x]_RD[3:0] 1st Half-byte 2nd Half-byte
(B)
RGMII[x]_RX_CTL RXDV RXERR
A. RGMII_RXC must be externally delayed relative to the data and control pins.
B. Data and control information is received using both edges of the clocks. RGMII_RXD[3:0] carries data bits 3-0 on the rising edge of
RGMII_RXC and data bits 7-4 on the falling edge of RGMII_RXC. Similarly, RGMII_RXCTL carries RXDV on rising edge of RGMII_RXC
and RXERR on falling edge of RGMII_RXC.
Section 6.9.5.3.3.3, Section 6.9.5.3.3.4 present switching characteristics for transmit - RGMII for 10 Mbps, 100
Mbps, and 1000 Mbps.
RGMII6
RGMII7
RGMII8
(A)
RGMII[x]_TXC
RGMII9
(B)
RGMII[x]_TD[3:0] 1st Half-byte 2nd Half-byte
RGMII10
(B)
RGMII[x]_TX_CTL TXEN TXERR
A. TXC is delayed internally before being driven to the RGMII[x]_TXC pin. This internal delay is always enabled.
B. Data and control information is received using both edges of the clocks. RGMII_TD[3:0] carries data bits 3-0 on the rising edge of
RGMII_TXC and data bits 7-4 on the falling edge of RGMII_TXC. Similarly, RGMII_TX_CTL carries TXDV on rising edge of RGMII_TXC
and RTXERR on falling edge of RGMII_TXC.
6.9.5.4 CPSW9G
For more details about features and additional description information on the device Gigabit Ethernet MAC, see
the corresponding sections within , Section 5.3, Signal Descriptions and Section 7, Detailed Description.
(1) x=0
MDIO3
MDIO4
MDIO5
MDIO[x]_MDC
MDIO1
MDIO2
MDIO[x]_MDIO
(input)
MDIO7
MDIO[x]_MDIO
(output)
CPSW2G_MDIO_TIMING_01
(1) x = 0 - 5, where x indicates the respective IO power rail. Refer to Pin Attributes for more information on IO power rail assinments.
RMII1
RMII2
RMII[x]_REF_CLK
RMII3
RMII4
RMII5
RMII[x]_REF_CLK
RMII[x]_RXD[1:0], RMII[x]_CRS_DV,
RMII[x]_RX_ER
Section 6.9.5.4.2.3 and present switching characteristics for CPSW9G RMII transmit.
RMII6
RMII[x]_REF_CLK
RMII[x]_TXD[1:0], RMII[x]_TX_EN
RGMII1
RGMII2
RGMII3
(A)
RGMII[x]_RXC
RGMII4
RGMII5
(B)
RGMII[x]_RD[3:0] 1st Half-byte 2nd Half-byte
(B)
RGMII[x]_RX_CTL RXDV RXERR
A. RGMII_RXC must be externally delayed relative to the data and control pins.
B. Data and control information is received using both edges of the clocks. RGMII_RXD[3:0] carries data bits 3-0 on the rising edge of
RGMII_RXC and data bits 7-4 on the falling edge of RGMII_RXC. Similarly, RGMII_RXCTL carries RXDV on rising edge of RGMII_RXC
and RXERR on falling edge of RGMII_RXC.
Section 6.9.5.4.3.3, Section 6.9.5.4.3.4, and Figure 6-52 present switching characteristics for transmit - RGMII
for 10 Mbps, 100 Mbps, and 1000 Mbps.
6.9.5.4.3.3 RGMII[x]_TXC Switching Characteristics – RGMII Mode
see Figure 6-52
NO. PARAMETER MODE MIN TYP MAX UNIT
10Mbps 360 440 ns
RGMII6 tc(txc) Cycle time, RGMII[x]_TXC 100Mbps 36 44 ns
1000Mbps 7.2 8.8 ns
10Mbps 160 240 ns
RGMII7 tw(txcH) Pulse duration, RGMII[x]_TXC high 100Mbps 16 24 ns
1000Mbps 3.6 4.4 ns
RGMII6
RGMII7
RGMII8
(A)
RGMII[x]_TXC
RGMII9
(B)
RGMII[x]_TD[3:0] 1st Half-byte 2nd Half-byte
RGMII10
(B)
RGMII[x]_TX_CTL TXEN TXERR
A. TXC is delayed internally before being driven to the RGMII[x]_TXC pin. This internal delay is always enabled.
B. Data and control information is received using both edges of the clocks. RGMII_TD[3:0] carries data bits 3-0 on the rising edge of
RGMII_TXC and data bits 7-4 on the falling edge of RGMII_TXC. Similarly, RGMII_TX_CTL carries TXDV on rising edge of RGMII_TXC
and RTXERR on falling edge of RGMII_TXC.
6.9.5.5 CSI-2
Note
For more information, see the Camera Streaming Interface Receiver (CSI_RX_IF) chapter in the
device TRM.
The CSI_RX_IF deals with the processing of the pixel data coming from an external image sensor and data from
memory. It is a key component for the following multimedia applications: camera viewfinder, video record, and
still image capture.
The CSI_RX_IF has a primary serial interface (CSI-2 port) compliant with the MIPI D-PHY RX specification v1.2
and the MIPI CSI-2 specification v1.3, with 4 differential data lanes plus 1 differential clock lane in synchronous
mode, double data rate. Refer to the specification for timing details.
• 2.5 Gbps (1.25 GHz) for each lane.
6.9.5.6 DDRSS
For more details about features and additional description information on the device LPDDR4 Memory
Interfaces, see the corresponding sections within Section 5.3, Signal Descriptions and Section 7, Detailed
Description.
The device has dedicated interface to LPDDR4. It supports JEDEC JESD209-4B standard compliant LPDDR4
SDRAM devices with the following features:
• 32-bit data path to external SDRAM memory
• Memory device capacity: Up to 8GB address space available over two chip selects (4GB per rank)
• No support for byte mode, or memories with more than 17 row address bits
Table 6-41 and Figure 6-53 present switching characteristics for DDRSS.
Table 6-41. Switching Characteristics for DDRSS
NO. PARAMETER DDR TYPE MIN MAX UNIT
1 tc(DDR_CKP/DDR_CKN) Cycle time, DDR0_CKP and DDR0_CKN LPDDR4 0.536 3.003 ns
DDR0_CKP
DDR0_CKN
For more information, see DDR Subsystem (DDRSS) section in Memory Controllers chapter in the device TRM.
6.9.5.7 DSS
For more details about features and additional description information on the device Display Subsystem – Video
Output Ports, see the corresponding sections within Section 5.3, Signal Descriptions and Section 7, Detailed
Description.
Table 6-42 represents DPI timing conditions.
Table 6-42. DPI Timing Conditions
PARAMETER MIN MAX UNIT
INPUT CONDITIONS
SRI Input slew rate 1.44 26.4 V/ns
OUTPUT CONDITIONS
CL Output load capacitance 1.5 5 pF
PCB CONNECTIVITY REQUIREMENTS
Propagation delay mismatch ps
td(Trace Mismatch Delay) 100
across all traces
Table 6-43, Table 6-44, Figure 6-54 and Figure 6-55 assume testing over the recommended operating conditions
and electrical characteristic conditions.
Table 6-43. DPI Video Output Switching Characteristics
NO.(2) PARAMETER MIN MAX UNIT
D1 tc(pclk) Cycle time, VOUT(x)_PCLK 6.06 ns
D2
D1 D3
Falling-edge Clock Reference
VOUT(x)_PCLK
Rising-edge Clock Reference
VOUT(x)_PCLK
D5
VOUT(x)_VSYNC
D5
VOUT(x)_HSYNC
D4
D5
VOUT(x)_DE
DPI_TIMING_01
A. The configuration of assertion of the data can be programmed on the falling or rising edge of the pixel clock.
B. The polarity and the pulse width of VOUT(x)_HSYNC and VOUT(x)_VSYNC are programmable, refer to Display Subsystem (DSS)
section in Peripherals chapter in the device TRM.
C. The VOUT(x)_PCLK frequency can be configured, refer to Display Subsystem section in Peripherals chapter in the device TRM.
D. x in VOUT(x) = 1 or 2.
D7
D6 D8
Falling-edge Clock Reference
VOUT(x)_EXTPCLKIN
Rising-edge Clock Reference
VOUT(x)_EXTPCLKIN
DPI_TIMING_02
For more information, see Display Subsystem (DSS) and Peripherals section in Peripherals chapter in the device
TRM.
6.9.5.8 eCAP
The supported features by the device ECAP are:
• 32-bit time base counter
• 4-event time-stamp registers (each 32 bits)
• Independent edge polarity selection for up to four sequenced time-stamp capture events
• Interrupt capabilities on any of the four capture events
• Input capture signal pre-scaling (from 1 to 16)
• Support of different capture modes (single shot capture, continuous mode capture, absolute timestamp
capture or difference mode time-stamp capture)
Table 6-45 represents ECAP timing conditions.
Table 6-45. ECAP Timing Conditions
PARAMETER MIN MAX UNIT
INPUT CONDITIONS
SRI Input slew rate 1 4 V/ns
OUTPUT CONDITIONS
CL Output load capacitance 2 7 pF
Section 6.9.5.8.1 and Section 6.9.5.8.2 present timing and switching characteristics for eCAP (see Figure 6-56
and Figure 6-57).
(1) P = sysclk
CAP1
CAP
EPERIPHERALS_TIMNG_01
(1) P = sysclk
CAP2
APWM
EPERIPHERALS_TIMNG_02
For more information, see Enhanced Capture (ECAP) Module section in Peripherals chapter in the device TRM.
6.9.5.9 EPWM
The supported features by the device EPWM are:
• Dedicated 16-bit time-base counter with period and frequency control
• Two independent PWM outputs which can be used in different configurations (with single-edge operation,
with dual-edge symmetric operation or one independent PWM output with dual-edge asymmetric operation)
• Asynchronous override control of PWM signals during fault conditions
• Programmable phase-control support for lag or lead operation relative to other EPWM modules
• Dead-band generation with independent rising and falling edge delay control
• Programmable trip zone allocation of both latched and un-latched fault conditions
• Events enabling to trigger both CPU interrupts and start of ADC conversions
Table 6-46 represents EPWM timing conditions.
Table 6-46. EPWM Timing Conditions
PARAMETER DESCRIPTION MIN MAX UNIT
INPUT CONDITIONS
SRI Input slew rate 1 4 V/ns
OUTPUT CONDITIONS
CL Output load capacitance 2 7 pF
Section 6.9.5.9.2, Section 6.9.5.9.1 and present timing and switching characteristics for eHRPWM (see Figure
6-59, Figure 6-60, Figure 6-61, and Figure 6-58).
(1) P = sysclk
PWM6
EHRPWM_SYNCI
PWM7
EHRPWM_TZn_IN
EPERIPHERALS_TIMNG_07
For more information, see Camera Subsystem section in Peripherals chapter in the device TRM.
6.9.5.9.2 Switching Characteristics for eHRPWM
(1) P = sysclk
PWM1
EHRPWM_A/B
PWM1
PWM2
EHRPWM_SYNCO
PWM5
EHRPWM_SOCA/B
EPERIPHERALS_TIMNG_04
PWM3
EPWM_A/B
EPQM_TZn_IN
EPERIPHERALS_TIMING_05
PWM4
EPWM_A/B
EPQM_TZn_IN
EPERIPHERALS_TIMING_06
6.9.5.10 eQEP
The supported features by the device eQEP are:
• Input Synchronization
• Three Stage/Six Stage Digital Noise Filter
• Quadrature Decoder Unit
• Position Counter and Control unit for position measurement
• Quadrature Edge Capture unit for low speed measurement
• Unit Time base for speed/frequency measurement
• Watchdog Timer for detecting stalls
Table 6-47 represents EQEP timing conditions.
Section 6.9.5.10.1 and Section 6.9.5.10.2 present timing requirements and switching characteristics for eQEP
(see Figure 6-62).
6.9.5.10.1 Timing Requirements for eQEP
(1) P = sysclk
QEP1
QEP_A/B
QEP2
QEP_I
QEP3
QEP4
QEP_S
QEP5 EPERIPHERALS_TIMNG_03
For more information, see Enhanced Quadrature Encoder Pulse (EQEP) Module section in Peripherals chapter
in the device TRM.
6.9.5.11 GPIO
The device has ten instances of GPIO modules. The GPIO modules are integrated in three groups.
• Group one: WKUP_GPIO0 and WKUP_GPIO1
• Group two: GPIO0, GPIO2, GPIO4, and GPIO6
• Group three: GPIO1, GPIO3, GPIO5, and GPIO7
Within each group, exactly one module is selected to control the corresponding I/O pins and pin interrupts.
The GPIO pins are grouped into banks (16 pins per bank), which means that each GPIO module provides up
to 144 dedicated general-purpose pins with input and output capabilities; thus, the general-purpose interface
supports up to 432 (3 instances × (9 banks × 16 pins)) pins. Since WKUP_GPIOu_[84:143] (u = 0, 1),
GPIOn_[128:143] (n = 0, 2, 4, 6), and GPIOm_[36:143] (m = 1, 3, 5 ,7) are reserved in this device, general
purpose interface supports up to 248 I/O pins.
For more details about features and additional description information on the device General-Purpose Interface,
see the corresponding sections within Section 5.3, Signal Descriptions and Section 7, Detailed Description.
Note
The general-purpose input/output i (i = 0 to 1) is also referred to as GPIOi.
(1) VDD stands for corresponding power supply. For more information on the power supply name and the corresponding ball(s), see
POWER column of the Pin Attributes table.
Section 6.9.5.11.1 and Section 6.9.5.11.2 present timings and switching characteristics of the GPIO Interface.
6.9.5.11.1 GPIO Timing Requirements
For more information, see General-Purpose Interface (GPIO) section in Peripherals chapter in the device TRM.
6.9.5.12 GPMC
For more details about features and additional description information on the device General-Purpose Memory
Controller, see the corresponding sections within Section 5.3, Signal Descriptions and Section 7, Detailed
Description.
Table 6-49 represents GPMC timing conditions.
Note
The IO timings provided in this section are applicable for all combinations of signals for GPMC0.
However, the timings are only valid for GPMC0 if signals within a single IOSET are used. The IOSETs
are defined in the Section 6.9.5.12.4 , GPMC0_IOSET,table.
(2) (3)
MIN MAX MIN MAX
NO. PARAMETER DESCRIPTION MODE (4) (4)
UNIT
100 MHz 133 MHz
F12 tsu(dV-clkH) Setup time, input data div_by_1_mode; 1.81 1.11 ns
GPMC_AD[15:0] valid before
not_div_by_1_mode; 1.06 ns
output clock GPMC_CLK high
F13 th(clkH-dV) Hold time, input data div_by_1_mode; 1.78 2.28 ns
GPMC_AD[15:0] valid after
not_div_by_1_mode; 1.78 ns
output clock GPMC_CLK high
F21 tsu(waitV-clkH) Setup time, input wait div_by_1_mode; 1.81 1.11 ns
GPMC_WAIT[j] valid before
(1) not_div_by_1_mode; 1.06 ns
output clock GPMC_CLK high
F22 th(clkH-waitV) Hold time, input wait div_by_1_mode; 1.78 2.28 ns
GPMC_WAIT[j] valid after output
(1) not_div_by_1_mode; 1.78 ns
clock GPMC_CLK high
•
(4) For 100 MHz:
• CTRLMMR_GPMC_CLKSEL[1-0] CLK_SEL = 01 = MAIN_PLL2_HSDIV1_CLKOUT / 3
F2 td(clkH-csnV) Delay time, output clock GPMC_CLK rising div_by_1_mode F(6)-2.2 F+3.75 F(6)-2.2 F(6)+3.75 ns
edge to output chip select GPMC_CSn[i] no extra_delay
transition(14)
F3 td(clkH-CSn[i]V) Delay time, output clock GPMC_CLK rising div_by_1_mode E(5)-2.2 E(5)+3.75 E(5)-2.2 E ns
edge to output chip select GPMC_CSn[i] no extra_delay (5)+3.75
invalid(14)
F4 td(aV-clk) Delay time, output address GPMC_A[27:1] div_by_1_mode B(2)-2.3 B(2)+4.5 B(2)-2.3 B(2)+4.5 ns
valid to output clock GPMC_CLK first edge
F5 td(clkH-aIV) Delay time, output clock GPMC_CLK rising div_by_1_mode; -2.3 4.5 -2.3 4.5 ns
edge to output address GPMC_A[27:1]
invalid
F6 td(be[x]nV-clk) Delay time, output lower byte enable and div_by_1_mode B(2)-2.3 B(2)+1.9 B(2)-2.3 B(2)+1.9 ns
command latch enable GPMC_BE0n_CLE,
output upper byte enable GPMC_BE1n
valid to output clock GPMC_CLK first edge
F7 td(clkH-be[x]nIV) Delay time, output clock GPMC_CLK rising div_by_1_mode D(4)-2.3 D(4)+1.9 D(4)-2.3 D(4)+1.9 ns
edge to output lower byte enable and
command latch enable GPMC_BE0n_CLE,
output upper byte enable GPMC_BE1n
invalid(11)
F7 td(clkL-be[x]nIV) Delay time, GPMC_CLK falling edge div_by_1_mode D(4)-2.3 D(4)+1.9 D(4)-2.3 D(4)+1.9 ns
to GPMC_BE0n_CLE, GPMC_BE1n
invalid(12)
F7 td(clkL-be[x]nIV). Delay time, GPMC_CLK falling edge div_by_1_mode D(4)-2.3 D(4)+1.9 D(4)-2.3 D(4)+1.9 ns
to GPMC_BE0n_CLE, GPMC_BE1n
invalid(13)
F8 td(clkH-advn) Delay time, output clock GPMC_CLK rising div_by_1_mode G(7)-2.3 G(7)+4.5 G(7)-2.3 G(7)+4.5 ns
edge to output address valid and address no extra_delay
latch enable GPMC_ADVn_ALE transition
F9 td(clkH-advnIV) Delay time, output clock GPMC_CLK rising div_by_1_mode; D(4)-2.3 D(4)+4.5 D(4)-2.3 D(4)+4.5 ns
edge to output address valid and address no extra_delay
latch enable GPMC_ADVn_ALE invalid
F10 td(clkH-oen) Delay time, output clock GPMC_CLK rising div_by_1_mode H(8)-2.3 H(8)+3.5 H(8)-2.3 H(8)+3.5 ns
edge to output enable GPMC_OEn_REn no extra_delay
transition
F11 td(clkH-oenIV) Delay time, output clock GPMC_CLK rising div_by_1_mode E(8)-2.3 E(8)+3.5 E(8)-2.3 E(8)+ 3.5 ns
edge to output enable GPMC_OEn_REn no extra_delay
invalid
F14 td(clkH-wen) Delay time, output clock GPMC_CLK rising div_by_1_mode I(9)- 2.3 I(9)+4.5 I(9)- 2.3 I(9)+4.5 ns
edge to output write enable GPMC_WEn no extra_delay
transition
F15 td(clkH-do) Delay time, output clock GPMC_CLK div_by_1_mode J(10)-2.3 J(10)+2.7 J(10)-2.3 J(10)+2.7 ns
rising edge to output data GPMC_AD[15:0]
transition(11)
F15 td(clkL-do) Delay time, GPMC_CLK falling edge to div_by_1_mode J(10)-2.3 J(10)+2.7 J(10)-2.3 J(10)+2.7 ns
GPMC_AD[15:0] data bus transition(12)
F15 td(clkL-do). Delay time, GPMC_CLK falling edge to div_by_1_mode J(10)-2.3 J(10)+2.7 J(10)-2.3 J(10)+2.7 ns
GPMC_AD[15:0] data bus transition(13)
F17 td(clkH-be[x]n) Delay time, output clock GPMC_CLK rising div_by_1_mode J(10)-2.3 J(10)+1.9 J(10)-2.3 J(10)+1.9 ns
edge to output lower byte enable and
command latch enable GPMC_BE0n_CLE
transition(11)
F17 td(clkL-be[x]n) Delay time, GPMC_CLK falling edge div_by_1_mode J(10)-2.3 J(10)+1.9 J(10)-2.3 J(10)+1.9 ns
to GPMC_BE0n_CLE, GPMC_BE1n
transition(12)
F17 td(clkL-be[x]n). Delay time, GPMC_CLK falling edge div_by_1_mode J(10)-2.3 J(10)+1.9 J(10)-2.3 J(10)+1.9 ns
to GPMC_BE0n_CLE, GPMC_BE1n
transition(13)
F18 tw(csnV) Pulse duration, output chip select Read A(1) A(1) ns
GPMC_CSn[i] low(14)
Write A(1) A(1) ns
F19 tw(be[x]nV) Pulse duration, output lower byte Read C(3) C(3) ns
enable and command latch enable
Write C(3) C(3) ns
GPMC_BE0n_CLE, output upper byte
enable GPMC_BE1n low
F20 tw(advnV) Pulse duration, output address valid and Read K(16) K(16) ns
address latch enable GPMC_ADVn_ALE
Write K(16) K(16) ns
low
– G = 0.5 × ADVExtraDelay × GPMC_FCLK(17) if (ClkActivationTime and ADVRdOffTime are odd) or (ClkActivationTime and
ADVRdOffTime are even)
– G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(17) otherwise
• Case GPMCFCLKDIVIDER = 2:
– G = 0.5 × ADVExtraDelay × GPMC_FCLK(17) if ((ADVRdOffTime - ClkActivationTime) is a multiple of 3)
– G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(17) if ((ADVRdOffTime - ClkActivationTime - 1) is a multiple of 3)
– G = (2 + 0.5 × ADVExtraDelay) × GPMC_FCLK(17) if ((ADVRdOffTime - ClkActivationTime - 2) is a multiple of 3)
• Case GPMCFCLKDIVIDER = 0:
– I = 0.5 × WEExtraDelay × GPMC_FCLK (17)
• Case GPMCFCLKDIVIDER = 1:
– I = 0.5 × WEExtraDelay × GPMC_FCLK(17) if (ClkActivationTime and WEOffTime are odd) or (ClkActivationTime and
WEOffTime are even)
– I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK(17) otherwise
• Case GPMCFCLKDIVIDER = 2:
– I = 0.5 × WEExtraDelay × GPMC_FCLK(17) if ((WEOffTime - ClkActivationTime) is a multiple of 3)
– I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK(17) if ((WEOffTime - ClkActivationTime - 1) is a multiple of 3)
– I = (2 + 0.5 × WEExtraDelay) × GPMC_FCLK(17) if ((WEOffTime - ClkActivationTime - 2) is a multiple of 3)
(10) J = GPMC_FCLK(17)
(11) First transfer only for CLK DIV 1 mode.
(12) Half cycle; for all data after initial transfer for CLK DIV 1 mode.
(13) Half cycle of GPMC_CLKOUT; for all data for modes other than CLK DIV 1 mode. GPMC_CLKOUT divide down from GPMC_FCLK.
(14) In GPMC_CSn[i], i is equal to 0, 1, 2, or 3. In GPMC_WAIT[j], j is equal to 0, 1, 2, or 3.
(15) P = GPMC_CLK period in ns
(16) For read: K = (ADVRdOffTime - ADVOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)
For write: K = (ADVWrOffTime - ADVOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)
(17) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns.
(18) Related to the GPMC_CLK output clock maximum and minimum frequencies programmable in the GPMC module by setting the
GPMC_CONFIG1_i configuration register bit field GPMCFCLKDIVIDER.
(19) For div_by_1_mode:
• GPMC_CONFIG1_i register: GPMCFCLKDIVIDER = 0h:
– GPMC_CLK frequency = GPMC_FCLK frequency
For no extra_delay:
• GPMC_CONFIG2_i Register: CSEXTRADELAY = 0h = CSn Timing control signal is not delayed
• GPMC_CONFIG4_i Register: WEEXTRADELAY = 0h = nWE timing control signal is not delayed
• GPMC_CONFIG4_i Register: OEEXTRADELAY = 0h = nOE timing control signal is not delayed
• GPMC_CONFIG3_i Register: ADVEXTRADELAY = 0h = nADV timing control signal is not delayed
(20) For 100 MHz:
• CTRLMMR_GPMC_CLKSEL[1-0] CLK_SEL = 01 = MAIN_PLL2_HSDIV1_CLKOUT / 3
F1
F0 F1
GPMC_CLK
F2 F3
F18
GPMC_CSn[i]
F4
GPMC_A[MSB:1] Valid Address
F6 F7
F19
GPMC_BE0n_CLE
F19
GPMC_BE1n
F6 F8 F8
F20 F9
GPMC_ADVn_ALE
F10 F11
GPMC_OEn_REn
F13
F12
GPMC_AD[15:0] D0
GPMC_WAIT[j]
GPMC_01
A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.
B. In GPMC_WAIT[j], j is equal to 0, 1, 2, or 3.
Figure 6-63. GPMC and NOR Flash — Synchronous Single Read (GPMCFCLKDIVIDER = 0)
F1
F0 F1
GPMC_CLK
F2 F3
GPMC_CSn[i]
F4
GPMCA[MSB:1] Valid Address
F6 F7
GPMC_BE0n_CLE
F7
GPMC_BE1n
F6 F8 F8 F9
GPMC_ADVn_ALE
F10 F11
GPMC_OEn_REn
F13 F13
F12 F12
GPMC_AD[15:0] D0 D1 D2 D3
A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.
B. In GPMC_WAIT[j], j is equal to 0, 1, 2, or 3.
Figure 6-64. GPMC and NOR Flash — Synchronous Burst Read — 4x16–bit (GPMCFCLKDIVIDER = 0)
F1
F1 F0
GPMC_CLK
F2 F3
GPMC_CSn[i]
F4
GPMC_A[MSB:1] Valid Address
F17
F6 F17 F17
GPMC_BE0n_CLE
F17
F17 F17
GPMC_BE1n
F6 F8 F8 F9
GPMC_ADVn_ALE
F14 F14
GPMC_WEn
F15 F15 F15
GPMC_AD[15:0] D0 D1 D2 D3
GPMC_WAIT[j]
GPMC_03
A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.
B. In GPMC_WAIT[j], j is equal to 0, 1, 2, or 3.
F1
F0 F1
GPMC_CLK
F2 F3
GPMC_CSn[i]
F6 F7
GMPC_BE0n_CLE Valid
F6 F7
GPMC_BE1n Valid
F4
GPMC_A[27:17] Address (MSB)
F12
F4 F5 F13 F12
GPMC_AD[15:0] Address (LSB) D0 D1 D2 D3
F8 F8 F9
GPMC_ADVn_ALE
F10 F11
GPMC_OEn_REn
GPMC_WAIT[j]
GPMC_04
A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.
B. In GPMC_WAIT[j], j is equal to 0, 1, 2, or 3.
Figure 6-66. GPMC and Multiplexed NOR Flash — Synchronous Burst Read
F1
F1 F0
GPMC_CLK
F2 F3
F18
GPMC_CSn[i]
F4
GPMC_A[27:17] Address (MSB)
F17
F6 F17 F17
GPMC_BE1n
F17
F6 F17 F17
BPMC_BE0n_CLE
F8 F8
F20 F9
GPMC_ADVn_ALE
F14 F14
GPMC_WEn
F15 F15 F15
GPMC_AD[15:0] Address (LSB) D0 D1 D2 D3
F21 F22
F22 F21
GPMC_WAIT[j]
GPMC_05
A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.
B. In GPMC_WAIT[j], j is equal to 0, 1, 2, or 3.
Figure 6-67. GPMC and Multiplexed NOR Flash — Synchronous Burst Write
(1) The FA5 parameter illustrates the amount of time required to internally sample input data. It is expressed in number of GPMC
functional clock cycles. From start of read cycle and after FA5 functional clock cycles, input data is internally sampled by active
functional clock edge. FA5 value must be stored inside the AccessTime register bit field.
(2) The FA20 prameter illustrates amount of time required to internally sample successive input page data. It is expressed in number of
GPMC functional clock cycles. After each access to input page data, next input page data is internally sampled by active functional
clock edge after FA20 functional clock cycles. The FA20 value must be stored in the PageBurstAccessTime register bit field.
(3) The FA21 parameter illustrates amount of time required to internally sample first input page data. It is expressed in number of GPMC
functional clock cycles. From start of read cycle and after FA21 functional clock cycles, first input page data is internally sampled by
active functional clock edge. FA21 value must be stored inside the AccessTime register bit field.
(4) P = PageBurstAccessTime × (TimeParaGranularity + 1) × GPMC_FCLK(6)
(5) H = AccessTime × (TimeParaGranularity + 1) × GPMC_FCLK(6)
(6) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns.
(7) For div_by_1_mode:
• GPMC_CONFIG1_i Register: GPMCFCLKDIVIDER = 0h:
– GPMC_CLK frequency = GPMC_FCLK frequency
(15)
MIN MAX
NO. PARAMETER DESCRIPTION MODE (16)
UNIT
133 MHz
FA0 tw(be[x]nV) Pulse duration, output lower-byte enable and Read N(12) ns
command latch enable GPMC_BE0n_CLE, output
Write N(12)
upper-byte enable GPMC_BE1n valid time
FA1 tw(csnV) Pulse duration, output chip select GPMC_CSn[i](13) Read A(1) ns
low
Write A(1)
FA3 td(csnV-advnIV) Delay time, output chip select GPMC_CSn[i](13) Read B(2)-2.55 B(2)+2.65 ns
valid to output address valid and address latch
Write B(2)-2.55 B(2)+2.65
enable GPMC_ADVn_ALE invalid
FA4 td(csnV-oenIV) Delay time, output chip select GPMC_CSn[i](13) div_by_1_mode; ns
valid to output enable GPMC_OEn_REn invalid C(3)-2.55 C(3)+2.65
(Single read)
FA9 td(aV-csnV) Delay time, output address GPMC_A[27:1] valid to div_by_1_mode; ns
J(9)-2.55 J(9)+2.65
output chip select GPMC_CSn[i](13) valid
FA10 td(be[x]nV-csnV) Delay time, output lower-byte enable and div_by_1_mode; ns
command latch enable GPMC_BE0n_CLE, output
J(9)-2.55 J(9)+2.65
upper-byte enable GPMC_BE1n valid to output
chip select GPMC_CSn[i](13) valid
FA12 td(csnV-advnV) Delay time, output chip select GPMC_CSn[i](13) div_by_1_mode; ns
K
valid to output address valid and address latch K(10)-2.55 (10)+2.65
enable GPMC_ADVn_ALE valid
FA13 td(csnV-oenV) Delay time, output chip select GPMC_CSn[i](13) div_by_1_mode; ns
L(11)-2.55 L(11)+2.65
valid to output enable GPMC_OEn_REn valid
FA16 tw(aIV) Pulse duration output address GPMC_A[26:1] div_by_1_mode; ns
invalid between 2 successive read and write G(7)
accesses
FA18 td(csnV-oenIV) Delay time, output chip select GPMC_CSn[i](13) div_by_1_mode; ns
valid to output enable GPMC_OEn_REn invalid I(8)-2.55 I(8)+2.65
(Burst read)
FA20 tw(aV) Pulse duration, output address GPMC_A[27:1] div_by_1_mode; ns
D(4)
valid - 2nd, 3rd, and 4th accesses
FA25 td(csnV-wenV) Delay time, output chip select GPMC_CSn[i](13) div_by_1_mode; ns
E(5)-2.55 E(5)+2.65
valid to output write enable GPMC_WEn valid
FA27 td(csnV-wenIV) Delay time, output chip select GPMC_CSn[i](13) div_by_1_mode; ns
F(6)-2.55 F(6)+2.65
valid to output write enable GPMC_WEn invalid
FA28 td(wenV-dV) Delay time, output write enable GPMC_WEn valid div_by_1_mode; ns
2.65
to output data GPMC_AD[15:0] valid
FA29 td(dV-csnV) Delay time, output data GPMC_AD[15:0] valid to div_by_1_mode; ns
J(9)-2.55 J(9)+2.65
output chip select GPMC_CSn[i](13) valid
FA37 td(oenV-aIV) Delay time, output enable GPMC_OEn_REn valid div_by_1_mode; ns
2.65
to output address GPMC_AD[15:0] phase end
GPMC_FCLK
GPMC_CLK
FA5
FA1
GPMC_CSn[i]
FA9
GPMC_A[MSB:1] Valid Address
FA0
FA10
GPMC_BE0n_CLE Valid
FA0
GPMC_BE1n Valid
FA10
FA3
FA12
GPMC_ADVn_ALE
FA4
FA13
GPMC_OEn_REn
GPMC_AD[15:0] Data IN 0 Data IN 0
GPMC_WAIT[j]
GPMC_06
Figure 6-68. GPMC and NOR Flash — Asynchronous Read — Single Word
GPMC_FCLK
GPMC_CLK
FA5 FA5
FA1 FA1
GPMC_CSn[i]
FA16
FA9 FA9
FA3 FA3
FA12 FA12
GPMC_ADCn_ALE
FA4 FA4
FA13 FA13
GPMC_OEn_REn
GPMC_AD[15:0] Data Upper
GPMC_WAIT[j]
GPMC_07
GPMC_FCLK
GPMC_CLK
FA21 FA20 FA20 FA20
FA1
GPMC_CSn[i]
FA9
GPMC_A[MSB:1] Add0 Add1 Add2 Add3 Add4
FA0
FA10
GPMC_BE0n_CLE
FA0
FA10
GPMC_BE1n
FA12
GPMC_ADVn_ALE
FA18
FA13
GPMC_OEn_REn
GPMC_AD[15:0] D0 D1 D2 D3 D3
GPMC_WAIT[j]
GPMC_08
Figure 6-70. GPMC and NOR Flash — Asynchronous Read — Page Mode 4x16–Bit
GPMC_FCLK
GPMC_CLK
FA1
GPMC_CSn[i]
FA9
GPMC_A[MSB:1] Valid Address
FA0
FA10
GPMC_BE0n_CLE
FA0
FA10
GPMC_BE1n
FA3
FA12
GPMC_ADVn_ALE
FA27
FA25
GPMC_WEn
FA29
GPMC_AD[15:0] Data OUT
GPMC_WAIT[j]
GPMC_09
Figure 6-71. GPMC and NOR Flash — Asynchronous Write — Single Word
GPMC_FCLK
GPMC_CLK
FA1
FA5
GPMC_CSn[i]
FA9
GPMC_A[27:17] Address (MSB)
FA0
FA10
GPMC_BE0n_CLE Valid
FA0
FA10
GPMC_BE1n Valid
FA3
FA12
GPMC_ADVn_ALE
FA4
FA13
GPMC_OEn_REn
FA29 FA37
GPMC_AD[15:0] Address (LSB) Data IN Data IN
GPMC_WAIT[j]
GPMC_10
Figure 6-72. GPMC and Multiplexed NOR Flash — Asynchronous Read — Single Word
GPMC_FCLK
GPMC_CLK
FA1
GPMC_CSn[i]
FA9
GPMC_A[27:17] Address (MSB)
FA0
FA10
GPMC_BE0n_CLE
FA0
FA10
GPMC_BE1n
FA3
FA12
GPMC_ADVn_ALE
FA27
FA25
GPMC_WEn
FA29 FA28
GPMC_AD[15:0] Valid Address (LSB) Data OUT
GPMC_WAIT[j]
GPMC_11
Figure 6-73. GPMC and Multiplexed NOR Flash — Asynchronous Write — Single Word
MIN MAX
NO. MODE(4) UNIT
133 MHz(5)
GNF12(1) tacc(d) Access time, input data GPMC_AD[15:0](3) div_by_1_mode; J(2) ns
(1) The GNF12 parameter illustrates the amount of time required to internally sample input data. It is expressed in number of GPMC
functional clock cycles. From start of the read cycle and after GNF12 functional clock cycles, input data is internally sampled by the
active functional clock edge. The GNF12 value must be stored inside AccessTime register bit field.
(2) J = AccessTime × (TimeParaGranularity + 1) × GPMC_FCLK(3)
(3) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns.
(4) For div_by_1_mode:
• GPMC_CONFIG1_i Register: GPMCFCLKDIVIDER = 0h:
– GPMC_CLK frequency = GPMC_FCLK frequency
(5) For 133 MHz:
• CTRLMMR_GPMC_CLKSEL[1-0] CLK_SEL = 00 = MAIN_PLL0_HSDIV3_CLKOUT
(15)
MIN MAX
NO. PARAMETER MODE (16)
UNIT
133 MHz
GNF0 tw(wenV) Pulse duration, output write enable GPMC_WEn div_by_1_mode; A(1) ns
valid
GNF1 td(csnV-wenV) Delay time, output chip select GPMC_CSn[i](13) div_by_1_mode; B(2)-2.55 B(2)+2.65 ns
valid to output write enable GPMC_WEn valid
GNF2 tw(cleH-wenV) Delay time, output lower-byte enable and div_by_1_mode; C(3)-2.55 C(3)+2.65 ns
command latch enable GPMC_BE0n_CLE high to
output write enable GPMC_WEn valid
GNF3 tw(wenV-dV) Delay time, output data GPMC_AD[15:0] valid to div_by_1_mode; D(4)-2.55 D(4)+2.65 ns
output write enable GPMC_WEn valid
GNF4 tw(wenIV-dIV) Delay time, output write enable GPMC_WEn div_by_1_mode; E(5)-2.55 E(5)+2.65 ns
invalid to output data GPMC_AD[15:0] invalid
GNF5 tw(wenIV-cleIV) Delay time, output write enable GPMC_WEn div_by_1_mode; F(6)-2.55 F(6)+2.65 ns
invalid to output lower-byte enable and command
latch enable GPMC_BE0n_CLE invalid
GNF6 tw(wenIV-CSn[i]V) Delay time, output write enable GPMC_WEn div_by_1_mode; G(7)-2.55 G(7)+2.65 ns
invalid to output chip select GPMC_CSn[i](13)
invalid
GNF7 tw(aleH-wenV) Delay time, output address valid and address latch div_by_1_mode; C(3)-2.55 C(3)+2.65 ns
enable GPMC_ADVn_ALE high to output write
enable GPMC_WEn valid
GNF8 tw(wenIV-aleIV) Delay time, output write enable GPMC_WEn div_by_1_mode; F(6)-2.55 F(6)+2.65 ns
invalid to output address valid and address latch
enable GPMC_ADVn_ALE invalid
GNF9 tc(wen) Cycle time, write div_by_1_mode; H(8) ns
GNF10 td(csnV-oenV) Delay time, output chip select GPMC_CSn[i](13) div_by_1_mode; I(9)-2.55 I(9)+2.65 ns
valid to output enable GPMC_OEn_REn valid
GNF13 tw(oenV) Pulse duration, output enable GPMC_OEn_REn div_by_1_mode; K(10) ns
valid
GNF14 tc(oen) Cycle time, read div_by_1_mode; L(11) ns
GNF15 tw(oenIV-CSn[i]V) Delay time, output enable GPMC_OEn_REn div_by_1_mode; M(12)-2.55 M ns
invalid to output chip select GPMC_CSn[i](13) (12)+2.65
invalid
GPMC_FCLK
GNF1 GNF6
GPMC_CSn[i]
GNF2 GNF5
GPMC_BE0n_CLE
GPMC_ADCn_ALE
GPMC_OEn_REn
GNF0
GPMC_WEn
GNF3 GNF4
GPMC_AD[15:0] Command
GPMC_12
A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.
GPMC_FCLK
GNF1 GNF6
GPMC_CSn[i]
GPMC_BE0n_CLE
GNF7 GNF8
GPMC_ADVn_ALE
GPMC_OEn_REn
GNF9
GNF0
GPMC_WEn
GNF3 GNF4
GPMC_AD[15:0] Address
GPMC_13
A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.
GPMC_FCLK
GNF12
GNF10 GNF15
GPMC_CSn[i]
GPMC_BE0n_CLE
GPMC_ADVn_ALE
GNF14
GNF13
GPMC_OEn_REn
GPMC_AD[15:0] DATA
GPMC_WAIT[j]
GPMC_14
A. GNF12 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional
clock cycles. From start of read cycle and after GNF12 functional clock cycles, input data will be internally sampled by active functional
clock edge. GNF12 value must be stored inside AccessTime register bits field.
B. GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.
C. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3. In GPMC_WAIT[j], j is equal to 0, 1, 2, or 3.
GPMC_FCLK
GNF1 GNF6
GPMC_CSn[i]
GPMC_BE0n_CLE
GPMC_ADVn_ALE
GPMC_OEn_REn
GNF9
GNF0
GPMC_WEn
GNF3 GNF4
GPMC_AD[15:0] DATA
GPMC_15
For more information, see Enhanced Pulse Width Modulation (EPWM) Module section in Peripherals chapter in
the device TRM.
6.9.5.12.4 GPMC0 IOSET
Table 6-50 present the specific groupings of signals (IOSET) for use with GPMC0.
Table 6-50. GPMC0 IOSET
Signals IOSET1 IOSET2
BALL NAME MUX BALL NAME MUX
GPMC0_WAIT2 MDIO0_MDC 8 MDIO0_MDC 8
GPMC0_BE1n PRG1_PRU0_GPO0 8 RGMII6_RD1 8
GPMC0_WAIT0 PRG1_PRU0_GPO1 8 PRG1_PRU0_GPO1 8
GPMC0_WAIT1 PRG1_PRU0_GPO2 8 PRG1_PRU0_GPO2 8
GPMC0_DIR PRG1_PRU0_GPO3 8 PRG1_PRU0_GPO3 8
GPMC0_CSn2 PRG1_PRU0_GPO4 8 PRG1_PRU0_GPO4 8
GPMC0_WEn PRG1_PRU0_GPO5 8 PRG1_PRU0_GPO5 8
GPMC0_CSn3 PRG1_PRU0_GPO6 8 PRG1_PRU0_GPO6 8
GPMC0_OEn_REn PRG1_PRU0_GPO8 8 PRG1_PRU0_GPO8 8
GPMC0_ADVn_ALE PRG1_PRU0_GPO9 8 PRG1_PRU0_GPO9 8
GPMC0_BE0n_CLE PRG1_PRU0_GPO10 8 PRG1_PRU0_GPO10 8
GPMC0_WPn PRG1_PRU1_GPO5 8 PRG1_PRU1_GPO5 8
GPMC0_CSn1 PRG1_PRU1_GPO8 8 PRG1_PRU1_GPO8 8
GPMC0_CSn0 PRG1_PRU1_GPO9 8 PRG1_PRU1_GPO9 8
GPMC0_CLKOUT PRG1_PRU1_GPO10 8 PRG1_PRU1_GPO10 8
GPMC0_AD0 PRG0_PRU0_GPO5 8 PRG0_PRU0_GPO5 8
GPMC0_AD1 PRG0_PRU0_GPO7 8 PRG0_PRU0_GPO7 8
GPMC0_AD2 PRG0_PRU0_GPO8 8 PRG0_PRU0_GPO8 8
GPMC0_AD3 PRG0_PRU0_GPO9 8 PRG0_PRU0_GPO9 8
GPMC0_AD4 PRG0_PRU0_GPO10 8 PRG0_PRU0_GPO10 8
GPMC0_AD5 PRG0_PRU0_GPO17 8 PRG0_PRU0_GPO17 8
6.9.5.13 HyperBus
For more details about features and additional description information on the device HyperBus, see the
corresponding sections within Section 5.3, Signal Descriptions and Section 7, Detailed Description.
Section 6.9.5.13.1, Section 6.9.5.13.2, and Section 6.9.5.13.3 assume testing over the recommended operating
conditions and electrical characteristic conditions (see Figure 6-78, Figure 6-79, and Figure 6-80).
Table 6-51 represents HyperBus timing conditions.
Table 6-51. HyperBus Timing Conditions
PARAMETER DESCRIPTION MIN MAX UNIT
INPUT CONDITIONS
SRI Input slew rate 2 5 V/ns
OUTPUT CONDITIONS
CL Output load capacitance 1.5 10 pF
PCB CONNECTIVITY REQUIREMENTS
td(Trace Mismatch Propagation delay mismatch between CK and CKn; ps
10
Delay) traces RWDS and DQ[7:0]
CK/CKn and RWDS; ps
200
CK/CKn and CSn
CK/CKn and DQ[7:0] 35 ps
RESETn and CSn[1:0] 340 ps
D8/LFD8 D2
CSn
D9/LFD9
D10/LFD10
CK, CKn
D7/LFD7
D4 D6/LFD6 D11/LFD11
RWDS
D12/LFD12 D12/LFD12
HYPERBUS_TIMING_01
D8/LFD8 D2
CSn
D9/LFD9
D10/LFD10
CK, CKn
D7/LFD7
D4
D6/LFD6
RWDS
D12/LFD12 D5/LFD5
D5/LFD5
HYPERBUS_TIMING_02
D1
RESETn
D3
CSn
HYPERBUS_TIMING_03
For more information, see HyperBus Interface section in Peripherals chapter in the device TRM.
6.9.5.14 I2C
The Inter-IC module is compliant with the Philips I2C Bus Specification, revision 2.1. Refer to the specification for
timing details for all but rise/fall time parameters.
Philips I2C specification rise/fall timings apply only to MCU_I2C0, WKUP_I2C0, and I2C[0-1]. All other instances
of I2C use standard LVCMOS buffers to emulate open-drain buffers, and their rise/fall times should be
referenced using the device IBIS model.
For more details about features and additional description information on the device Inter-Integrated Circuit, see
the corresponding sections within Section 5.3, Signal Descriptions and Section 7, Detailed Description.
6.9.5.15 I3C
For more details about features and additional description information on the device Inter-Integrated Circuit, see
the corresponding sections within Section 5.3, Signal Descriptions and Section 7, Detailed Description.
Table 6-52, Table 6-53 , Table 6-54, Figure 6-81, Table 6-56, Figure 6-82, and Figure 6-83 assume testing over
the recommended operating conditions and electrical characteristic conditions.
Table 6-52. I3C Timing Conditions
PARAMETER MIN MAX UNIT
INPUT CONDITIONS
SRI Input slew rate 0.2276 5 V/ns
OUTPUT CONDITIONS
CL Output load capacitance 50 pF
OD5
OD2
OD1
0.7xVDD
SCL
0.3xVDD
- Open drain with weak pull-up - Open drain with weak pull-up
Table 6-55. I3C Push-Pull Timing Requirements - SDR and HDR-DDR Modes
Figure 6-82 and Figure 6-83
NO. MODE MIN MAX UNIT
D8 th(sclV-sdaV) Hold time, SDA valid after SCL transition Master tr(scl) + 3 and tf(scl) + 3 ns
D9 tsu(sdaV-sclV) Seutp time, SDA valid before SCL transition Master 3 ns
Table 6-56. I3C Push-Pull Switching Characteristics - SDR and HDR-DDR Modes
see Figure 6-83, Figure 6-82
NO. PARAMETER MODE MIN MAX UNIT
D1 tc(scl) Cycle time, SCL Master 80 100000 ns
tw(sclL) 24 ns
D2 Pulse duration, SCL low Master
tw(sclL_dig) 32 ns
tw(sclH) 24 ns
D4 Pulse duration, SCL high Master
tw(sclH_dig) 32 ns
D6 tr(scl) Rise time, SCL Master 150 × 1 / tc(scl) 60 ns
D7 tf(scl) Fall time, SCL Master 150 × 1 / tc(scl) 60 ns
D10 td(Sr-sclV) Delay time, SCL valid after Repeated START (Sr) Master td(sclV-START), min ns
td(sclV-START),
D11 td(sclV-Sr) Delay time, Repeated START (Sr) after SCL valid Master ns
min / 2
0.7xVDD
SDA
0.3xVDD
D1 D11 D10
D2 D8
D8 D9 D8 D9
0.7xVDD
SCL
0.3xVDD
D4
Stop Start Repeated Stop
Start
0.7xVDD
SDA
0.3xVDD
D1 D11 D10
D2 D8 D9
0.7xVDD
SCL
0.3xVDD
D4
Stop Start Repeated Stop
Start
6.9.5.16 MCAN
For more details about features and additional description information on the device Controller Area Network
Interface, see the corresponding sections within Section 5.3, Signal Descriptions and Section 7, Detailed
Description.
Note
The device has multiple MCAN modules. MCANn is a generic prefix applied to MCAN signal names,
where n represents the specific MCAN module.
For more information, see Controller Area Network (MCAN) section in Peripherals chapter in the device TRM.
6.9.5.17 MCASP
For more details about features and additional description information on the device Multichannel Audio Serial
Port, see the corresponding sections within Section 5.3, Signal Descriptions and Section 7, Detailed Description.
Table 6-60 and Figure 6-84 present timing requirements for MCASP0 to MCASP11.
Table 6-59 represents MCASP timing conditions.
Table 6-59. MCASP Timing Conditions
PARAMETER MIN MAX UNIT
INPUT CONDITIONS
SRI Input slew rate 0.7 5 V/ns
OUTPUT CONDITIONS
CL Output load capacitance 1 10 pF
PCB CONNECTIVITY REQUIREMENTS
td(Trace Delay) Propagation delay of each trace 100 1100 ps
td(Trace Mismatch Delay) Propagation delay mismatch across all traces 100 ps
ASP2
ASP1
ASP2
MCASP[x]_AHCLKR/X (Falling Edge Priority)
ASP4
ASP3 ASP4
(A)
MCASP[x]_ACLKR/X (CLKRP = CLKXP = 0)
(B)
MCASP[x]_ACLKR/X (CLKRP = CLKXP = 1)
ASP6
ASP5
MCASP[x]_AFSR/X (Bit Width, 0 Bit Delay)
ASP8
ASP7
MCASP[x]_AXR[x] (Data In/Receive)
A. For CLKRP = CLKXP = 0, the MCASP transmitter is configured for rising edge (to shift data out) and the MCASP receiver is configured
for falling edge (to shift data in).
B. For CLKRP = CLKXP = 1, the MCASP transmitter is configured for falling edge (to shift data out) and the MCASP receiver is configured
for rising edge (to shift data in).
Table 6-61 and Figure 6-85 present switching characteristics over recommended operating conditions for
MCASP0 to MCASP11.
Table 6-61. MCASP Switching Characteristics
NO. PARAMETER DESCRIPTION MODE(1) MIN MAX UNIT
ASP9 tc(AHCLKRX) Cycle time, MCASP[x]_AHCLKR/X 20 ns
ASP10 tw(AHCLKRX) Pulse duration, MCASP[x]_AHCLKR/X high or low 0.5P(2) -2 ns
ASP11 tc(ACLKRX) Cycle time, MCASP[x]_ACLKR/X 20 ns
ASP12 tw(ACLKRX) Pulse duration, MCASP[x]_ACLKR/X high or low 0.5R(3) -2 ns
ASP13 td(ACLKRX-AFSRX) Delay time, MCASP[x]_ACLKR/X transmit edge to ACLKR/X int 0 7.25 ns
MCASP[x]_AFSR/X output valid
ACLKR/X ext in/out -15.28 12.84
ASP14 td(ACLKX-AXR) Delay time, MCASP[x]_ACLKX transmit edge to ACLKR/X int 0 7.25 ns
MCASP[x]_AXR output valid
ACLKR/X ext in/out -15.28 12.84
ASP15 tdis(ACLKX-AXR) Disable time, MCASP[x]_ACLKX transmit edge to ACLKR/X int 0 7.25 ns
MCASP[x]_AXR output high impedance
ACLKR/X ext in/out -14.9 14
ASP10
ASP9 ASP10
ASP12
ASP11
ASP12
(A)
MCASP[x]_ACLKR/X (CLKRP = CLKXP = 1)
(B)
MCASP[x]_ACLKR/X (CLKRP = CLKXP = 0)
ASP13 ASP13
ASP13 ASP13
MCASP[x]_AFSR/X (Bit Width, 0 Bit Delay)
A. For CLKRP = CLKXP = 1, the MCASP transmitter is configured for falling edge (to shift data out) and the MCASP receiver is configured
for rising edge (to shift data in).
B. For CLKRP = CLKXP = 0, the MCASP transmitter is configured for rising edge (to shift data out) and the MCASP receiver is configured
for falling edge (to shift data in).
For more information, see Multichannel Audio Serial Port (MCASP) section in Peripherals chapter in the device
TRM.
6.9.5.18 MCSPI
For more details about features and additional description information on the device Serial Port Interface, see
the corresponding sections within Section 5.3, Signal Descriptions and Section 7, Detailed Description.
For more information, see Multichannel Serial Peripheral Interface (MCSPI) section in Peripherals chapter in the
device TRM.
Table 6-62 represents MCSPI timing conditions.
Note
The IO timings provided in this section are applicable for all combinations of signals for MCU_SPI0
and MCU_SPI1. However, the timings are only valid for MCU_SPI0 and MCU_SPI1 if signals within a
single IOSET are used. The IOSETs are defined in the Table 6-67 and Table 6-68 tables.
th(spiclkV-
SM5 Hold time, SPI_D[x] valid after SPI_CLK active edge 3 ns
misoV)
When P > 20.8 ns, A = (TCS + 0.5) * Fratio * TSPICLKREF, where TCSns a bit field of the MCSPI_CHCONF_0/1/2/3 register.
PHA=0
EPOL=1
SPI_CS[i] (OUT)
SM1
SM3
SM8 SM2 SM9
SPI_SCLK (OUT) POL=0
SM1
SM3
SM2
POL=1
SPI_SCLK (OUT)
SM5
SM5
SM4 SM4
SPI_D[x] (IN) Bit n-1 Bit n-2 Bit n-3 Bit n-4 Bit 0
PHA=1
EPOL=1
SPI_CS[i] (OUT)
SM2
SM1
SM8 SM3 SM9
SPI_SCLK (OUT) POL=0
SM1
SM2
SM3
POL=1
SPI_SCLK (OUT)
SM5
SM4
SM4 SM5
SPI_D[x] (IN) Bit n-1 Bit n-2 Bit n-3 Bit 1 Bit 0
SPRSP08_TIMING_McSPI_02
PHA=0
EPOL=1
SPI_CS[i] (OUT)
SM1
SM3
SM8 SM2 SM9
SPI_SCLK (OUT) POL=0
SM1
SM3
POL=1 SM2
SPI_SCLK (OUT)
SPI_D[x] (OUT) Bit n-1 Bit n-2 Bit n-3 Bit n-4 Bit 0
PHA=1
EPOL=1
SPI_CS[i] (OUT)
SM1
SM2
SM8 SM3 SM9
SPI_SCLK (OUT) POL=0
SM1
SM2
POL=1 SM3
SPI_SCLK (OUT)
SPI_D[x] (OUT) Bit n-1 Bit n-2 Bit n-3 Bit 1 Bit0
SPRSP08_TIMING_McSPI_01
SS7 tsk(csV-somiV) Delay time, SPI_CSi active edge to SPI_D[x] transition 20.95 ns
PHA=0
EPOL=1
SPI_CS[i] (IN)
SS1
SS2
SS8 SS3 SS9
SPI_SCLK (IN) POL=0
SS1
SS2
POL=1 SS3
SPI_SCLK (IN)
SS5 SS4
SS4 SS5
SPI_D[x] (IN) Bit n-1 Bit n-2 Bit n-3 Bit n-4 Bit 0
PHA=1
EPOL=1
SPI_CS[i] (IN)
SS1
SS2
SS8 SS3 SS9
POL=0
SPI_SCLK (IN)
SS1
SS3
POL=1 SS2
SPI_SCLK (IN)
SS4
SS5
SS4 SS5
SPI_D[x] (IN) Bit n-1 Bit n-2 Bit n-3 Bit 1 Bit 0
SPRSP08_TIMING_McSPI_04
PHA=0
EPOL=1
SPI_CS[i] (IN)
SS1
SS2
SS8 SS3 SS9
SPI_SCLK (IN) POL=0
SS1
SS2
POL=1 SS3
SPI_SCLK (IN)
SPI_D[x] (OUT) Bit n-1 Bit n-2 Bit n-3 Bit n-4 Bit 0
PHA=1
EPOL=1
SPI_CS[i] (IN)
SS1
SS2
SS8 SS3 SS9
POL=0
SPI_SCLK (IN)
SS1
SS3
POL=1 SS2
SPI_SCLK (IN)
SPI_D[x] (OUT)
Bit n-1 Bit n-2 Bit n-3 Bit 1 Bit 0
SPRSP08_TIMING_McSPI_03
Table 6-67 and Table 6-68 present the specific groupings of signals (IOSET) for use with MCU_SPI0 and
MCU_SPI1.
Table 6-67. MCU_SPI0 IOSETs
Signals IOSET1 IOSET2
For more information, see Multichannel Serial Peripheral Interface (MCSPI) section in Peripherals chapter in the
device TRM.
6.9.5.19 MMCSD
The MMCSD Host Controller provides an interface to embedded Multi-Media Card (MMC), Secure Digital (SD),
and Secure Digital IO (SDIO) devices. The MMCSD Host Controller deals with MMC/SD/SDIO protocol at
transmission level, data packing, adding cyclic redundancy checks (CRCs), start/end bit insertion, and checking
for syntactical correctness.
For more details about MMCSD interfaces, see the corresponding MMC0, MMC1, and MMC2 sections within
Section 5.3, Signal Descriptions and Section 7, Detailed Description.
Note
Some operating modes require software configuration of the MMC DLL delay settings, as shown in
Table 6-69 and Table 6-78.
For more information, see Multi-Media Card/Secure Digital (MMCSD) Interface section in Peripherals chapter in
the device TRM.
6.9.5.19.1 MMC0 - eMMC Interface
MMC0 interface is compliant with the JEDEC eMMC electrical standard v5.1 (JESD84-B51) and it supports the
following eMMC applications:
• Legacy speed
• High speed SDR
• High speed DDR
• HS200
Table 6-69 presents the required DLL software configuration settings for MMC0 timing modes.
Table 6-69. MMC0 DLL Delay Mapping for All Timing Modes
REGISTER NAME MMCSD0_SS_PHY_CTRL_4_REG MMCSD0_SS_PHY_CTRL_5_REG
BIT FIELD [31:24] [20] [15:12] [8] [4:0] [17:16] [10:8] [2:0]
SELDLYTXCLK
BIT FIELD NAME STRBSEL OTAPDLYENA OTAPDLYSEL ITAPDLYENA ITAPDLYSEL FRQSEL CLKBUFSEL
SELDLYRXCLK
OUTPUT OUTPUT INPUT INPUT DLL/ DELAY
STROBE DLL REF
MODE DESCRIPTION DELAY DELAY DELAY DELAY DELAY CHAIN BUFFER
DELAY FREQUENCY
ENABLE VALUE ENABLE VALUE SELECT DURATION
8-bit PHY
Legacy
operating 1.8 V, 0x0 0x0 NA 0x1 0x10 0x1 0x0 0x7
SDR
25 MHz
High 8-bit PHY
Speed operating 1.8 V, 0x0 0x0 NA 0x1 0xA 0x1 0x0 0x7
SDR 50 MHz
Table 6-69. MMC0 DLL Delay Mapping for All Timing Modes (continued)
REGISTER NAME MMCSD0_SS_PHY_CTRL_4_REG MMCSD0_SS_PHY_CTRL_5_REG
BIT FIELD [31:24] [20] [15:12] [8] [4:0] [17:16] [10:8] [2:0]
SELDLYTXCLK
BIT FIELD NAME STRBSEL OTAPDLYENA OTAPDLYSEL ITAPDLYENA ITAPDLYSEL FRQSEL CLKBUFSEL
SELDLYRXCLK
OUTPUT OUTPUT INPUT INPUT DLL/ DELAY
STROBE DLL REF
MODE DESCRIPTION DELAY DELAY DELAY DELAY DELAY CHAIN BUFFER
DELAY FREQUENCY
ENABLE VALUE ENABLE VALUE SELECT DURATION
High 8-bit PHY
Speed operating 1.8 V, 0x0 0x1 0x5 0x1 0x3 0x0 0x4 0x7
DDR 50 MHz
8-bit PHY
HS200 operating 1.8 V, 0x0 0x1 0x6 0x1 Tuning 0x0 0x0 0x7
200 MHz
Table 6-78. MMC1/2 DLL Delay Mapping for All Timing Modes (continued)
REGISTER NAME MMCSD12_SS_PHY_CTRL_4_REG MMCSD12_SS_PHY_CTRL_5_REG
BIT FIELD [20] [15:12] [8] [4:0] [2:0]
BIT FIELD NAME OTAPDLYENA OTAPDLYSEL ITAPDLYENA ITAPDLYSEL CLKBUFSEL
INPUT INPUT DELAY
DELAY DELAY
MODE DESCRIPTION DELAY DELAY BUFFER
ENABLE VALUE
ENABLE VALUE DURATION
UHS-I 4-bit PHY operating
0x1 0xC 0x1 Tuning 0x7
SDR50 1.8 V, 100 MHz
UHS-I 4-bit PHY operating
0x1 0xC 0x1 0x2 0x7
DR50 1.8 V, 50 MHz
UHS-I 4-bit PHY operating
0x1 0x5 0x1 Tuning 0x7
SDR104 1.8, V 200 MHz
td(Trace Mismatch Propagation delay mismatch across all UHS–I DDR50, UHS–I SDR104 20 ps
Delay) traces All other modes 100 ps
MMC[x]_CLK
DS1 DS2
MMC[x]_CMD
DS3 DS4
MMC[x]_DAT[3:0]
DS5
DS6 DS7
MMC[x]_CLK
D S8
MMC[x]_CMD
D S9
MMC[x]_DAT[3:0]
MMC[x]_CLK
HS1 H S2
MMC[x]_CMD
HS3 H S4
MMC[x]_DAT[3:0]
HS5
HS6 HS7
MMC[x]_CLK
H S8
MMC[x]_CMD
H S9
MMC[x]_DAT[3:0]
MMC[x]_CLK
SDR121 SDR122
MMC[x]_CMD
SDR123 SDR124
MMC[x]_DAT[3:0]
SDR125
SDR126 SDR127
MMC[x]_CLK
SDR128 SDR128
MMC[x]_CMD
SDR129 SDR129
MMC[x]_DAT[3:0]
MMC[x]_CLK
SDR251 SDR252
MMC[x]_CMD
SDR253 SDR254
MMC[x]_DAT[3:0]
SDR255
SDR256 SDR257
MMC[x]_CLK
SDR258 SDR258
MMC[x]_CMD
SDR259 SDR259
MMC[x]_DAT[3:0]
SDR505
SDR506 SDR507
MMC[x]_CLK
SDR508 SDR508
MMC[x]_CMD
SDR509 SDR509
MMC[x]_DAT[3:0]
DDR505
DDR506 DDR507
MMC[x]_CLK
DDR508
MMC[x]_CMD
DDR509 DDR509
MMC[x]_DAT[3:0]
SDR1045
SDR1046 SDR1047
MMC[x]_CLK
SDR1048 SDR1048
MMC[x]_CMD
SDR1049 SDR1049
MMC[x]_DAT[3:0]
6.9.5.20 CPTS
Table 6-91 represents CPTS timing conditions.
Table 6-91. CPTS Timing Conditions
PARAMETER DESCRIPTION MIN MAX UNIT
INPUT CONDITIONS
SRI Input slew rate 0.5 5 V/ns
OUTPUT CONDITIONS
CL Output load capacitance 2 10 pF
Section 6.9.5.20.1, Section 6.9.5.20.2, Figure 6-108, and Figure 6-109 present timing requirements and
switching characteristics of the CPTS interface.
6.9.5.20.1 CPTS Timing Requirements
see Figure 6-108
NO. MIN MAX UNIT
T1 tw(HWnTSPUSHH) Pulse duration, HWnTSPUSH(2) high 12P + 2(1) ns
T2 tw(HWnTSPUSHL) Pulse duration, HWnTSPUSH(2) low 12P + 2(1) ns
T3 tc(RFT_CLK) Cycle time, RFT_CLK 5 8 ns
T4 tw(RFT_CLKH) Pulse duration, RFT_CLK high 0.45 * T(3) ns
T5 tw(RFT_CLKL) Pulse duration, RFT_CLK low 0.45 * T(3) ns
T1 T2
HWn_TSPUSH
T3 T4 T5
RFT_CLK
T6 T7
TS_COMP
T8 T9
TS_SYNC
T10 T11
SYNCn_OUT
For more information, see Navigator Subsystem (NAVSS) section in Data Movement Architecture (DMA) chapter
in the device TRM.
6.9.5.21 OSPI
For more details about features and additional description information on the device Octal Serial Peripheral
Interface, see the corresponding sections within Section 5.3, Signal Descriptions and Section 7, Detailed
Description.
Table 6-92 represents OSPI timing conditions.
Table 6-92. OSPI Timing Conditions
PARAMETER MIN MAX UNIT
INPUT CONDITIONS
SRI Input slew rate 3.3 V 2 6 V/ns
All other modes 1 6 V/ns
OUTPUT CONDITIONS
Note
I/O timing requirements and switching characteristics are not applicable when OSPI is used with data
training. Follow the Section 8.3.2, OSPI and QSPI Board Design and Layout Guidelines section to
ensure proper operation.
Note
The I/O Timings provided in this section are only applicable when data training is not implemented.
Additionally, the I/O Timings are valid only for some OSPI usage modes when the corresponding DLL
Delays are configured as described in Table 6-93 found in this section.
Section 6.9.5.21.1.2.4, Section 6.9.5.21.1.2.2, Section 6.9.5.21.1.2, and Section 6.9.5.21.1.2 present switching
characteristics for OSPI DDR and SDR Mode.
6.9.5.21.1.2.1 OSPI Timing Requirements – SDR Mode
Table 6-93. OSPI DLL Delay Mapping - SDR Timing Modes
MODE OSPI_PHY_CONFIGURATION_REG BIT FIELD DELAY VALUE
All modes PHY_CONFIG_TX_DLL_DELAY_FLD 0x0
PHY_CONFIG_RX_DLL_DELAY_FLD 0x0
OSPI_CLK
O19 O20
OSPI_D[i:0]
OSPI_TIMING_05
Figure 6-110. OSPI Timing Requirements – SDR, Internal Clock and Internal Pad Loopback Clock
OSPI_DQS
O21 O22
OSPI_D[i:0]
OSPI_TIMING_06
O10 td(CLK-CSn) Delay time, CLK rising edge to CSn active edge 1.8V 0.475 * P + 0.475 * P + ns
0.975 * N * R 0.975 * N * R
(2) (3) (5) + 1 (3) (3) (5)
3.3V 0.475 * P + 0.475 * P + ns
0.975 * N * R 0.975 * N * R
(2) (3) (5) + 1 (2) (3) (5)
O11 td(CLK-CSn) Delay time, CLK rising edge to CSn inactive 1.8V 0.475 * P + 0.475 * P + ns
edge 0.975 * N * R 0.975 * N * R
- 1 (2) (4) (5) + 1 (2) (4) (5)
3.3V -1+0.475 * P 1+0.475 * P + ns
+ 0.975 * N * 0.975 * N * R
R (2) (4) (5) (2) (4) (5)
O12 td(CLK-D) Delay time, CLK active edge to D[i:0] 1.8V -1.16 1.25 ns
transition(1)
3.3V -1.33 1.51 ns
OSPI_CSn
O10 O7 O11
OSPI_CLK O9 O8
O12
OSPI_D[i:0]
OSPI_TIMING_02
Section 6.9.5.21.1.2.3, Section 6.9.5.21.1.2.1, Section 6.9.5.21.1.2.2, Section 6.9.5.21.1.2.2, and Figure 6-111
presents timing requirements for OSPI DDR and SDR Mode.
6.9.5.21.1.2.3 OSPI Timing Requirements – DDR Mode
Table 6-94. OSPI DLL Delay Mapping - DDR Timing Modes
OSPI_PHY_CONFIGURATION_REG BIT DELAY VALUE
MODE
FIELD OSPI0 OSPI1
Transmit
1.8V PHY_CONFIG_TX_DLL_DELAY_FLD 0x40 0x41
3.3V PHY_CONFIG_TX_DLL_DELAY_FLD 0x3C 0x3E
Receive
1.8V, DQS PHY_CONFIG_RX_DLL_DELAY_FLD 0x13 0x15
3.3V, DQS PHY_CONFIG_RX_DLL_DELAY_FLD 0x1E 0x1E
All other modes PHY_CONFIG_RX_DLL_DELAY_FLD 0x0 0x0
OSPI_DQS
O15 O16
OSPI_D[i:0]
OSPI_TIMING_04
Figure 6-113. OSPI Timing Requirements – DDR, External Loopback Clock and DQS
280 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated
O4 td(CLK-CSn) Delay time, CSn active edge to CLK rising edge 1.8V 0.475 * P + 0.475 * P + ns
0.975 * N * R 0.975 * N * R
(2) (3) (5) + 1 (2) (3) (5)
3.3V 0.475 * P + 0.475 * P + ns
0.975 * N * R 0.975 * N * R
(2) (3) (5) + 1(2) (3) (5)
O5 td(CLK-CSn) Delay time, CLK rising edge to CSn inactive 1.8V 0.475 * P + 0.475 * P + ns
edge 0.975 * N * R 0.975 * N * R
- 7(2) (4) (5) (2) (4) (5)
O6 td(CLK-D) Delay time, CLK active edge to D[i:0] 1.8V, OSPI0 DDR TX; -7.71 -1.56 ns
transition(1) 1.8V, OSPI1 DDR TX
3.3V, OSPI0 DDR TX; -7.71 -1.56 ns
3.3V, OSPI1 DDR TX
OSPI_CSn
O4 O3 O5
OSPI_CLK
O2
O6 O6
O1
OSPI_D[i:0]
OSPI_TIMING_01
(1) T = OSPI_RD_DATA_CAPTURE_REG[DELAY_FLD]
(2) R = reference clock cycle time in ns
OSPI_CLK
O19 O20
OSPI_D[i:0]
OSPI_TIMING_05
OSPI_CSn
O10 O7 O11
OSPI_CLK O9 O8
O12
OSPI_D[i:0]
OSPI_TIMING_02
(1) T = OSPI_RD_DATA_CAPTURE_REG[DELAY_FLD]
(2) R = reference clock cycle time in ns
OSPI_CLK
OSPI_D[i:0]
OSPI_TIMING_03
OSPI_CSn
O4 O3 O5
OSPI_CLK
O2
O6 O6
O1
OSPI_D[i:0]
OSPI_TIMING_01
6.9.5.22 PCIE
The PCI-Express Subsystem is compliant with the PCIe® Base Specification, Revision 4.0. Refer to the
specification for timing details.
For more details about features and additional description information on the device Peripheral Component
Interconnect Express, see the corresponding sections within , Section 5.3, Signal Descriptions and Section 7,
Detailed Description.
For more information, see Peripheral Component Interconnect Express (PCIe) Subsystem section in Peripherals
chapter in the device TRM.
6.9.5.23 Timers
For more details about features and additional description information on the device Timers, see the
corresponding sections within , Section 5.3, Signal Descriptions and Section 7, Detailed Description.
Table 6-99 represents Timers timing conditions.
Table 6-99. Timers Timing Conditions
PARAMETER DESCRIPTION MODE MIN MAX UNIT
INPUT CONDITIONS
SRI Input slew rate CAPTURE 0.5 5 V/ns
Section 6.9.5.23.1, Section 6.9.5.23.2 and Figure 6-119 present timings and switching characteristics of the
Timers.
6.9.5.23.1 Timing Requirements for Timers
T1 T2
TIMER_IOx (inputs)
T3 T4
TIMER_IOx (outputs)
TIMER_01
For more information, see Timers section in Peripherals chapter in the device TRM.
6.9.5.24 UART
For more details about features and additional description information on the device Universal Asynchronous
Receiver Transmitter, see the corresponding sections within , Section 5.3, Signal Descriptions and Section 7,
Detailed Description.
Table 6-100 represents UART timing conditions.
Table 6-100. UART Timing Conditions
PARAMETER DESCRIPTION MIN MAX UNIT
INPUT CONDITIONS
SRI Input slew rate 0.5 5 V/ns
OUTPUT CONDITIONS
CL Output load capacitance 1 30 pF
PCB CONNECTIVITY REQUIREMENTS
td(Trace Mismatch Delay) Propagation delay mismatch across all traces 100 ps
Section 6.9.5.24.1, Section 6.9.5.24.2, and Figure 6-120 present timing requirements and switching
characteristics for UART interface.
6.9.5.24.1 Timing Requirements for UART
For more information, see Universal Asynchronous Receiver/Transmitter (UART) section in Peripherals chapter
in the device TRM.
6.9.5.25 USB
The USB 2.0 subsystem is compliant with the Universal Serial Bus (USB) Specification, revision 2.0. Refer to the
specification for timing details.
The USB 3.1 GEN1 Dual-Role Device Subsystem is compliant with the Universal Serial Bus (USB) 3.1
Specification, revision 1.0. Refer to the specification for timing details.
For more details about features and additional description information on the device Universal Serial Bus
Subsystem (USB), see the corresponding sections within Section 5.3, Signal Descriptions and Section 7,
Detailed Description.
Table 6-102 and Figure 6-121 assume testing over the recommended operating conditions and electrical
characteristic conditions.
Table 6-102. Trace Switching Characteristics
NO. PARAMETER MIN MAX UNIT
1.8 V Mode
DBTR1 tc(TRC_CLK) Cycle time, TRC_CLK 6.50 ns
DBTR2 tw(TRC_CLKH) Pulse width, TRC_CLK high 2.50 ns
DBTR3 tw(TRC_CLKL) Pulse width, TRC_CLK low 2.50 ns
DBTR4 tosu(TRC_DATAV-TRC_CLK) Output setup time, TRC_DATA valid to TRC_CLK edge 0.81 ns
DBTR5 toh(TRC_CLK-TRC_DATAI) Output hold time, TRC_CLK edge to TRC_DATA invalid 0.81 ns
DBTR6 tosu(TRC_CTLV-TRC_CLK) Output setup time, TRC_CTL valid to TRC_CLK edge 0.81 ns
DBTR7 toh(TRC_CLK-TRC_CTLI) Output hold time, TRC_CLK edge to TRC_CTL invalid 0.81 ns
3.3 V Mode
DBTR1 tc(TRC_CLK) Cycle time, TRC_CLK 9.75 ns
DBTR2 tw(TRC_CLKH) Pulse width, TRC_CLK high 4.13 ns
DBTR3 tw(TRC_CLKL) Pulse width, TRC_CLK low 4.13 ns
DBTR4 tosu(TRC_DATAV-TRC_CLK) Output setup time, TRC_DATA valid to TRC_CLK edge 1.22 ns
DBTR5 toh(TRC_CLK-TRC_DATAI) Output hold time, TRC_CLK edge to TRC_DATA invalid 1.22 ns
DBTR6 tosu(TRC_CTLV-TRC_CLK) Output setup time, TRC_CTL valid to TRC_CLK edge 1.22 ns
DBTR7 toh(TRC_CLK-TRC_CTLI) Output hold time, TRC_CLK edge to TRC_CTL invalid 1.22 ns
DBTR1
DBTR2 DBTR3
TRC_CLK
(Worst Case 1)
(Ideal)
(Worst Case 2)
DBTR4 DBTR5 DBTR4 DBTR5
DBTR6 DBTR7 DBTR6 DBTR7
TRC_DATA
TRC_CTL
SPRSP08_Debug_01
6.9.6.2 JTAG
For more details about features and additional description information on the device IEEE 1149.1 Standard–
Test–Access Port, see the corresponding sections within Section 5.3, Signal Descriptions and Section 7,
Detailed Description.
1. The JTAG signals are split across two IO power domains on the device. Timings parameters defined in
this table only apply when the two IO power domains are operating at the same voltage. Values for these
timing parameters are not defined when operating the two IO power domains at different voltages since
propagation delay through the device IO buffers differ when some are operating at 1.8V while others are
operating at 3.3V. This effectively reduces timing margin beyond the values defined in this table. The JTAG
interface is still expected to function when the two IO power domains are operated at different voltages,
assuming the system designer has implemented appropriate level shifters and the operating frequency is
reduced to accommodate additional delay inserted by the level-shifters and IO buffers operating at different
voltages.
6.9.6.2.1.2 JTAG Switching Characteristics
See Figure 6-122
NO. PARAMETER MIN MAX UNIT
J6 td(TCKL-TDOI) Delay time minimum, TCK low to TDO invalid 0 ns
J7 td(TCKL-TDOV) Delay time maximum, TCK low to TDO valid 37.75 ns
1. The JTAG signals are split across two IO power domains on the device. Timings parameters defined in
this table only apply when the two IO power domains are operating at the same voltage. Values for these
timing parameters are not defined when operating the two IO power domains at different voltages since
propagation delay through the device IO buffers differ when some are operating at 1.8V while others are
operating at 3.3V. This effectively reduces timing margin beyond the values defined in this table. The JTAG
interface is still expected to function when the two IO power domains are operated at different voltages,
assuming the system designer has implemented appropriate level shifters and the operating frequency is
reduced to accommodate additional delay inserted by the level-shifters and IO buffers operating at different
voltages.
J1
J2 J3
TCK
J4 J5 J4 J5
TDI / TMS
J7
J6
TDO
7 Detailed Description
7.1 Overview
DRA829 Jacinto™ 7 processors, based on the Arm®v8 64-bit architecture, provide advanced system integration
to enable lower system costs of applications such as Infotainment, Cluster, Premium Audio, and Gateway . The
integrated diagnostics and functional safety features are targeted to ASIL-B/C certification/requirements. The
integrated microcontroller (MCU) island eliminates the need for an external system MCU. The device features a
Gigabit Ethernet switch and a PCIe hub which enables networking use cases that require heavy data bandwidth.
The hardware accelerators allow for vision pre-processing, distance and motion processing with minimal impact
on system performance. Up to six Arm® Cortex®-R5F subsystems manage low level, timing critical processing
tasks leaving the Arm® Cortex®-A72’s unencumbered for applications. A dual-core cluster configuration of
Arm® Cortex®-A72 facilitates multi-OS applications with minimal need for a software hypervisor.
Note
For more information on features, subsystems, and architecture of superset device System on Chip
(SoC), see the device TRM.
Media Independent Interface (RGMII), Reduced Media Independent Interface (RMII), and the Management Data
Input/Output (MDIO) interface for physical layer device (PHY) management.
For more information, see Gigabit Ethernet Switch (CPSW0) section in Peripherals chapter in the device TRM.
7.4.5.5 CPSW9G
The 9-port Gigabit Ethernet Switch (CPSW0) subsystem provides Ethernet packet communication for the device
and can be configured as an Ethernet switch. CPSW0 features the Serial Gigabit Media Independent Interface
(SGMII), Reduced Gigabit Media Independent Interface (RGMII), Reduced Media Independent Interface (RMII)
and the Management Data Input/Output (MDIO) interface for physical layer device (PHY) management.
For more information, see Gigabit Ethernet Switch (MCU_CPSW0) section in Peripherals chapter in the device
TRM.
7.4.5.6 DCC
The Dual Clock Comparator (DCC) is used to determine the accuracy of a clock signal during the time
execution of an application. Specifically, the DCC is designed to detect drifts from the expected clock frequency.
The desired accuracy can be programed based on calculation for each application. The DCC measures the
frequency of a selectable clock source using another input clock as a reference.
For more information, see Dual Clock Comparator (DCC) section in Peripherals chapter in the device TRM.
7.4.5.7 DDRSS
The DDR subsystem in this device comprises DDR controller, DDR PHY and wrapper logic to integrate these
blocks in the device. The DDR subsystem is referred to as DDRSS0 and is used to provide an interface to
external SDRAM devices which can be utilized for storing program or data. DDRSS0 is accessed via MSMC,
and not directly through the system interconnect.
For more information, see DDR Subsystem (DDRSS) section in Peripherals chapter in the device TRM.
7.4.5.8 DSS
The DSS is a flexible composition-enabled display subsystem, that supports multiple high resolution display
outputs. It consists of one Display Controller (DISPC) and one Frame Buffer Decompression Core (FBDC).
The DISPC supports a multi-layer blending and transparency for each of its display outputs. The DISPC also
supports a write-back pipeline with scaling to enable memory-to-memory composition and/or to capture a display
output for Ethernet video encoding.
For more information, see Display Subsystem (DSS) section in Peripherals chapter in the device TRM.
7.4.5.8.1 DSI
The MIPI DSI v1.3.1 Controller (DSITX) implements the stream arbitration and low-level protocol layer
functionalities required by MIPI DSI 1.3 standard. It supports up to 4 x 2.5 Gbps D-PHY data lanes in a single-
link configuration and handles the byte lane mapping per use case (1, 2, 3, or 4-lanes). The accompaning DSI
(Physical Layer) D-PHY module (DPHYTX) provides the video output interfacing by implementing a four-lane
MIPI D-PHY transmitter.
For more information, see Display Subsystem (DSS) and Display Peripherals section in Peripherals chapter in
the device TRM.
7.4.5.8.2 eDP
The VESA DP1.4/eDP1.4 Compliant Transmitter Host Controller (EDP) can output up to 4 video streams
(through Multiple Stream Transport / MST) and one audio stream through the 4-lane accompaning SerDes
module. It provides up to 25.92 Gbps of application bandwidth. An additional eDP (Physical Layer) auxiliary PHY
(AUXPHY) module implements a doubly-terminated differential pair required for 1 Mbps data rates over a long
(15m) cable.
For more information, see Display Subsystem (DSS) and Display Peripherals section in Peripherals chapter in
the device TRM.
7.4.5.9 VPFE
The Video Processing Front End (VPFE) is an input interface module that receives raw (unprocessed) image/
video data or YUV digital video data from external imaging peripherals (such as image sensors, video decoders,
etc) and performs DMA transfers to store the captured data in the system DDR memory.
For more information, see Video Processing Front End (VPFE) section in Peripherals chapter in the device TRM.
7.4.5.10 eCAP
The enhanced Capture (ECAP) module can be used for:
• Sample rate measurements of audio inputs
• Speed measurements of rotating machinery (for example, toothed sprockets sensed via Hall sensors)
• Elapsed time measurements between position sensor pulses
• Period and duty cycle measurements of pulse train signals
• Decoding current or voltage amplitude derived from duty cycle encoded current/voltage sensors.
For more information, see Enhanced Capture (ECAP) Module section in Peripherals chapter in the device TRM.
7.4.5.11 EPWM
An effective PWM peripheral must be able to generate complex pulse width waveforms with minimal CPU
overhead or intervention. It needs to be highly programmable and very flexible while being easy to understand
and use. The EPWM unit described here addresses these requirements by allocating all needed timing and
control resources on a per PWM channel basis. Cross coupling or sharing of resources has been avoided;
instead, the EPWM is built up from smaller single channel modules with separate resources and that can
operate together as required to form a system. This modular approach results in an orthogonal architecture and
provides a more transparent view of the peripheral structure, helping users to understand its operation quickly.
In the further description the letter x within a signal or module name is used to indicate a generic EPWM instance
on a device. For example, output signals EPWMxA and EPWMxB refer to the output signals from the EPWM_x
instance. Thus, EPWM1A and EPWM1B belong to EPWM1, EPWM2A and EPWM2B belong to EPWM2, and so
forth.
Additionally, the EPWM integration allows this synchronization scheme to be extended to the capture peripheral
modules (ECAP). The number of modules is device-dependent and based on target application needs. Modules
can also operate stand-alone.
For more information, see Enhanced Pulse Width Modulation (EPWM) Module section in Peripherals chapter in
the device TRM.
7.4.5.12 ELM
The Error Location Module (ELM) is used with the GPMC. Syndrome polynomials generated on-the-fly when
reading a NAND flash page and stored in GPMC registers are passed to the ELM. A host processor can then
correct the data block by flipping the bits to which the ELM error-location outputs point.
When reading from NAND flash memories, some level of error-correction is required. In the case of NAND
modules with no internal correction capability, sometimes referred to as bare NANDs, the correction process is
delegated to the memory controller. ELM can be also used to support parallel NOR flash or NAND flash.
For more information, see Error Location Module (ELM) section in Peripherals chapter in the device TRM.
7.4.5.13 ESM
The Error Signaling Module (ESM) aggregates safety-related events and/or errors from throughout the device
into one location. It can signal both low and high priority interrupts to a processor to deal with a safety event
and/or manipulate an I/O error pin to signal an external hardware that an error has occurred. Therefore an
external controller is able to reset the device or keep the system in safe, known state.
For more information, see Error Signaling Module (ESM) section in Peripherals chapter in the device TRM.
7.4.5.14 eQEP
The Enhnanced Quadrature Encoder Pulse (EQEP) peripheral is used for direct interface with a linear or rotary
incremental encoder to get position, direction and speed information from a rotating machine for use in high
performance motion and position control system. The disk of an incremental encoder is patterned with a single
track of slots patterns. These slots create an alternating pattern of dark and light lines. The disk count is
defined as the number of dark/light line pairs that occur per revolution (lines per revolution). As a rule, a second
track is added to generate a signal that occurs once per revolution (index signal: QEPI), which can be used
to indicate an absolute position. Encoder manufacturers identify the index pulse using different terms such as
index, marker, home position and zero reference.
For more information, see Enhanced Quadrature Encoder Pulse (EQEP) Module section in Peripherals chapter
in the device TRM.
7.4.5.15 GPIO
The General-Purpose Input/Output (GPIO) peripheral provides dedicated general-purpose pins that can be
configured as either inputs or outputs. When configured as an output, the user can write to an internal register to
control the state driven on the output pin. When configured as an input, user can obtain the state of the input by
reading the state of an internal register.
In addition, the GPIO peripheral can produce host CPU interrupts and DMA synchronization events in different
interrupt/event generation modes.
For more information, see General-Purpose Interface (GPIO) section in Peripherals chapter in the device TRM.
7.4.5.16 GPMC
The General-Purpose Memory Controller is a unified memory controller dedicated for interfacing with external
memory devices like:
• Asynchronous SRAM-like memories and application-specific integrated circuit (ASIC) devices
• Asynchronous, synchronous, and page mode (available only in non-multiplexed mode) burst NOR flash
devices
• NAND flash
• Pseudo-SRAM devices
For more information, see General-Purpose Memory Controller (GPMC) section in Peripherals chapter in the
device TRM.
7.4.5.17 Hyperbus
The Hyperbus module is a part of the device Flash Subsystem (FSS).
The Hyperbus module is low pin count memory interface that provides high read/write performance. The
Hyperbus module connects to hyperbus memory (HyperFlash or HyperRAM) and uses simple hyperbus protocol
for read and write transactions.
There is one Hyperbus™ module inside the device. The Hyperbus module includes one Hyperbus Memory
Controller (HBMC).
For more information, see Hyperbus Interface section in Peripherals chapter in the device TRM.
7.4.5.18 I2C
The device contains ten multimaster Inter-Integrated Circuit (I2C) controllers each of which provides an interface
between a local host (LH), such as an Arm or a Digital Signal Processor (DSP), and any I2C-bus-compatible
device that connects via the I2C serial bus. External components attached to the I2C bus can serially transmit
and receive up to 8 bits of data to and from the LH device through the 2-wire I2C interface.
Each multimaster I2C module can be configured to act like a slave or master I2C-compatible device.
The WKUP_I2C0, MCU_I2C0, I2C0, and I2C1 controllers have dedicated I2C compliant open drain buffers, and
support high speed mode (up to 3.4 Mbps in 1.8 V mode and up to 400 kbps in 3.3 V mode). The MCU_I2C1,
I2C2, I2C3, I2C4, I2C5, and I2C6 controllers are multiplexed with standard LVCMOS I/O, connected to emulate
open drain, and support fast mode (up to 400 kbps in 1.8 V/3.3 V mode). The I2C emulation is achieved by
configuring the LVCMOS buffers to output Hi-Z instead of driving high when transmitting logic 1.
For more information, see Inter-Integrated Circuit (I2C) Interface section in Peripherals chapter in the device
TRM.
7.4.5.19 I3C
The device contains three Improved Inter-Integrated Circuit (I3C) controllers each of which provides an interface
between a local host (LH), such as an Arm, and any I3C-bus-compatible device that connects via the I3C serial
bus.
For more information, see Improved Inter-Integrated Circuit (I3C) Interface section in Peripherals chapter in the
device TRM.
7.4.5.20 MCAN
The Controller Area Network (CAN) is a serial communications protocol which efficiently supports distributed
real-time control. CAN has high immunity to electrical interference. In a CAN network, many short messages are
broadcast to the entire network, which provides for data consistency in every node of the system.
The MCAN module supports both classic CAN and CAN FD (CAN with Flexible Data-Rate) specifications. CAN
FD feature allows high throughput and increased payload per data frame. The classic CAN and CAN FD devices
can coexist on the same network without any conflict.
For more information, see Modular Controller Area Network (MCAN) section in Peripherals chapter in the device
TRM.
7.4.5.21 MCASP
The MCASP functions as a general-purpose audio serial port are optimized to the requirements of various audio
applications. The MCASP module can operate in both transmit and receive modes. The MCASP is useful for
time-division multiplexed (TDM) stream, Inter-IC Sound (I2S) protocols reception and transmission as well as
for an inter-component digital audio interface transmission (DIT). The MCASP has the flexibility to gluelessly
connect to a Sony/Philips digital interface (S/PDIF) transmit physical layer component.
Although inter-component digital audio interface reception (DIR) mode (this is, S/PDIF stream receiving) is not
natively supported by the MCASP module, a specific TDM mode implementation for the MCASP receivers allows
an easy connection to external DIR components (for example, S/PDIF to I2S format converters).
For more information, see Multichannel Audio Serial Port (MCASP) section in Peripherals chapter in the device
TRM.
7.4.5.22 MCRC Controller
VBUSM CRC controller is a module which is used to perform CRC (Cyclic Redundancy Check) to verify the
integrity of a memory system. A signature representing the contents of the memory is obtained when the
contents of the memory are read into MCRC Controller. The responsibility of MCRC controller is to calculate
the signature for a set of data and then compare the calculated signature value against a predetermined good
signature value. MCRC controller provides four channels to perform CRC calculation on multiple memories in
parallel and can be used on any memory system. Channel 1 can also be put into data trace mode, where MCRC
controller compresses each data being read through CPU read data bus.
For more information, see MCRC Controller section in Interprocessor Communication chapter in the device
TRM.
7.4.5.23 MCSPI
The MCSPI module is a multichannel transmit/receive, master/slave synchronous serial bus.
In the MCU domain the device provides 10 timer pins to be used as MCU Timer Capture inputs or as MCU Timer
PWM outputs. In order to provide maximum flexibility, these 10 pins may be used with any of MCU_TIMER0
through MCU_TIMER9 instances. System level muxes are used to control the capture source pin for each
MCU_TIMER[9-0] and the MCU_TIMER[9-0] source for each MCU_TIMER_IO[1-0] PWM output.
In the MAIN domain the device provides 8 timer pins to be used as Timer Capture inputs or as Timer PWM
outputs. For maximum flexibility, these 8 pins may be used with any of TIMER0 through TIMER19 instances.
System level muxes are used to control the capture source pin for each TIMER[19-0] and the TIMER[19-0]
source for each TIMER_IO[7-0] PWM output.
Each odd numbered timer instance from each of the domains may be optionally cascaded with the previous
even numbered timer instance from the same domain to form up to a 64-bit timer. For example, TIMER1 may be
cascaded to TIMER0, MCU_TIMER1 may be cascaded to MCU_TIMER0, etc.
When cascaded, TIMERi acts as a 32-bit prescaler to TIMERi+1, as well as MCU_TIMERn acts as a 32-bit
prescaler to MCU_TIMERn+1. TIMERi / MCU_TIMERn must be configured to generate a PWM output edge at
the desired rate to increment the TIMERi+1/ MCU_TIMERn+1 counter.
For more information, see Timers section in Peripherals chapter in the device TRM.
7.4.5.30 UART
The UART is a slave peripheral that utilizes the DMA for data transfer or interrupt polling via host CPU. There
are twelve UART modules in the device. All UART modules support IrDA and CIR modes when 48 MHz function
clock is used. Each UART can be used for configuration and data exchange with a number of external peripheral
devices or interprocessor communication between devices.
For more information, see Universal Synchronous/Asynchronous Receiver/Transmitter (UART) section in
Peripherals chapter in the device TRM.
7.4.5.31 USB
Similar to earlier versions of USB bus, USB 3.0 is a general-purpose cable bus, supporting data exchange
between a host device and a wide range of simultaneously accessible peripherals.
The device supports two identical USB subsystems:
• USB3SS0 is SuperSpeed (SS) USB 3.0 Dual-Role-Device (DRD) subsystem with on-chip SS (USB3.0) PHY
and HS/FS/LS (1) (USB2.0) PHY
• USB3SS1 is SuperSpeed (SS) USB 3.0 Dual-Role-Device (DRD) subsystem with on-chip SS (USB3.0) PHY
and HS/FS/LS (USB2.0) PHY
For more information, see Universal Serial Bus (USB) Subsystem section in Peripherals chapter in the device
TRM.
7.4.5.32 UFS
The Universal Flash Storage (UFS) interface is a standard-based serial interface engine.
There is one UFS module inside the device - UFS0. The UFS module includes one UFS 2.1 host controller (HC)
with an integrated M-PHY.
The UFS module complies with the standards as listed in Table 7-1.
Table 7-1. UFS Standards
DOCUMENT VERSION DESCRIPTION
JESD220-1A v1.1 Universal Flash Storage (UFS) Unified Memory Extension
JESD220-2 v1.0 Universal Flash Storage (UFS) Card Extension
JESD220C v2.1, March 2016 Universal Flash Storage (UFS)
JESD223-1B v1.1A Universal Flash Storage Host Controller Interface (UFSHCI) Unified Memory
Extension
JESD223C v2.1, March 2016 Universal Flash Storage Host Controller Interface (UFSHCI)
For more information, see Universal Flash Storage (UFS) Interface section in Peripherals chapter in the device
TRM.
Table 8-1. Combined MCU and Main Voltage Domain Power Rail Mapping
DOMAIN
TYPES VOLTAGE [V] DOMAIN NAMES POWER RAILS #
GROUPS
(VDDSHV0_MCU,
VDDSHV1_MCU,
VDDSHVn_MC
VDDSHV2_MCU,
U,VDDSHVn,
Digital IO 3.3 VDDSHV0,VDDSHV1, VDD_IO_3V3 1
VDDA_3P3_US
VDDSHV2, VDDSHV3,
B4
VDDSHV4, VDDSHV53,
1
VDDSHV6) , VDDA_3P3_USB 4
(VDDSHV0_MCU,
VDDSHV1_MCU,
VDDSHV2_MCU, VDDSHV0, VDDSHVn_MC
Digital IO 1.8 VDD_IO_1V8 2
VDDSHV1, VDDSHV2, U2 VDDSHVn3 2
VDDSHV, VDDSHV4,
VDDSHV53, VDDSHV6)2
Digital IO 1.8 VDDS_MMC06 VDDS_MMC06 VDDS_MMC0_1V86 3
(VDDA_1P8_CSIRX,
VDDA_1P8_USB,
VDDA_1P8_UFS,
VDDA_1P8_<p
Analog PHY 1.8 VDDA_1P8_DP, VDD_PHY_1V85 4
hy>5
VDDA_1P8_DSITX,
VDDA_1P8_MLB,
VDDA_1P8_SERDES)
VDDA_MCU_PLLGRP0,
VDDA_MCU_TEMP,
VDDA_ADC_MCU,
Analog Clk, VDDA_1P8_<cl
1.8 VDDA_POR_WKUP, VDA_LN_1V8 5
Meas k/meas>
VDDA_WKUP VDDS_OSC1,
VDDA_PLLGRP6:0,
VDDA_TEMP3:0
VDDA_0P8_PLL_MLB,
Analog, low VDDA_0P8_DP
0.80 VDDA_0P8_PLL_DDR, VDA_DPLL_0V8 6
voltage LL
VDDA_0P8_DLL_MMC0
Digital, AVS low
0.77 – 0.84 VDD_CPU VDD_CPU VDD_CPU_AVS 7
voltage
VDD_MCU7, VDD_CORE,
(VDDA_0P8_SERDES,
VDDA_0P8_SERDES_C,
VDDA_0P8_DP, VDD_MCU
Digital, low VDDA_0P8_DP_C, VDD_CORE
0.80 VDD_PROC_0V8 8
voltage VDDA_0P8_DSITX, VDDA_0P8_<p
VDDA_0P8_DSITX_C, hy>8
VDDA_0P8_CSIRX,
VDDA_0P8_UFS,
VDDA_0P8_USB) 8
VDDAR_MCU,
Digital, low
0.85 VDDAR_CORE, VDDAR VDD_RAM_0V85 9
voltage
VDDAR_CPU
VDDS_DDR_BIAS,
Digital, low
1.1 VDDS_DDR, VDDS_DDR VDD_DDR_1V1 10
voltage
VDDS_DDR_C
1. Any MCU or Main dual voltage IO supplies (VDDSHVn_MCU or VDDSHVn) being supplied by 3.3V to
support 3.3V digital interfaces
2. Any MCU or Main dual voltage IO supplies (VDDSHVn_MCU or VDDSHVn) being supplied by 1.8V to
support 1.8V digital interfaces
3. VDDSHV5 supports MMC1 signaling for SD memory cards. A dual voltage (3.3/1.8V) power rail is required
for compliant, high-speed SD card operations. If SD card is not needed or standard data rates with fixed
3.3V operation is acceptable, then domain can be grouped with digital IO 3.3V power rail. If a SD card is
capable of operating with fixed 1.8V, then domain can be grouped with digital IO 1.8V power rail.
4. VDDA_3P3_USB is 3.3V analog domain used for USB 2.0 differential interface signaling. A low noise,
analog supply is recommended to provide best signal integrity for USB data eye mask compliance. If USB
interface is not needed or data bit errors can be tolerated, then domain can be grouped with 3.3V digital IO
power rail either directly or through a supply filter.
5. VDDA_1P8_<phy> are 1.8V analog domains supporting multiple serial PHY interfaces. A low noise, analog
supply is recommended to provide best signal integrity, interface performance and spec compliance. If any of
these interfaces are not needed, data bit errors or non-compliant operation can be tolerated, then domains
can be grouped with digital IO 1.8V power rail either directly or through an in-line supply filter is allowed.
6. VDD_MMC0 is 1.8V digital supply supporting MMC0 signaling for eMMC interface. If MMC0 or eMMC0
interface is not needed, then domain can be grouped with digital IO 1.8V power rail. However, if MMC0
interface is needed, then VDD_MMC0 must not start ramp-up until VDD_CORE has reached Vopr min.
7. VDD_MCU is a digital voltage supply with a wide operational voltage range and power sequencing flexibility,
enabling it to be grouped and ramped-up with either 0.8V VDD_CORE or 0.85V RAM array domains
(VDDAR_xxx).
8. VDDA_1P8_<clk/pll/ana> are 1.8V analog domains supporting clock oscillator, PLL and analog circuitry
needing a low noise supply for optimal performance.
Table 8-2. Isolated MCU and Main Voltage Domain Power Rail Mapping
DOMAIN
TYPES VOLTAGE [V] DOMAIN NAMES POWER RAILS #
GROUPS
(VDDSHV0_MCU,
VDDSHVn_MC
Digital IO 3.3 VDDSHV1_MCU, VDD_MCUIO_3V3 1
U
VDDSHV2_MCU)1
(VDDSHV0, VDDSHV1,
VDDSHVn,
VDDSHV2, VDDSHV3,
Digital IO 3.3 VDDA_3P3_US VDD_IO_3V3 2
VDDSHV4, VDDSHV53,
B4
VDDSHV6)1, VDDA_3P3_USB4
(VDDSHV0_MCU,
VDDSHVn_MC
Digital IO 1.8 VDDSHV1_MCU, VDD_MCUIO_1V8 3
U2
VDDSHV2_MCU)2
(VDDSHV0, VDDSHV1,
VDDSHV2, VDDSHV3,
Digital IO 1.8 VDDSHVn2 3 VDD_IO_1V8 4
VDDSHV4, VDDSHV53,
VDDSHV6)2
Digital IO 1.8 VDDS_MMC06 VDDS_MMC06 VDDS_MMC0_1V86 5
VDDA_MCU_PLLGRP0,
VDDA_MCU_TEMP,
Analog Clk, VDDA_MCU1P
1.8 VDDA_ADC_MCU, VDA_MCU_1V8 6
Meas 8_<clk/meas>
VDDA_POR_WKUP,
VDDA_WKUP
VDDS_OSC1,
Analog Clk, VDDA_1P8_<cl
1.8 VDDA_PLLGRP6:0, VDA_DPLL_1V8 7
Meas k/meas>
VDDA_TEMP3:0
(VDDA_1P8_CSIRX,
VDDA_1P8_USB,
VDDA_1P8_UFS,
VDDA_1P8_<p
Analog PHY 1.8 VDDA_1P8_DP, VDA_PHY_1V85 8
hy>5
VDDA_1P8_DSITX,
VDDA_1P8_MLB,
VDDA_1P8_SERDES)5
VDDA_0P8_PLL_MLB,
Analog, low VDDA_0P8_DP
0.80 VDDA_0P8_PLL_DDR, VDA_DPLL_0V8 9
voltage LL
VDDA_0P8_DLL_MMC0
Digital, low VDD_MCU,
0.80 VDD_MCU, VDDAR_MCU VDD_MCU_0V85 10
voltage VDDAR_MCU
Digital, AVS low 0.77 – 0.84 vdd_cpu VDD_CPU VDD_CPU_AVS 11
voltage
Table 8-2. Isolated MCU and Main Voltage Domain Power Rail Mapping (continued)
DOMAIN
TYPES VOLTAGE [V] DOMAIN NAMES POWER RAILS #
GROUPS
Digital, low 0.80 VDD_CORE, VDD_CORE, VDD_CORE_0V8 12
voltage (VDDA_0P8_SERDES, VDDA_0P8_<p
VDDA_0P8_SERDES_C, hy>8
VDDA_0P8_DP,
VDDA_0P8_DP_C,
VDDA_0P8_DSITX,
VDDA_0P8_DSITX_C,
VDDA_0P8_CSIRX,
VDDA_0P8_UFS,
VDDA_0P8_USB)8
Digital, low 0.85 VDDAR_CORE, VDDAR_CPU VDDAR VDD_RAM_0V85 13
voltage
Digital, low 1.1 VDDS_DDR_BIAS,VDDS_DDR, VDDS_DDR VDD_DDR_1V1 14
voltage VDDS_DDR_C
1. Any MCU or Main dual voltage IO supplies (VDDSHVn_MCU or VDDSHVn) being supplied by 3.3V to
support 3.3V digital interfaces
2. Any MCU or Main dual voltage IO supplies (VDDSHVn_MCU or VDDSHVn) being supplied by 1.8V to
support 1.8V digital interfaces
3. VDDSHV5 supports MMC1 signaling for SD memory cards. A dual voltage (3.3/1.8V) power rail is required
for compliant, high-speed SD card operations. If SD card is not needed or standard data rates with fixed
3.3V operation is acceptable, then domain can be grouped with digital IO 3.3V power rail. If a SD card is
capable of operating with fixed 1.8V, then domain can be grouped with digital IO 1.8V power rail.
4. VDDA_3P3_USB is 3.3V analog domain used for USB 2.0 differential interface signaling. A low noise,
analog supply is recommended to provide best signal integrity for USB data eye mask compliance. If USB
interface is not needed or data bit errors can be tolerated, then domain can be grouped with 3.3V digital IO
power rail either directly or through a supply filter.
5. VDDA_1P8_<phy> are 1.8V analog domains supporting multiple serial PHY interfaces. A low noise, analog
supply is recommended to provide best signal integrity, interface performance and spec compliance. If any of
these interfaces are not needed, data bit errors or non-compliant operation can be tolerated, then domains
can be grouped with digital IO 1.8V power rail either directly or through an in-line supply filter is allowed.
6. VDD_MMC0 is 1.8V digital supply supporting MMC0 signaling for eMMC interface. If MMC0 or eMMC0
interface is not needed, then domain can be grouped with digital IO 1.8V power rail. However, if MMC0
interface is needed, then VDD_MMC0 must not start ramp-up until VDD_CORE has reached VOPR MIN.
7. VDD_MCU is a digital voltage supply with a wide operational voltage range and power sequencing flexibility,
enabling it to be grouped and ramped-up with either 0.8V VDD_CORE or 0.85V RAM array domains
(VDDAR_xxx).
8. VDDA_1P8_<clk/pll/ana> are 1.8V analog domains supporting clock oscillator, PLL and analog circuitry
needing a low noise supply for optimal performance.
8.2 Device Connection and Layout Fundamentals
8.2.1 Power Supply Decoupling and Bulk Capacitors
8.2.1.1 Power Distribution Network Implementation Guidance
The Jacinto 7 Processor Power Distribution Networks: Implementation and Analysis (SPRACN5) provides
guidance for successful implementation of the power distribution network. This includes PCB stackup guidance
as well as guidance for optimizing the selection and placement of the decoupling capacitors. TI supports only
designs that follow the board design guidelines contained in the application report.
8.2.2 External Oscillator
For more information, see Section 6.9.4.1, Input and output Clocks/Oscillators.
A B
R1
0 Ω*
OSPI/QSPI/SPI
MCU_OSPI[x]_CLK
device clock input
MCU_OSPI[x]_D[y], OSPI/QSPI/SPI
MCU_OSPI[x]_CSn[z] device IOy, CS#
OSPI_Board_01
* 0 Ω resistor (R1), located as close as possible to the MCU_OSPI[x]_CLK pin, is placeholder for fine tuning, if needed.
Note
The OSPI Board Loopback Hold time requirement (described in Section 6.9.5.21, OSPI) is larger than
the Hold time provided by a typical flash device. Therefore, the length of MCU_OPSI[x]_LBCLKO pin
to the MCU_OSPI[x]_DQS pin (C to D) can be shortened to compensate.
A B
R1
0 Ω*
OSPI/QSPI/SPI
MCU_OSPI[x]_CLK
device clock input
C
R1
0 Ω*
MCU_OSPI[x]_LBCLKO
MCU_OSPI[x]_DQS
E F
MCU_OSPI[x]_D[y], OSPI/QSPI/SPI
MCU_OSPI[x]_CSn[z] device IOy, CS#
OSPI_Board_02
* 0 Ω resistor (R1), located as close as possible to the MCU_OSPI[x]_CLK and MCU_OSPI[x]_LBCLKO pins, is a placeholder for fine
tuning, if needed.
A B
R1
0 Ω*
OSPI/QSPI/SPI
MCU_OSPI[x]_CLK
device clock input
C D
E F
MCU_OSPI[x]_D[y], OSPI/QSPI/SPI
MCU_OSPI[x]_CSn[z] device IOy, CS#
J7ES_OSPI_Board_03
* 0 Ω resistor (R1), located as close as possible to the MCU_OSPI[x]_CLK pin, is a placeholder for fine tuning, if needed.
Device
USBn_VBUS
16.6 kΩ 3.4 kΩ
±1% ±1%
VBUS signal
10 kΩ
±1% 6.8V
(BZX84C6V8 or equivalent)
VSS VSS
J7ES_USB_VBUS_01
A. USBn_VBUS, where n = 0 or 1.
The USB0_VBUS and USB1_VBUS pins can be considered to be fail-safe because the external circuit in Figure
8-4 limits the input current to the actual device pin in a case where VBUS is applied while the device is powered
off.
8.3.5 System Power Supply Monitor Design Guidelines
The VMON_ER_VSYS pin provides a way to monitor a system power supply. This system power supply is
typically a single pre-regulated power source for the entire system. This supply is monitored by comparing
the output of an external voltage divider circuit sourced by this supply with an internal voltage reference, with
a power fail event being triggered when the voltage applied to VMON_ER_VSYS drops below the internal
reference voltage. The actual system power supply voltage trip point is determined by the system designer when
selecting component values used to implement the external resistor voltage divider circuit. When designing the
resistor divider circuit it is important to understand various factors which contribute to variability in the system
power supply monitor trip point. The first thing to consider is the initial accuracy of the VMON_ER_VSYS input
threshold which has a nominal value of 0.45 V, with a variation of ±3%. Precision 1% resistors with similar
thermal coefficient are recommended for implementing the resistor voltage divider. This minimizes variability
contributed by resistor value tolerances. Input leakage current associated with VMON_ER_VSYS must also be
considered since any current flowing into the pin creates a loading error on the voltage divider output. The
VMON_ER_VSYS input leakage current may be in the range of 10 nA to 2.5 μA when applying 0.45 V.
Note
The resistor voltage divider shall be designed such that its output voltage never exceeds themaximum
value defined in Section 6.4 , Recommended Operating Conditions during normal operating
conditions.
Figure 8-5 presents an example, where the system power supply is nominally 5 V and the maximum trigger
threshold is 5 V - 10%, or 4.5 V.
For this example, it is important to understand which variables effect the maximum trigger threshold when
selecting resistor values. It is obvious a device which has a VMON_ER_VSYS input threshold of 0.45 V + 3%
needs to be considered when trying to design a voltage divider that doesn’t trip until the system supply drops
10%. The effect of resistor tolerance and input leakage also needs to be considered, but how these contributions
effect the maximum trigger point may not be obvious. When selecting component values which produce a
maximum trigger voltage, the system designer must consider a condition where the value of R1 is 1% low and
the value of R2 is 1% high combined with a condition where input leakage current for the VMON_ER_VSYS pin
is 2.5 μA. When implementing a resistor divider where R1 = 4.81 KΩ and R2 = 40.2 KΩ, the result is a maximum
trigger threshold of 4.523 V.
Once component values have been selected to satisfy the maximum trigger voltage as described above, the
system designer can determine the minimum trigger voltage by calculating the applied voltage that produces an
output voltage of 0.45 V - 3% when the value of R1 is 1% high and the value of R2 is 1% low, and the input
leakage current is 10 nA, or zero. Using an input leakage of zero with the resistor values given above, the result
is a minimum trigger threshold of 4.008 V.
This example demonstrates a system power supply voltage trip point that ranges from 4.008 V to 4.523 V.
Approximately 250 mV of this range is introduced by VMON_ER_VSYS input threshold accuracy of ±3%,
approximately 150 mV of this range is introduced by resistor tolerance of ±1%, and approximately 100 mV of this
range is introduced by loading error when VMON_ER_VSYS input leakage current is 2.5 μA.
The resistor values selected in this example produces approximately 100 μA of bias current through the resistor
divider when the system supply is 4.5 V. The 100 mV of loading error mentioned above could be reduced to
about 10 mV by increasing the bias current through the resistor divider to approximately 1 mA. So resistor
divider bias current vs loading error is something the system designer needs to consider when selecting
component values.
The system designer should also consider implementing a noise filter on the voltage divider output since
VMON_ER_VSYS has minimum hysteresis and a high-bandwidth response to transients. This could be done
by installing a capacitor across R1 as shown in Figure 8-5. However, the system designer must determine the
response time of this filter based on system supply noise and expected response to transient events.
Figure 8-5 presents an example, when the system power supply voltage is nominally 5 V and the desired trigger
threshold is -10% or 4.5 V.
Device
VMON_VSYS
R2
VSYS
40.2 kΩ ±1% (System Power Supply)
R1 4.81 kΩ
C1
±1%
Value = Determined by system designer
VSS
SPRSP56_VMON_ER_MON_01
TMDX Development-support product that has not yet completed Texas Instruments internal qualification testing.
TMDS Fully-qualified development-support product.
X and P devices and TMDX development-support tools are shipped against the following disclaimer:
"Developmental product is intended for internal evaluation purposes."
Production devices and TMDS development-support tools have been characterized fully, and the quality and
reliability of the device have been demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (X or P) have a greater failure rate than the standard production
devices. Texas Instruments recommends that these devices not be used in any production system because their
expected end-use failure rate still is undefined. Only qualified production devices are to be used.
For orderable part numbers of DRA829 devices in the ALF package type, see the Package Option Addendum of
this document, the TI website (ti.com), or contact your TI sales representative.
9.1.1 Standard Package Symbolization
Note
Some devices may have a cosmetic circular marking visible on the top of the device package which
results from the production test process. In addition, some devices may also show a color variation in
the package substrate which results from the substrate manufacturer. These differences are cosmetic
only with no reliability impact.
xBBBBBBBBzYrPPPcQ1
PIN ONE INDICATOR XXXXXXX
YYY ZZZ G1
O
J7ES_SPRSP35_PACK_01
(1) J721E is the base part number for the preproduction superset device. Software should constrain the features used to match the
intended production device.
(2) For HS device support, TI recommends the 0, 5, or D device types. The R and P (HS “prime”) device types are not recommended for
most applications, as they require extra steps in the manufacturing process and have a higher cost.
Note
BLANK in the symbol or part number is collapsed so there are no gaps between characters.
9.7 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
10 Revision History
Changes from August 28, 2021 to April 22, 2024 (from Revision J (August 2021) to Revision K
(April 2024)) Page
• Global:: Updated document title........................................................................................................................ 1
• Global: Added Silicon Revision 2.0 (SR2.0) device-specific info throughout the document..............................1
• Global:: Moved the Revision History section to the back of the document........................................................1
• Global:: Deleted all OLDI/LVDS content; n/a to this device suite...................................................................... 1
• Global:: Deleted the "Power Consumption Summary" section (was after Section 6.5, Operating Performance
Points).................................................................................................................................................................1
• (Features): Updated/Changed the Integrated Ethernet switch bullets and sub-bullets...................................... 1
• (Description): Updated the lead-in sentence...................................................................................................... 2
• (Package Information): Updated/Changed the "Device Information" table to "Package Information" table and
revamped table content to new format............................................................................................................... 2
• (Functional Block Diagram): Added SDK software build sheet Note..................................................................3
• (Device Comparison): Updated/Changed the MSMC capacity for DRA829VM to "8MB". Now both DRA829JM
and DRA829VM devices are "8MB (On-Chip SRAM with ECC)"....................................................................... 6
• (Device Comparison): Moved the "Security Accelerators" row to be group sequenced with the other
accelerator rows and to match other device comparison tables within this device suite....................................6
• (Device Comparison): Added SDK software build sheet Note........................................................................... 6
• (Pin Attributes): Added the secondary pin multiplexing functions for the DSI and controlled by CTRLMMR
regs...................................................................................................................................................................10
• (Pin Attributes): Added the secondary pin multiplexing functions for the MCU_ADC and controlled by
CTRLMMR regs................................................................................................................................................10
• (Pin Attributes): Added "The MUXMODE field is not used to select …" footnote for the WKUP_GPIO0_[68:83]
signals in the Pin Attributes table..................................................................................................................... 10
• (Pin Attributes): Added reset states to the BALL RESET STATE column for mmc0_* pins in the Pin Attributes
table.................................................................................................................................................................. 10
• (WKUP Domain GPIO0 Signal Descriptions): Added missing WKUP_GPIO0_[68:83] signals........................82
• (Power Supply Signal Description): Added "±10%" to the "This pin must always be … capacitor to
VSS" footnote................................................................................................................................................. 128
• (Connections for Unused Pins): Added the "VMON_ER_VSYS" (M26) and "VMON_IR_VEXT" (V19) signals
to the "Each of these balls must be connected to VSS .." CONNECTIONS REQUIREMENT description.... 147
• (Connections for Unused Pins): Updated/Changed "All VMON and power balls must be …" Note deleting
"VMON and"................................................................................................................................................... 147
• (Pin Connectivity Requirements): Updated/Changed the section title (was "Connections for Unused Pins") 147
• (Connectivity Requirements (ALF Package)): Updated/Changed the table title (was "Unused Balls Specific
Connection Requirements")............................................................................................................................147
• (Pin Connectivity Requirements): Added "as a boot source" to the Note specifying MMC1_SDCD and
MMC2_SDCD should be pulled down to work properly................................................................................. 147
• (Absolute Maximum Ratings): Moved "VMON_IR_VEXT" and "VMON_ER_VSYS"signals from "Steady State
Max. Voltage at all other IO pins" to "Steady State Max. Voltage at all fail-safe IO pins".............................. 150
• Added the "VMON_IR_VEXT" and "VMON_ER_VSYS"signals to the "Fail-safe IO terminals are designed …"
paragraph....................................................................................................................................................... 150
• (Absolute Maximum Ratings): Updated/Changed "JESD78D (Class II)" to " JESD78E (Class II)" in the "For
current pulse injection: .." footnote................................................................................................................. 150
• Updated/Changed the UNIT specified for the Latch-Up Performance MAX parameter from "mV" to "V"...... 150
• (ESD Ratings): Added the AEC - Q100 document revision letter to both HBM and CDM rows.....................153
• (Recommended Operating Conditions): Deleted the "Refer to Power-On-Hour (POH) Limits for limitations."
footnote and associated cross-reference....................................................................................................... 153
• (I2C, Open-Drain, Fail-Safe (I2C OD FS) Electrical Characteristics): Updated/Changed the VOL, Output low-
level voltage MAX value under the 3.3-V MODE from "0.4 × VDDSHV" to "0.4" V........................................157
• (I2C OD FS Electrical Characteristics): Added a footnote to explain the IOL parameter................................ 157
• (I2C OD FS Electrical Characteristics): Defined MAX VIH values for 1.8-V mode and 3.3-V mode and included
a footnote that describes how these values are also defined in the absolute maximum input voltage.......... 157
• (I2C OD FS Electrical Characteristics): Added the MIN input slew rate value and added associated footnotes
to describe the SRI parameter for 1.8-V MODE............................................................................................. 157
• (I2C OD FS Electrical Characteristics): Added both the MIN and MAX input slew rate value and added
associated footnotes to describe the SRI parameter for 3.3-V MODE........................................................... 157
• (I2C OD FS Electrical Characteristics): Added associated "I2C Hs-mode is not supported …" footnote to the
3.3-V MODE table section.............................................................................................................................. 157
• (I2C OD FS Electrical Characteristics): Added associated "The IOL parameter defines …" footnote to the IOL,
low level output current parameter for both 1.8-V MODE and 3.3-V MODE.................................................. 157
• (SDIO Electrical Characteristics): Added the MIN input slew rate value and added associated footnotes to
describe the SRI parameter for 1.8-V MODE................................................................................................. 159
• (SDIO Electrical Characteristics): Added both the MIN and MAX input slew rate value and added associated
footnotes to describe the SRI parameter for 3.3-V MODE............................................................................. 159
• (CSI-2/DSI D-PHY Electrical Characteristics): Updated the section title........................................................160
• (CSI-2/DSI D-PHY Electrical Characteristics): Deleted the Electrical Characteristics table and added a Note
for the CSI-2/DSI D-PHY interfaces electrical characteristics compliance with MIPI D-PHY specifications v1.2
dated August 1, 2014..................................................................................................................................... 160
• (LVCMOS Electrical Characteristics): Added a footnote to explain the IOL and IOH parameters.................... 162
• (LVCMOS Electrical Characteristics): Added the MIN input slew rate value and added associated footnotes to
describe the SRI parameter for 1.8-V MODE................................................................................................. 162
• (LVCMOS Electrical Characteristics): Added both the MIN and MAX input slew rate value and added
associated footnotes to describe the SRI parameter for 3.3-V MODE........................................................... 162
• (LVCMOS Electrical Characteristics): Defined the minimum input slew rate value and added notes to describe
this parameter.................................................................................................................................................162
• (SerDes 4-L-PHY/2-L-PHY Electrical Characteristics): Updated/Changed the section title........................... 163
• (2-L-PHY SERDES REFCLK Electrical Characteristics): Added missing table..............................................163
• (UFS M-PHY Electrical Characteristics): Added missing section title............................................................ 165
• (eDP/DP AUX-PHY Electrical Characteristics): Added missing section title.................................................. 165
• (WKUP_OSC0 Switching Characteristics – Crystal Mode): Updated/Changed CXIXO, XI to XO Mutual
Capacitance MAX value from "0.9fF" to "0.1pF"............................................................................................ 192
• (WKUP_LFOSC0 Internal Oscillator Clock Source): Updated/Changed the ESR row UNIT column from "Ω" to
"kΩ" in the WKUP_LFOSC0 Crystal Electrical Characteristics table..............................................................200
• (LFXOSC Modes of Operation table): Updated/Changed the value of PD_C for BYPASS mode from "X" to
"0"................................................................................................................................................................... 200
• (DDRSS): Added a bullet below the JEDEC JESD209-4B standard compliant LPDDR4 SDRAM devices
features currently supported bullets............................................................................................................... 218
• (GPIO): Updated/Changed the GPIO Timings Conditions table and associated footnote..............................224
• (GPIO Timing Requirements): Updated/Changed the GPIO Timings Requirements table............................ 225
• (GPIO Switching Characteristics): Updated/Changed the GPIO Switching Characteristics table..................225
• (MMC1/2 - SD/SDIO Interface): Updated/Changed the "OTAPDLYENA, DELAY ENABLE" and
"OTAPDLYSEL, DELAY VALUE" for the Default Speed and High Speed modes from "0x0" to "0x1"........... 267
• (OSPI DLL Delay Mapping - DDR Timing Modes): Updated/Changed the DELAY VALUES for both OSPI0
and OSPI1 and re-worked the Table formatting view..................................................................................... 280
• (OSPI Tap Mode): Added new section........................................................................................................... 282
• (OSPI Timing Requirements – Tap SDR Mode): Added new section.............................................................282
• (OSPI Timing Requirements – Tap DDR Mode): Added new section............................................................ 284
• (Nomenclature Description): Added "C" value to the "r, Device revision" row to represent SR 2.0 parts.......314
• (Device Naming Convention): Added content to the "Base production part number" Values plus Description
and "Device Type" Description columns of the Nomenclature Description table............................................314
• (Tools and Software/Development Tools): Deleted the Clock Tree Tool reference and content.....................315
• (Documentation Support): Updated/Changed the document titles for both the TRM and Errata to include
Silicon Revisions 2.0, 1.1, and still 1.0........................................................................................................... 316
www.ti.com 2-Oct-2024
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)
DRA829JMTGBALFR ACTIVE FCBGA ALF 827 250 RoHS & Green Call TI Level-3-250C-168 HR -40 to 105 DRA829JMTGBALF Samples
942
DRA829JMTGBALFRQ1 ACTIVE FCBGA ALF 827 250 RoHS & Green Call TI Level-3-250C-168 HR -40 to 125 DRA829JMTGBALFQ1 Samples
942
DRA829VMTGBALFR ACTIVE FCBGA ALF 827 250 RoHS & Green Call TI Level-3-250C-168 HR -40 to 105 DRA829VMTGBALF Samples
942
DRA829VMTGBALFRQ1 ACTIVE FCBGA ALF 827 250 RoHS & Green Call TI Level-3-250C-168 HR -40 to 125 DRA829VMTGBALFQ1 Samples
942
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 2-Oct-2024
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 13-Jun-2024
B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers
Sprocket Holes
Q1 Q2 Q1 Q2
Pocket Quadrants
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 13-Jun-2024
Width (mm)
H
W
Pack Materials-Page 2
PACKAGE OUTLINE
ALF0827A SCALE 0.650
FCBGA - 2.8 mm max height
PLASTIC BALL GRID ARRAY
24.1 A
B
23.9
BALL A1 CORNER
( 20) 24.1
23.9
( 18)
2.8 MAX
SEATING PLANE
0.5 BALL TYP
TYP 0.15 C
0.3
22.4 TYP
SYMM (0.8) TYP
AJ
AH
AG (0.8) TYP
AF
AE
AD
AC
AB
AA
Y
W
V
U
T SYMM
22.4 R
P
TYP N
M
L
K
J
H
G 835X 0.45-0.55
F
E 0.15 C A B
D
C 0.08 C
B
A
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29
0.8 TYP 2 4 6 8 10 12 14 16 18 20 22 24 26 28
BALL A1 CORNER 0.8 TYP 4224732/B 02/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Pb-Free die bump and Pb-Free solder ball.
www.ti.com
EXAMPLE BOARD LAYOUT
ALF0827A FCBGA - 2.8 mm max height
PLASTIC BALL GRID ARRAY
C
(0.8) TYP
D
E
F
G
H
J
K
L
M
N
P SYMM
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
AG
AH
AJ
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
4. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For information, see Texas Instruments literature number SPRU811 (www.ti.com/lit/spru811).
www.ti.com
EXAMPLE STENCIL DESIGN
ALF0827A FCBGA - 2.8 mm max height
PLASTIC BALL GRID ARRAY
A
B
(0.8) C
TYP D
E
F
G
H
J
K
L
M
N
P SYMM
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
AG
AH
AJ
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
4224732/B 02/2019
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
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