Digital Electronics Experiment No.

1. Implementation of following logic expression using minimum numbers

of NAND Gates:

Apparatus: Digital training kit, Power supply, Connecting Wires, IC 7400

(NAND Gate IC).

Before Implementing the above experiment, we need to understand basic

and universal logic gates.

Theory: Logic Gates are electronic circuits to perform logical operations.

Each Gate can have one (for NOT Gate) or multiple input variables (for all
other Gates) and generate one output. AND, OR and NOT Gates are basic
logic Gates; NAND and NOR are called Universal logic Gates; Apart from
that there are two more special Gates XOR and XNOR. The input
combinations of a logic Gate and corresponding output can be written in
a Tabular form, which is called Truth Table. Various Gates, their Symbols,
and Truth Tables are illustrated in Table1.

IC configurations: In this experiment, we will use IC 7400 (NAND Gate IC).

The IC configuration is illustrated in the figures below -

Figure 1: 7400 IC Configurations.

 Table1

Being universal Gates, NAND and NOR can be used to implement any
logic Gate; In below examples, we show the Implementation of different
Logic Gates (AND, OR, NOT, NOR) using NAND Gates.
Experiment: Implementation of following logic expression using AOI logic and
then implement using minimum numbers of NAND Gates:

Truth Table:

0 0 0 0 1 1
0 0 1 0 0 0
0 1 0 0 1 1
0 1 1 0 0 0
1 0 0 0 1 1
1 0 1 0 0 0
1 1 0 1 1 1
1 1 1 1 0 1

Simplification:
 Digital Electronics Experiment No: 2

To verify the working principle of 8:1 Multiplexer Objective:

Design the following Boolean function using 8:1 multiplexer: ( , ,

) = Σ (0, 2, 4, 6, 7)

Components and Equipment required: Digital IC trainer kit, IC’s (74151) &
connecting wires.

Theory:
n
A multiplexer is a combinational circuit that has 2 input lines and a single
output line. Simply, the multiplexer is a multi-input and single-output
combinational circuit. The binary information is received from the input lines
and directed to the output line. On the basis of the values of the selection
lines, one of these data inputs will be connected to the output. So,there are n
n
selection lines and 2 input lines.

IC PINOUT:
●D0- D7 (PIN 1-4, 12-15) are the Input.

●S2, S1, S0 (PIN 9-11) are the select lines.

● VCC (PIN 16) is the bias voltage.

●GND (PIN 8) is the ground.
● Y (PIN 5) is the output PIN

Truth Table:
Select Outp
lines ut
S2 S1 S0 F
0 0 0 D0
0 0 1 D1
0 1 0 D2
0 1 1 D3
1 0 0 D4
1 0 1 D5
1 1 0 D6
1 1 1 D7

Truth table to be implemented:

Inpu Outp
ts ut
X Y Z F
0 0 0 1
0 0 1 0
 0 1 0 1
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 1

If we map S2, S1, S0 to X, Y, Z respectively, then

Inp Outp
uts ut
S2 S1 Y S0 F
X Z
0 0 0 D0
1
0 0 1 D1
0
0 1 0 D2
1
0 1 1 D3
0
1 0 0 D4
1
1 0 1 D5
0
1 1 0 D6
1
1 1 1 D7
1
 Experiment 3

Aim: Design a 2-bit asynchronous counter using JK Flip-Flop (IC 7473).

Apparatus: Digital trainer kit, Power supply, Connecting wires, IC 7473.

Theory: The flip-flop is a basic bi-stable memory element widely used in
sequential logic circuits. Usually there are two outputs, Q and its
complementary value. They are called state variables. State variables
which change only between logic 1 and logic 0 are calledbinary state
variables. There are two types of triggering are considered in the JK flip
flop; Positive and Negative edge triggering.
For a positive-edge triggered JK flip-flop:
● If the J and K inputs change while the clock transitions from
low to high, the flip-flop will respond to those changes.
● If the J and K inputs change while the clock is in a high state,
the changes will not affect the flip-flop's state until the next rising
edge of the clock.
For a negative-edge triggered JK flip-flop:
If the J and K inputs change while the clock transitions from high
 to low, the flip-flop will respond to those changes.
If the J and K inputs change while the clock is in a low state, the
changes will not affect the flip- flop's state until the next falling edge of
the clock.
In JK flip-flop is a type of flip-flop circuit that has two inputs, J (set) and K
(reset). When the clear input is activated, it overrides the behavior of the flip-
flop and forces its outputs to a ‘LOW’ state and is the set input is particularly
useful when you want to initialize or force a ‘HIGH ‘in a sequential circuit.

JK Flip Flop
1. Assemble the circuit for testing the behavior of JK flip
flop. Pin connections are shownabove.
2.Set J=0, K=1, provide Clock pulse. Note logic level of Q and Q’
3.Set J=0, K=0, provide Clock pulse. Note logic level of Q and Q’
4.Set J=1, K=0, provide Clock pulse. Note logic level of Q and Q’
5.Set J=0, K=0, provide Clock pulse. Note logic level of Q and Q’
6.Set J=1, K=1, provide Clock pulse. Note logic level of Q and Q’
7. Again provide Clock pulse without changing the J & K
inputs i.e. keep J=1, K=1. Note logiclevel of Q and Q’.
Repeat this step 2-3 times.
8.Check the output with CLR pin.
9.Prepare the truth table of the JK flip flop for all the possible input combinations.
10. Write your observations indicating for which J & K inputs,
the flip flop Q output is set to ‘1’and reset to ‘0’

2- bit Asynchronous Counter

 1. Wire up the two flip flops of IC 7473 as shown.
2. Connect the Q outputs of the flip flops to LED indicators on the
kit. In the above diagram,Flip flop Q1 provides the MSB and Q0
provides the LSB of the counter.
3. Connect the common CLR line of the two flips through a switch on
the trainer Kit.
4. At the beginning reset the Q outputs of the two flips by switching
the CLR line to “LOW”level and then to “HIGH”. Keep it HIGH
thereafter for rest of the performance.
5. Now Pulse the CLK_IN line on the trainer kit and note down the Q1 &
Q0.
6. Keep on pulsing the CLK_IN line and note the direction of count.
7. In the above diagram Q output of first flop is connected as CLK input to
second flip flop. Nowchange the CLK input of second flip flop to
output of first flop. Now pulse the CLK_IN line of the counter again and
note the direction of count noting the Q1 & Q0 outputs of the two flip flo

Experiment.4

Aim: Study the operation of diode rectifier circuits & clipper circuit using diodes.

Apparatus required :
Items
P
N
ju
nc
 ti
o
n
Di
o
de

St
ep

d
o
w
n
tr
a
ns
fo
r
m
er
Br
ea
d
b
o
ar
d
D
S
O
/
C
R
O
AC
voltag
e
sourc
e
Resist
ors
Jumper wires

Theory:
Diode Rectifier Circuits
One of the important applications of a semiconductor diode is in
rectification of AC signals to DC. Diodes are very commonly used for
obtaining DC voltage supplies from the readily available AC voltage. There
are many possible ways to construct rectifier circuits using diodes. The basic
 types of rectifier circuits are:
The

Hal
f
Wa
ve
Rec
tifie
r
The

Full

Wa
ve
Rec
tifie
r

Half-wave Rectifier
This is the simplest form of rectifier. Often using only a single diode is
blocks half the cycle and allows through the other. As such only half of the
waveform is used. A simple half-wave rectifier using an ideal diode and a
load is shown in Figure 4.1
Since the diode only conducts when the anode is positive with respect
to the cathode, current will flow only during the positive half cycle of the
input voltage. The output of this rectifier gives a pulsating DC signal.

Figure 4.1 Half wave rectifier with input & output wave

forms The supply voltage is given by:

AC input = Vs = Vm sinὼt
Where
ὼ=2πf=2π/T= is the angular frequency in rad/s
We are interested in obtaining DC voltage across the “load resistance” RL.
We notice that the output voltage varies between the peak voltage Vm and
zero in each cycle. This variation is called “ripple”, and the corresponding
voltage is called the peak-to-peak ripple voltage, Vp-p.
Clipper Circuit
The clipper circuit can be designed by utilizing both the
linear and nonlinear elements such as resistors, diodes or
transistors. The Diode Clipper, also known as a Diode Limiter, is a
wave shaping circuit that takes an input waveform and clips or
cuts off its top half, bottom half or both halves together.
In general, clippers are classified into two types: Series Clippers and Shunt
Clippers.

Series Clippers:

Series Negative Clipper

Fig 4.2 Series Negative ClipperFig 4.3 Series Positive Clipper

The figure (Fig 4.2) shows a series negative clipper with its
 output waveforms. During
the positive half cycle the diode (considered as ideal diode)
appears in the forward biased and conducts such that the entire
positive half cycle of input appears across the resistor connected
in parallel as output waveform. During the negative half cycle the
diode is in reverse biased. No output appears across the resistor.
Thus, it clips the negative half cycle of the input waveform, and
therefore, it is called as a series negative clipper.

Series Positive Clipper

The series positive clipper circuit is connected as shown in
the figure (Fig 4.3). During the positive half cycle, diode becomes
reverse biased, and no output is generated across the resistor, and
during the negative half cycle, the diode conducts and the entire
input appears as output across the resistor.

Parallel Clippers:

Parallel Positive Clipper (Fig. 4.4)

In this diode clipping circuit, the diode is forward biased

(anode more positive than cathode) during the positive half cycle
of the sinusoidal input waveform. For the diode to become
forward biased, it must have the input voltage magnitude greater
than +0.7 volts (0.3 volts for a germanium diode).
When this happens the diodes begins to conduct and holds
the voltage across itself constant at 0.7V until the sinusoidal
waveform falls below this value. Thus the outputvoltage which is
taken across the diode can never exceed 0.7 volts during the
positive half cycle.
During the negative half cycle, the diode is reverse biased
(cathode more positive than anode) blocking current flow through
itself and as a result has no effect on the negative half of

the sinusoidal voltage which passes to the load unaltered. Then the
diode limits the positive half of the input waveform and is known as a
positive clipper circuit.

Fig 4.4 Parallel positive ClipperFig 4.5 Parallel Negative Clipper

Parallel Negative Clipper (Fig. 4.5)

Here the reverse is true. The diode is forward biased during
the negative half cycle of the sinusoidal waveform and limits or
clips it to -0.7 volts while allowing the positive half cycle to pass
unaltered when reverse biased. As the diode limits the negative
half cycle of the input voltage it is therefore called a negative
clipper circuit.

Procedure
1. Make the connections as shown in figures.
2. Connect the primary side of transformer to AC mains & secondary side
to the circuit input. Get the connections checked from teacher incharge
3. Now, connect an oscilloscope at the input & output of the circuit and
display these input & output signal on oscilloscope.
4. Observe the output using CRO/DSO.
5. Plot these input and output voltage waveforms on a graph paper.

Experiment based on Analog Electronics: 05

Aim: Study the switching characteristics of bipolar transistors (BJT) and

calculate the delay time, rise time, ON time, storage time, fall time, OFF
time.
Apparatus required:
ItemsQuantity
Transistor (BC107)1
Resistors (68K, 2.2K, 1K)1each
Capacitor (0.1uF)1
DC variable power supply 1
CRO/DSO 2
Breadboard 1
Jumper wiresas per requirement
Theory
One of the most fundamental applications of a transistor is using it
to control the flow of power to another part of the circuit – using it as an
electric switch. Driving it in either cut-off or saturation mode, the transistor
can create the binary on/off effect of a switch.

Cut-off Region
Here the operating conditions of the transistor are zero input base
current ( IB ), zero output collector current ( IC ) and maximum collector
voltage ( VCE ) which results in a large depletion layer and no current flowing
through the device. Therefore the transistor is switched “Fully-OFF”.

•The input and Base are grounded (0v)

•Base-Emitter voltage VBE < 0.7v
•Base-Emitter junction is reverse biased
•Base-Collector junction is reverse biased
•Transistor is “fully-OFF” (Cut-off region)
•No Collector current flows ( IC = 0 )
•VOUT = VCE = VCC = ”1″
•Transistor operates as an “open switch”

Figure 2.1 Transistor in Cut-off Region

Then we can define the “cut-off region” or “OFF mode” when using a bipolar
transistor as a switch as being, both junctions reverse
biased, VB < 0.7v and IC = 0. For a PNP transistor, the Emitter potential must
be negative with respect to the Base.

Saturation Region
Here the transistor will be biased so that the maximum amount of
base current is applied, resulting in maximum collector current resulting in
the minimum collector emitter voltage drop which results in the depletion
layer being as small as possible and maximum current flowing through the
 transistor. Therefore the transistor is switched “Fully-ON”.
•The input and Base are connected to VCC
•Base-Emitter voltage VBE > 0.7v
•Base-Emitter junction is forward biased
•Base-Collector junction is forward biased
.Transistor is “fully-ON” (saturation region)
•Max Collector current flows ( IC = Vcc/RL )
•VCE = 0 (ideal saturation)
•VOUT = VCE =”0″
•Transistor operates as a “closed switch”

Figure 2.2 Transistor in saturation Region

Then we can define the “saturation region” or “ON mode” when using
a bipolar transistor as a switch as being, both junctions forward
biased, VB > 0.7v and IC = Maximum. For a PNP transistor, the Emitter
potential must be positive with respect to the Base.
A transistor cannot be turned on instantaneously because of
presence of internal capacitances. The figure shows the switching
waveforms of an NPN transistor with resistive load between collector and
emitter.
When base-emitter voltage is VBE is applied, the base current rises to I
BS . The collector current however remains zero or equal to collector-emitter

leakage current ICE0 as shown in figure.

Figure 2.3 Circuit diagram of transistor as a switch with input/output

waveforms

After some time delay td called delay time, the collector current
begins to rise. This delay is due to the time required to charge base emitter
capacitance to VBES=0.7V. After this delay td, Collector current rises to
steady state value ICS in time tr, which is known as “Rise Time” . This means
 that turn on time for BJT is
ton = td + tr .

Rise time depends upon the input capacitance. During rise time tr, Collector-
emitter voltage falls from VCC to VCES. When the base-emitter voltage VBE is
removed at time t 1, the collector current doesn’t change for a time ts , called
“Storage time”.
During ts, saturating charge is removed from the base. After ts,
collector current begins to fall and at the same time collector voltage
starts building up. After time tf , called “Fall Time”. I C decreases to I CE0
(Almost zero) and collector-emitter voltage rises to VCC . Sum of “Storage
time” and “fall time” gives “Turn off” time.
toff = ts + tf

Procedure

1. Connect the circuit as shown in figure 2.3

2. Set input (say 5V, 100KHZ) using a function generator.
3. Observe the output at collector of transistor using CRO/DSO.
4. Note down the parameters listed above and plot it on a graph paper.

Result:
The Switching characteristics of the transistor have been studied and the
required parameters are observed.

Precautions:
1. All the Connections should be tight
2. While doing the experiment do not exceed the ratings of the transistor. This
may lead to damage of the transistor.
3. Transistor terminals must be identified and connected carefully.
4. Switch “ON “the power supply after completing the circuit.