unit 2

UNIT III
SYNCHRONOUS SEQUENTIAL LOGIC
Sequential Circuits - Storage Elements: Latches , Flip-Flops - Analysis of Clocked Sequential Circuits - State
Reduction and Assignment - Design Procedure - Registers and Counters - HDL Models of Sequential
Circuits
SEQUENTIAL CIRCUITS
Sequential circuits:
➢ Sequential circuits employ storage elements in addition to logic gates. Their outputs are a function of
the inputs and the state of the storage elements.
➢ Because the state of the storage elements is a function of previous inputs, the outputs of a sequential
circuit depend not only on present values of inputs, but also on past inputs, and the circuit behavior
must be specified by a time sequence of inputs and internal states.
Types of sequential circuits:

There are two main types of sequential circuits, and their classification is a function ofthe timing
of their signals.
1. Synchronous sequential circuit:
It is a system whose behaviorcan be defined from the knowledge of its signals at discrete
instants of time.
2. Asynchronous sequential circuits:
The behaviorof an asynchronous sequential circuit depends upon the input signals at any
instant of timeand the order in which the inputs change. The storage elements commonly used
in asynchronoussequential circuits are time-delay devices.
LATCHES AND FLIP FLOPS

Flip-Flop:
➢ The storage elements (memory) used in clocked sequential circuits are called flipflops. A flip-flop is
a binary storage device capable of storing one bit of information. In a stable state, the output of a flip-
flop is either 0 or 1.
➢ A sequential circuit may use many flip-flops to store as many bits as necessary. The block diagram of
a synchronous clocked sequential circuit is shown in Fig.
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CS3351/ DPCO/ Dr.J.Rajalakshmi/SRM MCET
➢ A storage element in a digital circuit can maintain a binary state indefinitely (as long as power is
delivered to the circuit), until directed by an input signal to switch states.
➢ The major differences among various types of storage elements are in the number of inputs they
possess and in the manner in which the inputs affect the binary state.
Latch:
➢ The storage elements that operate with signal levels (rather than signal transitions) are referred to as
latches; those controlled by a clock transition are flip-flops.Latches are said to be level sensitive
devices; flip-flops are edge-sensitive devices.
SR Latch: Using NOR gate
Realize SR Latch using NOR and NAND gates and explain its operation.
➢ The SR latch is a circuit with two cross-coupled NOR gates or two cross-coupled NAND gates, and
two inputs labeled S for set and R for reset.
➢ The SR latch constructed with two cross-coupled NOR gates is shown in Fig.
➢ The latch has two useful states. When output Q = 1 and Q’= 0, the latch is said to be in the set state .
When Q = 0 and Q’ = 1, it is in the reset state . Outputs Q and Q’ are normally the complement of
each other.
➢ However, when both inputs are equal to 1 at the same time, a condition in which both outputs are
equal to 0 (rather than be mutually complementary) occurs.
➢ If both inputs are then switched to 0 simultaneously, the device will enter an unpredictable or
undefined state or a metastable state. Consequently, in practical applications, setting both inputs to 1
is forbidden.
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FLIP FLOPS
Triggering of Flip Flops:
Explain about triggering of flip flops in detail.
➢ The state of a latch or flip-flop is switched by a change in the control input. This momentary change
is called a trigger, and the transition it causes is said to trigger the flip-flop.
Level Triggering:
➢ SR, D, JK and T latches are having enable input.
➢ Latches are controlled by enable signal, and they are level triggered, either positive level triggered or
negative level triggered as shown in figure (a).
➢ The output is free to change according to the input values, when active level is maintained at the
enable input.
Edge Triggering:
➢ A clock pulse goes through two transitions: from 0 to 1 and the return from 1 to 0.
➢ As shown in above Fig (b) and (c)., the positive transition is defined as the positive edge and the
negative transition as the negative edge.
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Explain the operation of flipflops.(Nov 2017)
FLIP FLOP CONVERSIONS
The purpose is to convert a given type A FF to a desired type B FF using some conversion logic.
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The key here is to use the excitation table, which shows the necessary triggering signal (S,R, J,K, D and
T) for a desired flipflop state transition :
Excitation table for all flip flops:
1. SR Flip Flop to JK Flip Flop

The truth tables for the flip flop conversion are given below. The present state is represented by
Qp and Qp+1 is the next state to be obtained when the J and K inputs are applied.
For two inputs J and K, there will be eight possible combinations. For each combination of J, K and Qp,
the corresponding Qp+1 states are found. Qp+1 simply suggests the future values to be obtained by the
JK flip flop after the value of Qp.
The table is then completed by writing the values of S and R required to get each Qp+1 from the
corresponding Qp. That is, the values of S and R that are required to change the state of the flip flop from
Qp to Qp+1 are written.
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2.JK Flip Flop to SR Flip Flop
This will be the reverse process of the above explained conversion. S and R will be the external
inputs to J and K. As shown in the logic diagram below, J and K will be the outputs of the combinational
circuit. Thus, the values of J and K have to be obtained in terms of S, R and Qp. The logic diagram is
shown below.
A conversion table is to be written using S, R, Qp, Qp+1, J and K. For two inputs, S and R, eight
combinations are made. For each combination, the corresponding Qp+1 outputs are found. The outputs
for the combinations of S=1 and R=1 are not permitted for an SR flip flop. Thus the outputs are
considered invalid and the J and K values are taken as “don’t cares”.
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3.SR Flip Flop to D Flip Flop
As shown in the figure, S and R are the actual inputs of the flip flop and D is the external input of
the flip flop. The four combinations, the logic diagram, conversion table, and the K-map for S and R in
terms of D and Qp are shown below.
4.D Flip Flop to SR Flip Flop

D is the actual input of the flip flop and S and R are the external inputs. Eight possible
combinations are achieved from the external inputs S, R and Qp. But, since the combination of S=1 and
R=1 are invalid, the values of Qp+1 and D are considered as “don’t cares”. The logic diagram showing
the conversion from D to SR, and the K-map for D in terms of S, R and Qp are shown below.
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5.JK Flip Flop to T Flip Flop
J and K are the actual inputs of the flip flop and T is taken as the external input for conversion.
Four combinations are produced with T and Qp. J and K are expressed in terms of T and Qp. The
conversion table, K-maps, and the logic diagram are given below.
6.JK Flip Flop to D Flip Flop

D is the external input and J and K are the actual inputs of the flip flop. D and Qp make four
combinations. J and K are expressed in terms of D and Qp. The four combination conversion table, the
K-maps for J and K in terms of D and Qp, and the logic diagram showing the conversion from JK to
D are given below.
7.D Flip Flop to JK Flip Flop

AUQ: How will you convert a D flip-flop into JK flip-flop? (AUQ: Dec 2009,11,Apr 2017)
In this conversion, D is the actual input to the flip flop and J and K are the external inputs. J, K
and Qp make eight possible combinations, as shown in the conversion table below. D is expressed in
terms of J, K and Qp.The conversion table, the K-map for D in terms of J, K and Qp and the logic
diagram showing the conversion from D to JK are given in the figure below.
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MEALY AND MOORE MODELS
Write short notes on Mealy and Moore models in sequential circuits.

➢ In synchronous sequential circuit the outputs depend upon the order in which its input variables
change and can be affected at discrete instances of time.
General Models:
➢ There are two models in sequential circuits. They are:
1. Mealy model
2. Moore model
Moore machine:
➢ In the Moore model, the outputs are a function of present state only.
Mealy machine:
➢ In the Mealy model, the outputs are a function of present state and external inputs.
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Difference between Moore model and Mealy model.
Example:
A sequential circuit with two ‘D’ Flip-Flops A and B, one input (x) and one output (y).
The Flip-Flop input functions are:
DA= Ax+ Bx
DB= A’x and
the circuit output function is, Y= (A+ B) x’.
(a) Draw the logic diagram of the circuit, (b) Tabulate the state table, (c) Draw the state diagram.
Solution:
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State table:
State diagram:
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TWO MARKS
1. Difference between Combinational & Sequential Circuits.
S .no Combinational Circuits Sequential Circuits
1 The output at all times depends only on The output not only depends on the present
the present combination of input input but also depends on the past history input
variables. variables.
2 Memory unit is not Required Memory unit is required to store the past
history of input variable
3 Clock input is not needed. Clock input is needed.
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4 Faster in Speed Speed is Slower
5 Easy to design. Difficult to design. Eg: Shift Register,
Eg:Mux, Demux, Encoder, Decoder, Counters.
Adders, Subtractors.
2. What are the classifications of sequential circuits?

The sequential circuits are classified on the basis of timing of their signals in to two types. They are
1) Synchronous sequential circuit.2) Asynchronous sequential circuit.
3. Define Latch.
The basic unit for storage is Latch. A Latch maintain its output state either at 1or 0 until directed by
an input signal to change its state.
4. Define a flip flop.
A flip-flop is a storage device capable of storing one bit of information. It has two states either 0 or 1.
It is also called bistable multivibrator.
5. What are the different types of flip-flop?
The various types of flip flops are 1). SR flip-flop 2). D flip-flop 3). JK flip-flop 4). T flip-flop
6. What is the main difference between a latch and flip flop?
✓ The output of latch changes immediately when its input changes.
✓ The output of a flip-flop changes only when its clock pulse is active and its input changes.
Input changes do not affect output if its clock is not activated.
7. State few application of Flip-Flop.
✓ Used as a memory element.
✓ Used as delay elements.
✓ Data transfer
✓ Used as a building block in sequential circuits such as counters and registers.
8. What is the operation of D flip-flop?
In D flip-flop during the occurrence of clock pulse if D=1, the output Q is set and if D=0, the output
is reset. Set – 1, Reset – 0.
9. What is the operation of JK flip-flop?
When K input is low and J input is high the Q output of flip-flop is set.
When K input is high and J input is low the Q output of flip-flop is reset.
When both the inputs K and J are low the output does not change
When both the inputs K and J are high it is possible to set or reset the flip-flop(ie) the output toggle
onthe next positive clock edge.
10. What is the operation of T flip-flop? (Nov 2018)
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T flip-flop is also known as Toggle flip-flop. 1). When T=0 there is no change in the output. 2). When
T=1 the output switch to the complement state (ie) the output toggles.
11. Define race around condition.
In JK flip-flop output is fed back to the input. Therefore change in the output results change in
the input. Due to this in the positive half of the clock pulse if both J and K are high then output
toggles continuously. This condition is called ‘race around condition’.
12. What is triggering? What is the need for trigger in flip-flop?
A flip-flop is made to change its state by application of a clock pulse after giving inputs. This is
called triggering. The clock (triggering input) is given to synchronize the change in the output with it.
13. What is meant by level and edge-triggering? (Nov 2017) (Apr – 2019)
✓ If flip-flop changes its state when the clock is positive (high) or negative (low) then, that flip-
flop is said to be level triggering flip-flop.
✓ If the flip-flop changes its state at the positive edge (rising edge) or negative edge (falling
edge) of the clock is sensitive to its inputs only at this transition of the clock then flip-flop is
said to be edge triggered flip-flop.
14. How do you eliminate race around condition in JK flip flop. ?
Using master-slave flip-flop which consists of two flip-flops where one circuit serves as a master and
the other as a slave race around condition in JK flip flop is eliminated .
15. Define rise time.
The time required to change the voltage level from 10% to 90% is known as rise time (tr).
16. Define fall time.
The time required to change the voltage level from 90% to 10% is known as falltime (tf).
17. Define skew and clock skew.
The phase shift between the rectangular clock waveforms is referred to as skew and the time
delay between the two clock pulses is called clock skew.
18. Define setup time.
The setup time is the minimum time required to maintain a constant voltage levels at the excitation inputs of the
flip-flop device prior to the triggering edge of the clock pulse in order for the levels to be reliably clocked into
the flip flop.
19. Draw the logic diagram and write the function table of D Latch. (Apr 2019)
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20. Define hold time.
The hold time is the minimum time for which the voltage levels at the excitation inputs must remain
constant after the triggering edge of the clock pulse in order for the levels to be reliably clocked into the flip flop.
21. Define propagation delay.
A propagation delay is the time required to change the output after the application of the input
22. Explain the flip-flop excitation tables for RS FF.
In RS flip-flop there are four possible transitions from the present state to theNext state. They are
1). 0→0 transition: This can happen either when R=S=0 or when R=1 and S=0.
2). 0→ 1 transition: This can happen only when S=1 and R=0.
3). 1→0 transition: This can happen only when S=0 and R=1.
4). 1→1 transition: This can happen either when S=1 and R=0 or S=0 and R=0.
23. Give some applications of clocked RS Flip-flop.
Clocked RS flip flops are used in Calculators & Computers.
It is widely used in modern electronic products.
24. What is the drawback of SR Flipflop? How is this minimized? (Apr 2018)
In SR flipflop when both S and R inputs are one it will generate a Undetermined state.This is
Minimized by providing feedback path or by using JK flip flop.
25. How many flip flops are required to build a Binary counter that counts from 0 to 1023?
210= 1024 hence 10 flipflops are required.
26. State the difference between latches and flipflops. (Apr 2019)
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27. What is mealy and Moore circuit? Or what are the models used to represent clocked sequential
circuits?
✓ Mealy circuit is a network where the output is a function of both present state and input.
✓ Moore circuit is a network where the output is function of only present state
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COUNTERS
Counter:
➢ A counter is a register (group of Flip-Flop) capable of counting the number of clock pulse
arriving at its clock input.
➢ A counter that follows the binary number sequence is called a binary counter.
➢ Counter are classified into two types,
1. Asynchronous (Ripple) counters.
2. Synchronous counters.
➢ In ripple counter, a flip- flop output transition serves as clock to next flip-flop.
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o With an asynchronous circuit, all the bits in the count do not all change at the same time.
➢ In a synchronous counter, all flip-flops receive common clock.
o With a synchronous circuit, all the bits in the count change synchronously with the
assertion of the clock
➢ A counter may count up or count down or count up and down depending on the input control.
Uses of Counters:
The most typical uses of counters are
✓ To count the number of times that a certain event takes place; the occurrence of event to be
counted is represented by the input signal to the counter
✓ To control a fixed sequence of actions in a digital system
✓ To generate timing signals
✓ To generate clocks of different frequencies
Modulo 16 ripple /Asynchronous Up Counter

Explain the operation of a 4-bit binary ripple counter.
➢ The output of up-counter is incremented by one for each clock transition.
➢ A 4-bit asynchronous up-counter consists of 4JK Flip-Flops.
➢ The external clock signal is connected to the clock input of the first FlipFlop.
➢ The clock inputs of the remaining Flip-Flops are triggered by the Q output of the previous stage.
➢ We know that in JK Flip-Flop, if J=1 , K=1 and clock is triggered the past output will be
complemented.
➢ Initially, the register is cleared, QDQCQBQA =0000.
➢ During the first clock pulse, Flip-Flop A triggers, therefore QA=1, QB=QC=QD=0.
QDQCQBQA=0001
➢ At the second clock pulse FLipFlop A triggers, therefore QA changes from 1 to 0, which triggers
FlipFlop B, therefore QB=1,QA=QC=QD=0
QDQCQBQA=0010
➢ At the third clock pulse FlipFlop A triggers, therefore QA changes from 0 to 1, This never triggers
FlipFlop B because 0 to 1 transition gives a positive edge triggering,but here the FlipFlops are
triggered only at negative edge( 1 to 0 transition) therefore QA=QB=1, QC=QD=0.
QDQCQBQA=0011
➢ At the fourth clock pulse Flip-Flop A triggers, therefore QA changes from 1 to 0, This triggers
FlipFlop B therefore QB changes from 1 to 0. The change in QB from 1 to 0 triggers C Flip-Flop,
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➢ Therefore QC changes from 0 to 1. Therefore QA=QB=QD=0, QC=1.
QDQCQBQA=0100
Truth table:
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Timing diagram:
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Modulo 16 /4 bit Ripple Down counter/ Asynchronous Down counter
Explain about Modulo 16 /4 bit Ripple Down counter.
➢ The output of down-counter is decremented by one for each clock transition.
➢ A 4-bit asynchronous down-counter consists of 4JK Flip-Flops.
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➢ The external clock signal is connected to the clock input of the first Flip-Flop.
➢ The clock inputs of the remaining Flip-Flops are triggered by the Q output of the previous stage.
➢ We know that in JK Flip-Flop, if J=1 , K=1 and clock is triggered the past output will be
complemented.
➢ Initially, the register is cleared, QDQCQBQA =0000.

➢ During the first clock pulse, Flip-Flop A triggers, therefore QA changes from 0 to 1 also QA
changes from 1 to 0.This triggers Flip-Flop B, therefore QB changes from 0 to 1, also QB changes
from 1 to 0which triggers Flip-FlopC. Hence QC changes from 0 to 1 and QC changes from 1 to
0, which further triggers, Flip-Flop D.
QDQCQBQA=1111
QD QC QB QA=0000
➢ During the second clock pulse Flip-Flop A triggers, therefore QA changes from 1 to 0 also QA
changes from 0 to 1 which never triggers B Flip-Flop. Therefore C and D Flip-Flop are not
triggered.
QDQCQBQA =1110
➢ The same procedure repeats until the counter decrements upto 0000.
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Asynchronous Up/Down Counter:
Explain about Asynchronous Up/Down counter.
➢ The up-down counter has the capability of counting upwards as well as downwards. It is also
called multimode counter.
➢ In asynchronous up-counter, each flip-flop is triggered by the normal output Q of the preceding
flip-flop.
➢ In asynchronous down counter, each flip-flop is triggered by the complement output Q of the
preceding flip-flop.
➢ In both the counters, the first flip-flop is triggered by the clock output.
➢ If Up/Down =1, the 3-bit asynchronous up/down counter will perform up-counting. It will count
from 000 to 111. If Up/Down =1 gates G2 and G4 are disabled and gates G1 and G3 are enabled.
So that the circuit behaves as an up-counter circuit.
➢ If Up/Down =0, the 3-bit asynchronous up/down counter will perform down-counting. It will
count from 111 to 000. If Up/Down =0 gates G2 and G4 are enabled and gates G1 and G3 are
disabled. So that the circuit behaves as an down-counter circuit.
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4- bitSynchronous up-counter:
Explain about 4-bit Synchronous up-counter.
➢ In JK Flip-Flop, If J=0, K=0 and clock is triggered, the output never changes. If J=1 and K=1 and
the clock is triggered, the past outpit will be complemented.
Initially the register is cleared QDQCQBQA= 0000.
During the first clock pulse, JA= KA = 1, QA becomes 1, QB, QC, QD remains 0.
QDQCQBQA= 0001.
During second clock pulse, JA= KA = 1, QA=0.
JB= KB = 1, QB =1, QC, QD remains 0.
QDQCQBQA= 0010.
During third clock pulse, JA= KA = 1, QA=1.
JB= KB = 0, QB =1, QC, QD remains 0.
QDQCQBQA= 0011.
During fourth clock pulse, JA= KA = 1, QA=0.
JB= KB = 1, QB =0
JC= KC = 1, QC=1
QD remains 0
QDQCQBQA= 0100.
The same procedure repeats until the counter counts up to 1111.
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4- bit Synchronous down-counter:
Explain about 4-Bit Synchronous down counter.
In JK Flip-Flop, If J=0, K=0 and clock is triggered, the output never changes. If J=1 and K=1 and the
clock is triggered, the past outpit will be complemented.
Initially the register is cleared QDQCQBQA= 0000
QDQCQBQA= 1111
During the first clock pulse, JA= KA = 1, QA=1

JB= KB = 1, QB =1
JC= KC = 1, QC =1
JD= KD = 1, QD =1
QDQCQBQA= 1111
QDQCQBQA= 0000
During the second clock pulse, JA= KA = 1, QA =0

JB= KB = 0, QB =1
JC= KC = 0, QC =1
JD= KD = 0, QD =1
QDQCQBQA= 1110
QDQCQBQA= 0001
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During the second clock pulse, JA= KA = 1, QA =1
JB= KB = 1, QB =0
JC= KC = 0, QC =1
JD= KD = 0, QD =1
QDQCQBQA= 1101
The process repeats until the counter down-counts up to 0000.
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Modulo 8 Synchronous Up/Down Counter:
Explain about Modulo 8 Synchronous Up/Down Counter.
In synchronous up-counter the QA output is given to JB, KBand QA. QB is given to JC, KC. But in
synchronous down –counter QAoutput is given toJB, KB and QA. QB is given to JC, KC.
A control input Up/Down is used to select the mode of operation.
If Up/Down =1, the 3-bit asynchronous up/down counter will perform up-counting. It will count from
000 to 111. If Up/Down =1 gates G2 and G4 are disabled and gates G1 and G3 are enabled. So that the
circuit behaves as an up-counter circuit.
If Up/Down =0, the 3-bit asynchronous up/down counter will perform down-counting. It will count from
111 to 000. If Up/Down =0 gates G2 and G4 are enabled and gates G1 and G3 are disabled. So that the
circuit behaves as an down-counter circuit.
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TWO MARKS
1. What is counter?
A counter is a register (group of Flip-Flop) capable of counting the number of clock pulse
arriving at its clock input.
2. What is binary counter?
A counter that follows the binary number sequence is called a binary counter.
3. State the applications of counters.
1. Used as a memory Element.
2. Used as a Delay Element.
3. Used as a basic building block in sequential circuits such as counters and registers.
4. Used for Data Transfer, Frequency Division & Counting.
4. List the types of counters.
Counter are classified into two types,
✓ Asynchronous (Ripple) counters.
✓ Synchronous counters.
5. Give the comparison between synchronous & Asynchronous counters. (Nov/Dec 2009, Nov
2017)
S.No Asynchronous counters Synchronous counters
1. In this type of counter flip-flops are connected in In this type there is no connection between
such a way that output of 1st flip-flop drives output of first flip-flop and clock input of the next
the clock for the next flip - flop. flip – flop
2 All the flip-flops are not clocked All the flip-flops are clocked simultaneously
simultaneously
3 Logic circuit is very simple even for Design involves complex logic circuit as
more number of states number of states increases
4 Counters speed is low. Counters speed is high.
6. State the Steps or Design procedure for Synchronous Counter.
Preparation of 1). State Diagram
2). State Table
3). State Assignment
4). Excitation Table (Consider which Memory Unit Using)
5). K-Map
6). Circuit Diagram
7. What is modulo-N counter?
A modulo–ncounter will count n states. For example a mod-6 counter will count the sequence
000,001,010,011,100,101 and then recycles to 000. Mod -6 counter skips 110 and 111 states and it goes through only
six different states.
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DESIGN OF RIPPLE COUNTERS
3-Bit Asynchronous Binary Counter/ modulo -7 ripple counter:
Design a 3-bit binary counter using T-flip flops. [NOV – 2019]
Explain about 3-Bit Asynchronous binary counter. (Nov -2009)
The following is a three-bit asynchronous binary counter and its timingdiagram for one cycle. It
works exactly the same way as a two-bitasynchronous binary counter mentioned above, except it has
eight statesdue to the third flip-flop.
Asynchronous counters are commonly referred to as ripple counters forthe following reason: The
effect of the input clock pulse is first “felt” byFFO. This effect cannot get to FF1 immediately because of
thepropagation delay through FF0. Then there is the propagation delaythrough FF1 before FF2 can be
triggered. Thus, the effect of an inputclock pulse “ripples” through the counter, taking some time, due
topropagation delays, to reach the last flip-flop.
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ANALYSIS OF CLOCKED SEQUENTIAL CIRCUIT
Design and analyze of clocked sequential circuit with an example.
The analysis of a sequential circuit consists of obtaining a table or a diagram for the time sequence of
inputs, outputs and internal states.
Fig: Example of sequential circuit
Consider the sequential circuit is shown in figure. It consists of two D flip-flops A and B, an input x and
an output y.
A state equation specifies the next state as function of the present state and inputs.
A(n+1)= A(n)x(n)+B(n)x(n)
B(n +1)= A(n)x(n)
They can be written in simplified form as,
A(n+1) = Ax +Bx
B(n +1) = Ax
The present state value of the output can be expressed algebraically as,
y(n)=(A+B) x
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DESIGN OF SYNCHRONOUS COUNTERS
Design and analyze of clocked sequential circuit with an example.
The procedure for designing synchronous sequential circuit is given below,
1. From the given specification, Draw the state diagram.
2. Plot the state table.
3. Reduce the number of states if possible.
4. Assign binary values to the states and plot the transition table by choosing the type of Flip-Flop.
5. Derive the Flip flop input equations and output equations by using K-map.
6. Draw the logic diagram.
State Diagram:
➢ State diagram is the graphical representation of the information available in a state table.
➢ In state diagram, a state is represented by a circle and the transitions between states are indicated by
directed lines connecting the circles.
State Table:
➢ A state table gives the time sequence of inputs, outputs ad flip flops states. The table consists of
four sections labeled present state, next state, input and output.
➢ The present state section shows the states of flip flops A and B at any given time ‘n’. The input
section gives a value of x for each possible present state.
➢ The next state section shows the states of flip flops one clock cycle later, at time n+1.
The state table for the circuit is shown. This is derived using state equations.
The above state table can also be expressed in different forms as follows.
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The state diagram for the logic circuit in below figure.
Flip-Flop Input Equations:

The part of the circuit that generates the inputs to flip flops is described algebraically by a set of Boolean
functions called flip flop input equations.
The flip flop input equations for the circuit is given by,
DA =Ax +Bx
DB = Ax
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TWO MARKS
1. Define state diagram.
State diagram is the graphical representation of the information available in a state table.
In state diagram, a state is represented by a circle and the transitions between states are indicated
by directed lines connecting the circles.
2. What is the use of state diagram?
i) Behavior of a state machine can be analyzed rapidly.
ii) It can be used to design a machine from a set of specification.
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3. What is state table? (Nov 2018)
A stable table is a table that represents relationship between inputs, outputs and flip-flop
states, is called state table. Generally it consists of four section present state, next state, input and
output.
4. What is a state equation?
A state equation also called, as an application equation is an algebraic expression that specifies the condition
for a flip-flop state transition. The left side of the equation denotes the next state of the flip-flop and the right
side, a Boolean function specifies the present state.
5. Define sequential circuit.

Sequential circuits are circuits in which the output variables dependent not only on the
present input variables but they also depend up on the past output of these input variables.
6. What do you mean by present state?
The information stored in the memory elements at any given time defines the present state
of the sequential circuit.
7. What do you mean by next state?
The present state and the external inputs determine the outputs and the next state of the
sequential circuit.
8. Define synchronous sequential circuit.
SynchronousSequential circuits are circuits in which the signals can affect the memory elements
only atdiscrete instant of time.
9. What are the steps for the design of asynchronous sequential circuit?
i) Construction of primitive flow table
ii) Reduction of flow table
iii) State assignment is made
iv) Realization of primitive flow table
*****************************************
Design of a Synchronous Decade Counter Using JK Flip- Flop (Apr 2018, Nov 2018)
A synchronous decade counter will count from zero to nine and repeat thesequence.
State diagram:
The state diagram of this counter is shown in Fig.
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Excitation table:
K-Map:
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Logic Diagram:
*************************************
Design of an Asynchronous Decade Counter Using JK Flip- Flop.

An asynchronous decade counter will count from zero to nine and repeat thesequence. Since the
JK inputs are fed from the output of previous flip-flop,therefore, the design will not be as complicated as
the synchronous version.
At the ninth count, the counter is reset to begin counting at zero. The NAND gateis used to reset
the counter at the ninth count. At the ninth count the outputs offlip-flop Q3 and Q1 will be high
simultaneously. This will cause the output ofNAND to go to logic “0” that would reset the flip-flip. The
logic design of thecounter is shown in Fig.
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**************************************
Design of a Synchronous Modulus-Six Counter Using SR Flip-Flop(Nov 2017)

The modulus six counters will count 0, 2, 3, 6, 5, and 1 and repeat the sequence.This modulus six
counter requires three SR flip-flops for the design.
State diagram:
Truth table:
K-Map:
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Logic Diagram:
SHIFT REGISTERS
Explain various types of shift registers. (or) Explain the operation of a 4-bit bidirectional shift register.
(Or) What are registers? Construct a 4 bit register using D-flip flops and explain the operations on the
register. (or) With diagram explain how two binary numbers are added serially using shift registers.
(Apr – 2019)[NOV – 2019]
➢ A register is simply a group of Flip-Flops that can be used to store a binary number.
➢ There must be one Flip-Flop for each bit in the binary number.
➢ For instance, a register used to store an 8-bit binary number must have 8 Flip-Flops.
➢ The Flip-Flops must be connected such that the binary number can be entered (shifted) into the
register and possibly shifted out.
➢ A group of Flip-Flops connected to provide either or both of these functions is called a shift register.
➢ A register capable of shifting the binary information held in each cell to its neighboring cell in a
selected direction is called a shift register.
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➢ There are four types of shift registers namely:
1. Serial In Serial Out Shift Register,
2. Serial In Parallel Out Shift Register
3. Parallel In Serial Out Shift Register
4. Parallel In Parallel Out Shift Register
1.Serial In Serial Out Shift Register

➢ The block diagram of a serial out shift register is as below.
➢ As seen, it accepts data serially .i.e., one bit at a time on a single input line. It produces the stored
information on its single output also in serial form.
➢ Data may be shifted left using shift left register or shifted right using shift right register.
Shift Right Register

The circuit diagram using D flip-fops is shown in figure
➢ As shown in above figure,the clock pulse is applied to all the flip-flops simultaneously.
➢ The output of each flip-flop is connected to D input of the flip-flop at its right.
➢ Each clock pulse shifts the contents of the register one bit position to the right.
➢ New data is entered into stage A whereas the data presented in stage D are shifted out.
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➢ For example, consider that all stages are reset and a steady logical 1 is applied to the serial input
line.
➢ When the first clock pulse is applied, flip-flop A is set and all other flip-flops are reset.
➢ When the second clock pulse is applied,the ‘1’ on the data input is shifted into flip-flop A and ‘1’
that was in flip flop A is shifted to flip-flop B.
➢ This continues till all flip-flop sets.
➢ The data in each stage after each clock pulse is shown in table below
Shift Left Register

The figure below shows the shift left register using D flip-flops.
➢ The clock is applied to all the flip-flops simultaneously. The output of each flip-flop is connected
to D input of the flip-flop at its left.
➢ Each clock pulse shifts the contents of the register one bit position to the left.
➢ Let us illustrate the entry of the 4-bit binary number 1111 into the register beginning with the
right most bit.
➢ When the first clock pulse is applied, flip flop A is set and all other flip-flops are reset.
➢ When second clock pulse is applied, ’1’ on the data input is shifted into flip-flop A and ‘1’ that
was in flip flop A is shifted toflip-flop B. This continues fill all flip-flop are set.
➢ The data in each stage after each clock pulse is shown in table below.
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2. Serial in Parallel out shift register:
A 4 bit serial in parallel out shift register is shown in figure.
➢ It consists of one serial input and outputs are taken from all the flip-flops simultaneously.
➢ The output of each flip-flop is connected to D input of the flip-flop at its right. Each clock pulse
shifts the contents of the register one bit position to the right.
➢ For example, consider that all stages are reset and a steady logical ‘1’ is applied to the serial
input line.
➢ When the first clock pulse is applied flip flop A is set and all other flip-flops are reset.
➢ When the second pulse is applied the ‘1’ on the data input is shifted into flip flop A and ‘1’ that
was in flip flop A is shifted into flip-flop B. This continues till all flip-flops are set. The data in
each stage after each clock pulse is shown in table below.
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3. Parallel In Serial Out Shift register:
➢ For register with parallel data inputs, register the bits are entered simultaneously into their
respective stages on parallel lines.
➢ A four bit parallel in serial out shift register is shown in figure. Let A,B,C and D be the four
parallel data input lines and SHIFT/LOAD is a control input that allows the four bits of data to be
entered in parallel or shift the serially.
➢ When SHIFTS/LOAD is low, gates G1 through G3 are enabled, allowing the data at parallel
inputs to the D input of its respective flip-flop. When the clock pulse is applied the flip-flops with
D=1 will set and those with D=0 will reset, thereby storing all four bits simultaneously.
➢ When SHIFT/LOADis high. AND gates G1 through G3 are disabled and gates G4 through G6are
enabled, allowing the data bits to shifts right from one stage to next. The OR gates allow either
the normal shifting operation or the parallel data entry operation, depending on which AND gates
are enabled by the level on the SHIFT/LOAD input.
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Parallel In Parallel OutShift Register:
➢ In parallel in parallel out shift register, data inputs can be shifted either in or out of the register in
parallel.
➢ A four bit parallel in parallel out shift register is shown in figure.Let A, B, C, D be the four
parallel data input lines and QA,QB,QC and QD be four parallel data output lines. The
SHIFT/LOAD is the control input that allows the four bits data to enter in parallel or shift the
serially.
➢ When SHIFT/LOAD is low, gates G1 through G3 are enabled, allowing the data at parallel inputs
to the D input of its respective flip-flop. When the clock pulse is applied, the flip-flops with D =1
willset those with D=0 will reset thereby storing all four bits simultaneously. These are
immediately available at the outputs QA,QB,QC and QD.
➢ When SHIFT/LOAD is high, gates G1, through G3 are disabled and gates G4 through G6 are
enabled allowing the data bits to shift right from one stage to another. The OR gates allow either
the normal shifting operation or the parallel data entry operation, depending on which AND gates
are enabled by the level on the SHIFT/LOAD input.
**************************************
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Universal Shift Register:
Explain about universal shift register.( Apr -2018)
➢ A register that can shift data to right and left and also has parallel load capabilities is called
universal shift register.
➢ It has the following capabilities.
1. A clear control to clear the register to 0.
2. A clock input to synchronize the operations.
3. A shift right control to enable the shift right operation and the associated serial input
and output lines.
4. A shift left control to enable the shift left operation and the associated serial input and
output lines.
5. A parallel load control to enable a parallel transfer and the n input lines.
6. n parallel output lines.
7. A control state that leaves the information in the register unchanged in the presence of
the clock.
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➢ The diagram of 4-bit universal shift register that has all that capabilities listed above is shown in
figure. It consists of four D flip-flop and four multiplexers.All the multiplexers have two common
selection inputs S1 and S0. Input 0 is selected when S1S0=00, input 1 is selected when S1S0=01
and similarly for other two inputs.
➢ The selection inputs control the mode of operation of the register. When S1S0=00, the present
value of the register is applied to the D inputs of the flip-flop. The next clock pulse transfers into
each flip-flop the binary value it held previously, and no change of state occurs.
➢ When S1S0=01,terminal 1 of the multiplexer inputs has a path to be the D inputs of the flip-flops.
This causes a shift right operation, with the serial input transferred into flip-flop A3.
➢ When S1S0=10, a shift left operation results with the other serial input going into flip-flop A0.
Finally, when S1 S0 = 11, the binary information on the parallel input lines is transferred into the
register simultaneously during the next clock edge. The function table is shown below.
****************************************
SHIFT REGISTER COUNTERS:
Explain about Johnson and Ring counter. (Nov 2018)
Most common shift register counters are Johnson counter and ring counter.
Johnson counter:
➢ A 4 bit Johnson counter using D flip-flop is shown in figure. It is also called shift counter or
twisted counter.
Page 43
➢ The output of each flip-flop is connected to D input of the next stage. The inverted output of last
flip-flop QDis connected to the D input of the first flip-flop A.
➢ Initially, assume that the counter is reset to 0. i.e., QA QB QC QD =0000. The value at DB =
DC=DD=0, whereas DA =1 since QD.
➢ When the first clock pulse is applied, the first flip-flop A is set and the other flip-flops are reset.
i.e., QA QB QC QD =1000.
➢ When the second clock pulse is applies, the counter is QA QB QC QD = 1100. This continues and
the counter will fill up with 1’s from left to right and then it will fill up with 0’s again.
➢ The sequence of states is shown in the table. As observed from the table, a 4-bit shift counter has
8 states. In general, an n-flip-flop Johnson counter will result in 2n states.
The timing diagram of Johnson counter is as follows:
Page 44
Ring Counter:
A 4- bit ring counter using D Flip-Flop is shown in figure.
➢ As shown in figure, the true output of flip-flop D. i.e., QD is connected back to serial input of flip-
flop A.
➢ Initially, 1 preset into the first flip-flop and the rest of the flip-flops are cleared i.e.,
QAQBQCQD=1000.
➢ When the first clock pulse is applied, the second flip-flop is set to 1while the other three flip flops
are reset to 0.
➢ When the second clock pulse is applied, the ‘1’ in the second flip-flop is shifted to the third flip-
flop and so on.
➢ The truth table which describes the operation of the ring counter is shown below.
➢ As seen a 4-bit ring counter has 4 states. In general, an n-bit ring counter has n states. Since a
single ‘1’ in the register is made to circulate around the register, it is called a ring counter. The
timing diagram of the ring counter is shown in figure.
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******************************************
TWO MARKS
1. Define registers.
A register is a group of flip-flops. An-bit register has a group of n flip-flops and is capable of storing
any binary information/number containing n-bits.
2. Define shift registers.
A register capable of shifting its binary information in one or both directions is called as a
shift register. It consists of a chain of flip flops in cascade, with the output of one flip flop
connected to the input of the next flip-flop
3. What are the different types of shift registers?[Nov 2010,April 2007,Apr 2018, Nov 2018]
✓ Serial In Serial Out Shift Register
✓ Serial In Parallel Out Shift Register
✓ Parallel In Serial Out Shift Register
✓ Parallel In Parallel Out Shift Register
✓ Bidirectional Shift Register
4. State the applications of shift register.
Shift registers are widely used in
✓ Time delay circuits
✓ As Serial to parallel converter
✓ As Parallel to serial converters
✓ As Counters
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5. Define Shift Register Counter.
A shift register can also be used as a counter. A shift register with the serial output
connection back to the serial input is called Shift register counter
6. What is bi-directional shift register and unidirectional shift register?
A register capable of shifting both right and left is called bi-directional shift register. A register capable of
shifting only one direction is called unidirectional shift register.
7. What are the two types of shift register counters?[April/May 2007,Nov/Dec 2006,2011,2012]
There are 2 types of shift Register counters are:
Ring counter:
A ring counter is a circular shift register with only one flip flop being set, at any particular
time, all others are cleared.
Johnson counters:
The Johnson counter is K-bit switch-tail rings counter2k decodinggates to provide outputs
for 2k t i m i n g s i g n a l s .
8. How can a SIPO shift register is converted in to SISO shift register? (Apr/May 2010)
By taking output only on the Q output of last flip flop SIPO shift register is converted in to
SISO shift register.
9. What is bi-directional shift register and unidirectional shift register?
A register capable of shifting both right and left is called bi-directional shift register. A register capable of
shifting only one direction is called unidirectional shift register.
10. What is sequence generator?
The sequential circuit used to repeat a particular sequence repeatedly is called Sequence
generator.
***********************************
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HDL FOR SEQUENTIAL CIRCUITS
Write coding in HDL for various flip-flops.
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Test Bench:
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Write the VHDL Code for 4-Bit Binary Up Counter and explain. (Apr 2019)
VHDL Code for 4-Bit Binary Up Counter
The clock inputs of all the flip-flops are connected together and are triggered by the input pulses. Thus,
all the flip-flops change state simultaneously (in parallel).
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity vhdl_binary_counter is
port(C, CLR : in std_logic;
Q : out std_logic_vector(3 downto 0));
end vhdl_binary_counter;
architecture bhv of vhdl_binary_counter is
signal tmp: std_logic_vector(3 downto 0);
begin
process (C, CLR)
begin
if (CLR=’1′) then
tmp <= "0000";
elsif (C’event and C=’1′) then
tmp <= tmp + 1;
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end if;
end process;
Q <= tmp;
end bhv;
******************************************
TWO MARKS
1. Draw 5-bit Johnson counter.
2. Draw the diagram of 3-bit ripple counter.
3. Give few applications of shift register.

✓ Serial to parallel converter
✓ Parallel to serial converter
✓ As a counter
✓ To introduce delay in a digital circuit.
************************
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UNIT III

SYNCHRONOUS SEQUENTIAL LOGIC

Types of sequential circuits:

LATCHES AND FLIP FLOPS

SR Latch: Using NOR gate

FLIP FLOP CONVERSIONS

T) for a desired flipflop state transition :

Excitation table for all flip flops:

1. SR Flip Flop to JK Flip Flop

4.D Flip Flop to SR Flip Flop

6.JK Flip Flop to D Flip Flop

7.D Flip Flop to JK Flip Flop

Write short notes on Mealy and Moore models in sequential circuits.

2. What are the classifications of sequential circuits?

Modulo 16 ripple /Asynchronous Up Counter

➢ Initially, the register is cleared, QDQCQBQA =0000.

During the first clock pulse, JA= KA = 1, QA=1

During the second clock pulse, JA= KA = 1, QA =0

A control input Up/Down is used to select the mode of operation.

Fig: Example of sequential circuit

Flip-Flop Input Equations:

5. Define sequential circuit.

Design of an Asynchronous Decade Counter Using JK Flip- Flop.

Design of a Synchronous Modulus-Six Counter Using SR Flip-Flop(Nov 2017)

1.Serial In Serial Out Shift Register

Shift Right Register

Shift Left Register

The timing diagram of Johnson counter is as follows:

A 4- bit ring counter using D Flip-Flop is shown in figure.

2. Draw the diagram of 3-bit ripple counter.

3. Give few applications of shift register.

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