et3491notesprint
et3491notesprint
et3491notesprint
6 The Instruction set of The instruction sets are simple with less
microprocessor is complex with number of instructions.
large number of instructions.
8051 MICRCONTROLLER:
It has hardware architecture with RISC (Reduced Instruction Set Computer) concept.
The block diagram of 8051 microcontroller is shown in Fig 3.
8051 has 8-bit ALU.
ALU can perform all the 8-bit arithmetic and logical operations in one machine cycle.
The ALU is associated with two registers A & B
A and B Registers:
The A and B registers are special function registers.
A & B registers hold the results of many arithmetic and logical operations of 8051.
The A register is also called the Accumulator.
A register is used as a general register to accumulate the results of a large number of instructions.
By default, it is used for all mathematical operations and data transfer operations between CPU and
external memory.
The B register is mainly used for multiplication and division operations along with A register.
Ex: MUL AB : DIV AB.
It has no other function other than as a store data.
R registers:
"R" registers are a set of eight registers that are named R0, R1, etc. up to R7.
These registers are used as auxiliary registers in many operations.
The "R" registers are also used to temporarily store values.
Fig.3. Block Diagram of 8051 Microcontroller
The bits PSW3 and PSW4 are denoted as RS0 and RS1.
These bits are used to select the bank registers of the RAM location.
The selection of the register Banks and their addresses are given below.
0 0 0 00H-07H
0 1 1 08H-0FH
1 0 2 10H-17H
1 1 3 18H-1FH
RAM & ROM:
The 8051 microcontroller has 128 bytes of Internal RAM and 4KB of on chip ROM.
The RAM is also known as Data memory and the ROM is known as program (Code) memory.
Code memory holds program that is to be executed.
Program Address Register holds address of the ROM/ Flash memory.
Data Address Register holds address of the RAM.
I/O ports:
The 8051 microcontroller has 4 parallel I/O ports, each of 8-bits.
So, it provides 32 I/O lines for connecting the microcontroller to the peripherals.
The four ports are P0 (Port 0), P1 (Port1), P2 (Port 2) and P3 (Port3).
The way in which the data operands are specified is known as the addressing modes. There are various
methods of denoting the data operands in the instruction.
The 8051 microcontroller supports 5 addressing modes. They are
1. Immediate addressing mode
2. Direct Addressing mode
3. Register addressing mode
4. Register indirect addressing mode
5. Indexed addressing mode
Immediate addressing mode:
The addressing mode in which the data operand is a constant and it is a part of the instruction itself is
known as Immediate addressing mode.
Normally the data must be preceded by a # sign.
This addressing mode can be used to transfer the data into any of the registers including
DPTR. Examples:
MOV A, # 27 H : The data (constant) 27 is moved to the accumulator register
ADD R1, #45 H : Add the constant 45 to the contents of the accumulator
MOV DPTR, # 8245H : Move the data 8245 into the data pointer register.
Direct addressing mode:
In the addressing mode, the data operand is in the RAM location (00 -7FH) and the address of the
data operand is given in the instruction.
The direct addressing mode uses the lower 128 bytes of Internal RAM and the
SFRs Examples:
MOV R1, 42H : Move the contents of RAM location 42 into R1 register
MOV 49H, A : Move the contents of the accumulator into the RAM location 49.
ADD A, 56H : Add the contents of the RAM location 56 to the accumulator
Arithmetic instructions:
ADD
• 8-bit addition between the accumulator (A) and a second operand.
• The result is always in the accumulator.
• The CY flag is set/reset appropriately.
ADDC
• 8-bit addition between the accumulator, a second operand and the previous value of the
CY flag.
• Useful for 16-bit addition in two steps.
• The CY flag is set/reset appropriately.
DAA
• Decimal adjust the accumulator.
• Format the accumulator into a proper 2 digit packed BCD number.
• Operates only on the accumulator.
• Works only after the ADD instruction.
SUBB
• Subtract with Borrow.
• Subtract an operand and the previous value of a borrow (carry) flag from the
accumulator.
• A A - <operand> - CY.
• The result is always saved in the accumulator.
• The CY flag is set/reset appropriately.
INC
• Increment the operand by one.
• The operand can be a register, a direct address, an indirect address, the data pointer.
DEC
• Decrement the operand by one.
• The operand can be a register, a direct address, an indirect address.
MUL AB / DIV AB
• Multiply A by B and place result in A and B registers.
• Divide A by B and place quotient in A register & remainder in B register.
Logical instructions in 8051.
ANL : It performs AND logical operation between two operands.
Work on byte sized operands or the CY flag.
• ANL A, Rn
• ANL A, direct
• ANL A, @Ri
• ANL A, #data
• ANL direct, A
• ANL direct, #data
• ANL C, bit
• ANL C, /bit
ORL: It performs OR logical operation between two operands.
Work on byte sized operands or the CY flag.
• ORL A, Rn
• ORL A, direct
• ORL A, @Ri
• ORL A, #data
XRL
Works on bytes only.
• XRL A, Rn
• XRL A, direct
CPL / CLR
Complement / Clear.
Work on the accumulator or a bit.
• CLR P1.2
• CPL Rn
RL / RLC / RR / RRC
Rotate the accumulator.
• RL and RR without the carry
• RLC and RRC rotate through the carry.
• SWAP A: Swap the upper and lower nibbles of the accumulator.
Data transfer instructions in 8051.
MOV
8-bit data transfer for internal RAM and the SFR.
• MOV A, Rn
• MOV A, direct
• MOV A, @Ri
• MOV A, #data
• MOV Rn, A
• MOV Rn, direct
• MOV Rn, #data
• MOV direct, A
• MOV direct, Rn
• MOV direct, direct
• MOV direct, @Ri
• MOV direct, #data
• MOV @Ri, A
• MOV @Ri, direct
• MOV @Ri, #data
MOV
1-bit data transfer involving the CY flag
• MOV C, bit
• MOV bit, C
MOV
16-bit data transfer involving the DPTR
• MOV DPTR, #data
MOVC
Move Code Byte
• Load the accumulator with a byte from program memory.
• Must use indexed addressing
• MOVC A, @A+DPTR
• MOVC A, @A+PC
MOVX
Data transfer between the accumulator and a byte from external data memory.
• MOVX A, @Ri
• MOVX A, @DPTR
• MOVX @Ri, A
• MOVX @DPTR, A
PUSH / POP
Push and Pop a data byte onto the stack.
The data byte is identified by a direct address from the internal RAM locations.
• PUSH DPL
• POP 40H
XCH
Exchange accumulator and a byte operand
• XCH A, Rn
• XCH A, direct
• XCH A, @Ri
XCHD
Exchange lower digit of accumulator with the lower digit of the memory location specified.
• XCHD A, @Ri
• The lower 4-bits of the accumulator are exchanged with the lower 4-bits of the internal
memory location identified indirectly by the index register.
• The upper 4-bits of each are not modified.
The 8051 microcontroller has 128 bytes of Internal RAM and 4kB of on chip ROM.
The RAM is also known as Data memory and the ROM is known as program (Code) memory.
Code memory holds the actual 8051 program to be executed.
In 8051, memory is limited to 64KB.
Code memory may be found on-chip, as ROM or EPROM.
It may also be stored completely off- chip in an external ROM / EPROM.
The 8051 has only 128 bytes of Internal RAM but it supports 64KB of external RAM.
Since the memory is off-chip, it is not as flexible for accessing and is also slower.
Internal RAM is found on-chip on the 8051. So it is the fastest RAM available.
It is flexible in terms of reading, writing and modifying its contents.
Internal RAM is volatile.
When the 8051 is reset, internal RAM is cleared.
The 128 bytes of internal RAM is organized as below.
Four register banks (Bank0, Bank1, Bank2 and Bank3) each of 8-bits (total 32 bytes).
The default bank register is Bank0.
The remaining Banks are selected with the help of RS0 and RS1 bits of PSW Register.
16 bytes of bit addressable area and
80 bytes of general purpose area (Scratch pad memory) of internal RAM as shown in the diagram below.
This area is utilized by the microcontroller as a storage area for the operating stack.
The 32 bytes of RAM from address 00 H to 1FH are used as working registers organized as four banks
of eight registers each.
The registers are named as R0-R7.
Each register can be addressed by its name or by its RAM address.
For example: MOV A, R7 or MOV R7,#05H
Structure of Internal ROM (On –chip ROM / Program Memory / Code Memory):
The 8051 microcontroller has 4KB of on chip ROM, but it can be extended up to 64K B.
This ROM is also called program memory or code memory.
The CODE segment is accessed using the program counter (PC) for opcode fetches and by DPTR for
data.
The external ROM is accessed when the EA pin is connected to ground or the contents of program
counter exceeds 0FFFH.
When the Internal ROM address is exceeded the 8051 automatically fetches the code bytes from the
external program memory.
In 8051 microcontroller, there are registers which uses the RAM addresses from 80h to FFh.
They are used for certain specific operations. These registers are called Special Function Registers
(SFRs).
Most of SFRs are bit addressable and other few registers are byte addressable.
In these SFRs, some of them are related to I/O ports (P0, P1, P2 and P3) and some of them are for
control operations (TCON, SCON & PCON).
Remaining are the auxiliary SFRs, that they don't directly configure the 8051.
The list of SFRs and their functional names are given below.
2 B* B-Register 0F0
6 P0* Port 0 80
P1* Port 1 90
8 P2* Port 2 0A
9 P3* Port 3 0B
Interrupt Structure :
An interrupt is an external or internal event that disturbs the microcontroller to inform it that a device
needs its service.
The program which is associated with the interrupt is called the interrupt service routine (ISR) or
interrupt handler.
Upon receiving the interrupt signal, the microcontroller finishes current operation and saves the PC on
stack.
Jumps to a fixed location in memory depending on type of interrupt.
Starts to execute the interrupt service routine until RETI.
Upon executing the RETI the microcontroller returns to the place where it was interrupted. Get pop PC
from stack.
The 8051 microcontroller has FIVE interrupts in addition to Reset. They are
Each interrupt has a specific place in code memory where program execution begins.
EA : Global enable/disable. To enable the interrupts, this bit must be set high.
Upon reset, the interrupts have the following priority from top to down. The interrupt with the highest
PRIORITY gets serviced first.
IP.7: reserved
IP.6: reserved
TIMERS OF 8051
Timer Registers.
The 8051 has two timers/counters, they can be used either as timers (used to generate a time delay)
or as event counters.
TIMER 0:
Timer 0 is a 16-bit register and can be treated as two 8-bit registers (TL0 & TH0).
These registers can be accessed similar to any other registers like A, B or R1 etc
Ex : The instruction MOV TL0,#07 moves the value 07 into lower byte of Timer0.
Similarly MOV R1, TH0 saves the contents of TH0 in the R1 register.
TIMER 1:
Timer 1 is also a 16-bit register and can be treated as two 8-bit registers (TL1 & TH1).
These registers can be accessed similar to any other registers like A, B or R1etc
Ex : The instruction MOV TL1,#05 moves the value 05 into lower byte of Timer1.
Similarly MOV R0,TH1 saves the contents of TH1 in the R0 register.
GATE:
This bit is used to start or stop the timers by hardware.
When GATE= 1, the timers can be started / stopped by the external sources.
When GATE= 0, the timers can be started or stopped by software instruct ions like SETB
TRX or CLR TRX.
C/T (Counter/Timer):
This bit decides whether the timer is used as delay generator or event counter.
Notice that to repeat the process, we must reload the TL and TH registers, and start the process is repeated.
Example 2:
In Example 1, calculate the amount of time delay in the DELAY subroutine generated by the timer.
Assume XTAL = 11.0592 MHz.
Solution:
The timer works with a clock frequency of 1/12 of the XTAL frequency, we have 11.0592 MHz / 12 =
921.6 kHz as the timer frequency.
As a result, each clock has a period of T =1/921.6kHz,T=1.085µs.
In other words, Timer 0 counts up each 1.085 µs resulting in delay = number of counts × 1.085 µs.
The number of counts for the roll over is FFFFH – FFF2H = 0DH (13 decimal).
Add one to 13 because of the extra clock needed when it rolls over from FFFF to 0 and raise the TF flag.
This gives 14 × 1.085µs = 15.19µs for half the pulse. For the entire period it is T = 2 × 15.19µs =
30.38µs as the time delay generated by the timer.
(a) In hexadecimal
(FFFF – YYXX + 1) ×1.085 µs, where YYXX are TH, TL initial values respectively. Notice that value YYXX
are in hex.
(b) In decimal
Convert YYXX values of the TH, TL register to decimal to get a NNNN decimal, then (65536 - NNNN) ×
1.085 µs
Example 3:
In Example 1, calculate the frequency of the square wave generated on pin P1.5.
Solution:
In the timer delay calculation of Example 1, we did not include the overhead due to instruction in the
loop.
To get a more accurate timing, we need to add clock cycles due to these instructions in the loop.
To do that, we use the machine cycle as shown below.
Cycles
HERE: MOV TL0,#0F2H 2
MOV TH0,#0FFH 2
CPL P1.5 1
ACALL DELAY 2
SJMP HERE 2
The frequency for the timer is always 1/12th the frequency of the crystal attached to the 8051.
Example 6:
Assuming that clock pulses are fed into pin T1, write a program for counter 1 in mode 2 to count the pulses and
display the state of the TL1 count on P2, which connects to 8 LEDs.
Solution:
MOV TM0D,#01100000B ;counter 1, mode 2, C/T=1 external pulses
MOV TH1,#0 ;clear TH1
SETB P3.5 ;make T1 input
AGAIN: SETB TR1 ;start the counter
BACK: MOV A,TL1 ;get copy of TL
MOV P2,A ;display it on port 2
JNB TF1,Back ;keep doing, if TF = 0
CLR TR1 ;stop the counter 1
CLR TF1 ;make TF=0
SJMP AGAIN ;keep doing it
Notice in the above program the role of the instruction SETB P3.5.
Since ports are set up for output when the 8051 is powered up.
So, we make P3.5 an input port by making it high.
In other words, we must configure (set high) the T1 pin (pin P3.5) to allow pulses to be fed into it.
SERIAL COMMUNICATION
RS232
It is an interfacing standard RS232.
It was set by the Electronics Industries Association (EIA) in 1960.
The standard was set long before the advent of the TTL logic family.
Its input and output voltage levels are not TTL compatible.
In RS232, a 0 is represented by -3 to -25 V, while a 1 bit is +3 to +25 V.
IBM introduced the DB-9 version of the serial I/O standard.
MAX232
A line driver ( MAX232) is required to convert RS232 voltage levels to TTL levels, and vice versa.
8051 has two pins that are used specifically for transferring and receiving data serially.
These two pins are called TxD and RxD and are part of the port 3 (P3.0 and P3.1).
These pins are TTL compatible.
They require a line driver to make them RS232 compatible.
Baud rate:
The baud rates in 8051 are programmable.
8051 divides the crystal frequency by 12 to get machine cycle frequency.
8051 UART circuitry divides the machine cycle frequency by 32.
Explain in detail the serial communication registers of the 8051. (NOV 2009)
SBUF:
It is an 8-bit register used for serial communication.
For a byte data to be transferred via the TxD line:
Byte must be placed in the SBUF register.
Bytes are framed with the start and stop bits and transferred serially via the TxD line.
SBUF holds the byte of data when it is received by 8051 RxD line.
When the bits are received serially via RxD.
8051 de-frames byte by eliminating the stop and start bits.
SCON:
It is an 8-bit register used to program the start bit, stop bit and data bits of data framing.
SM0 SM1 SM2 REN TB8 RB8 TI RI
1. TMOD register is loaded with the value 20H, indicating the use of timer 1 in mode 2 (8-bit auto-
reload) to set baud rate.
2. The TH1 is loaded with one of the values to set baud rate for serial data transfer.
3. The SCON register is loaded with the value 50H, indicating serial mode 1, where an 8-bit data is framed
with start and stop bits.
4. TR1 is set to 1 to start timer 1
5. TI is cleared by CLR TI instruction.
6. The character byte to be transferred serially is written into SBUF register.
7. The TI flag bit is monitored with the use of instruction JNB TI, xx, to see if the character has been
transferred completely.
8. To transfer the next byte, go to step 5.
Write a program for the 8051 to transfer letter “A” serially at 4800 baud, continuously.
Solution:
By checking the TI flag bit, we know whether or not the 8051 is ready to transfer another byte
It must be noted that TI flag bit is raised by 8051 itself when it finishes data transfer
It must be cleared by the programmer with instruction CLR TI
If we write a byte into SBUF before the TI flag bit is raised, we risk the loss of a portion of the
byte being transferred
The TI bit can be checked by the instruction JNB TI,xx Using an interrupt.
Write a program for the 8051 to transfer “YES” serially at 9600 baud, 8-bit data, 1 stop bit do this
continuously. (May 2006)
Solution:
In receiving bit via its RxD pin, 8051 goes through the following steps.
1. It receives the start bit
Indicating that the next bit is the first bit of the character byte it is about to receive
2. The 8-bit character is received one bit at time
3. The stop bit is received
When receiving the stop bit 8051 makes RI = 1,indicating that an entire
character byte has been received.
5. After the SBUF contents are copied into a safe place.
The RI flag bit must be forced to 0 by CLR RI in order to allow the next received
character byte to be placed in SBUF.
Failure to do this causes loss of the received character.
There are two ways to increase the baud rate of data transfer
To use a higher frequency crystal
To change a bit in the PCON register
PCON
PCON register is an 8-bit register
When 8051 is powered up, SMOD is zero.
We can set it to high by software and thereby double the baud rate.
GF1, GF0: General flag bits
PD: Power down mode
IDL: Ideal mode
PIN Diagram of 8051 Microcontroller:
The 8051 microcontroller is available as a 40 pin DIP chip and it works at +5 volts DC.
Among the 40 pins, a total of 32 pins are allotted for the four parallel ports P0, P1, P2 and P3 i.e each
port occupies 8-pins.
The remaining pins are VCC, GND, XTAL1, XTAL2, RST, EA ,PSEN.
XTAL1, XTAL2:
These two pins are connected to Quartz crystal oscillator which runs the on-chip oscillator.
The quartz crystal oscillator is connected to the two pins along with a capacitor of 30pF as shown in the
circuit.
If use a source other than the crystal oscillator, it will be connected to XTAL1 and XTAL2 is left
unconnected.
RST:
P0.0- P0.7(AD0-AD7) :
The port 0 pins multiplexed with Address/data pins.
If the microcontroller is accessing external memory, these pins will act as address/data pins, otherwise
they are used for Port 0 pins.
P2.0- P2.7 (A8-A15) :
The port2 pins are multiplexed with the higher order address pins.
When the microcontroller is accessing external memory, these pins provide the higher order address
byte, otherwise they act as Port 2 pins.
P1.0- P1.7 :
These 8-pins are dedicated to perform input or output port operations.
P3.0- P3.7:
These 8-pins are meant for Port3 operations and also for some control operations like read, Write,
Timer0, Timer1, INT0, INT1, RxD and TxD.
Program 1: Using timers in 8051 write a program to generate square wave 100ms, 50% duty
cycle.
MOV TMOD, #01 Here:
MOV TL0, #D7 MOV TH0,
#B4
CPL P1.3 SETB
TRO
Again: JNB TF0, Again CLR
TR0
CLR TF0
SJMP Here
Program 2: Write an 8051 ALP to multiply the given number 48H and 30H. (April 2017)
Mnemonics Comments
Opcode Operand
MOV A,#48 ;Store data1 in accumulator
MOV B,#30 ;Store data2 in B register
MUL AB ;Multiply both
MOV DPTR,#4500 ;Initialize memory location
MOVX @DPTR,A ;Store lower order result
INC DPTR ;Go to next memory location
MOV A,B ;Store higher order result
MOVX @DPTR,A
L1: SJMP L1 ;Stop the program
Program 3: Write a program to add two 16 bit numbers. The numbers are 8C8D and
8D8C. Place the sum in R7 and R6. R6 should have the lower byte. (NOV 2010)
Mnemonics Comments
Opcode Operand
MOV A, #8D ;Store LSB data1 in accumulator
MOV B, #8C ;Store LSB data2 in B register
ADD A, B ;Add both
MOV R6, A ;Store LSB result
MOV A, #8C ;Store MSB data1 in accumulator
MOV B, #8D ;Store MSB data2 in B register
ADD A, B ;Add both
MOV R7, A ;Store MSB result
L1: SJMP L1 ;Stop the program
UNIT- II EMBEDDED SYSTEMS
7
In battery powered applications, power consumption is very important.
In non-battery powered applications, excessive power consumption can increase heat.
One way to consume less power is to run the system more slowly. But slow down the
system can obviously lead to missed deadlines.
Careful design is required to slow down the non-critical parts of the machine.
How do we design for upgradeability?
Hardware platform may be used over several product generations or for several different
versions of a product in the same generation with few or no changes.
Hardware is designed such that the features are added by changing software.
Does it really work?
Reliability is very important when selling products. Reliability is important because running
system try to eliminate bugs will too late and fixing bugs will more expensive.
7
Major levels of abstraction in the design process
The top–downdesign will begin with the most abstract description of the system and
conclude with concrete details. The alternative is a bottom–up view in which we
start with components to build a system.
Bottom–up design steps are shown in the figure as dashed- line arrows. We need
bottom–up design because we do not have perfect insight into how later stages of the
design process will turn out.
Decisions at one stage of design are based upon estimates of what will happen later:
How fast can we make a particular function run? How much memory will we need?
How much system bus capacity do we need? We also need to consider the major
goals of the design.
Manufacturing cost.
Performance (both overall speed and deadlines); and
Power consumption.
o We must also consider the tasks we need to perform at every step in
the design process. At each step in the design, we add detail:
o We must analyze the design at each step to determine how we
can meet the Specifications.
We must then refine the design to add detail.
o We must verify the design to ensure that it still meets all system
goals, such as cost, speed and so on. Requirements
Clearly, before we design a system, we must know what we are designing.
The initial stages of the design process capture this information for use in
creating the architecture and components
7
We generally proceed in two phases: First, we gather an informal description from the customers
known as requirements, and we refine the requirements into a specification that contains enough
information to begin designing the system architecture.
Separating out requirements analysis and specification is often necessary because of the large gap
between what the customers can describe about the system they want and what the architects need
to design the system.
Consumers of embedded systems are usually not themselves embedded system designers or even
product designers. Their understanding of the system is based on how they envision users’
interactions with the system. They may have unrealistic expectations as to what can be done within
their budgets; and they may also express their desires in a language very different from system
architects’ jargon.
Capturing a consistent set of requirements from the customer and then massaging those requirements
into a more formal specification is a structured way to manage the process of translating from the
consumer’s language to the designer’s.
Requirements may be functional or nonfunctional. We must of course capture the basic functions
of the embedded system, but functional description is often not sufficient.
Typical nonfunctional requirements include:
Performance: The speed of the system is often a major consideration both for the
usability of the system and for its ultimate cost. As we have noted, performance may
be a combination of soft performance metrics such as approximate time to perform a
user- level function and hard deadlines by which a particular operation must be
completed.
Cost: The target cost or purchase price for the system is almost always a consideration. Cost
typically has two major components: manufacturing cost includes the cost of components and
assembly; nonrecurring engineering (NRE) costs include the personnel and other costs of
designing the system.
Physical size and weight: The physical aspects of the final system can vary greatly depending upon
the application. An industrial control system for an assembly line may be designed to fit into a
standard-size rack with no strict limitations on weight. A handheld device typically has tight
requirements on both size and weight that can ripple through the entire system design.
Power consumption: Power, of course, is important in battery-powered systems and is often
important in other applications as well. Power can be specified in the requirements stage in terms of
battery life—the customer is unlikely to be able to describe the allowable wattage.
Validating a set of requirements is ultimately a psychological task since it requires understanding
both what people want and how they communicate those needs.
One good way to refine at least the user interface portion of a system’s requirements is to build a
mock-up.
The mock- up may use canned data to simulate functionality in a restricted
demonstration, and it may be executed on a PC or a workstation. But it should give the
customer a good idea of how the system will be used and how the user can react to it.
Physical, nonfunctional models of devices can also give customers a better idea of
characteristics such as size and weight.
Sample require ments form.
Name
Purpose
Inputs
Outputs
Functions
Performance
Manufacturing cost
Power
Physical size and weight
Requirements analysis for big systems can be complex and time consuming. However,
capturing a relatively small amount of information in a clear, simple format is a good
start toward understanding system requirements.
To introduce the discipline of requirements analysis as part of system design, we will
use a simple requirements methodology.
We can use the requirement form as a checklist in considering the basic characteristics of the
system.
Name: This is simple but helpful. Giving a name to the project not only simplifies talking
about it to other people but can also crystallize the purpose of the machine.
Purpose: This should be a brief one- or two- line description of what the system is supposed to
do. If you can’t describe the essence of your system in one or two lines, chances are that you
don’t understand it well enough.
Inputs and outputs: These two entries are more complex than they seem. The inputs and
outputs to the system encompass a wealth of detail:
Types of data: Analog electronic signals? Digital data? Mechanical inputs?
Data characteristics: Periodically arriving data, such as digital audio samples? Occasional user
inputs? How many bits per data element?
Types of I/O devices: Buttons? Analog/digital converters? Video displays?
Functions: This is a more detailed description of what the system does. A good way to
approach this is to work from the inputs to the outputs: When the system receives an input, what
does it do? How do user interface inputs affect these functions? How do different functions
interact?
Performance: Many embedded computing systems spend at least some time controlling
physical devices or processing data coming from the physical world. In most of these cases,
the computations must be performed within a certain time frame. It is essential that the
performance requirements be identified early since they must be carefully measured during
implementation to ensure that the system works properly.
Manufacturing cost: This includes primarily the cost of the hardware components. Even if
you don’t know exactly how much you can afford to spend on system components, you should
have some idea of the eventual cost range. Cost has a substantial influence on architecture: A
machine that is meant to sell at $10 most likely has a very different internal structure than a
$100 system.
Power: Similarly, you may have only a rough idea of how much power the system can
consume, but a little information can go a long way. Typically, the most important decision is
whether the machine will be battery powered or plugged into the wall. Battery-powered
machines must be much more careful about how they spend energy.
Physical size and weight:You should give some indication of the physical size of the
system to help guide certain architectural decisions. A desktop machine has much more
flexibility in the components used than, for example, a lapel mounted voice recorder.
DESIGN EXAMPLE: MODEL TRAIN CONTROLLER
In order to learn how to use UML to model systems, we will specify a simple system,
a model train controller. The user sends messages to the train with a control box
attached to the tracks.
The control box may have familiar controls such as a throttle, emergency stop button,
and so on. Since the train receives its electrical power from the two rails of the track,
the control box can send signals to the train over the tracks by modulating the power
supply voltage. As shown in the figure, the control panel sends packets over the
tracks to the receiver on the train.
The train includes analog electronics to sense the bits being transmitted and a
control system to set the train motor’s speed and direction based on those
commands.
Each packet includes an address so that the console can control several trains on the
same track; the packet also includes an error correction code (ECC) to guard against
transmission errors. This is a one-way communication system the model train cannot
send commands back to the user.
We start by analyzing the requirements for the train control system.We will base our
system on a real standard developed for model trains.We then develop two
specifications: a simple, high- level specification and then a more detailed
specification.
Requirements
Before we can create a system specification, we have to understand the requirements. Here is a
basic set of requirements for the system:
The console shall be able to control up to eight trains on a single track.
The speed of each train shall be controllable by a throttle to at least 63 different levels in
each direction (forward and reverse).
There shall be an inertia control that shall allow the user to adjust the responsiveness of
the train to commanded changes in speed.
There shall be an emergency stop button.
An error detection scheme will be used to transmit messages
Higher inertia means that the train responds more slowly to a change in the throttle,
simulating the inertia of a large train. The inertia control will provide at least eight different
levels.
12
Putting the requirements into chart format:
When the system receives an input, what does it do? How do user interface inputs affect these
functions? How do different functions interact?
□ Performance: Many embedded computing systems spend at least some time
controlling physical devices or processing data coming from the physical
world.
□ In most of these cases, the computations must be performed within a certain time frame. It
is essential that the performance requirements be identified early since they must be
carefully measured during implementation to ensure that the system works properly.
□ Manufacturing cost: This includes primarily the cost of the hardware components. Even
if you don’t know exactly how much you can afford to spend on system components, you
should have some idea of the eventual cost range. Cost has a substantial influence on
architecture.
□ A machine that is meant to sell at $10 most likely has a very different internal
structure than a $100 system.
□ Power: Similarly, you may have only a rough idea of how much power the system can
consume, but a little information can go a long way. Typically, the most important
decision is whether the machine will be battery powered or plugged into the wall. Battery-
powered machines must be much more careful about how they spend energy.
□ Physical size and weight: You should give some indication of the physical size of the
system to help guide certain architectural decisions. A desktop machine has much
more flexibility in the components used than, for example, a lapel mounted voice
recorder.
DCC
□ The Digital Command Control (DCC) was created by the National Model Railroad
Association to support interoperable digitally-controlled model trains.
□ Hobbyists started building homebrew digital control systems in the 1970s
and Marklin developed its own digital control system in the 1980s.
□ DCC was created to provide a standard that could be built by any manufacturer
so that hobbyists could mix and match components from multiple vendors.
The DCC standard is given in two documents:
□ Standard S-9.1, the DCC Electrical Standard, defines how bits are
encoded on the rails for transmission.
□ Standard S-9.2, the DCC Communication Standard, defines the packets
that carry information.
□ Any DCC-conforming device must meet these specifications. DCC also provides
several recommended practices. These are not strictly required but they provide
some hints to manufacturers and users as to how to best use DCC.
□ The DCC standard does not specify many aspects of a DCC train system. It doesn’t
define the control panel, the type of microprocessor used, the programming
language to be used, or many other aspects of a real model train system.
□ The standard concentrates on those aspects of system design that are necessary for
interoperability.
□ Over standardization, or specifying elements that do not really need to be
standardized, only makes the standard less attractive and harder to
implement.
□ The Electrical Standard deals with voltages and currents on the track
□ The standard must be carefully designed because the main function of the track is to
carry power to the locomotives. The signal encoding system should not interfere with
power transmission either to DCC or non-DCC locomotives. A key requirement is
that the data signal should not change the DC value of the rails.
□ The data signal swings between two voltages around the power supply voltage. bits
are encoded in the time between transitions, not by voltage levels. A 0 is at least
100 ms while a 1 is nominally 58ms.
□ The durations of the high (above nominal voltage) and low (below nominal voltage)
parts of a bit are equal to keep the DC value constant. The specification also gives
the allowable variations in bit times that a conforming DCC receiver must be able to
tolerate.
□ The standard also describes other electrical properties of the system, such as
allowable transition times for signals.
□ The DCC Communication Standard describes how bits are combined into packets and
the meaning of some important packets.
□ Some packet types are left undefined in the standard but typical uses are given in
Recommended Practices documents.
15
□ We can write the basic packet format as a regular expression:
PSA (sD) + E ( 1.1)
16
Conceptual Specification:
□ Digital Command Control specifies some important aspects of the system,
particularly those that allow equipment to interoperate. But DCC deliberately
does not specify everything about a model train control system.
□ A conceptual specification allows us to understand the system a little better. This
specification does not correspond to what any commercial DCC controllers do,
but is simple enough to allow us to cover some basic concepts in system design
□ A train control system turns commands into packets. A command comes from the
command unit while a packet is transmitted over the rails.
□ Commands and packets may not be generated in a 1-to-1 ratio. In fact, the DCC
standard says that command units should resend packets in case a packet is
dropped during transmission.
□ We now need to model the train control system itself. There are clearly two major
subsystems: the command unit and the train-board component. Each of these
subsystems has its own internal structure.
□ The command unit and receiver are each represented by objects; the command
unit sends a sequence of packets to the train’s receiver, as illustrated by the arrow.
□ The notation on the arrow provides both the type of message sent and its sequence
in a flow of messages; since the console sends all the messages, we have numbered
the arrow’s messages as 1..n. Those messages are of course carried over the track.
□ Since the track is not a computer component and is purely passive, it does not
appear in the diagram. However, it would be perfectly legitimate to model the
track in the collaboration diagram, and in some situations it may be wise to model
such nontraditional components in the specification diagrams. For example, if we
are worried about what happens when the track breaks, modeling the tracks would
help us identify failure modes and possible recovery mechanisms.
1
7
Class diagram for the train controller messages.
UML collaboration diagram for major subsystems of the train controller system.
1
8
1
A UML class diagram for the train controller showing the composition of the subsystems.
□ Let’s break down the command unit and receiver into their major components. The
console needs to perform three functions: read the state of the front panel on the
command unit, format messages, and transmit messages. The train receiver must
also perform three major functions: receive the message, interpret the message.
□ It shows the console class using three classes, one for each of its major
components. These classes must define some behaviors, but for the moment we
will concentrate on the basic characteristics of these classes:
□ The Console class describes the command unit’s front panel, which contains
the analog knobs and hardware to interface to the digital parts of the system.
□ The Formatter class includes behaviors that know how to read the panel knobs
and creates a bit stream for the required message.
□ The Transmitter class interfaces to analog electronics to send the message along
the track.
□ There will be one instance of the Console class and one instance of each of the component
classes, as shown by the numeric values at each end of the relationship links. We have also
shown some special classes that represent analog components, ending the name of each with
an asterisk:
□ Knobs describes the actual analog knobs, buttons, and levers on the control panel.
□ Sender describes the analog electronics that send bits along the track.
□ Likewise, the Train makes use of three other classes that define its components:
□ The Receiver class knows how to turn the analog signals on the track into digital form.
□ The Controller class includes behaviors that interpret the commands and figures out how
to control the motor.
□ The Motor interface class defines how to generate the analog signals required to control the
motor.
ARM PROCESSOR
Introduction:
ARM is actually a family of RISC architectures that have been developed over
many years. ARM does not manufacture its own VLSI devices; rather, it licenses its
architecture to companies who either manufacture the CPU itself or integrate the ARM
processor into a larger system. The textual description of instructions, as opposed to
their binary representation, is called an assembly language. ARM instructions are
written one per line, starting after the first column. Comments begin with a semicolon
and continue to the end of the line. A label, which gives a name to a memory location,
comes at the beginning of the line, starting in the first column.
Q1. Discuss about ARM architecture versions.
ARM Architecture Versions:
The ARM architecture has evolved significantly and will continue to be
developed in the future. Six major versions of the instruction set have been defined to
date, denoted by the version numbers from 1 to 6. Of these, the first three versions
including the original 26-bit architecture (the 32-bit architecture was introduced at
ARMv3) are now OBSOLETE. Other versions are Version 4, version 5 and
version6.Versions can be qualified with variant letters to specify collections of
additional instructions that are included as an architecture extension. Extensions are
typically included in the base architecture of the next version number, ARMv5T being
the notable exception. Provision is also made to exclude variants by prefixing the
variant letter with x, for example the XP variant described below in the summary of
version 5 features.
The valid architecture variants are as follows: ARMv4, ARMv4T, ARMv5T,
(ARMv5TExP), ARMv5TE, ARMv5TEJ, and ARMv6
The following architecture variants are now OBSOLETE: ARMv1, ARMv2, ARMv2a,
ARMv3, AR M v 3 G , AR M v 3 M, ARMv4xM, ARMv4TxM, ARMv5, ARMv5xM,
and ARMv5TxM.
Version 4 and the introduction of Thumb (T variant):
The Thumb instruction set is a re-encoded subset of the ARM instruction set. Thumb
instructions execute in their own processor state, with the architecture defining the
mechanisms required to transition between ARM and Thumb states. The key difference
is that Thumb instructions are half the size of ARM instructions (16 bits compared with
32 bits).
Thumb code usually uses more instructions for a given task, making ARM code
best for maximizing performance of time-critical code.
ARM state and some associated ARM instructions are required for
exception handling.
3
The current processor mode governs which of several banks is accessible. Each mode
can access
a particular set of r0-r12 registers
a particular r13 (the stack pointer, sp) and r14 (the link register)
the program counter, r15 (pc)
the current program status register, CPSR
Privileged modes (except System) can also access
a particular SPSR(saved program status register)
Features of ARM Processor:
The ARM processors provide advanced features for a variety of applications.
Several extensions provide improved digital signal processing.
Saturation arithmetic can be performed with no overhead.
A new instruction is used for arithmetic normalization.
Multimedia operations are supported by single instruction multiple data
operations.
A separate monitor mode allows the processor to enter a secure world to
perform operations not permitted in normal mode.
5
Q3. Compare ARM processor with other processors.
ARM Processor vs other Processors:
ARM is designed on RISC Architecture, hence it is having reduced instructions,
where Intel and AMD are designed on x86 CISC architecture.
The core difference between these is ARM instructions operates only on registers
with a few instructions for loading and saving data from or to memory while x86
can operate on directly memory as well.
ARM is a simpler architecture, leading to small silicon area and lots of power save
features while x86 becoming a power beast in terms of both power consumption
and production.
The ARM is a Reduced Instruction Set Computer (RISC), as it incorporates these typical
RISC architecture features:
o A large uniform register file.
o A load/store architecture, where data-processing operations only operate on
register contents, not directly on memory contents.
o Uniform and fixed-length instruction fields, to simplify instruction decode.
Harvard architecture Vs Von-Neumann architecture:
Von-Neumann architecture Harvard architecture
The memory holds both data and Harvard architecture is like the von
instructions, and can be read or written Neumann architecture. Harvard
whengiven an address.. machine has separate memories for data
and program.
ARM Registers:
ARM has 31 general-purpose 32-bit registers. At any one time, 16 of these registers
are visible. The other registers are used to speed up exception processing. All the
register specifiers in ARM instructions can address any of the 16 visible registers.
The main bank of 16 registers is used by all unprivileged code. These are the User
mode registers. User mode is different from all other modes as it is unprivileged,
which means:
User mode can only switch to another processor mode by generating an
exception. The SWI instruction provides this facility from program control.
Memory systems and coprocessors might allow User mode less access to
memory and coprocessor functionality than a privileged mode.
Three of the 16 visible registers have special roles:
Stack pointer:
Software normally uses R13 as a Stack Pointer (SP). R13 is used by the PUSH and
POP instructions in T variants, and by the SRS and RFE instructions from ARMv6.
Link register:
6
Register 14 is the Link Register (LR). This register holds the address of the next
instruction after a Branch and Link (BL or BLX) instruction, which is the instruction
used to make a subroutine call. It is also used for return address information on entry
to exception modes. At all other times, R14 can be used as a general-purpose register.
Program counter:
Register 15 is the Program Counter (PC). It can be used in most instructions as a
pointer to the instruction which is two instructions after the instruction being
executed. In ARM state, all ARM instructions are four bytes long (one 32-bit word)
and are always aligned on a word boundary.
Supervisor mode:
• Supervisor mode is an execution mode on some processors which enables the
execution of all instructions, including privileged instructions.
• It is thus capable of executing both input/output operations and privileged
operations. The operating system of a computer usually operates in this mode.
• Supervisor mode helps in preventing applications from corrupting the data of the
operating system.
• The ARM instruction that puts the CPU in supervisor mode is called SWI.
(SWI CODE_1)
• The argument to SW1 is a 24-bit immediate value that is passed on to the supervisor
mode code; it allows the program to request various services from the supervisor
mode.
• In supervisor mode control programs are executed
Exceptions:
An exception (or exceptional event) is a problem that arises during the execution of a
program. It is an internally detected error. When an Exception occurs the normal flow
of the program is disrupted and the program/Application terminates abnormally,
therefore these exceptions are to be handled.
A simple example is division by zero. One way to handle this problem would be to
check every divisor before division to be sure it is not zero, but this would both
substantially increase the size of numerical programs and cost a great deal of CPU
time evaluating the divisor’s value.
ARM supports seven types of exception, and a privileged processing mode for each
type. The seven types of exception are:
reset
attempted execution of an Undefined instruction
software interrupt (SWI) instructions, can be used to make a call to an
operating system
Prefetch Abort, an instruction fetch memory abort
Data Abort, a data access memory abort
IRQ, normal interrupt
FIQ, fast interrupt.
Traps:
A trap, also known as a software interrupt, is an instruction that explicitly
generates an exception condition. The most common use of a trap is to enter
supervisor mode. The entry into supervisor mode must be controlled to
7
given an address. A computer whose memory holds both data and instructions is
known as a von Neumann machine.
An alternative to the von Neumann style of organizing computers is the Harvard
architecture, which is nearly as old as the von Neumann .
Assembly Language:
Assembly language follows this relatively structured form to make it easy for the
assembler to parse the program and to consider most aspects of the program line by
line.
One instruction appears per line.
Labels, which give names to memory locations, start in the first column.
Instructions must start in the second column or after to distinguish them from
labels.
Comments run from some designated comment character (; in the case of
ARM) to the end of the line.
Addressing:
Base-plus-offset addressing in ARM processor:
The ARM also supports several forms of base-plus-offset addressing, which is
related to indirect addressing. But rather than using a register value directly as an
address, the register value is added to another value to form the address. For instance,
LDR r0, [r1,#16] loads r0 with the value stored at location r1_16.
Here, r1 is referred to as the base and the immediate value the offset. When the offset is
an immediate, it may have any value up to 4,096; another register may also be used as
the offset.
The base-plus-offset addressing mode has two other variations: auto-indexing and post-
indexing. Auto-indexing updates the base register, such that
Eg: LDR r0,[r1,#16]!
LDR r0, [r1],#16
VLIW vs Superscalar:
VLIW architectures are distinct from traditional RISC and CISC architectures
implemented in current mass-market microprocessors. It is important to distinguish
instruction-set architecture—the processor programming model—from implementation
— the physical chip and its characteristics.
9
Very long instruction word (VLIW) processors are most likely used by digital
signal, processing systems. These Processors r e l y on t h e compiler t o identify sets
o f instructions that can be executed in parallel. The efficiencies of the VLIW processors can
more easily be leveraged by digital signal processing software. VLIW processors consume
less power and are very smaller than superscalar processors. Since it is very small, it is used in
signal processing and multimedia applications.
Superscalar
Processor:
A single-issue processor executes one instruction at a time. Although it may have
several instructions at different stages of execution, only one can be at any particular
stage of execution. Several other types of processors allow multiple-issue
instruction. A superscalar processor uses specialized logic to identify at run time
instructions that can be executed simultaneously. Superscalar processors often use
too much energy and are too expensive for widespread use in embedded systems.
A data dependency is a relationship between the data operated on by instructions. In
the example of Figure given below, the first instruction writes into r0 while the second
instruction reads from it. As a result, the first instruction must finish before the second
instruction can perform its addition. The data dependency graph shows the order in
which these operations must be performed.
The ARM instruction set can be divided into six broad classes of instruction:
Branch instructions
Data-processing instructions on page
Status register transfer instructions on page
Load and store instructions on page
Coprocessor instructions on page
Exception-generating instructions on page.
Branch Instructions:
The B (branch) instruction is the basic mechanism in ARM for changing the flow of
control. The address that is the destination of the branch is often called the branch
target.
Branches are PC-relative—the branch specifies the offset from the current PC value
to the branch target. The offset is in words, but because the ARM is byte
addressable, the offset is multiplied by four (shifted left two bits, actually) to form a
byte address. Thus, the instruction B #100 will add 400 to the current PC value.
There are also branch instructions which can switch instruction set, so that
execution continues at the branch target using the Thumb instruction set. Thumb
support allows ARM code to call Thumb subroutines, and ARM subroutines to
return to a Thumb caller. Similar instructions in the Thumb instruction set allow the
corresponding Thumb → ARM switches.
Data-processing instructions on page
The da t a -processing i n s t r uc t i o n s pe r f o r m c a l c ula t i o n son t h
e g e n e r a l -purpose
Registers. There are five types of data-processing
instructions:
Arithmetic/logic instructions
Comparison instructions
Single Instruction Multiple Data (SIMD) instructions
Multiply instructions on page
Miscellaneous Data Processing instructions on page.
Arithmetic/logic instructions:
The arithmetic or logical instructions is used to perform arithmetic or logical
operations. The source operands used here is two and the result is made to store
at the destination register. Based on the result the code flag condition will get
updated. Of the two source operands:
One is always a register
The other has two basic forms:
an immediate value
a register value, optionally shifted.
The arithmetic operations perform addition and subtraction; the with-carry versions
include the current value of the carry bit in the computation.
ADD r0, r1, r2
11
This instruction sets register r0 to the sum of the values stored in r1 and r2.
In addition to specifying registers as sources for operands, instructions may also
provide immediate operands, which encode a constant value directly in the
instruction. For example,
ADD r0, r1,#2 sets r0 to r1+2.
Comparison instructions:
The comparison instructions use the same instruction format as the
arithmetic/logic instructions. These perform an arithmetic or logical operation on two
source operands, but do not write the result to a register. They always update
the condition flags, based on the result. The source operands of comparison
instructions take the same forms as those of arithmetic/logic instructions, including
the ability to incorporate a shift operation.
Comparison of Instruction and MOVE instruction in ARM processor:
The compare instruction
CMP r0, r1 computes r0 – r1, sets the status bits, and throws away the result of
the subtraction.
CMN uses an addition to set the status bits. TST performs a bit-wise AND on the
operands, while TEQ performs an exclusive-OR.
The instruction
MOV r0, r1 sets the value of r0 to the current value of r1.
The MVN instruction complements the operand bits (one’s complement) during
themove.
Single Instruction Multiple Data (SIMD) instructions:
The add and subtract instructions treat each operand as two parallel 16-bit numbers,
or four parallel 8-bit numbers. They can be treated as signed or unsigned. The
operations can optionally be saturating, wrap around, or the results can be halved to
avoid overflow. These instructions are available in ARMv6.
Multiply instructions on page:
There are several classes of multiply instructions, introduced at different times
intothe architecture.
Miscellaneous Data Processing instructions on page:
These include Count Leading Zeros (CLZ) and Unsigned Sum of Absolute
Differences with optional Accumulate (US AD8 and US ADA8).
Examples
B loop A ; Branch to loop A
BL funC ; Branch with link (Call) to function funC,
return address; stored in LR
BX LR ; Return from function call
BLX R0 ;Branch with link and exchange (Call) to a address
stored ; in R0
BEQ labelD ; Conditionally branch to labelD if last flag setting
; instruction set the Z flag, else do not branch.
Stacks and Subroutines:
Stack:
The stack is an area of memory identified by the programmer for temporary
storage of information.
The stack is a LIFO (Last in First Out.) structure.
The stack normally grows backwards into memory.
In other words, the programmer defines the bottom of the stack and the stack
grows up into reducing address range.
Given that the stack grows backwards into memory, it is customary to place
the bottom of the stack at the end of memory to keep it as far away from
user programs as possible.
In the 8085, the stack is defined by setting the SP (Stack Pointer) register.
LXI SP, FFFFH.
This sets the Stack Pointer to location FFFFH (end of memory for the 8085).
o Increment SP
o MP reads the subroutine address from the next two memory location and
stores the higher order 8bit of the address in the W register and stores the
lower order 8bit of the address in the Z register.
o Push the address of the instruction immediately following the CALL onto
the stack(Return address)
o Loads the program counter with the 16-bit address supplied with the CALL
instruction from WZ register.
The RTE Instruction
RTE
o 1-byte instruction
o Retrieve the return address from the top of the stack and increments stack
pointer register by two.
o Load the program counter with the return address.
o Unconditionally returns from a subroutine.
An exte nde d data flow graph for our sample basic block.
O The data flow graph for our single-assignment code The single-assignment form
means that the data flow graph is acyclic
O If we assigned to x multiple times, then the second assignment would form a cycle
in the graph including x and the operators used to compute x.
Figure 5.6 shows a bit of C code with control constructs and the CDFG constructed
from it. The rectangular nodes in the graph represent the basic blocks.
The basic blocks in the C code have been represented by function calls for simplicity.
The diamond-shaped nodes represent the conditionals.
The node’s condition is given by the label, and the edges are labeled with the
possible outcomes of evaluating the condition.
Building a CDFG for a while loop is straightforward, as shown in Figure 5.7.
The while loop consists of both a test and a loop body, each of which we know how
to represent in a CDFG. We can represent for loops by remembering that, in C, a for
loop is defined in terms of a while loop.
The following for loop
for (i = 0; i < N; i++) {
loop_body();
}
is equivalent to
i = 0;
while (i < N)
{
loop_body();
i++;
}
if (cond1)
basic_block_1( );
else
basic_block_2();
2
2
basic_block_3( );
switch (test1) {
case c1: basic_block_4( );
break; case c2: basic_block_5(
); break; case c3:
basic_block_6( ): break;
}
For a complete CDFG model, we can use a data flow graph to model each data
flow node. Thus, the CDFG is a hierarchical representation data flow CDFG can be
expanded to reveal a complete data flow graph.
An execution model for a CDFG is very much like the execution of the program it
represents. The CDFG does not require explicit declaration of variables, but we
assume that the implementation has sufficient memory for all the variables.
2
As we execute the program, we either execute the data flow node or compute the 3
decision in the decision node and follow the appropriate edge, depending on the type
of node the program counter points on.
Even though the data flow nodes may specify only a partial ordering on the data flow
computations, the CDFG is a sequential representation of the program. There is only
one program counter in our execution model of the CDFG, and operations are not
executed in parallel.The CDFG is not necessarily tied to high- level language control
structures. We can also build a CDFG for an assembly language program. A jump
instruction corresponds to a nonlocal edge in the CDFG.
ASSEMBLY AND LINKING:
□ Assembly and linking are the last steps in the compilation process they turn a list of
instructions into an image of the program’s bits in memory.
□ Loading actually puts the program in memory so that it can be executed.
□ The compilation process is often hidden from us by compilation commands that do
everything required to generate an executable program.
□ As the figure shows, most compilers do not directly generate machine code, but instead
create the instruction- level program in the form of human-readable assembly language.
□ Generating assembly language rather than binary instructions frees the compiler writer
from details extraneous to the compilation process, which includes the instruction format
as well as the exact addresses of instructions and data.
□ The assembler’s job is to translate symbolic assembly language statements into bit- level
representations of instructions known as object code. T
□ The assembler takes care of instruction formats and does part of the job of translating
labels into addresses.
□ However, since the program may be built from many files, the final steps in determining
the addresses of instructions and data are performed by the linker, which produces an
executable binary file.
□ That file may not necessarily be located in the CPU’s memory, however, unless the
linker happens to create the executable directly in RAM. The program that brings the
program into memory for execution is called a loader.
□ The simplest form of the assembler assumes that the starting address of the assembly
language program has been specified by the programmer. The addresses in such a
program are known as absolute addresses.
2
4
Assemblers
□ When translating assembly code into object code, the assembler must translate opcodes
and format the bits in each instruction, and translate labels into addresses.
□ Labels make the assembly process more complex, but they are the most important
abstraction provided by the assembler.
□ Labels let the programmer (a human programmer or a compiler generating assembly
code) avoid worrying about the locations of instructions and data. Label processing
requires making two passes through the assembly source code as follows:
□ The first pass scans the code to determine the address of each label.
□ The second pass assembles the instructions using the label values computed in the first
pass.
□ The name of each symbol and its address is stored in a symbol table that is built during
the first pass. The symbol table is built by scanning from the first instruction to the last.
□ During scanning, the current location in memory is kept in a program location counter
(PLC).
□ Despite the similarity in name to a program counter, the PLC is not used to execute the
program, only to assign memory locations to labels.
□ For example, the PLC always makes exactly one pass through the program, whereas the
program counter makes many passes over code in a loop.
□ Thus, at the start of the first pass, the PLC is set to the program’s starting address and the
assembler looks at the first line.
□ After examining the line, the assembler updates the PLC to the next location and looks at
the next instruction.
□ If the instruction begins with a label, a new entry is made in the symbol table, which
includes the label name and its value. The value of the label is equal to the current value
of the PLC.
□ At the end of the first pass, the assembler rewinds to the beginning of the assembly
language file to make the second pass.
2
5
□ During a second pass when a label name is found, the label is looked up in the symbol
table and its value substituted into the appropriate place in the instruction.
□ But how do we know the starting value of the PLC? The simplest case is absolute
addressing.
□ In this case, one of the first statements in the assembly language program is a pseudo-op
that specifies the origin of the program, that is, the location of the first address in the
program.
□ A common name for this pseudo-op (e.g., the one used for the ARM) is the ORG
statement, which puts the start of the program at location 2000.
ORG 2000
□ This pseudo-op accomplishes this by setting the PLC’s value to its argument’s value,
2000 in this case.
□ Assemblers generally allow a program to have many ORG statements in case instructions
or data must be spread around various spots in memory.
Linking:
□ Many assembly language programs are written as several smaller pieces rather than as a
single large file.
□ Breaking a large program into smaller files helps delineate program modularity.
□ If the program uses library routines, those will already be preassembled, and assembly
language source code for the libraries may not be available for purchase.
□ A linker allows a program to be stitched together out of several smaller pieces.
□ The linker operates on the object files created by the assembler and modifies the
assembled code to make the necessary links between files.
□ Some labels will be both defined and used in the same file. Other labels will be defined in
a single file but used elsewhere.
□ The place in the file where a label is defined is known as an entry point. The place in the
file where the label is used is called an external reference.
□ The main job of the loader is to resolve external references based on available entry
points.
□ As a result of the need to know how definitions and references connect, the assembler
passes to the linker not only the object file but also the symbol table.
2
6
□ Even if the entire symbol table is not kept for later debugging purposes, it must at least
pass the entry points.
□ External references are identified in the object code by their relative symbol identifiers.
□ Compilation begins with high- level language. Simplifying arithmetic expressions is one
example of a machine- independent optimization. Not all compilers do such
optimizations, and compilers can vary widely regarding which combinations of machine-
independent optimizations they do perform.
□ Instruction- level optimizations are aimed at generating code.
□ They may work directly on real instructions or on a pseudo- instruction format that is
later mapped onto the instructions of the target CPU.
□ This level of optimization also helps modularize the compiler by allowing code
generation to create simpler code that is later optimized. For example, consider the
following array access code:
x[i] = c*x[i];
□ A simple code generator would generate the address for x[i] twice, once for each
appearance in the statement.
3
□ 1
While in this simple case it would be possible to create a code generator that never
generated the redundant expression, taking into account every such optimization at code
generation time is very difficult.
□ Better code and more reliable compilers are get by generating simple code first and then
optimizing it.
How to analyze programs to estimate their run times and examine how to optimize programs to
improve their execution times? (May 2023)
It is important to keep in mind that CPU performance is not judged in the same
way as program performance.
Certainly, CPU clock rate is a very unreliable metric for program performance.
But more importantly, the fact that the CPU executes part of our program quickly
does not mean that it will execute the entire program at the rate we desire.
As illustrated in Figure 5.22, the CPU pipeline and cache act as windows into our
program. In order to understand the total execution time of our program, we must
look at execution paths, which in general are far longer than the pipeline and
cache windows.
The pipeline and cache influence execution time, but execution time is a global
property of the program.
The execution time of programs could be precisely determined; this is in fact difficult to do in
practice:
■ The execution time of a program often varies with the input data values because those
values select different execution paths in the program.
For example, loops may be executed a varying number of times, and different branches
may execute blocks of varying complexity.
■ The cache has a major effect on program performance, and once again, the cache’s
behavior depends in part on the data values input to the program.
Execution times may vary even at the instruction level. Floating-point operations
are the most sensitive to data values, but the normal integer execution pipeline can
also introduce data-dependent variations.
In general, the execution time of an instruction in a pipeline depends not only on
that instruction but on the instructions around it in the pipeline.
3
3
We can measure program performance in several ways:
■ Average-case execution time: This is the typical execution time we would expect
for typical data. Clearly, the first challenge is defining typical inputs.
■ Worst-case execution time: The longest time that the program can spend on any
input sequence is clearly important for systems that must meet deadlines. In some cases, the
input set that causes the worst-case execution time is obvious, but in many cases it is not.
■ Best-case execution time: This measure can be important in mult i-rate real-
time systems
The key to evaluating execution time is breaking the performance problem into parts.
Program execution time can be seen as
3
3
UNIT-III PROCESS ES AND OPERATING S YS TEMS
Structure of a real – time system – Task Assignment and Scheduling – Multiple Tasks and
Multiple Processes – Multirate Systems – Pre emptive real – time Operating systems – Priority
based scheduling – Interprocess Communication Mechanisms – Distributed Embedded Systems
–MPSoCs and Shared Memory Multiprocessors – Design Example – Audio Player, Engine
Control Unit and Video Accelerator.
□ Most operating systems (even those that support multiple scheduling policies) schedule
all applications according to the same scheduling algorithm at any given time.
□ Whether each application can meet its timing requirements is determined by a global
schedulability analysis based on parameters of every task in the system.
□ The necessity of detailed timing and resource usage information of all applications that
may run together often forces the applications to be developed together and, thus, keeps
the system closed.
□ Hard real-time applications can run with soft real-time and non- real-time applications in
this environment. It makes use of the two- level scheduling scheme.
□ This scheme enables each real- time application to be scheduled in a way best suited for
the application and the schedulability of the application to be determined independent of
other applications that may run with it on the same hardware platform.
□ Many (if not most) embedded computing systems do more than one thing—that is, the
environment can cause mode changes that in turn cause the embedded system to behave
quite differently.
□ For example, when designing a telephone answering machine, one can define recording a
phone call and operating the user‘s control panel as distinct tasks, because they perform
logically distinct operations and they must be performed at very different rates.
□ These different tasks are part of the system‘s functionality, but that application- level
organization of functionality is often reflected in the structure of the program as well.
1
□ A process is a single execution of a program. If a user runs the same program two
different times, then two different processes are created. Each process has its own state
that includes not only its registers but all of its memory.
□ In some OSs, the memory management unit is used to keep each process in a separate
address space. In others, particularly lightweight RTOSs, the processes run in the same
address space. Processes that share the same address space are often called threads.
The terms tasks and processes somewhat interchangeably, as do many people in the field.
To be more precise, task can be composed of several processes or threads; it is also true
that a task is primarily an implementation concept and processes more of an
implementation concept.
□ To understand why the separation of an application into tasks may be reflected in the
program structure, consider how to build a stand-alone compression unit based on the
compression algorithm. This device is connected to serial ports on both ends.
□ The input to the box is an uncompressed stream of bytes. The box emits a compressed
string of bits on the output serial line, based on a predefined compression table. Such a
box may be used, for example, to compress data being sent to a modem.
□ The program‘s need to receive and send data at different rates for example, the program
may emit 2 bits for the first byte and then 7 bits for the second byte will obviously find
itself reflected in the structure of the code.
□ It is easy to create irregular, ungainly code to solve this problem; a more elegant solution
is to create a queue of output bits, with those bits being removed from the queue and sent
to the serial port in 8-bit sets.
□ But beyond the need to create a clean data structure that simplifies the control structure of
the code, and it is necessary to ensure that input and output signals are to be processed at
the proper rates.
□ For example, if too much of time is spent in packaging and emitting output characters,
then input character can be dropped. Solving timing problems is a more challenging
problem.
□ Again, with a few exceptions, a real-time operating system consists of a microkernel that
provides the basic operating system functions described below. Figure 4.2 shows a
general structure of a microkernel.
□ There are three reasons for the kernel to take control from the executing thread and
execute itself: to respond to a system call, do scheduling and service timers, and handle
external interrupts. The kernel also deals with recovery from hardware and software
exceptions, but activities are ignored.
□ System Calls. The kernel provides many functions which, when called, do some work on
behalf of the calling thread. An application can access kernel data and code via these
functions. They are called Application Program Interface (API) functions.
□ A system call is a call to one of the API functions. In a system that provides memory
protection, user and kernel threads execute in separate memory spaces.
□ Upon receiving a system call, the kernel saves the context of the calling thread and
switches from the user mode to the kernel mode. It then picks up the function name and
arguments of the call from the thread‘s stack and executes the function on behalf of the
thread.
□ When the system call completes, the kernel executes a return from exception. As a result,
the system returns to the user mode. The calling thread resumes if it still has the highest
priority. If the system call causes some other thread to have the highest priority, then that
thread executes.
□ The calling thread is blocked until the kernel completes the called function. When the call
is asynchronous (e.g., in the case of an asynchronous I/O request), the calling thread
3
continues to execute after making the call. The kernel provides a separate thread to
execute the called function.
□ Many embedded operating systems do not provide memory protection; the kernel and
user execute in the same space.
□ Reasons for this choice are the relative trustworthiness of embedded applications and the
need to keep overhead small. (The extra memory space needed to provide full memory
protection is on the order of a few kilobytes per process. This overhead is more serious for
small embedded applications than the higher context-switch overhead that also incurs with
memory protection.)
□ In such a system, a system call is just like a procedure or function call within the
application. Figure 4.2 shows examples of thread management functions: create thread,
suspend thread, resume thread and destroy thread.
□ The timer functions listed below them exemplify the time services a real- time operating
system provides.
□ The output interface, output conditioning, and the actuator are interfaced in a
complementary manner. In the following, content briefly describe the roles of the
different functional blocks of a real-time system.
□ Sensor: A sensor converts some physical characteristic of its environment into electrical
signals. An example of a sensor is a photo- voltaic cell which converts light energy into
electrical energy. A wide variety of temperature and pressure sensors are also used.
□ A temperature sensor typically operates based on the principle of a thermocouple.
Temperature sensors based on many other physical principles also exist.
□ For example, one type of temperature sensor employs the principle of variation of
electrical resistance with temperature (called a varistor). A pressure sensor typically
operates based on the piezoelectricity principle. Pressure sensors based on other physical
principles also exist.
□ Actuator: An actuator is any device that takes its inputs from the output interface of a
computer and converts these electrical signals into some physical actions on its
environment.
□ The physical actions may be in the form of motion, change of thermal, electrical,
pneumatic, or physical characteristics of some objects. A popular actuator is a motor.
Heaters are also very commonly used. Besides, several hydraulic and pneumatic actuators
are also popular.
□ Signal Conditioning Units: The electrical signals produced by a computer can rarely be
used to directly drive an actuator. The computer signals usually need conditioning before
they can be used by the actuator.
□ This is termed output conditioning. Similarly, input conditioning is required to be carried
out on sensor signals before they can be accepted by the computer.
□ For example, a sensor might produce voltage in the millivolts range, whereas the inp ut
interface of a computer may require the input signal level to be of the order of a volt.
□ Voltage Level Shifting: Voltage level shifting is often required to align the voltage level
generated by a sensor with that acceptable to the computer.
□ For example, a sensor may produce voltage in the range -0.5 to +0.5 volt, whereas the
input interface of the computer may accept voltage only in the range of 0 to 1 volt. In this
case, the sensor voltage must undergo level shifting before it can be used by the
computer.
□ Frequency Range Shifting and Filtering: Frequency range shifting is often used to reduce
the noise components in a signal. Many types of noise occur in narrow bands and the
signal must be shifted from the noise bands so that noise can be filtered out.
□ Signal Mode Conversion: A type of signal mode conversion that is frequently carried out
during signal conditioning involves changing direct current into alternating current and
vice-versa.
□ Another type signal mode conversion that is frequently used is conversion of analog
signals to a constant amplitude pulse train such that the pulse rate or pulse width is
proportional to the voltage level.
□ Conversion of analog signals to a pulse train is often necessary for input to systems such
as transformer coupled circuits that do not pass direct current. D/A
□ Interface Unit: Normally commands from the CPU are delivered to the actuator through
an output interface. An output interface converts the stored voltage into analog form and
then outputs this to the actuator circuitry.
4.1.4. Estimating program run times
Q4. Discuss about estimating program run times /Enumerate the need for host based
systems for stages of simulation, porting kernels and estimating program run times in
embedded application deployment (DEC2022/JAN2023)
6
□ Processes can have several different types of timing requirements imposed on them by
the application. The timing requirements on a set of processes strongly influence the type
of scheduling that is appropriate.
□ A scheduling policy must define the timing requirements that it uses to determine
whether a schedule is valid. Before studying scheduling proper, some outline of the types
of process timing requirements that are useful in embedded system design.
□ Figure 4.5 illustrates different ways in which two important requirements on processes
can be defined: release time and deadline.
□ The release time is the time at which the process becomes ready to execute; this is not
necessarily the time at which it actually takes control of the CPU and starts to run.
□ An aperiodic process is by definition initiated by an event, such as external data arriving
or data computed by another process.
□ The release time is generally measured from that event, although the system may want to
make the process ready at some interval after the event itself.
□ For a periodically executed process, there are two common possibilities. In simpler
systems, the process may become ready at the beginning of the period. More
sophisticated systems, such as those with data dependencies between processes, may set
the release time at the arrival time of certain data, at a time after the start of the period.
□ A deadline specifies when a computation must be finished. The deadline for an aperiodic
process is generally measured from the release time, since that is the only reasonable time
reference. The deadline for a periodic process may in general occur at some time other
than the end of the period. Some scheduling policies make the simplifying assumption
that the deadline occurs at the end of the period.
7
□ Rate requirements are also fairly common. A rate requirement specifies how quickly
processes must be initiated.
□ The period of a process is the time between successive executions. For example, the
period of a digital filter is defined by the time interval between successive input samples.
□ The process‘s rate is the inverse of its period. In a multirate system, each process
executes at its own distinct rate.
□ The most common case for periodic processes is for the initiation interval to be equal to
the period. However, pipelined execution of processes allows the initiation interval to be
less than the period. Figure 4.6 illustrates process execution in a system with four CPUs.
□ The various execution instances of program P1 have been subscripted to distinguish their
initiation times. In this case, the initiation interval is equal to one fourth of the period.
□ It is possible for a process to have an initiation rate less than the period even in single-
CPU systems.
□ If the process execution time is significantly less than the period, it may be possible to
initiate multiple copies of a program at slightly offset times violation depend on the
application—the results can be catastrophic in an automotive control system, whereas a
missed deadline in a multimedia system may cause an audio or video glitch.
□ The system can be designed to take a variety of actions when a deadline is missed.
Safety-critical systems may try to take compensatory measures such as approximating
data or switching into a special safety mode. Systems for which safety is not as important
may take simple measures to avoid propagating bad data, such as inserting silence in a
phone line, or may completely ignore the failure.
□ Even if the modules are functionally correct, their timing improper behavior can
introduce major execution errors. Application Example 4.6 describes a timing problem in
space shuttle software that caused the delay of the first launch of the shuttle.
□ The order of execution of processes may be constrained when the processes pass data
between each other. Figure 4.6 shows a set of processes with data dependencies among
them. Before a process can become ready, all the processes on which it depends must
complete and send their data to
8
it.
□ The data dependencies define a partial ordering on process execution—P1 and P2 can
execute in any order (or in interleaved fashion) but must both complete before P3, and P3
must complete before P4.All processes must finish before the end of the period.
□ The data dependencies must form a directed acyclic graph (DAG)—a cycle in the data
dependencies is difficult to interpret in a periodically executed system.
□ A set of processes with data dependencies is known as a task graph. Although the
terminology for elements of a task graph varies from author to author, some of the
component of the task graph is considered (a set of nodes connected by data
dependencies) as a task and the complete graph as the task set.
□ The figure also shows a second task with two processes. The two tasks ({P1, P2, P3, P4}
and {P5, P6}) have no timing relationships between them.
□ Communication among processes that run at different rates cannot be represented by data
dependencies because there is no one-to-one relationship between data coming out of the
source process and going into the destination process Nevertheless, communication
among processes of different rates is very common.
□ Figure 4.7 illustrates the communication required among three elements of an MPEG
audio/video decoder.
□ Data come into the decoder in the system format, which multiplexes audio and video
data. The system decoder process demultiplexes the audio and video data and distributes
it to the appropriate processes.
□ Multirate communication is necessarily one way—for example, the system process writes
data to the video process, but a separate communication mechanism must be provided for
communication from the video process back to the system process.
Utilization is the ratio of the CPU time that is being used for useful computations to the total
available CPU time. This ratio ranges between 0 and 1, with 1 meaning that all of the available
CPU time is being used for system purposes. The utilization is often expressed as a percentage.
Q5. Explain Task Assignment and Scheduling/ Scheduling of real time systems/ what is
the purpose of Priority based scheduling? Discuss in detail with appropriate diagrams
(Dec 2022/Jan 2023, May 2023, Dec 2023)
Scheduling
□ The first job of the OS is to determine that process runs next. The work of choosing the
order of running processes is known as scheduling.
□ The OS considers a process to be in one of three basic scheduling states: waiting, ready,
or executing. There is at most one process executing on the CPU at any time. (If there is
no useful work to be done, an idling process may be used to perform a null operation.)
Any process that could execute is in the ready state; the OS chooses among the ready
processes to select the next executing process.
□ A process may not, however, always be ready to run. For instance, a process may be
waiting for data from an I/O device or another process, or it may be set to run from a
timer that has not yet expired. Such processes are in the waiting state.
□ A process goes into the waiting state when it needs data that it has not yet received or
when it has finished all its work for the current period.
□ A process goes into the ready state when it receives its required data and when it enters a
new period.
□ A process can go into the executing state only when it has all its data, is ready to run, and
the scheduler selects the process as the next process to run.
Scheduling Policies
□ A scheduling policy defines how processes are selected for promotion from the ready
state to the running state. Every multitasking OS implements some type of scheduling
policy.
10
□ Choosing the right scheduling policy not only ensures that the system will meet all its
timing requirements, but it also has a profound influence on the CPU horsepower
required to implement the system‘s functionality.
□ Schedulability means whether there exists a schedule of execution for the processes in a
system that satisfies all their timing requirements. In general, it is necessary to construct a
schedule to show schedulability, but in some cases some sets of processes as
unschedulable using some very simple tests can be eliminated.
□ Utilization is one of the key metrics in evaluating a scheduling policy. Our most basic
requirement is that CPU utilization be no more than 100% since one can‘t use the CPU
more than 100% of the time.
Priority-Based Scheduling
After assigning priorities, the OS takes care of the rest by choosing the highest-priority
ready process.
There are two major ways to assign priorities: static priorities that do not change during
execution and dynamic priorities that do change.
Rate-Monotonic Scheduling
Rate-monotonic scheduling (RMS), introduced by Liu and Layland, was one of the first
scheduling policies developed for real- time systems and is still very widely used. RMS is
a static scheduling policy.
It turns out that these fixed priorities are sufficient to efficiently schedule the processes in
many situations. The theory underlying RMS is known as rate-monotonic analysis
(RMA).
This theory, as summarized below, uses a relatively simple model of the system.
11
□ All deadlines are at the ends of their periods.
□ The highest-priority ready process is always selected for execution.
The major result of RMA is that a relatively simple scheduling policy is optimal under
certain conditions.
Priorities are assigned by rank order of period, with the process with the shortest period
being assigned the highest priority.
Applying the principles of RMA, P1 is provided with the highest priority, P2 the middle priority,
and P3 the lowest priority. To understand all the interactions between the periods, it is needed to
construct a time line equal in length to hyper period, which are 12 in this case.
□ All three periods start at time zero. P1‘s data arrive first. Since P1 is the highest-priority
process, it can start to execute immediately.
□ After one time unit, P1 finishes and goes out of the ready state until the start of its next
period. At time 1, P2 starts executing as the highest-priority ready process. At time 3, P2
finishes and P3 starts executing. P1‘s next iteration starts at time 4, at which point it
interrupts P3. P3 gets one more time unit of execution between the second iterations of
P1 and P2, but P3 does not get to finish until after the third iteration of P1.
□ Consider the following different set of execution times for these processes, keeping the
same deadlines.
□ In this case, no feasible assignment of priorities that guarantees scheduling can be shown.
Even though each process alone has an execution time significantly less than its period,
combinations of processes can require more than 100% of the available CPU cycles.
12
□ For example, during one 12 time-unit interval, P1 was executed three times, requiring 6
units of CPU time; P2 twice, costing 6 units of CPU time; and P3 one time, requiring 3
units of CPU time. The total of 6 + 6 + 3 = 15 units of CPU time is more than the 12 time
units available, clearly exceeding the available CPU capacity.
13
RMS vs. EDF
□ Which scheduling policy is better: RMS or EDF? That depends on criteria of a user. EDF
can extract higher utilization out of the CPU, but it may be difficult to diagnose the
possibility of an imminent overload.
□ Because the scheduler does take some overhead to make scheduling decisions, a factor
that is ignored in the schedulability analysis of both EDF and RMS, running a scheduler
at very high utilizations is somewhat problematic.
□ RMS achieves lower CPU utilization but is easier to ensure that all deadlines will be
satisfied. In some applications, it may be acceptable for some processes to occasionally
miss deadlines. For example, a set-top box for video decoding is not a safety-critical
application, and the occasional display artifacts caused by missing deadlines may be
acceptable in some markets.
What if your set of processes is unschedulable and you need to guarantee that they
complete their deadlines? There are several possible ways to solve this problem:
□ Get a faster CPU. That will reduce execution times without changing the periods, giving
you lower utilization. This will require you to redesign the hardware, but this is often
feasible because you are rarely using the fastest CPU available.
□ Redesign the processes to take less execution time. This requires knowledge of the code
and may or may not be possible.
□ Rewrite the specification to change the deadlines. This is unlikely to be feasible, but may
be in a few cases where some of the deadlines were initially made tighter than necessary.
14
Example:
Consider a standalone compression unit, this device is connected to serial ports on
both ends.
The input to the box is an uncompressed stream of bytes.
The box emits a compressed string of bits on the output serial line, based on a
predefined compression table.
Such a box may be used, to compress data being sent to a modem.
The program’s need to receive and send data at different rates.
For example, the program may emit 2 bits for the first byte and then 7 bits for the
second byte will obviously find itself reflected in the structure of the code.2
It is easy to create irregular code to solve this problem; a more elegant solution is to create
a queue of output bits, with those bits being removed from the queue and sent to the serial
port in 8-bit sets.
An on-the-
15
For example, if too much time is spend in packaging and emitting output characters, we
may drop an input character. Solving timing problems is a more challenging problem.
The text compression box provides a simple example of rate control problems.
A control panel on a machine provides an example of a different type of rate control
problem, the asynchronous input.
The control panel of the compression box may include a compression mode button that
disables or enables compression, so that the input text is passed through unchanged when
compression is disabled.
16
5.1.3 Timing Requirements on Processes
Explain in detail about timing re quireme nt on processes.
Processes can have several different types of timing requirements imposed on them by
the application.
The timing requirements on a set of processes strongly influence the type of
scheduling that is appropriate.
A scheduling policy must define the timing requirements that it uses to determine
whether a schedule is valid.
There are two important timing requirements on processes: release time and deadline.
Release time:
The release time is the time at which the process becomes ready to execute.
An aperiodic process is initiated by an event, such as external data arriving or data
computed by another process.
The release time is generally measured from that event.
For a periodically executed process, there are two common possibilities.
In simpler systems, the process may become ready at the beginning of the period
More sophisticated systems may set the release time at the arrival time of certain
data, at a time after the start of the period.
Deadline:
□ A deadline specifies when a computation must be finished.
□ The deadline for an aperiodic process is generally measured from the release time
□ The deadline for a periodic process may occur at some time other than the end of the
period.
□ The period of a process is the time between successive executions. For example, the
period of a digital filter is defined by the time interval between successive input
samples.
□ The process’s rate is the inverse of its period. In a multirate system, each process
executes at its own distinct rate.
17
5
18
6
The CPU time is not equal to the completion time minus initiation time; several other
processes may interrupt execution.
The total CPU time consumed by a set of processes is
To measure the efficiency of CPU,the simplest and most direct measure is utilization:
U= CPU time for useful
work Total available
CPU time
U=T/t
Utilization is the ratio of the CPU time that is being used for useful computations to the total
available CPU time.
This ratio ranges between 0 and 1, with 1 meaning that all of the available CPU time is
being used for system purposes.
The utilization is often expressed as a percentage.
19
7
□ That, together with the timer, will allow moving between functions whenever necessary
based upon the system’s timing constraints.
□ The CPU is shared across two processes. The kernel is the part of the OS that determines
what process is running.
□ The kernel is activated periodically by the timer.
□ The length of the timer period is known as the time quantum because it is the smallest
increment in which we can control CPU activity.
□ The kernel determines what process will run next and causes that process to run.
□ On the next timer interrupt, the kernel may pick the same process or another process
to run.
□ Before, using the timer to control loop iterations, with one loop iteration including
the execution of several complete processes.
□ Here, the time quantum is in general smaller than the execution time of any of the
processes.
□ The timer interrupts causes control to change from the currently executing process to the
kernel; assembly language can be used to save and restore registers.
□ Similarly use assembly language to restore registers not from the process that was
interrupted by the timer but to use registers from any process we want.
□ The set of registers that define a process are known as its context and switching from one
process’s register set to another is known as context switching.
□ The data structure that holds the state of the process is known as the process control
block.
20
8
21
9
Types of scheduling:
Cyclostatic Scheduling:
One very simple scheduling policy is known as cyclostatic scheduling or sometimes as
Time Division Multiple Access scheduling.
A cyclostatic schedule is divided into equal- sized time slots over an interval equal to the
length of the hyperperiod H.
Processes always run in the same time slot.
Cyclostatic scheduling.
Two factors affect utilization in cyclostatic scheduling
□ The number of time slots used
□ The fraction of each time slot that is used for useful work.
Depending on the deadlines for some of the processes, some time slots may need to
beleave empty.
Since the time slots are of equal size, some short processes may have time left over in
their time slot
Round-robin scheduling:
Round robin uses the same hyperperiod as in cyclostatic.
It also evaluates the processes in order.
Round-robin scheduling.
But unlike cyclostatic scheduling, if a process does not have any useful work to do, the
round-robin scheduler moves on to the next process in order to fill the time slot with
useful work.
In this example, all three processes execute during the first hyperperiod, but during the
second one, P1 has no useful work and is skipped.
The processes are always evaluated in the same order.
The last time slot in the hyperperiod is left empty; if we have occasional, non-periodic
tasks without deadlines.
Round-robin scheduling is often used in hardware such as buses because it is very simple
to implement but it provides some amount of flexibility.
22
1
0
23
1
1
Applying the principles of RMA, we give P1 the highest priority, P2 the middle
priority, and P3 the lowest priority.
To understand all the interactions between the periods, construct a time line equal in
length to hyperperiod, which is 12 in this case.
All three periods start at time zero. P1’s data arrive first. Since P1 is the highest-priority
process, it can start to execute immediately.
After one time unit, P1 finishes and goes out of the ready state until the start of its next
period. At time 1, P2 starts executing as the highest-priority ready process.
At time 3, P2 finishes and P3 starts executing. P1’s next iteration starts at time 4, at
which point it interrupts P3.
P3 gets one more time unit of execution between the second iterations of P1 and P2, but
P3 does not get to finish until after the third iteration of P1.
In this case the CPU time execute with in the period of 12 units. Even though each
process alone has an execution time significantly less than its period, combinations of
processes can require more than 100% of the available CPU cycles.
Response Time: Response time of a process is the time at which the process finishes.
Critical Instant: The critical instant for a process is defined as the instant during execution
at which the task has the largest response time.
The proof using critical instants is easy while knowing the RMA when it is ready and all
higher priority processes are also ready.
Also critical instant is used to determine whether there is any feasible schedule for the
system.
Critical- instant analysis also implies that priorities should be assigned in order of periods.
24
12
12
13
The hyperperiod is 30. According to the above system the P1 has the highest priority, P2 is the
middle priority and P3 is the lowest priority. Then the deadline table is written as
Time Running pr ocess Deadli ne
0 P1
1 P2
2 P3
3 P3
4 P1 P1
5 P2 P2
6 P1 P3
7 P3 P1
8 P3
9 P1 P2
10 P2 P1
11 P3 P3
12 P1
13 P3 P1, P 2
14 P2 P2
15 P1 P2, P3
16 P2
17 P3 P1
18 P1 P2 P 3
19 Idle
20 P3 P1
21 P2
22 P1 P 2, P3
23 P3 P1
24 P3 P2
25 P1 P3
26 P2 P1, P2
27 P2 P3
28 P1 P1
29 P3 P2, P3
The one time slot is idle at t =19 then the CPU utilization is 19/30. Hence the EDF is achieved
nearly to 100% utilization of CPU.
Compare RMS versus EDF (NOV/DEC 2018)
RMS vs EDF
Compare Rate-Monotonic Scheduling and Earliest –Dead line – First scheduling
Which scheduling policy is better: RMS or EDF? That depends on the criteria.
EDF can extract higher utilization out of the CPU, but it may be difficult to diagnose the
possibility of an imminent overload.
RMS achieves lower CPU utilization but it is easier to ensure that all deadlines. Able to
diagnose the possibility of an imminent overload.
13
14
If a set of processes is unschedulable and we need to guarantee that they complete their
deadlines? There are several possible ways to solve this problem:
Get a faster CPU. That will reduce execution times without changing the periods, giving
you lower utilization.
Redesign the processes to take less execution time. This requires knowledge of the code
and may or may not be possible.
Rewrite the specification to change the deadlines. This is unlikely to be feasible, but
may be in a few cases where some of the deadlines were initially made tighter than
necessary.
5.6. MULTIPROCESSOR:
Write short notes on Multiprocessor (April 2010)
A multiprocessor is, in general, any computer system with two or more processors
coupled together.
Multiprocessors used for scientific or business applications tend to have regular
architectures: several identical processors that can access a uniform memory space.
Embedded system designers must take a more general view of the nature of
multiprocessors.
The first reason for using an embedded multiprocessor is that they offer significantly
better cost/performance that is, performance and functionality per dollar spent on the
system
The cost of a microprocessor increases greatly as the clock speed increases.
Clock speeds are normally distributed by normal variations in VLSI processes; because
the fastest chips are rare, they naturally command a high price in the marketplace.
Because the fastest processors are very costly, splitting the application so that it can be
performed on several smaller processors is usually much cheaper.
Even with the added costs of assembling those components, the total system comes out
to be less expensive.
In addition to reducing costs, using multiple processors can also help with real time
performance.
It may take an extremely large and powerful CPU to provide the same responsiveness
that can be had from a distributed system.
Many of the technology trends encourage us to use multiprocessors for performance also
lead us to multiprocessing for low power embedded computing.
Some Processors running at slower clock rates consume less power than a single large
processor: performance scales linearly with power supply voltage but power scales with
V2.
14
15
15
16
16
17
17
18
If the flag was nonzero, we loop back to try to get the flag once again.
5.7.1. Message Passing:
Message passing communication complements the shared memory model each
communicating entity has its own message send/receive unit.
The message is not stored on the communications link, but rather at the senders/
receivers at the end points.
In contrast, shared memory communication can be seen as a memory block used as a
communication device, in which all the data are stored in the communication
link/memory.
18
19
to save and restore context and we must execute additional instructions to implement the
scheduling policy.
On the other hand, context switching can be implemented efficiently context, switching
need not kill performance.
The effects of nonzero context switching time must be carefully analyzed in the context
of a particular implementation to be sure that the predictions of an ideal scheduling policy
are sufficiently accurate.
In most real-time operating systems, a context switch requires only a few hundred
instructions, with only slightly more overhead for a simple real-time scheduler like RMS.
When the overhead time is very small relative to the task periods, then the zero-time
context switch assumption is often a reasonable approximation.
Problems are most likely to manifest themselves in the highest-rate processes, which are
often the most critical in any case.
Completely checking that all deadlines will be met with nonzero context switching time
requires checking all possible schedules for processes and including the context switch
time at each preemption or process initiation
19
5.8.3. DISTRIBUTED EMBEDDED SYSTEMS
1. Discuss in detail about the distributed embedded architecture. (Nov/Dec 2014,
April 2018, NOV/DEC 2018)
2. Explain about distributed embedded architecture with suitable examples.
(Apr/May2015) (Dec2022/Jan2023)
□ Distributed system is more than two CPUs communicated in a tightly coupled
manner.
□ The main reason to implementing distributed system in the embedded field is it
will provide high performance to perform complicated task in an easy manner,
high processing rate.
Types
1. System Architecture
2. Software Architecture
□ A distributed embedded system can be organized in many different ways, but its basic
units are PE and the network processing element (PE) is either microprocessors or ASIC
used to connect by a network.
□ Processing element allows the network to communicate.
□ A distributed embedded system can be organized in many different ways,
□ A PE may be an instruction set processor such as a DSP, CPU, or microcontroller, as
well as a nonprogrammable unit such as the ASICs used to implement PE 4.
□ An I/O device such as PE 1 (which we call here a sensor or actuator, depending on
whether it provides input or output) may also be a PE, so long as it can speak the network
protocol to communicate with other PEs.
□ The network in this case is a bus, but other network topologies are also possible.
□ It is also possible that the system can use more than one network, such as when relatively
independent functions require relatively little communication among them.
□ We often refer to the connection between PEs provided by the network as a
communication link.
□ The system of PEs and networks forms the hardware platform on which the
application runs.
□ In particular, PEs do not fetch instructions over the network as they do on the
microprocessor bus
20
2
8
□ The speed at which PEs can communicate over the bus would be difficult if not
impossible to predict if we allowed arbitrary instruction and data fetches as we do on
microprocessor buses.
In distributed embedded system having several PEs and network it leads to more
complicated than using a single large microprocessor to perform the same tasks.
□ Networks are complex systems. Ideally, they provide high- level services while
hiding many of the details of data transmission from the other components.
□ In order to help understand (and design) networks, the International Standards
Organization has developed a seven- layer model for networks known as
Open Systems Interconnection (OSI) models.
□ Understanding the OSI layers will help us to understand the details of real networks.
□ The seven layers of the OSI model, are intended to cover a broad spectrum of networks
and their uses.
21
2
9
□ Some networks may not need the services of one or more layers because the higher layers
may be totally missing or an intermediate layer may not be necessary.
□ However, any data network should fit into the OSI model.
The OSI layers from lowest to highest level of abstraction are described below.
Physical Layer
□ The physical layer defines the basic properties of the interface between systems,
including the physical connections, electrical properties, basic functions of the
electrical and physical components and the basic procedures for exchanging bits.
Data Link Layer
□ The primary purpose of this layer is error detection and control across a single link.
□ If the network requires multiple hops over several data links, the data link layer does
not define the mechanism for data integrity between hops, but only within a single
hop.
Network Layer
□ This layer defines the basic end-to-end data transmission service. The network layer
is particularly important in multi hop networks.
□ This layer divides the message into packet form.
Transport Layer
□ The transport layer defines connection oriented services that ensures that data
are delivered in the proper order and without errors across multiple links.
□ This layer may also try to optimize network resource utilization.
Presentation Layer:
□ Presentation layer defines data exchange formats and provides transformation
utilities to application programs.
Session Layer
□ A session provides mechanisms for controlling the interaction of end user
services across a network, such as data grouping and check pointing.
Application Layer
□ The application layer provides the application interface between the network and end-
user programs.
22
3
0
□ Simple embedded networks provide internet service that will implement the full range of
functions in the OSI model.
5.9.5. Write short notes on MPSoCs and Shared me mory multiprocessors (NOV 2017)
(Dec2022/Jan 2023)
□ Shared memory processors are well-suited to applications that require a large amount of data to be
processed. Signal processing systems stream data and can be well- suited to shared memory
processing.
□ Most MPSoCs are shared memory systems. Shared memor y allows for processors to communicate
with varying patterns. If the pattern of communication is very fixed and if the processing of
different steps is performed in different units, then a networked multiprocessor may be most
appropriate.
□ If the communication patterns between steps can vary, then shared memory provides that
flexibility. If one processing element is used for several different steps, then shared memory also
allows the required flexibility in communication.
□ Different processing elements perform different functions. The PEs may be programmable
processors with different instruction sets or specialized accelerators that provide little or no
programmability.
23
□ In both cases, the motivation for using different types of PEs is efficiency. Processors with
different instruction sets can perform different tasks faster and using less energy. Accelerators
provide even faster and lower-power operation for a narrow range of functions.
24
46
AUDIO PLAYER
5.9a.1. Design an Audio Player (NOV 2017)
Audio players are defined as any media player which can only play audio files.
Players capable of video playback are included under comparison of video pla yer
software, even if they are primarily well known for audio playback.
Theory of operation and requirements:
Audio players are often called MP3 players.
After the popular audio data format, a number of audio compression formats have been
developed and are in regular use.
The earliest portable MP3 players were based on compact disc mechanisms and modern
MP3 players use either flash memory or disk drivers to store music.
Functions:
An MP3 player performs three basic functions such as
1. Audio storage
2. Audio compression
3. User Interface
Audio decompression: It is relatively light weight. The incoming bit stream has been
encoded using a Huffmann style code, which must be encoded. The audio data itself is
applied to reconstruction filter, along with a new other parameters.
Audio compression: It is a lossy process that relies on perceptual coding. The
coder eliminates certain features of the audio stream so that the result can be encoded in
fewer bits. It tries to eliminate features that are not easily perceived by human audio system.
25
Masking: It is one perceptual phenomenon that is exploited by perceptual coding. One
tone can be masked by another if the tones are sufficiently close in frequency. Some audio
features can also be masked if they occur too close in time after another feature.
50
Encoder: Audio signals tend to be more correlated within a narrower band, so splitting
into sub bands help the encoder reduce the bit rate.
Quantizer: It scales each sub band so that it fits within 6 bits of dynamic range, then
quantizes based upon the current scale factor for that sub band.
Masking model: It selects the scale factors. It driven by a separate Fast Fourier
Transform (FFT), the filter bank could be used for masking; a separate FFT provides
better results.
Multiplexer: The multiplexer at the output of the encoder passes along all the required
data.
MPEG Layer 1 decoder:
□ MPEG audio decoding is a straight forward process.
□ After disassembling the data frame, the data are unscaled and inverse quantized to produce
sample streams for the sub band.
□ An inverse filter bank reassembles the sub bands into the uncompressed data.
26
5
1
Choose
Filter requantiz
bank *
FFT Masking
demux Scale
0101.. inverse
quantize Inverse
filter
expand
Step
Fig.MPEG layer 1 decoder
User interface: The user interface of an MP3 player is usually kept simple to minimize both
physical size and power consumption of the device. Many players provide only a simple
display and a few buttons.
File system: The file system of the player must be compatible with PCs. The CD/MP3 players
used compact discs that had been created on PCs. Today’s players can be plugged into USB
ports and treated as disk drivers on the host processor.
Specification:
The file ID class is an abstraction of a file in the flash file system. The controller
class provides the method that operates the player.
27
5
2
The file management is performed on a host device, then the basic operations to
be specified are simple.
28
5
3
This state diagram refers to send the samples to the audio system rather than
explicitly sending them because playback and reading the next data frame must be
overlapped to ensure continuous operation.
29
54
Explain in detail the design of engine control unit (NOV 2017, NOV/DEC 2018,
APRIL/MAY2019)/ Multitasking capacity of RTOS helps in engine control
automation(DEC2022/JAN2023)
Engine Control Unit (ECU) is a generic term for any embedded system that
controls one or more of the electrical system or subsystems in a motor
vehicle.
An Engine Control Unit (ECU) is a type of electric control unit that controls
a series of actuator on an internal combustion engine to ensure optimal
engine performance.
It does this by reading values from a multitude of sensors within the engine
body, interpreting the data using multidimensional performance maps called
Lockup tables and adjusting the engine actuators accordingly.
Engine control unit controls the operation of a fuel injected engine based on
several measures taken from the running engine.
Design a basic engine controller for a simple Fuel injected engine. The block
diagram of engine is shown in below figure.
The Throttle is the command input. The engine measures throttle. RPM intake air
volume, and other variables.
54
55
The engine controller computes injector pulse width and spark. This doesn’t compute all
the outputs required by a real engine.
Requirements
Requirements for the engine Control unit shown in the below figure.
Name ECU
Purpose Engine controller for fuel- injected engine
Inputs Throttle, RPM, intake air volume, intake manifold pressure
Outputs Injector pulse width, spark advance angle.
Functions Compute injector pulse width and spark advance angle as a
function of throttle, RPM, intake air volume, intake manifold
pressure.
Performance Injector pulse updated at 2- ms period, spark advance angle
updated at 1- ms period.
Manufacturing Cost Approximately $ 50
Power Power by engine generator
Physical size and weight Approx. 4 in x 4 in, less than 1 pound
55
56
SPECIFICATION
The engine controller must deal with processes that happen at different rates.
Below figure shows the updates periods for the different signals.
Use NE and T to represent the change in RPM and throttle position, respectively.
Our controller computes two output signals, injector pulse width PW and spark
advance angle S.
□ As the intake air temperature (THA) increases during the engine warm- up, the
controller reduces the injection duration.
□ As the throttle opens, the controller temporarily increases the injection frequency.
□ The Controller adjusts duration up or down based upon readings from the exhaust oxygen
sensor (OX).
□ The injection duration is increased as the battery voltage (+B) drops.
SYSTEM ARCHITECTURE
Below figure shows the class diagram for the engine controller. The two major process,
pulse-width and advance-angle, compute the control parameters for the sparkplugs and
injectors.
56
57
The Control Parameters rely on charges in some of the input signals. Use
the physical sensor classes to compute these values.
Each change must be updated at the variables sampling rate. The update processes
is simplified by performing it in a task runs at the required update rate.
State diagram
State diagram for throttle position sensing is shown in below figure. It saves both
the current value and change in value of the throttle.
Use similar control flow to compute changes to the other variables.
57
58
Below figure shows the state diagram for injector pulse width and spark advance angle.
In each case the value is computed in two stages, first an initial value followed by a correction.
The pulse width and advance angle processes do not generate the waveforms
to drive the spark and injector waveforms.
These waveforms must be carefully timed to the engine’s current state.
Each spark plug and injector must fix at exactly the right time in the engine cycle,
taking into account the engine’s current speed as well as the control parameters.
58
59
Some engine controller platforms provide Hardware units that generate high
rate, changing waveforms.
For example consider MPC5602D. Then main processor is a power PC processor.
The enhanced modular I/O subsystem provides 28 input and output channels
controlled by Timers.
Each channel can perform a variety of functions.
The output pulse width and frequency modulation buffered mode will
automatically generate a waveform whose period and duty cycle can be varied by
writing registers in the enhanced modular I/) subsystems.
The details of the waveform timing are handled by the output channel hardware.
Because these objects must be updated at different rates, their execution will be
controlled by an RTOS. Depending on the RTOS Latency, separate the I/O
functions into interrupt service handlers and threads.
The various tasks must be coded to satisfy the requirements of RTOS processes.
Variables that are maintained across task execution must be allocated and
saved in appropriate memory locations.
The RTOS initialization phase is used to set up the task periods.
Because some of the output variables depend on changes in states, these tasks
should be tested with multiple input variables sequences to ensure that both the
basic and adjustment calculations are performed correctly.
Engine generates huge amounts of electrical noise that can cripple digital electronics.
They also operate over very wide temperature ranges.
Any testing performed on an actual engine must be conducted using an engine controller
that has been designed to withstand the harsh environment of the engine compartment.
59
60
A video accelerator is a hardware circuit on a display adapter that speed up full motion video,
which also frees the CPU to take care of other tasks. Motion estimation engines are used in
real-time search engines; we may want to have one attached to our personal computer to
experiment with video processing techniques.
□ Block motion estimation is used in digital video compression algorithms so that one
frame in the video can be described in terms of the differences between it and another
frame.
□ Because objects in the frame often move relatively little, describing one frame in terms of
another greatly reduces the number of bit
□ The goal is to perform a two-dimensional correlation to find the best match between
regions in the two frames.
□ We divide the current frame into macroblocks.
□ We want to find the region in the previous frame that most closely matches the
macroblock.
□ Searching over the entire previous frame would be too expensive, so we usually limit the
search to a given area, centered around the macroblock and larger than the macroblock.
□ Intensity is measured as an 8-bit luminance that represents a monochrome pixel—color
information is not used in motion estimation.
□ We choose the macroblock position relative to the search area that gives us the smallest
value for this metric.
60
61
□ The offset at this chosen position describes a vector from the search area center to
the macroblock’s center that is called the motion vector.
□ For simplicity, we will build an engine for a full search, which compares the macroblock
and search area at every possible point.
Requirements:
Name: Block motion estimator
Purpose: Perform block motion estimation within a PC system
Inputs: Macroblocks and search areas
Outputs: Motion vectors
Functions: Compute motion vectors using full search algorithms
Performance: As fast as we can get
Manufacturing cost: Hundreds of dollars
Power: Powered by PC power supply
Physical size: Packaged as PCI card for PC
Specification
□ The specification for the system is relatively straightforward because the algorithm is
simple.
□ Because the behavior is simple, we need to define only two classes to describe it:
the accelerator itself and the PC.
61
62
Architecture
□ The accelerator will be implemented in an FPGA on a card connected to a PC’s PCI slot.
□ Such accelerators can be purchased or they can be designed from scratch.
□ If you design such a card from scratch, you have to decide early on whether the card will
be used only for this video accelerator or if it should be made general enough to support
other applications as well.
62
63
Component Design
System Testing
□ Testing video algorithms requires a large amount of data. Luckily, the data represents
images and video, which are plentiful.
63
64
□ Because we are designing only a motion estimation accelerator and not a complete video
compressor, it is probably easiest to use images, not video, for test data.
□ You can use standard video tools to extract a few frames from a digitized video and store
them in JPEG format.
□ Open source for JPEG encoders and decoders is available. These programs can be
modified to read JPEG images and put out pixels in the format required by your
accelerator.
□ With a little more cleverness, the resulting motion vector can be written back onto the
image for a visual confirmation of the result. If you want to be adventurous and try
motion estimation on video, open source MPEG encoders and decoders are also
available
64
65
UNIT IV IOT ARCHITECTURE AND PROTOCOLS 9
Internet – of – Things – Physical Design, Logical Design – IoT Enabling Technologies – DomainSpecific
IoTs – IoT and M2M – IoT System Management with NETCONF – YANG – IoT PlatformDesign –
Methodology – IoT Reference Model – Domain Model – Communication Model – IoTReference
Architecture – IoT Protocols - MQTT, XMPP, Modbus, CANBUS and BACNet.
Internet – of – Things
The Internet of Things (IoT) is a network of connected devices that can communicate with each
other, share data, and perform tasks without human intervention. The importance of
communication in IoT cannot be overstated, as it is the foundation on which the entire system is
built. The devices that make up the IoT ecosystem need to be able to communicate with each
other in order to function properly and achieve their intended purpose.
Effective communication in IoT enables devices to share data, receive instructions, and respond
to requests in a timely and accurate manner. This is critical for the successful implementation of
IoT solutions across various industries, such as healthcare, manufacturing, transportation, and
smart homes.`
For example, in a smart home, the communication between the devices (such as lights,
thermostats, and security systems) allows them to work together to create a more convenient and
secure living environment for the occupants. Similarly, in a healthcare setting, IoT devices can
be used to monitor patients remotely and alert healthcare providers in case of an emergency,
ensuring that timely medical intervention is provided.
Physical Design, Logical Design
While talking about the logical and physical design of IoT we are talking about the physical devices and
the protocols that take data from one device to another. All of the work together as a single unit. Each of
the physical devices is called a node and each device has its own unique identity with the help of protocol
they do things like monitoring, sensing and tracking. IoT today are becoming immensely popular.
Companies today are implementing IoT technologies more so if you want to be relevant to the tech
industry you have to know one or two things about IoT sadly very few do this.
Home Automation
Smart Cities
Environment
Energy systems
Retail
Logistics
Industry
Agriculture
Health
Bluetooth
Bluetooth works in a frequency range of 2.4GHz. It covers a range of 10m to 100m, and its data
rate goes up to 1MBPS. It supports two network topologies – point-to-point and mesh. It is
suitable to send a small amount of data to personal devices like speakers, earphones, smart
watches, smart shoes, etc. This protocol can also be used for Smart Homes, including Alarms,
HVAC, lighting, etc.
Zigbee
This is based on the IEEE802.15.4 standard. Its frequency range is the same as that of Bluetooth,
which is 2.4GHz. Its range is up to 100 meters, and the data rate is a maximum of 250KBPS.
Zigbee protocol can transmit small amounts of data within a short range. This can be used in
systems that require high authentication and robustness. It supports star topology, mesh
topology, and cluster tree topology. Major applications observed are sensing device health in
industries, smart homes, etc.,
6LoWPAN
PAN stands for Personal Area Network, and 6LoWPAN refers to IPV6 Low Power PAN. It
works in a frequency ranging from 900 to 2400MHz. The data rate is 250KBPS, supporting two
network topologies - star and mesh.
Short Range Communication, High Data
Rate WirelessLAN - Wi-Fi
Wi-Fi has high bandwidth and allows a data rate of 54MBPS and goes up to 600MBPS. Covers a
range of 50m in the local area where providing private antennas goes to 30 km. IoT devices can
be easily connected using Wi-Fi and share a large amount of data. This protocol is used in smart
homes, smart cities, offices, etc
Long Range Communication, High Data Rate, Low
power LoRaWAN
This stands for Long Range Wide Area Network. Its range is approximately 2.5km and can go
up to 15km. The data rate is very low, which is 03, and KBPS and goes up to a maximum of
50KBPS. It can support many connected devices and is used in applications like Smart City,
Supply Chain Management, etc.
LTE-M
LTE-M stands for Long Term Evolution for Machines. This is a type of LPWAN – Low Power
Wide Area Network. This is used along with cellular networks to provide security. LTE-M
works in a frequency range of 1.4MHz-5MHz, and the data rate can go up to 4MBPS.
Long Range, Low Data Rate, Low Power
Consumption
Sigfox
Sigfox is used when wide area coverage is required with minimum power consumption. It aims
at connecting billions of IoT devices. This protocol’s frequency range is 900MHZ, covering a
range of 3km to 50km. The maximum data rate is very low, which is 1KBPS.
Long Range, Low Data Rate, High Power
Consumption
Cellular
This is also known as a mobile network. Cellular networks are 2G, 3G, 4G, and 5G. It Has
frequency ranges – 900MHz, 1.8/1.9/2.1 GHz. The range is approximately 35km and goes up to
200km. The average data rate is 35KBPS – 170KBPS. Cellular networks consume high power.
This protocol is not used for most IoT devices due to frequency and security issues. It can be
used with IoT applications like connected cars.
IOT Communication models:
Client-Server Model
In the Client-Server communication model, the client sends encoded requests to the server for
information as needed. This model is stateless, meaning that each request is handled
independently and data is not retained between requests. The server categorizes the request,
retrieves the data from the database or resource representation, and converts it to an encoded
response that is sent back to the client. The client then receives the response.
On the other hand, in the Request-Response communication model, the client sends a request to
the server and the server responds to the request by deciding how to retrieve the data or
resources needed to prepare the response. Once prepared, the server sends the response back to
the client.
Publish-Subscribe Model
The Publish-Subscribe communication model consists of three entities: Publishers, Brokers, and
Consumers.
Publishers are responsible for generating and sending data to specific topics managed by the
broker. Publishers are not aware of the consumers subscribed to the topic.
Consumers subscribe to the topics managed by the broker to receive data from the publishers.
The broker is responsible for sending the data to the appropriate consumers based on their
subscription to specific topics.
The broker is responsible for accepting data from the publishers and forwarding it to the
appropriate consumers subscribed to that specific topic. The broker is the only entity that has
information regarding the consumer to which a particular topic belongs, and publishers are not
aware of this information.
Push-Pull Model
The Push-Pull communication model consists of three entities: data publishers, data consumers,
and data queues. Publishers and consumers are not aware of each other. Publishers push
messages or data into the queue, and consumers on the other end pull data out of the queue. The
queue acts as a buffer for messages when there is a difference in the rate of data push or pull by
the publisher and consumer.
Queues play an essential role in decoupling messaging between the producer and consumer, and
they act as a buffer in situations where there is a mismatch in the rate at which data is pushed
by
producers and pulled by consumers. This buffer helps ensure smooth communication between
the two entities.
Once a connection is established, both the client and server can exchange messages with each
other. As long as the client does not request to close the connection, it remains open, and the
server is aware of every open connection. This enables the client and server to communicate
seamlessly and in real- time.
One of the most significant trends in IoT communication models is the shift towards edge
computing. This approach involves processing data c loser to the source, rather than transmitting
it to a centralized cloud server. By moving processing closer to the edge of the network, latency
can be reduced, and real-time responses can be achieved. This approach also reduces the amount
of data that needs to be transmitted, reducing bandwidth requirements and improving efficiency.
Another trend is the development of hybrid communication models that combine different
communication protocols to achieve the best possible results. For example, a hybrid model might
combine the Publish-Subscribe model with the Request-Response model to achieve real-time
data updates while still allowing for targeted data requests.
IoT devices are found everywhere and will enable circulatory intelligence in the future. For
operational perception, it is important and useful to understand how various IoT devices
communicate with each other. Communication models used in IoT have great value. The IoTs
allow people and things to be connected any time, any space, with anything and anyo ne, using
any network and any service.
Types of Communication Model :
1. Request & Response Model –
This model follows a client-server architecture.
The client, when required, requests the information from the server. This request is
usually in the encoded format.
This model is stateless since the data between the requests is not retained and each
request is independently handled.
The server Categories the request, and fetches the data from the database and its resource
representation. This data is converted to response and is transferred in an encoded format
to the client. The client, in turn, receives the response.
On the other hand — In Request-Response communication model client sends a request
to the server and the server responds to the request. When the server receives the request
it decides how to respond, fetches the data retrieves resources, and prepares the response,
and sends it to the client.
2. Publisher-Subscriber Model –
This model comprises three entities: Publishers, Brokers, and Consumers.
Publishers are the source of data. It sends the data to the topic which are managed by the
broker. They are not aware of consumers.
Consumers subscribe to the topics which are managed by the broker.
Hence, Brokers responsibility is to accept data from publishers and send it to the
appropriate consumers. The broker only has the information regarding the consumer to
which a particular topic belongs to which the publisher is unaware of.
3. Push-Pull Model –
The push-pull model constitutes data publishers, data consumers, and data queues.
Publishers and Consumers are not aware of each other.
Publishers publish the message/data and push it into the queue. The consumers, present
on the other side, pull the data out of the queue. Thus, the queue acts as the b uffer for the
message when the difference occurs in the rate of push or pull of data on the side of a
publisher and consumer.
Queues help in decoupling the messaging between the producer and consumer. Queues
also act as a buffer which helps in situations where there is a mismatch between the rate
at which the producers push the data and consumers pull the data.
4. Exclusive Pair –
Exclusive Pair is the bi-directional model, including full-duplex communication among
client and server. The connection is constant and remains open till the client sends a
request to close the connection.
The Server has the record of all the connections which has been opened.
This is a state-full connection model and the server is aware of all open connections.
WebSocket based communication API is fully based on this model.
Conclusion
Finally, there is a growing focus on security and privacy in IoT communication models. As the
number of connected devices continues to grow, the risk of security breaches and data theft also
increases. Communication models that prioritize security and privacy will become increasingly
important in the future to ensure the safe and secure exchange of data.
UNIT-5
UNIT V IOT SYSTEM DESIGN 9
Basic building blocks of an IoT device – Raspberry Pi – Board – Linux on Raspberry Pi – Interfaces–
Programming with Python – Case Studies: Home Automation, Smart Cities, Environment andAgriculture.
The Internet of Things denotes the connection of devices, machines, and sensors to the Internet.
An IoT system comprises four basic building blocks: sensors, processors, gateways, and
applications. This article will thoroughly discuss what each component of the IoT architecture
represents.
3. Gateways are the combination of hardware and software used to connect one network to
another. Gateways are responsible for bridging sensor nodes with the external Internet or
World Wide Web. The figure below depicts how using gateways works.
4. Applications provide a user interface and effective utilization of the data
collected. The figure above illustrates some examples of IoT applications.
In summary, the IoT architecture comprises four basic building blocks: sensors, processors,
gateways, and applications. Sensors are responsible for converting a non-electrical input to an
electrical signal; processors ―handle‖ the signals; gateways are used to connect a netwo rk to
another, and, ultimately, an application offers a user interface and effective utilization of the data
collected.
History Of Raspberry Pi
One-board Raspberry Pi computers have been developed in the United Kingdom by
the Raspberry Pi Foundation to promote basic computer science teaching in schools and
developing countries.
The original model became more popular than expected, selling out of its target
market for use as robots. Includes peripherals (such as keyboards and mice) or cases.UK
Relief Society registered in the UK (No. 1129409), May 2009.
Supported by the University of Cambridge Computer Laboratory and technology firm
Broadcomm.
Raspberry Pi Hardware has been upgraded with several versions that include
memory capacity variations and peripheral compatible device support.
Important Components Of Hardware
The Raspberry Pi has a Broadcom BCM2835system on chip (SoC), which includes
the ARM1176JZF-S 700 MHz processor, which was later upgraded to Broadcom
BCM2711, Quad-core Cortex-A72 (ARM v8) 64-bit SoC 1.5GHz.
Originally shipped with 256 megabytes of RAM, later upgraded to 4GB.
Does not include a built- in hard disk, but uses an SD card for boot and long-term storage.
OS Support: Linux-based (Fedora, Raspbian, Debian, ArchLinux ARM, etc ..).
Planning Languages
By default, it supports Python as a language of instruction.
Any integrated ARMv6 language can be used with Raspberry Pi.
Automatically installed in Raspberry Pi:
C or C ++ or Java or Ruby or Scratch
Application
Can be used to make high-end computers.
Raspberry Pi Medical Device Shield.
Solar Raspberry Pi Power Pack.
Voice Crafted Coffee Machine.
Raspberry Pi Dynamic Bike Headlight Prototype.
IoT Based Smart Application.
Raspberry Pi Interfaces
Raspberry Pi is most popular SBC(Single Board Computer). We can used Raspberry Pi as an IoT
device and IoT Gateway. In this article we discuss Raspberry Pi Interfaces. Interfaces used for
connecting Sensors and actuators.
What is Raspberry pi ?
The Raspberry Pi is a low cost, credit-card sized computer that plugs into a computer monitor
or TV, and uses a standard keyboard and mouse. It is a capable little device that enables people
of all ages to explore computing, and to learn how to program in languages like Scratch and
Python. It‘s capable of doing everything you‘d expect a desktop computer to do, from browsing
the internet and playing high-definition video, to making spreadsheets, word-processing, and
playing games.‖
If you know about Raspberry Pi more, Visit this : Raspberry Pi Tutorials
If you have a Raspberry Pi and you want to setup for use in Headless mode, Visit This
: Raspberry Pi Headless Mode Setup
Raspberry pi has Serial, SPI and I2C interfaces for data transfer.
Serial : The Serial interface on Raspberry Pi has receive (Rx) and transmit (Tx) pins for
communication with serial peripherals.
SPI : Serial Peripheral Interface (SPI) is a synchronous serial data protocol used for
communicating with one or more peripheral devices. in an SPI connection, there are five pins on
Raspberry Pi for SPI interface :
MISO (Master in slave out) – Master line for sending data to the peripherals.
MOSI (Master out slave in) – Slave line for sending data to the master.
SCK (Serial Clock) – Clock generated by master to synchronize data transmission
CE0 (Chip Enable 0) – To enable or disable devices
CE0 (Chip Enable 1) – To enable or disable devices
I2C :
The I2C interface pins on Raspberry Pi allow you to connect hardware modules. I2C interface
allows synchronous data transfer with just two pins – SDA (data line) an SCL (Clock Line).
The Python programming language actually started as a scripting language for Linux.
Python programs are similar to shell scripts in that the files contain a series of commands
that the computer executes from top to bottom.
Compare a “hello world” program written in C to the same program written in Python:
Unlike C programs, Python programs don’t need to be compiled before running them.
However, you will need to install the Python interpreter on your computer to run them. The
Python interpreter is a program that reads Python files and executes the code.
It is possible to run Python programs without the Python interpreter installed though.
Programs like Py2exe or Pyinstaller will package your Python code into stand-alone
executable programs.
WHAT CAN A PYTHON PROGRAM DO?
Like shell scripts, Python can automate tasks like batch renaming and moving large
amounts of files. It can be used just like a command line with IDLE, Python’s REPL (read,
eval, print, loop) function. However, there are more useful things you can do with Python.
For example, you can use Python to program things like:
Web applications
Special GUIs
Small databases
2D games
Python also has a large collection of libraries, which speeds up the development proc ess.
There are libraries for everything you can think of – game programming, rendering graphics,
GUI interfaces, web frameworks, and scientific computing.
Many (but not all) of the things you can do in C can be done in Python. Python is generally
slower at computations than C, but its ease of use makes Python an ideal language for
prototyping programs and designing applications that aren’t computationally intensive.
Enter this code into Nano, then press Ctrl-X and Y to exit and save the file:
#!/usr/bin/python
All Python program files will need to be saved with a “.py” extension. You can write the
program in any text editor such as Notepad or Notepad++, just be sure to save the file
with a “.py” extension.
python hello-world.py
MAKE A PYTHON FILE EXECUTABLE
Making a Python program executable allows you to run the program without
entering python before the file name. You can make a file executable by entering this at the
command prompt:
chmod +x file-name.py
./file-name.py
Here are some additional resources that will help you make the most out of programming in
Python:
The rise of Wi-Fi‘s role in home automation has primarily come about due tothe
networked nature of deployed electronics where electronic devices (TVsand AV
receivers, mobile devices, etc.) have started becoming part of thehome IP network
and due the increasing rate of adoption of mobile computingdevices (smartphones,
tablets, etc.), see above Figure.
The networking aspectsare bringing online streaming services or network
playback, while becoming amean to control of the device functionality over the
network. At the same timemobile devices ensure that consumers have access to a
portable ‗controller‘ forthe electronics connected to the network. Both types of
devices can be used asgateways for IoT applications.
In this context many companies are consideringbuilding platforms that integrate
the building automation with entertainment,healthcare monitoring, energy
monitoring and wireless sensor monitoring inthe home and building environments.
IoT applications using sensors to collect information about the operating
conditions combined with cloud hosted analytics software that analyzes
disparatedata points will help facility managers become far more proactive about
managingbuildings at peak efficiency
INSTALLING AND UPDATING PYTHON
Python 2 and Python 3 come pre-installed on Raspbian operating systems, but to install
Python on another Linux OS or to update it, simply run one of these commands at the
command prompt:
sudo apt-get install python3
Figure shows that openHAB has an event bus. The bus is asynchronous. The
event bus refers to a communication bus for all protocol bindings. The bindings
link to the hardware. The event bus is the base service of openHAB.
Figure shows data-flow diagram and domain architecture reference model for
the smart city applications and services.
Two domains are
(i) City devices and Gateways domain,
(ii) shared network, cloud IoT platform and applications domains.
Services, security and city services management are cross-domain functions.
Assume the edge sensors and devices consist of, say i-smart devices, j-
sensors, k-intrusion sensors and l- mobile and fixed assets and devices
whereas i, j, k and l can be very large numbers.
The edge sensors and devices wirelessly connect within small cells; systems
connect with WLAN (Wireless LAN). They communicate using LPWAN.
The distributed network of edge-computing systems connects using IP
protocols or using the Multiprotocol Label Switching (MPLS).
The MPLS assigns the labels to data packets and forward the labels to city
cloud IoT platform. City cloud IoT platform collects messages, triggers,
alerts and data files at data store.
The platform does device and connectivity management functions,
application enabler functions, and data processing and analytics.
The platform generates triggers which follows actions, such as connect to
social media, set of web services, applications, iOS apps and Android apps.
The platform connects to a number of city applications and services.
Smart city applications and services can deploy CISCO IoT, IOx and Fog.
This is because of usages of shared networks and distributed access point
nodes, and the need of an ecosystem with ability to transform sensor data
and perform the control functions within the distributed network nodes.
This enables development of applications, such as site asset management,
energy monitoring, and smart parking infrastructure and connected cities.
SMART CITY PARKING
A growing problem in cities is of vehicular traffic congestion and parking spaces.
A modern city, therefore, provides a number of multilevel parking spaces which
spread all over the city.
A driver needs a mobile app. Significant fuel saving can result from provisioning
of smart parking spaces in a city. A smart parking-service should enable the
following:
1. Guides the drivers for the available parking slots and spaces
2. Provides a mobile app, and the app assists a driver and enables him/her to obtain
the appropriate parking-slot information remotely.
3. Publishes messages in real time for available slots and alerts for slot
unavailability at the parking utility
4. Consists of a central supervisory control and monitoring system (CSS) which
connects the edge sensors and devices, accurately senses the slots available for
occupancy of vehicles in real time, and predicts the expected availability time in
case of non-availability of slots
5. Optimizes the usages of parking spaces and reaching time
6. Provides display boards at road traffic junctions for status of availability
7. Provides good parking experience to users
8. Adds value for all parking stakeholders, drivers and service providers
Sensors play vital role in the smart parking. The application is ranked as topmost
among sensor-applications for a smarter world.
Figure 12.10 shows data-flow diagram, domains and architecture reference
model for smart parking applications and services.
The figure shows four layers at two domains.
Parking spaces are at layer 1. They are sensed using coordinators at each
level in multilevel parking spaces. An actuator for the light at each slot is
used. Lighting control module at the coordinator actuates the parking space
lights. The lightings can be switched on and off as per requirement for each
space.
A Parking Assistance System (PAS) is at layer 2. This includes CCS and
three modules for monitoring, control and display.
Layers 1 and 2 communication protocols are ZigBee, LWM2M and UDP.
The CSS maintains a real-time database of time-series data of the parking
spaces.
The system connects layer 3, which includes the SMS gateway and cloud
IoT platform.
Layer 2 connects CSS with all coordinators. Layer 2 includes a real-time time-
series database.
Layer 2 also connects with three modules for (i) displaying, (ii) space monitoring
and (iii) control commands for actuators for each parking slot.
Layer 3 consists of SMS gateway and City cloud IoT platform that connects CSS,
modules and database using the Wi-Fi, HTTP and HTTPS services.
The platform has data store, data processing and analytics, and parking areas and
connectivity management modules. The CSS sends the UDP packets using MPLS
and uses a SMS service to communicate with the mobile app.
The SMS service communicates parking information. A packet provides
information such as slot available, slot allocated, time parked, billing information
and directional and parking space route details to the user‘s mobile phone.
The user downloads a PAS app from the App store. The user‘s mobile also
connects to a payment gateway for parking service bill payment.
Layer 4 web services connect the cloud data store, and use the PaaS cloud for
the analytics.
Hardware Prototype Development and Deployment described sensors for
ultrasonic pulse detectors.
When a car parking slot is occupied, then the parked car reflects back ultrasonic
pulses to the source. The sensor measures the reflected directional intensity and
delay period for the reflections. The coordinator updates the parked slots status on
each alert from a circuit. The sensor associated circuit at coordinator alerts the CSS
for status change and generates time-series messages from the sensor data and
communicates to the CSS for saving at the real-time database.
Figure 12.11 shows the design principle for a set up for identifying vacant spaces
and slot IDs using ultrasonic pulses and back reflections to the transceiver (emitter
and sensors) at the coordinator.
SMART ENVIRONMENT
2. Establish the trends in environmental parameters and current status of the environment
3. Interpretation of data and evaluate environmental quality indices
1. Each measuring node for weather parameters is assigned an ID. Each lamppost
deploys a wireless sensor node. Each node measures the T, RH and other weather
parameters at assigned locations. A group of WSNs communicates using ZigBee and
forms a network. Each network has an access point, which receives the messages from
each node. They depicted interconnections between nodes, coordinators, routers and
access points. Each access point associates a gateway.
2. The nodes communicate the parameters up to the access point using WSNs at multiple
locations.
4. Publishes weather messages for the display boards at specific locations in the city and
communicates to weather API at mobile and web users
5. Publishes the messages in real time and send alerts using a weather reporting
application 6. Analyze and assess the environment impact .
7.Enables intelligent decisions using data and historical analytics reports at city cloud
weather data store
Two domains and their high-level service capabilities in the weather monitoring
services in Io T architecture reference model are:
1. Device and Gateway Domain: Assume that the system deploys m weather-sensor
embedded devices, each with a location-data sensor and n access-points for the WSNs. A
sensor node does minimum required computations, gathers sensed information and
communicates with other connected nodes in the network
A data adaptation layer for the data, messages, triggers and alerts does the main
computations and puts the result in real time updated database. The items identified for
communication from gateway are queried from the database.
The items communicate from gateway using network protocols and HTTP/HTTPS
services.
(i) Device subdomain: Hardware WSN board consists of sensors for weather
parameters. A board example is Waspmote.
(ii) Gateway Subdomain: The parameters and alerts communicate to a local or
remote web service, time-and location-stamping service, item provider, protocol
bindings and 6LowPAN/IP v6 modules as per configuration setting at the
configurationadministration service of OSGi framework. The bindings between
ZigBee LANs, 6LowPAN and LPWAN and IP v6 protocols are used for
networking of the devices, WSNs, OSGi with the HTTP/HTTP S services.
2. Application and Network Domain: Applications and network domain deploys the
applications and services and has high-level capabilities, such analytics, data
visualization, display-board feeds, weather reporting application
A microcontroller circuit consists of memory, over the air programmability (OTP) and
transceiver associated with each sensor or node. The weather monitoring circuit deploys
sensors for T, RH and atmospheric pressure (Patm) and may include solar visible
radiation, wind speed and direction, and rainfall.Hardware design of the sensor and WSN
node can use Arduino board with ZigBee shield.
A bot is an application that runs automated or semi-automated scripts a for specific set of
tasks and communicates the results over the Internet. A bot generally performs the task
which are simple and structurally repetitive, such as a, weather reporting bot. The word
‗bot‘ is derided from the word robot. A bot can communicate with an API using Instant
Messaging (IM) or Internet Relay Chat (IRC) or to Twitter or Facebook.
A bot can also chat and give responses to the questions from user API. The bot uses the
weather parameters and generates the alert messages from the database and messages for
forecast by a cloud analytics service
A mobile app can display the report in two succeeding frames repeatedly.
The first frame shows the weather condition of the current day, as:
1. First line: condition such as clear, rain, partly rain, cloudy or partly cloudy
2. Second line, first part text gives the day current T and four or five spaces
3. Second line, second part text gives superscripted text for the maximum T expected and
subscripted text for minimum T expected, followed by four or five spaces
4. Second line, third part text gives superscripted text for current RH% value and
subscripted text for wind-speed in kmph (kilometer per hour).
Thus, first reporting frame displays the current condition and day‘s forecast for Tmax and
Tmin. Second frame shows the forecast for today, tomorrow and day after for weather as:
1. First line: ―Sat Sun Mon‖
2. Second line shows a symbol which is completely unfilled circle for sunny, or cloud
image with sun for partly cloudy, or cloud sign for fully cloudy below each day Sat, Sun
and Mon.
After the sign, a superscripted word gives maximum T, and a subscripted word, the
minimum expected on that day. Thus, forecast for three days is reported, viz. today,
tomorrow and day after. Example of creating a weather bot is Slack weatherbot API.
The API is a node.js module for the bot. It displays Second frame shows the forecast for
today, tomorrow and day after days for weather, for example as follows:
3. Third line shows ―Today (such as SAT): T, condition (such as sunny, partly cloudy,
cloudy or rain)‖
A growing problem for all residents is air pollution from cars, toxic gases generated in
factories and farms, such as carbon monoxide (CO). Pollution needs monitoring and to
ensure the safety of workers and goods inside chemical plants.
1. Monitoring and measuring levels of CO, a gas dangerous above 50 –100 ppm level;
carbon dioxide (CO2), a gas causes which greenhouse effect; and ozone (O3), a gas
dangerous above 0.1 mg/per kg air level, for controlling air pollution
2. Monitoring and measuring levels of hydrogen sulfide (H2S), a highly toxic gas. It is a
greenhouse gas so its increase may contribute to global warming as well.
6. Compute Air Quality Index (AQI) from the parameters, such as hourly or daily
averages of air pollutant concentration, particulate matter (such as dust or carbon particle)
8. Data visualization
9. Report the pollution status to monitoring authorities
Sensors play a vital role in air-quality monitoring. The application has eleventh ranking
among sensor-applications for a smarter world.
A data-flow diagram and domain architecture reference model for air pollution
monitoring services are similar to Figure 12.12.
Two domains and their high-level service capabilities in the air quality and pollution
monitoring services in Io T architecture reference model are:
1. Device and Gateway Domain: Assume that the system deploys m gas sensor
embedded devices at each WSN with a location-data sensor and n access-points for the
WSNs (Figures 7.17).
The data-adaptation layer at gateway does the aggregation, compaction and fusion
computations for each sensor node data. The queries gather sensed information from the
database and the items selected communicate using HTTP/HTTPS/MPLS services. WSN
board IO ports connect the sensors for gaseous, particulate matter and weather
parameters. Each sensor node is configured by assigning a node ID. A node ID maps with
the GPS location found earlier from GPS modules at the data adaptation layer at the
gateway.
A sensor ID is configured for each sensor at the node. Each sensor associated circuit is
also configured for frequency of measurements every day and interval between two
successive measurements. The sensor circuit is configured to activate only for
measurement duration at a measuring instance followed by long inactive intervals.
An example is Waspmote board which can be used with sensors such as city pollution
CO, NO, NO2, O3, SO2 and dust particles sensors and air-quality finding sensors for
SO2, NO2, dust particles, CO, CO2, O3 and NH3. The Arduino or Eclipse IDE can be
used to develop codes for the Waspmote.
2. The Applications and Network Domain: The applications and network domain
deploys the applications and services and have high-level capabilities, such as events,
messages, alerts and data processing, databases, applications and services, analytics, data
visualization, display-board feeds, pollution reporting applications and services, and
IFTTT triggers and actions. The cloud platform can be TCUP, AWS Io T, IBM Blue mix
or Nimbits.
A big problem for countries with large forest areas is forest fires. A fire monitoring
service does the following tasks:
The application has tenth ranking among 50 sensor-applications for a smarter world.
Figure 12.13 shows a data-flow diagram and domain architecture reference model for
the monitoring service.
The figure shows that the service deploys m embedded-sensor devices at each of n
WSN associated with x access points.
Device and gateway domain functions in the fire monitoring service for forests in
Io T architecture reference model is as follows:
A lookup table enables mapping of two entities. Location-data stamping uses sensor
IDs at a lookup table. Data adaptation of each sensor is at the layer. Data aggregates,
compacts and fuses, computes, gathers sensed information and the algorithms use that
for alarm and faulty sensor identification and configuration management. Data store at
the database, updates in real time. The alerts and messages communicate to Io T cloud
platform. Hardware WSN board and sensors can use Waspmote board.24 Each WSN
communicates to access points using a multiprotocol wireless router
SMART AGRICULTURE
Following section describes two applications viz., smart irrigation in crop fields and
smart wine quality enhancing
Smart Irrigation
1. Sensors for moisture and actuators for watering channels are used in smart irrigation.
2. Uses soil moisture sensors with a sensor circuitry board with each one installed at
certain depth in the fields.
3. Uses an array of actuators (solenoid valves) which are placed along the water channels
and that control deficiencies in moisture levels above thresholds during a given crop
period. 4. Uses sensors placed at three depths for monitoring of moisture in fruit plants
such as grapes or mango, and monitors evapotranspiration (evaporation and transpiration)
7.Access point receives the data and transfers it to an associated gateway. Data adapts at
the gateway and then communicates to a cloud platform using LPWAN.
10. Measurements at the sensors are at preset intervals and actuators activate at analysed
required values of the intervals.
11. The platform uploads the programs to sensors and actuators circuitry and sets preset
measurement intervals of T1 (say, 24 hour) each and the preset actuation interval of t2
(say, on 120 hour)
12. Sensed moisture values when exceed preset thresholds then trigger the alarm
13. An algorithm uploads and updates the programs for the gateways and nodes.
14. Runs at the data-adaptation layer and finds the faulty or inaccessible moisture sensors
at periodic intervals
15. Open source SDK and IDE are used for prototyping the monitoring system
Smart Wine Quality Enhancing
The sensors monitor the soil moisture and trunk diameter in vineyards. The monitoring
controls the sugar content in grapes and health of grapevines. Data-flow diagram and
domain architecture reference-model for the monitoring service are similar to ones shown
in Figure 12.12.
A WSN measures moisture and other parameters and has an ID. Each node is a WSN.
Each WSN measures at assigned places in a crop or vineyard at certain depth(s) inside
the soil. Sensors at three equally spaced depths are used for the vineyard grapes sugar-
control.
A group of WSNs communicate among themselves using ZigBee and form a network.
Each network has an access point, which receives the messages from each node using
LPWAN. Figures 7.17 show the WSNs. They show interconnections between nodes,
coordinators, routers and access points. Each access point associates a gateway. Each
gateway communicates to the cloud using LPWAN
ENERGY
Energy IoT applications for smart energy systems:
a). Smart Grid b). Renewable Energy Systems c). Prognostics
SMART GRIDS
Smart grid technology provides predictive information and recommendations to
utilize, their suppliers, and their customers on how best to manage power.
Smart grid collects the data regarding:
Electricity generation
Electricity consumption
Storage
Distribution and equipment health data
• By analyzing the data on power generation, transmission and consumption of
smart grids can improve efficiency throughout the electric system. Storage
collection and analysis of smarts grids data in the cloud can help in dynamic
optimization of system operations, maintenance, and planning.
• Cloud-based monitoring of smart grids data can improve energy usage levels
viaenergy feedback to users coupled with real-time pricing information.
• Condition monitoring data collected from power generation and transmission
systems can help in detecting faults and predicting outages.
RENEWABLE ENERGY SYSTEM
• Due to the variability in the output from renewable energy sources (such as solar
and wind), integrating them into the grid can cause grid stability and reliability
problems.
• IoT based systems integrated with the transformer at the point of interconnection
measure the electrical variables and how much power is fed into the grid
• To ensure the grid stability, one solution is to simply cut off the overproductions.
• Communication systems for grid integration of renewable energy resources
[IEEE Network, 2011] -provided the closed-loop controls for wind energy system
that can be used to regulate the voltage at point of interconnection which
coordinate wind turbine outputs and provides reactive power support.
PROGNOSTICS
• IoT based prognostic real-time health management systems can predict
performance of machines of energy systems by analyzing the extent of deviation of
a system from its normal operating profiles.
• In the system such as power grids, real time information is collected using
specialized electrical sensors called Phasor Measurement Units (PMU)
• Analyzing massive amounts of maintenance data collected from sensors in
energy systems and equipment can provide predictions for impending failures.
• OpenPDC is a set of applications for processing of streaming time-series data
collected from Phasor Measurements Units (PMUs) in real-time.
ApplicationsofIoTinLogistics
Trucks are the lifeline of any logistics company. In the US alone, more than 70% of
all the goodsare transported by trucks. In fact, around 95% of all the manufactured
goods at one point aretransported via trucks. Logistics and fleet companies hence
require systems that can help themmanagetheirtruck operations.
The location and route management solution of Io T for logistics industry is hence
quite popular.This solution enables a logistics manager to monitor the location of
their trucks in real-time. Byusing GPS tracking systems and geofencing techniques,
the route taken by the trucks can also bemonitored from remote locations. This
further helps the logistics companies to track driveractivitiesand ensuretimelycargo
delivery.
Moreover, the real-time alert system of these vehicle tracking solutions alarm
managers aboutany anomaly like thunderstorms or accident on a freeway via push
notifications that may affectthestatusof shipment.
Thesefeaturesactasanassistantforlogisticscompaniesandassistintheplanningandmanage
ment of delivery schedules. Time-delaying barriers are instantly identified and
mitigatedthatresult instreamlined businessprocessesandcent percent
customersatisfaction.
2) InventoryTrackingandWarehousing
Io T in logistics other than providing fleet management services also facilitates the
RFID tags and sensorsallow companies to easily keep track of their inventory
itemsalong with their status and position. In other terms, Io T facilitates the
development of a smartwarehouse system that allows a company to prevent losses,
ensure safe storage of goods,
andefficientlylocatetheitemsinneed.Furthermore,italsohelpscompaniestorevamptheir
warehousingoperations,resultinginthereductionoflaborcostsandanincreaseinefficiency
dueto less manual handlingerrors.
3) CBMand BreakdownPrevention:
Io Tapplicationsinlogisticssegmentarenotonlylimitedtothemonitoringandmanag
ementofassets.However,itsmostbeneficialapplicationistheidentificationofbottlenecks
that may result in the breakdown of these assets. Internet of Things has
helpedindustriestojumponpredictivemaintenanceandcondition-
basedmaintenanceinsteadofdependingon scheduled inspection procedures.
Bymeasuringandanalyzingparametersthatdefinetheperformanceofthetrucks,co
mpanies can predict patterns related to common truck breakdown. Similarly, real-
time alertsystems can be used to gain alerts about probable unexpected malfunctions
that can be preventedviacondition-based maintenance.
4) Io TandBlock chainforDigitalBOL:
5) AutonomousandSelf-DrivingCars:
Logistics managers are not only responsible to manage the management of assets
beingtransported. They are also supposed to ensure the safety of truckers and the
cargo being shipped.Thiscan beaccomplished bythe implementationof self-
drivingvehicles.
6) Drone-BasedDelivery:
Unmanned Aerial Vehicles (UAVs) or drones are the new medium to deliver
packages. Theirpotential lies strongly in the field of retail, logistics, agriculture, and
e-commerce. Amazon, oneof the Big 4 tech companies in the world has also unveiled
the use of drones for deliveringordereditems to people located in remoteareas.
Drones applications and implementation of Internet of Things in logistics can ensure
automatedprocess execution and quick delivery of goods. The market of drones based
delivery systems isgrowing at a rapid rate and is expected to reach a market valuation
of
Remote patient monitoring is the most common application of Io T devices for healthcare.
Io T devices can automatically collect health metrics like heart rate, blood pressure,
temperature, and more from patients who are not physically present in a healthcare
facility, eliminating the need for patients to travel to the providers, or for patients to
collect it themselves.
When an Io T device collects patient data, it forwards the data to a software application
where healthcare professionals and/or patients can view it. Algorithms may be used to
analyze the data in order to recommend treatments or generate alerts. For example, an
Io T sensor that detects a patient‘s unusually low heart rate may generate an alert so that
healthcare professionals can intervene.
A major challenge with remote patient monitoring devices is ensuring that the highly
personal data that these Io T devices collect is secure and private.
Glucose monitoring
For the more than 30 million Americans with diabetes, glucose monitoring has
traditionally been difficult. Not only is it inconvenient to have to check glucose levels
and manually record results, but doing so reports a patient‘s glucose levels only at the
exact time the test is provided. If levels fluctuate widely, periodic testing may not be
sufficient to detect a problem.
Io T devices can help address these challenges by providing continuous, automatic
monitoring ofglucose levels in patients. Glucose monitoring devices eliminate the need to
keep records manually, and they can alert patients when glucose levels are problematic.
Challenges include designing an IoT device for glucose
monitoring that:
Is small enough to monitor continuously without causing a disruption to patients
Does not consume so much electricity that it needs to be recharged frequently.
These are not insurmountable challenges, however, and devices that address them
promise to revolutionize the way patients handle glucose monitoring.
Heart-rate monitoring
Like glucose, monitoring heart rates can be challenging, even for patients who are present
in healthcare facilities. Periodic heart rate checks don‘t guard against rapid fluctuations in
heart rates, and conventional devices for continuous cardiac monitoring used in hospitals
require patients to be attached to wired machines constantly, impairing their mobility.
Today, a variety of small Io T devices are available for heart rate monitoring, freeing
patients to move around as they like while ensuring that their hearts are monitored
continuously. Guaranteeing ultra-accurate results remains somewhat of a challenge, but
most modern devices can deliver accuracy rates of about 90 percent or better.
Hand hygiene monitoring
Traditionally, there hasn‘t been a good way to ensure that providers and patients inside a
healthcare facility washed their hands properly in order to minimize the risk of spreading
contagion.
Today, many hospitals and other health care operations use Io T devices to remind people
to sanitize their hands when they enter hospital rooms. The devices can even give
instructions on how best to sanitize to mitigate a particular risk for a particular patient.
A major shortcoming is that these devices can only remind people to clean their hands;
they can‘t do it for them. Still, research suggests that these devices can reduce infection
rates by more than 60 percent in hospitals.
Depression and mood monitoring
Information about depression symptoms and patients‘ general mood is another type of
data that has traditionally been difficult to collect continuously. Healthcare providers
might periodically ask patients how they are feeling, but were unable to anticipate sudden
mood swings. And, often, patients don‘t accurately report their feelings.
―Mood-aware‖ Io T devices can address these challenges. By collecting and analyzing data
such as heart rate and blood pressure, devices can infer information about a patient‘s mental
state. Advanced Io T devices for mood monitoring can even track data such as the movement
of a patient‘s eyes.
The key challenge here is that metrics like these can‘t predict depression symptoms or
other causes for concern with complete accuracy. But neither can a traditional in-person
mental assessment.
In order to treat Parkinson‘s patients most effectively, healthcare providers must be able
to assess how the severity of their symptoms fluctuate through the day.
Io T sensors promise to make this task much easier by continuously collecting data about
Parkinson‘s symptoms. At the same time, the devices give patients the freedom to go
about their lives in their own homes, instead of having to spend extended periods in a
hospital for observation.
Other examples of Io T/IoMT
While wearable devices like those described above remain the most commonly used type
of IoT device in healthcare, there are devices that go beyond monitoring to actually
providing treatment, or even ―living‖ in or on the patient. Examples include the following.
Connected inhalers
Conditions such as asthma or COPD often involve attacks that come on suddenly, with
little warning. Io T-connected inhalers can help patients by monitoring the frequency of
attacks, as well as collecting data from the environment to help healthcare providers
understand what triggered an attack.
In addition, connected inhalers can alert patients when they leave inhalers at home,
placing them at risk of suffering an attack without their inhaler present, or when they use
the inhaler improperly.
Ingestible sensors
Collecting data from inside the human body is typically a messy and highly disruptive
affair. No no enjoys having a camera or probe stuck into their digestive tract, for
example.
With ingestible sensors, it‘s possible to collect information from digestive and other
systems in a much less invasive way. They provide insights into stomach PH levels, for
instance, or help pinpoint the source of internal bleeding.
These devices must be small enough to be swallowed easily. They must also be able to
dissolve or pass through the human body cleanly on their own. Several companies are
hard at work on ingestible sensors that meet these criteria.
Whether they‘re used to improve health outcomes or for other purposes, smart lenses
promise to turn human eyes into a powerful tool for digital interactions.
Robotic surgery
By deploying small Internet-connected robots inside the human body, surgeons can
perform complex procedures that would be difficult to manage using human hands. At
the same time, robotic surgeries performed by small Io T devices can reduce the size of
incisions required to perform surgery, leading to a less invasive process and faster
healing.