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    3130306 (4)

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    Heer Vaghela
    This document is an examination paper for the 'Fundamentals of Digital Electronics' course at Gujarat Technological University, scheduled for January 25, 2024. It includes various questions covering topics such as binary arithmetic, logic gates, Boolean algebra, flip-flops, and Karnaugh maps, with a total of 70 marks. Students are instructed to attempt all questions and make suitable assumptions where necessary.

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    © All Rights Reserved
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    3130306 (4)

    Uploaded by

    Heer Vaghela
    2 views2 pages
    This document is an examination paper for the 'Fundamentals of Digital Electronics' course at Gujarat Technological University, scheduled for January 25, 2024. It includes various questions covering topics such as binary arithmetic, logic gates, Boolean algebra, flip-flops, and Karnaugh maps, with a total of 70 marks. Students are instructed to attempt all questions and make suitable assumptions where necessary.

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    This document is an examination paper for the 'Fundamentals of Digital Electronics' course at Gujarat Technological University, scheduled for January 25, 2024. It includes various questions covering topics such as binary arithmetic, logic gates, Boolean algebra, flip-flops, and Karnaugh maps, with a total of 70 marks. Students are instructed to attempt all questions and make suitable assumptions where necessary.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    2 views2 pages

    3130306 (4)

    Uploaded by

    Heer Vaghela
    This document is an examination paper for the 'Fundamentals of Digital Electronics' course at Gujarat Technological University, scheduled for January 25, 2024. It includes various questions covering topics such as binary arithmetic, logic gates, Boolean algebra, flip-flops, and Karnaugh maps, with a total of 70 marks. Students are instructed to attempt all questions and make suitable assumptions where necessary.

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    © All Rights Reserved
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    You are on page 1of 2

    Seat No.: ________ Enrolment No.

    ___________

    GUJARAT TECHNOLOGICAL UNIVERSITY


    BE - SEMESTER–III (NEW) EXAMINATION – WINTER 2023
    Subject Code:3130306 Date:25-01-2024
    Subject Name:Fundamentals of Digital Electronics
    Time:10:30 AM TO 01:00 PM Total Marks:70
    Instructions:
    1. Attempt all questions.
    2. Make suitable assumptions wherever necessary.
    3. Figures to the right indicate full marks.
    4. Simple and non-programmable scientific calculators are allowed.
    MARKS
    Q.1 (a) Subtract below binary numbers using 1’s complement. 03
    (1010)2 – (1111)2
    (b) Convert Decimal number (17)10 into Binary, Octal, Hexadecimal and 04
    BCD code.
    (c) Draw and explain symbol and truth table of AND Gate, OR Gate, NOT 07
    Gate, X-OR Gate, X-NOR Gate, NAND Gate and NOR Gate.

    Q.2 (a) Draw and explain TTL Realization of NOT Gate. 03


    (b) Explain the difference between Analog and Digital system. Also 04
    explain Integrated Circuit.
    (c) Explain different Axioms and Laws of Boolean Algebra using example. 07
    OR
    (c) Draw and explain Full Adder in detail. 07

    Q.3 (a) Convert F (A, B, C) = BC +AB into standard minterm form. 03


    (b) Minimise the logic function using Karnaugh map. 04
    F (A,B,C,D) = πm (0,1, 2, 3, 8, 9, 10, 11,14).
    (c) Draw and explain 4 bit magnitude comparator. 07
    OR
    Q.3 (a) Reduce the expression F(A,B) = ((AB)’+A+AB)’ 03
    (b) Minimise the logic function using Karnaugh map. 04
    F (A,B,C,D) = ∑ m(0,1, 2, 3, 8, 9, 10, 11,14)
    (c) Find the minimal expression for 07
    𝑓 = ∑m (2, 8, 9, 10, 11, 12, 14) using tabular method.

    Q.4 (a) Draw and explain Master-Slave Flip-Flops. 03


    (b) Minimise the logic function using Karnaugh map. 04
    F (A,B,C,D) = ∑ m(1, 2, 3, 8, 9, 10, 11,14) + d (7, 15)
    (c) Write a short note on PLA. 07
    OR
    Q.4 (a) Explain the difference between Combinational and sequential circuit using 03
    example.
    (b) Design a 8 to 1 multiplexer by using the four variable function given 04
    by F(A,B,C,D) =Σm(0,1,3,4,8,9,15).
    (c) Draw and explain Decoder and Encoder. 07

    Q.5 (a) Draw and explain SR flipflop. 03


    (b) Minimise the logic function using Karnaugh map. 04
    F (A,B,C,D) = ∑ (0, 2, 5, 7, 8, 10, 13,15)
    (c) Draw and explain Johnson counter in detail. 07

    1
    OR

    Q.5 (a) Draw and explain D Flipflop. 03


    (b) Explain shift register. 04
    (c) Draw the state diagram for 2 bit binary up counter and design 2 bit 07
    binary up counter using T flipflop.

    *************

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