Mixed Signal Microcontroller: Features

MSP430F673x MSP430F672x
www.ti.com SLAS731A DECEMBER 2011 REVISED APRIL 2012
MIXED SIGNAL MICROCONTROLLER

1
FEATURES
Low Supply Voltage Range: 1.8 V to 3.6 V Ultra-Low Power Consumption Active Mode (AM): All System Clocks Active 265 A/MHz at 8 MHz, 3.0 V, Flash Program Execution (Typical) 140 A/MHz at 8 MHz, 3.0 V, RAM Program Execution (Typical) Standby Mode (LPM3): Real-Time Clock With Crystal, Watchdog, and Supply Supervisor Operational, Full RAM Retention, Fast Wake-Up: 1.7 A at 2.2 V, 2.5 A at 3.0 V (Typical) Off Mode (LPM4): Full RAM Retention, Supply Supervisor Operational, Fast Wake-Up: 1.6 A at 3.0 V (Typical) Shutdown RTC Mode (LPM3.5): Shutdown mode, Active Real Time Clock with Crystal: 1.24 A at 3.0 V (Typical) Shutdown Mode (LPM4.5): 0.78 A at 3.0 V (Typical) Wake-Up From Standby Mode in 3 s (Typical) 16-Bit RISC Architecture, Extended Memory, up to 25-MHz System Clock Flexible Power Management System Fully Integrated LDO With Programmable Regulated Core Supply Voltage Supply Voltage Supervision, Monitoring, and Brownout System Operation From up to Two Auxiliary Power Supplies Unified Clock System FLL Control Loop for Frequency Stabilization Low-Power Low-Frequency Internal Clock Source (VLO) Low-Frequency Trimmed Internal Reference Source (REFO) 32-kHz Crystals (XT1) One 16-Bit Timer With Three Capture/Compare Registers Three 16-Bit Timers With Two Capture/Compare Registers Each Enhanced Universal Serial Communication Interfaces eUSCI_A0, eUSCI_A1, and eUSCI_A2 Each Support: Enhanced UART Supporting AutoBaudrate Detection IrDA Encoder and Decoder Synchronous SPI eUSCI_B0 Supports: I2C With Multi-Slave Addressing Synchronous SPI Password-Protected Real-Time Clock With Crystal Offset Calibration and Temperature Compensation Separate Voltage Supply for Backup Subsystem 32-kHz Low-Frequency Oscillator (XT1) Real-Time Clock Backup Memory (4 x 16 Bits) Three 24-Bit Sigma-Delta Analog-to-Digital (A/D) Converters With Differential PGA Inputs Integrated LCD Driver With Contrast Control for up to 320 Segments in 8-Mux Mode Hardware Multiplier Supports 32-Bit Operations 10-Bit 200-ksps A/D Converter Internal Reference Sample-and-Hold, Autoscan Feature Up to Six External Channels, Two Internal Channels, Including Temperature Sensor Three-Channel Internal DMA Serial Onboard Programming, No External Programming Voltage Needed Family Members are Summarized in Table 1 Available in 100-Pin and 80-Pin LQFP Packages For Complete Module Descriptions, See the MSP430x5xx and MSP430x6xx Family User's Guide (SLAU208)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. I2C is a trademark of others.
Copyright 20112012, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
SLAS731A DECEMBER 2011 REVISED APRIL 2012 www.ti.com
DESCRIPTION
The Texas Instruments MSP430 family of ultra-low-power microcontrollers consists of several devices featuring different sets of peripherals targeted for various applications. The architecture, combined with extensive lowpower modes, is optimized to achieve extended battery life in portable measurement applications. The device features a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency. The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in 3 s (typical). The MSP430F67xx series are microcontroller configurations with three high-performance 24-bit sigma-delta A/D converters, a 10-bit analog-to-digital (A/D) converter, four enhanced universal serial communication interfaces (three eUSCI_A and one eUSCI_B), four 16-bit timers, hardware multiplier, DMA, real-time clock module with alarm capabilities, LCD driver with integrated contrast control, auxiliary supply system, and up to 72 I/O pins in 100-pin devices and 52 I/O pins in 80-pin devices. Typical applications for these devices are 2-wire and 3-wire single-phase metering, including tamper-resistant meter implementations. Family members available are summarized in Table 1. Table 1. Family Members
eUSCI Device Flash (KB) 128 128 96 64 32 16 128 128 96 64 32 16 128 128 96 64 32 16 128 128 96 64 32 16 SRAM (KB) 8 4 4 4 2 1 8 4 4 4 2 1 8 4 4 4 2 1 8 4 4 4 2 1 SD24_B Converters 3 3 3 3 3 3 2 2 2 2 2 2 3 3 3 3 3 3 2 2 2 2 2 2 ADC10_A Channels 6 ext, 2 int 6 ext, 2 int 6 ext, 2 int 6 ext, 2 int 6 ext, 2 int 6 ext, 2 int 6 ext, 2 int 6 ext, 2 int 6 ext, 2 int 6 ext, 2 int 6 ext, 2 int 6 ext, 2 int 3 ext, 2 int 3 ext, 2 int 3 ext, 2 int 3 ext, 2 int 3 ext, 2 int 3 ext, 2 int 3 ext, 2 int 3 ext, 2 int 3 ext, 2 int 3 ext, 2 int 3 ext, 2 int 3 ext, 2 int Timer_A (1) Channel A: UART, IrDA, SPI 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 Channel B: SPI, I2C 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 I/O Package Type 100 PZ 100 PZ 100 PZ 100 PZ 100 PZ 100 PZ 100 PZ 100 PZ 100 PZ 100 PZ 100 PZ 100 PZ 80 PN 80 PN 80 PN 80 PN 80 PN 80 PN 80 PN 80 PN 80 PN 80 PN 80 PN 80 PN
MSP430F6736IPZ MSP430F6735IPZ MSP430F6734IPZ MSP430F6733IPZ MSP430F6731IPZ MSP430F6730IPZ MSP430F6726IPZ MSP430F6725IPZ MSP430F6724IPZ MSP430F6723IPZ MSP430F6721IPZ MSP430F6720IPZ MSP430F6736IPN MSP430F6735IPN MSP430F6734IPN MSP430F6733IPN MSP430F6731IPN MSP430F6730IPN MSP430F6726IPN MSP430F6725IPN MSP430F6724IPN MSP430F6723IPN MSP430F6721IPN MSP430F6720IPN
3, 2, 2, 2 3, 2, 2, 2 3, 2, 2, 2 3, 2, 2, 2 3, 2, 2, 2 3, 2, 2, 2 3, 2, 2, 2 3, 2, 2, 2 3, 2, 2, 2 3, 2, 2, 2 3, 2, 2, 2 3, 2, 2, 2 3, 2, 2, 2 3, 2, 2, 2 3, 2, 2, 2 3, 2, 2, 2 3, 2, 2, 2 3, 2, 2, 2 3, 2, 2, 2 3, 2, 2, 2 3, 2, 2, 2 3, 2, 2, 2 3, 2, 2, 2 3, 2, 2, 2
72 72 72 72 72 72 72 72 72 72 72 72 52 52 52 52 52 52 52 52 52 52 52 52
(1)
Each number in the sequence represents an instantiation of Timer_A with its associated number of capture compare registers and PWM output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_A, the first instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output generators, respectively.
Table 2. Ordering Information (1)

TA PACKAGED DEVICES (2) PLASTIC 100-PIN LQFP (PZ) MSP430F6736IPZ MSP430F6735IPZ MSP430F6734IPZ MSP430F6733IPZ MSP430F6731IPZ 40C to 85C MSP430F6730IPZ MSP430F6726IPZ MSP430F6725IPZ MSP430F6724IPZ MSP430F6723IPZ MSP430F6721IPZ MSP430F6720IPZ (1) (2) PLASTIC 80-PIN LQFP (PN) MSP430F6736IPN MSP430F6735IPN MSP430F6734IPN MSP430F6733IPN MSP430F6731IPN MSP430F6730IPN MSP430F6726IPN MSP430F6725IPN MSP430F6724IPN MSP430F6723IPN MSP430F6721IPN MSP430F6720IPN
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
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Functional Block Diagram, MSP430F673xIPZ, MSP430F672xIPZ

XIN XOUT DVCC DVSS AVCC AVSS AUX1 AUX2 AUX3 RST/NMI PA P1.x P2.x PB P3.x P4.x PC P5.x P6.x P7.x PD P8.x PE P9.x
(32kHz)
ACLK Unified Clock System SMCLK MCLK Flash 128kB 96KB 64KB 32KB 16KB 8kB 4KB 2KB 1KB RAM SYS Watchdog Port Mapping Controller CRC16 MPY32
I/O Ports P1/P2 28 I/Os Interrupt & Wakeup PA 116 I/Os
I/O Ports P3/P4 28 I/Os
I/O Ports P9 14 I/O
PB 116 I/Os
PC 116 I/Os
PD 116 I/Os
PE 14 I/O
CPUXV2 and Working Registers (25MHz)
EEM (S: 3+1) PMM Auxiliary Supplies LDO SVM/SVS BOR SD24_B 3 Channel 2 Channel ADC10_A 10 Bit 200 KSPS
LCD_C 8MUX Up to 320 Segments
REF Reference 1.5V, 2.0V, 2.5V

RTC_C
JTAG/ SBW Interface/ Port PJ
TA0 Timer_A 3 CC Registers
TA1 TA2 TA3 Timer_A 2 CC Registers
eUSCI_A0 eUSCI_A1 eUSCI_A2 (UART, IrDA,SPI)
eUSCI_B0 (SPI, I2C)
DMA 3 Channel
PJ.x
Functional Block Diagram, MSP430F673xIPN, MSP430F672xIPN

XIN XOUT DVCC DVSS AVCC AVSS AUX1 AUX2 AUX3 RST/NMI PA P1.x P2.x PB P3.x P4.x PC P5.x P6.x
(32kHz)
ACLK Unified Clock System SMCLK MCLK 128KB 96KB 64KB 32KB 16KB Flash 8KB 4KB 2KB 1KB RAM SYS DMA 3 Channel Watchdog Port Mapping Controller CRC16 MPY32
I/O Ports P1/P2 28 I/Os Interrupt & Wakeup PA 116 I/Os
PB 116 I/Os
PC 116 I/Os
CPUXV2 and Working Registers (25MHz)
EEM (S: 3+1) PMM Auxiliary Supplies LDO SVM/SVS BOR SD24_B 3 Channel 2 Channel ADC10_A 10 Bit 200 KSPS
LCD_C 8MUX Up to 320 Segments
REF Reference 1.5V, 2.0V, 2.5V

RTC_C
TA0 Timer_A 3 CC Registers
JTAG/ SBW Interface/ Port PJ
TA1 TA2 TA3 Timer_A 2 CC Registers
eUSCI_A0 eUSCI_A1 eUSCI_A2 (UART, IrDA,SPI)
eUSCI_B0 (SPI, I2C)
PJ.x
Pin Designation, MSP430F673xIPZ

PJ.2/ADC10CLK/TMS PJ.1/MCLK/TDI/TCLK RST/NMI/SBWTDIO PJ.0/SMCLK/TDO PJ.3/ACLK/TCK TEST/SBWTCK
P7.1/S10
P6.7/S12
P6.6/S13
P6.5/S14
P6.4/S15
P6.3/S16
P6.2/S17
SD0P0 SD0N0 SD1P0 SD1N0 SD2P0 SD2N0 VREF AVSS AVCC VASYS P9.1/A5 P9.2/A4 P9.3/A3 P1.0/PM_TA0.0/VeREF-/A2 P1.1/PM_TA0.1/VeREF+/A1 P1.2/PM_UCA0RXD/PM_UCA0SOMI/A0 P1.3/PM_UCA0TXD/PM_UCA0SIMO/R03 AUXVCC2 AUXVCC1 VDSYS DVCC DVSS VCORE XIN XOUT
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 1 75 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 PZ PACKAGE 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52
P6.1/S18
P7.0/S11
P8.3/S0
P8.2/S1
P8.1/S2
P8.0/S3
P7.7/S4
P7.6/S5
P7.5/S6
P7.4/S7
P7.3/S8
P7.2/S9
DVSS DVSYS P6.0/S19 P5.7/S20 P5.6/S21 P5.5/S22 P5.4/S23 P5.3/S24 P5.2/S25 P5.1/S26 P5.0/S27 P4.7/S28 P4.6/S29 P4.5/S30 P4.4/S31 P4.3/S32 P4.2/S33 P4.1/S34 P4.0/S35 P3.7/PM_SD2DIO/S36 P3.6/PM_SD1DIO/S37 P3.5/PM_SD0DIO/S38 P3.4/PM_SDCLK/S39 P3.3/PM_TA0.2 P3.2/PM_TACLK/PM_RTCCLK
25 51 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 P3.0/PM_TA2.0/BSL_TX P2.6/PM_TA1.0 P9.0/TACLK/RTCCLK P2.7/PM_TA1.1 P8.4/TA1.0 P8.5/TA1.1 P8.6/TA2.0 P8.7/TA2.1 COM0 COM1 COM2 COM3 P2.1/PM_UCB0SIMO/PM_UCB0SDA/COM7 P2.3/PM_UCA2TXD/PM_UCA2SIMO P1.6/PM_UCA0CLK/COM4 P1.7/PM_UCB0CLK/COM5 P1.5/PM_UCA1TXD/PM_UCA1SIMO/R23 P2.0/PM_UCB0SOMI/PM_UCB0SCL/COM6 P1.4/PM_UCA1RXD/PM_UCA1SOMI/LCDREF/R13 P2.2/PM_UCA2RXD/PM_UCA2SOMI P3.1/PM_TA2.1/BSL_RX AUXVCC3 P2.4/PM_UCA1CLK P2.5/PM_UCA2CLK LCDCAP/R33
NOTE: The secondary digital functions on Ports P1, P2, and P3 are fully mappable. The pin designation shows the default mapping. See Table 14 for details. NOTE: The pins VDSYS and DVSYS must be connected externally on board for proper device operation. CAUTION: The LCDCAP/R33 pin must be connected to DVSS if not used.
Table 3. Pinout Differences Between MSP430F673xIPZ and MSP430F672xIPZ (1)

PIN NUMBER 1 2 3 4 5 6 7 53 54 55 56 (1) PIN NAME MSP430F673xIPZ SD0P0 SD0N0 SD1P0 SD1N0 SD2P0 SD2N0 VREF P3.4/PM_SDCLK/S39 P3.5/PM_SD0DIO/S38 P3.6/PM_SD1DIO/S37 P3.7/PM_SD2DIO/S36 MSP430F672xIPZ SD0P0 SD0N0 SD1P0 SD1N0 NC NC VREF P3.4/PM_SDCLK/S39 P3.5/PM_SD0DIO/S38 P3.6/PM_SD1DIO/S37 P3.7/PM_NONE/S36
Signal names that differ between devices are indicated by italic typeface.
Pin Designation, MSP430F673xIPN

PJ.2/ADC10CLK/TMS PJ.1/MCLK/TDI/TCLK RST/NMI/SBWTDIO PJ.0/SMCLK/TDO PJ.3/ACLK/TCK
TEST/SBWTCK
P5.5/S10
P5.3/S12
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 SD0P0 SD0N0 SD1P0 SD1N0 SD2P0 SD2N0 VREF AVSS AVCC VASYS P1.0/PM_TA0.0/VeREF-/A2 P1.1/PM_TA0.1/VeREF+/A1 P1.2/PM_UCA0RXD/PM_UCA0SOMI/A0 P1.3/PM_UCA0TXD/PM_UCA0SIMO/R03 AUXVCC2 AUXVCC1 VDSYS DVCC DVSS VCORE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 PN PACKAGE 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 DVSS DVSYS P5.1/S14 P5.0/S15 P4.7/S16 P4.6/S17 P4.5/S18 P4.4/S19 P4.3/S20 P4.2/S21 P4.1/S22 P4.0/S23 P3.7/PM_SD2DIO/S24 P3.6/PM_SD1DIO/S25 P3.5/PM_SD0DIO/S26 P3.4/PM_SDCLK/S27 P3.3/PM_TA0.2/S28 P3.2/PM_TACLK/PM_RTCCLK/S29 P3.1/PM_TA2.1/S30/BSL_RX P3.0/PM_TA2.0/S31/BSL_TX
20 41 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 XOUT XIN COM0 COM1 COM2 COM3 P2.6/PM_TA1.0/S33 P2.1/PM_UCB0SIMO/PM_UCB0SDA/COM7/S38 P2.3/PM_UCA2TXD/PM_UCA2SIMO/S36 P1.6/PM_UCA0CLK/COM4 P1.7/PM_UCB0CLK/COM5 P2.4/PM_UCA1CLK/S35 P1.5/PM_UCA1TXD/PM_UCA1SIMO/R23 P1.4/PM_UCA1RXD/PM_UCA1SOMI/LCDREF/R13 P2.0/PM_UCB0SOMI/PM_UCB0SCL/COM6/S39 P2.2/PM_UCA2RXD/PM_UCA2SOMI/S37 P2.5/PM_UCA2CLK/S34 P2.7/PM_TA1.1/S32 AUXVCC3 LCDCAP/R33
NOTE: The secondary digital functions on Ports P1, P2, and P3 are fully mappable. The pin designation shows the default mapping. See Table 14 for details. NOTE: The pins VDSYS and DVSYS must be connected externally on board for proper device operation. CAUTION: The LCDCAP/R33 pin must be connected to DVSS if not used.
P5.2/S13
P5.4/S11
P6.7/S0
P6.6/S1
P6.5/S2
P6.4/S3
P6.3/S4
P6.2/S5
P6.1/S6
P6.0/S7
P5.7/S8
P5.6/S9
Table 4. Pinout Differences Between MSP430F673xIPN and MSP430F672xIPN (1)

PIN NUMBER 1 2 3 4 5 6 7 45 46 47 48 (1) PIN NAME MSP430F673xIPN SD0P0 SD0N0 SD1P0 SD1N0 SD2P0 SD2N0 VREF P3.4/PM_SDCLK/S27 P3.5/PM_SD0DIO/S26 P3.6/PM_SD1DIO/S25 P3.7/PM_SD2DIO/S24 MSP430F672xIPN SD0P0 SD0N0 SD1P0 SD1N0 NC NC VREF P3.4/PM_SDCLK/S27 P3.5/PM_SD0DIO/S26 P3.6/PM_SD1DIO/S25 P3.7/PM_NONE/S24
Signal names that differ between devices are indicated by italic typeface.
Table 5. Terminal Functions, MSP430F67xxIPZ

TERMINAL NAME SD0P0 SD0N0 SD1P0 SD1N0 SD2P0 SD2N0 VREF AVSS AVCC VASYS NO. PZ 1 2 3 4 5 6 7 8 9 10 I I I I I I I SD24_B positive analog input for converter 0 (2) SD24_B negative analog input for converter 0 (2) SD24_B positive analog input for converter 1 (2) SD24_B negative analog input for converter 1 (2) SD24_B positive analog input for converter 2 (2) (not available on F672x devices) SD24_B negative analog input for converter 2 (2) (not available on F672x devices) SD24_B external reference voltage Analog ground supply Analog power supply Analog power supply selected between AVCC, AUXVCC1, AUXVCC2. Connect recommended capacitor value of CVSYS (see Auxiliary Supplies - Recommended Operating Conditions). I/O General-purpose digital I/O Analog input A5 - 10-bit ADC General-purpose digital I/O Analog input A4 - 10-bit ADC General-purpose digital I/O Analog input A3 - 10-bit ADC General-purpose digital I/O with port interrupt and mappable secondary function Default mapping: Timer TA0 CCR0 capture: CCI0A input, compare: Out0 output Negative terminal for the ADC's reference voltage for an external applied reference voltage Analog input A2 - 10-bit ADC General-purpose digital I/O with port interrupt and mappable secondary function Default mapping: Timer TA0 CCR1 capture: CCI1A input, compare: Out1 output Positive terminal for the ADC's reference voltage for an external applied reference voltage Analog input A1 - 10-bit ADC General-purpose digital I/O with port interrupt and mappable secondary function Default mapping: eUSCI_A0 UART receive data; eUSCI_A0 SPI slave out/master in Analog input A0 - 10-bit ADC General-purpose digital I/O with port interrupt and mappable secondary function Default mapping: eUSCI_A0 UART transmit data; eUSCI_A0 SPI slave in/master out Input/output port of lowest analog LCD voltage (V5) Auxiliary power supply AUXVCC2 Auxiliary power supply AUXVCC1 Digital power supply selected between DVCC, AUXVCC1, AUXVCC2. Connect recommended capacitor value of CVSYS (see Auxiliary Supplies - Recommended Operating Conditions). Digital power supply Digital ground supply Regulated core power supply (internal use only, no external current loading) I Input terminal for crystal oscillator I/O (1) DESCRIPTION
P9.1/A5
11
P9.2/A4
12
I/O
P9.3/A3
13
I/O
P1.0/PM_TA0.0/VeREF-/A2
14
I/O
P1.1/PM_TA0.1/VeREF+/A1
15
I/O
P1.2/PM_UCA0RXD/ PM_UCA0SOMI/A0
16
I/O
P1.3/PM_UCA0TXD/ PM_UCA0SIMO/R03 AUXVCC2 AUXVCC1 VDSYS (3) DVCC DVSS VCORE XIN (1) (2) (3) (4)
(4)
17 18 19 20 21 22 23 24
I/O
I = input, O = output It is recommended to short unused analog input pairs and connect them to analog ground. The pins VDSYS and DVSYS must be connected externally on board for proper device operation. VCORE is for internal use only. No external current loading is possible. VCORE should only be connected to the recommended capacitor value, CVCORE. Submit Documentation Feedback 9
Table 5. Terminal Functions, MSP430F67xxIPZ (continued)

TERMINAL NAME XOUT AUXVCC3 NO. PZ 25 26 O Output terminal for crystal oscillator Auxiliary power supply AUXVCC3 for back up subsystem General-purpose digital I/O with port interrupt and mappable secondary function Default mapping: eUSCI_A1 UART receive data; eUSCI_A1 SPI slave out/master in External reference voltage input for regulated LCD voltage Input/output port of third most positive analog LCD voltage (V3 or V4) General-purpose digital I/O with port interrupt and mappable secondary function Default mapping: eUSCI_A1 UART transmit data; eUSCI_A1 SPI slave in/master out Input/output port of second most positive analog LCD voltage (V2) LCD capacitor connection Input/output port of most positive analog LCD voltage (V1) CAUTION: This pin must be connected to DVSS if not used. General-purpose digital I/O Timer TA1 CCR0 capture: CCI0A input, compare: Out0 output General-purpose digital I/O Timer TA1 CCR1 capture: CCI1A input, compare: Out1 output LCD common output COM0 for LCD backplane LCD common output COM1 for LCD backplane LCD common output COM2 for LCD backplane LCD common output COM3 for LCD backplane General-purpose digital I/O with port interrupt and mappable secondary function Default mapping: eUSCI_A0 clock input/output LCD common output COM4 for LCD backplane General-purpose digital I/O with port interrupt and mappable secondary function Default mapping: eUSCI_B0 clock input/output LCD common output COM5 for LCD backplane General-purpose digital I/O with port interrupt and mappable secondary function Default mapping: eUSCI_B0 SPI slave out/master in; eUSCI_B0 I2C clock LCD common output COM6 for LCD backplane General-purpose digital I/O with port interrupt and mappable secondary function Default mapping: eUSCI_B0 SPI slave in/master out; eUSCI_B0 I2C data LCD common output COM7 for LCD backplane General-purpose digital I/O Timer TA2 CCR0 capture: CCI0A input, compare: Out0 output General-purpose digital I/O Timer TA2 CCR1 capture: CCI1A input, compare: Out1 output General-purpose digital I/O Timer clock input TACLK for TA0, TA1, TA2, TA3 RTCCLK clock output General-purpose digital I/O with port interrupt and mappable secondary function Default mapping: eUSCI_A2 UART receive data; eUSCI_A2 SPI slave out/master in General-purpose digital I/O with port interrupt and mappable secondary function Default mapping: eUSCI_A2 UART transmit data; eUSCI_A2 SPI slave in/master out I/O (1) DESCRIPTION
P1.4/PM_UCA1RXD/ PM_UCA1SOMI/LCDREF/R13
27
I/O
P1.5/PM_UCA1TXD/ PM_UCA1SIMO/R23
28
I/O
LCDCAP/R33
29
I/O
P8.4/TA1.0
30
I/O
P8.5/TA1.1 COM0 COM1 COM2 COM3 P1.6/PM_UCA0CLK/COM4
31 32 33 34 35 36
I/O O O O O I/O
P1.7/PM_UCB0CLK/COM5
37
I/O
P2.0/PM_UCB0SOMI/ PM_UCB0SCL/COM6
38
I/O
P2.1/PM_UCB0SIMO/ PM_UCB0SDA/COM7
39
I/O
P8.6/TA2.0
40
I/O
P8.7/TA2.1
41
I/O
P9.0/TACLK/RTCCLK
42
I/O
P2.2/PM_UCA2RXD/ PM_UCA2SOMI P2.3/PM_UCA2TXD/ PM_UCA2SIMO
43
I/O
44
I/O
10

TERMINAL NAME P2.4/PM_UCA1CLK NO. PZ 45 I/O General-purpose digital I/O with port interrupt and mappable secondary function Default mapping: eUSCI_A1 clock input/output General-purpose digital I/O with port interrupt and mappable secondary function Default mapping: eUSCI_A2 clock input/output General-purpose digital I/O with port interrupt and mappable secondary function Default mapping: Timer TA1 capture CCR0: CCI0A input, compare: Out0 output General-purpose digital I/O with port interrupt and mappable secondary function Default mapping: Timer TA1 capture CCR1: CCI1A input, compare: Out1 output General-purpose digital I/O with mappable secondary function Default mapping: Timer TA2 capture CCR0: CCI0A input, compare: Out0 output Bootstrap loader: Data transmit General-purpose digital I/O with mappable secondary function Default mapping: Timer TA2 capture CCR1: CCI1A input, compare: Out1 output Bootstrap loader: Data receive General-purpose digital I/O with mappable secondary function Default mapping: Timer clock input TACLK for TA0, TA1, TA2, TA3; RTCCLK clock output General-purpose digital I/O with mappable secondary function Default mapping: Timer TA0 capture CCR2: CCI2A input, compare: Out2 output General-purpose digital I/O with mappable secondary function Default mapping: SD24_B bit stream clock input/output LCD segment output S39 General-purpose digital I/O with mappable secondary function Default mapping: SD24_B converter-0 bit stream data input/output LCD segment output S38 General-purpose digital I/O with mappable secondary function Default mapping: SD24_B converter-1 bit stream data input/output LCD segment output S37 General-purpose digital I/O with mappable secondary function Default mapping: SD24_B converter-2 bit stream data input/output (not available on F672x devices) LCD segment output S36 General-purpose digital I/O LCD segment output S35 General-purpose digital I/O LCD segment output S34 General-purpose digital I/O LCD segment output S33 General-purpose digital I/O LCD segment output S32 General-purpose digital I/O LCD segment output S31 General-purpose digital I/O LCD segment output S30 Submit Documentation Feedback 11 I/O (1) DESCRIPTION
P2.5/PM_UCA2CLK
46
I/O
P2.6/PM_TA1.0
47
I/O
P2.7/PM_TA1.1
48
I/O
P3.0/PM_TA2.0/BSL_TX
49
I/O
P3.1/PM_TA2.1/BSL_RX
50
I/O
P3.2/PM_TACLK/PM_RTCCLK
51
I/O
P3.3/PM_TA0.2
52
I/O
P3.4/PM_SDCLK/S39
53
I/O
P3.5/PM_SD0DIO/S38
54
I/O
P3.6/PM_SD1DIO/S37
55
I/O
P3.7/PM_SD2DIO/S36
56
I/O
P4.0/S35
57
I/O
P4.1/S34
58
I/O
P4.2/S33
59
I/O
P4.3/S32
60
I/O
P4.4/S31
61
I/O
P4.5/S30
62
I/O

TERMINAL NAME P4.6/S29 NO. PZ 63 I/O General-purpose digital I/O LCD segment output S29 General-purpose digital I/O LCD segment output S28 General-purpose digital I/O LCD segment output S27 General-purpose digital I/O LCD segment output S26 General-purpose digital I/O LCD segment output S25 General-purpose digital I/O LCD segment output S24 General-purpose digital I/O LCD segment output S23 General-purpose digital I/O LCD segment output S22 General-purpose digital I/O LCD segment output S21 General-purpose digital I/O LCD segment output S20 General-purpose digital I/O LCD segment output S19 Digital power supply for I/Os Digital ground supply I/O General-purpose digital I/O LCD segment output S18 General-purpose digital I/O LCD segment output S17 General-purpose digital I/O LCD segment output S16 General-purpose digital I/O LCD segment output S15 General-purpose digital I/O LCD segment output S14 General-purpose digital I/O LCD segment output S13 General-purpose digital I/O LCD segment output S12 General-purpose digital I/O LCD segment output S11 General-purpose digital I/O LCD segment output S10 I/O (1) DESCRIPTION
P4.7/S28
64
I/O
P5.0/S27
65
I/O
P5.1/S26
66
I/O
P5.2/S25
67
I/O
P5.3/S24
68
I/O
P5.4/S23
69
I/O
P5.5/S22
70
I/O
P5.6/S21
71
I/O
P5.7/S20
72
I/O
P6.0/S19 DVSYS (5) DVSS P6.1/S18
73 74 75 76
I/O
P6.2/S17
77
I/O
P6.3/S16
78
I/O
P6.4/S15
79
I/O
P6.5/S14
80
I/O
P6.6/S13
81
I/O
P6.7/S12
82
I/O
P7.0/S11
83
I/O
P7.1/S10 (5) 12
84
I/O
The pins VDSYS and DVSYS must be connected externally on board for proper device operation. Submit Documentation Feedback

TERMINAL NAME P7.2/S9 NO. PZ 85 I/O General-purpose digital I/O LCD segment output S9 General-purpose digital I/O LCD segment output S8 General-purpose digital I/O LCD segment output S7 General-purpose digital I/O LCD segment output S6 General-purpose digital I/O LCD segment output S5 General-purpose digital I/O LCD segment output S4 General-purpose digital I/O LCD segment output S3 General-purpose digital I/O LCD segment output S2 General-purpose digital I/O LCD segment output S1 General-purpose digital I/O LCD segment output S0 Test mode pin select digital I/O on JTAG pins Spy-Bi-Wire input clock General-purpose digital I/O SMCLK clock output Test data output General-purpose digital I/O MCLK clock output Test data input or Test clock input General-purpose digital I/O ADC10_A clock output Test mode select General-purpose digital I/O ACLK clock output Test clock Reset input active low Non-maskable interrupt input Spy-Bi-Wire data input/output I/O (1) DESCRIPTION
P7.3/S8
86
I/O
P7.4/S7
87
I/O
P7.5/S6
88
I/O
P7.6/S5
89
I/O
P7.7/S4
90
I/O
P8.0/S3
91
I/O
P8.1/S2
92
I/O
P8.2/S1
93
I/O
P8.3/S0
94
I/O
TEST/SBWTCK
95
PJ.0/SMCLK/TDO
96
I/O
PJ.1/MCLK/TDI/TCLK
97
I/O
PJ.2/ADC10CLK/TMS
98
I/O
PJ.3/ACLK/TCK
99
I/O
RST/NMI/SBWTDIO
100
I/O
13
Table 6. Terminal Functions, MSP430F67xxIPN

TERMINAL NAME SD0P0 SD0N0 SD1P0 SD1N0 SD2P0 SD2N0 VREF AVSS AVCC VASYS NO. PN 1 2 3 4 5 6 7 8 9 10 I I I I I I I SD24_B positive analog input for converter 0 (2) SD24_B negative analog input for converter 0 (2) SD24_B positive analog input for converter 1 (2) SD24_B negative analog input for converter 1 (2) SD24_B positive analog input for converter 2 (2) (not available on F672x devices) SD24_B negative analog input for converter 2 (2) (not available on F672x devices) SD24_B external reference voltage Analog ground supply Analog power supply Analog power supply selected between AVCC, AUXVCC1, AUXVCC2. Connect recommended capacitor value of CVSYS (see Auxiliary Supplies - Recommended Operating Conditions). General-purpose digital I/O with port interrupt and mappable secondary function Default mapping: Timer TA0 CCR0 capture: CCI0A input, compare: Out0 output Negative terminal for the ADC's reference voltage for an external applied reference voltage Analog input A2 - 10-bit ADC General-purpose digital I/O with port interrupt and mappable secondary function Default mapping: Timer TA0 CCR1 capture: CCI1A input, compare: Out1 output Positive terminal for the ADC reference voltage for an external applied reference voltage Analog input A1 - 10-bit ADC General-purpose digital I/O with port interrupt and mappable secondary function Default mapping: eUSCI_A0 UART receive data; eUSCI_A0 SPI slave out/master in Analog input A0 - 10-bit ADC General-purpose digital I/O with port interrupt and mappable secondary function Default mapping: eUSCI_A0 UART transmit data; eUSCI_A0 SPI slave in/master out Input/output port of lowest analog LCD voltage (V5) Auxiliary power supply AUXVCC2 Auxiliary power supply AUXVCC1 Digital power supply selected between DVCC, AUXVCC1, AUXVCC2. Connect recommended capacitor value of CVSYS (see Auxiliary Supplies - Recommended Operating Conditions). Digital power supply Digital ground supply Regulated core power supply (internal use only, no external current loading) I O Input terminal for crystal oscillator Output terminal for crystal oscillator Auxiliary power supply AUXVCC3 for back up subsystem General-purpose digital I/O with port interrupt and mappable secondary function Default mapping: eUSCI_A1 UART receive data; eUSCI_A1 SPI slave out/master in External reference voltage input for regulated LCD voltage Input/output port of third most positive analog LCD voltage (V3 or V4) I/O (1) DESCRIPTION
P1.0/PM_TA0.0/VeREF-/A2
11
I/O
P1.1/PM_TA0.1/VeREF+/A1
12
I/O
P1.2/PM_UCA0RXD/ PM_UCA0SOMI/A0
13
I/O
P1.3/PM_UCA0TXD/ PM_UCA0SIMO/R03 AUXVCC2 AUXVCC1 VDSYS (3) DVCC DVSS VCORE (4) XIN XOUT AUXVCC3
14 15 16 17 18 19 20 21 22 23
I/O
P1.4/PM_UCA1RXD/ PM_UCA1SOMI/LCDREF/R13
24
I/O
(1) (2) (3) (4) 14
I = input, O = output It is recommended to short unused analog input pairs and connect them to analog ground. The pins VDSYS and DVSYS must be connected externally on board for proper device operation. VCORE is for internal use only. No external current loading is possible. VCORE should only be connected to the recommended capacitor value, CVCORE. Submit Documentation Feedback
Table 6. Terminal Functions, MSP430F67xxIPN (continued)

TERMINAL NAME NO. PN 25 I/O General-purpose digital I/O with port interrupt and mappable secondary function Default mapping: eUSCI_A1 UART transmit data; eUSCI_A1 SPI slave in/master out Input/output port of second most positive analog LCD voltage (V2) LCD capacitor connection Input/output port of most positive analog LCD voltage (V1) CAUTION: This pin must be connected to DVSS if not used. LCD common output COM0 for LCD backplane LCD common output COM1 for LCD backplane LCD common output COM2 for LCD backplane LCD common output COM3 for LCD backplane General-purpose digital I/O with port interrupt and mappable secondary function Default mapping: eUSCI_A0 clock input/output LCD common output COM4 for LCD backplane General-purpose digital I/O with port interrupt and mappable secondary function Default mapping: eUSCI_B0 clock input/output LCD common output COM5 for LCD backplane General-purpose digital I/O with port interrupt and mappable secondary function Default mapping: eUSCI_B0 SPI slave out/master in; eUSCI_B0 I2C clock LCD common output COM6 for LCD backplane LCD segment output S39 General-purpose digital I/O with port interrupt and mappable secondary function Default mapping: eUSCI_B0 SPI slave in/master out; eUSCI_B0 I2C data LCD common output COM7 for LCD backplane LCD segment output S38 General-purpose digital I/O with port interrupt and mappable secondary function Default mapping: eUSCI_A2 UART receive data; eUSCI_A2 SPI slave out/master in LCD segment output S37 General-purpose digital I/O with port interrupt and mappable secondary function Default mapping: eUSCI_A2 UART transmit data; eUSCI_A2 SPI slave in/master out LCD segment output S36 General-purpose digital I/O with port interrupt and mappable secondary function Default mapping: eUSCI_A1 clock input/output LCD segment output S35 General-purpose digital I/O with port interrupt and mappable secondary function Default mapping: eUSCI_A2 clock input/output LCD segment output S34 General-purpose digital I/O with port interrupt and mappable secondary function Default mapping: Timer TA1 capture CCR0: CCI0A input, compare: Out0 output LCD segment output S33 General-purpose digital I/O with port interrupt and mappable secondary function Default mapping: Timer TA1 capture CCR1: CCI1A input, compare: Out1 output LCD segment output S32 I/O (1) DESCRIPTION
LCDCAP/R33 COM0 COM1 COM2 COM3 P1.6/PM_UCA0CLK/COM4
26 27 28 29 30 31
I/O O O O O I/O
P1.7/PM_UCB0CLK/COM5
32
I/O
P2.0/PM_UCB0SOMI/ PM_UCB0SCL/COM6/S39
33
I/O
P2.1/PM_UCB0SIMO/ PM_UCB0SDA/COM7/S38
34
I/O
P2.2/PM_UCA2RXD/ PM_UCA2SOMI/S37
35
I/O
P2.3/PM_UCA2TXD/ PM_UCA2SIMO/S36
36
I/O
P2.4/PM_UCA1CLK/S35
37
I/O
P2.5/PM_UCA2CLK/S34
38
I/O
P2.6/PM_TA1.0/S33
39
I/O
P2.7/PM_TA1.1/S32
40
I/O
15

TERMINAL NAME NO. PN General-purpose digital I/O with mappable secondary function Default mapping: Timer TA2 capture CCR0: CCI0A input, compare: Out0 output LCD segment output S31 Bootstrap loader: Data transmit General-purpose digital I/O with mappable secondary function Default mapping: Timer TA2 capture CCR1: CCI1A input, compare: Out1 output LCD segment output S30 Bootstrap loader: Data receive General-purpose digital I/O with mappable secondary function Default mapping: Timer clock input TACLK for TA0, TA1, TA2, TA3; RTCCLK clock output LCD segment output S29 General-purpose digital I/O with mappable secondary function Default mapping: Timer TA0 capture CCR2: CCI2A input, compare: Out2 output LCD segment output S28 General-purpose digital I/O with mappable secondary function Default mapping: SD24_B bit stream clock input/output LCD segment output S27 General-purpose digital I/O with mappable secondary function Default mapping: SD24_B converter-0 bit stream data input/output LCD segment output S26 General-purpose digital I/O with mappable secondary function Default mapping: SD24_B converter-1 bit stream data input/output LCD segment output S25 General-purpose digital I/O with mappable secondary function Default mapping: SD24_B converter-2 bit stream data input/output (not available on F672x devices) LCD segment output S24 General-purpose digital I/O LCD segment output S23 General-purpose digital I/O LCD segment output S22 General-purpose digital I/O LCD segment output S21 General-purpose digital I/O LCD segment output S20 General-purpose digital I/O LCD segment output S19 General-purpose digital I/O LCD segment output S18 General-purpose digital I/O LCD segment output S17 General-purpose digital I/O LCD segment output S16 I/O (1) DESCRIPTION
P3.0/PM_TA2.0/S31/BSL_TX
41
I/O
P3.1/PM_TA2.1/S30/BSL_RX
42
I/O
P3.2/PM_TACLK/PM_RTCCLK/ S29
43
I/O
P3.3/PM_TA0.2/S28
44
I/O
P3.4/PM_SDCLK/S27
45
I/O
P3.5/PM_SD0DIO/S26
46
I/O
P3.6/PM_SD1DIO/S25
47
I/O
P3.7/PM_SD2DIO/S24
48
I/O
P4.0/S23
49
I/O
P4.1/S22
50
I/O
P4.2/S21
51
I/O
P4.3/S20
52
I/O
P4.4/S19
53
I/O
P4.5/S18
54
I/O
P4.6/S17
55
I/O
P4.7/S16
56
I/O
16

TERMINAL NAME P5.0/S15 NO. PN 57 I/O General-purpose digital I/O LCD segment output S15 General-purpose digital I/O LCD segment output S14 Digital power supply for I/Os Digital ground supply I/O General-purpose digital I/O LCD segment output S13 General-purpose digital I/O LCD segment output S12 General-purpose digital I/O LCD segment output S11 General-purpose digital I/O LCD segment output S10 General-purpose digital I/O LCD segment output S9 General-purpose digital I/O LCD segment output S8 General-purpose digital I/O LCD segment output S7 General-purpose digital I/O LCD segment output S6 General-purpose digital I/O LCD segment output S5 General-purpose digital I/O LCD segment output S4 General-purpose digital I/O LCD segment output S3 General-purpose digital I/O LCD segment output S2 General-purpose digital I/O LCD segment output S1 General-purpose digital I/O LCD segment output S0 Test mode pin select digital I/O on JTAG pins Spy-Bi-Wire input clock General-purpose digital I/O SMCLK clock output Test data output General-purpose digital I/O MCLK clock output Test data input or Test clock input I/O (1) DESCRIPTION
P5.1/S14 DVSYS (5) DVSS P5.2/S13
58 59 60 61
I/O
P5.3/S12
62
I/O
P5.4/S11
63
I/O
P5.5/S10
64
I/O
P5.6/S9
65
I/O
P5.7/S8
66
I/O
P6.0/S7
67
I/O
P6.1/S6
68
I/O
P6.2/S5
69
I/O
P6.3/S4
70
I/O
P6.4/S3
71
I/O
P6.5/S2
72
I/O
P6.6/S1
73
I/O
P6.7/S0
74
I/O
TEST/SBWTCK
75
PJ.0/SMCLK/TDO
76
I/O
PJ.1/MCLK/TDI/TCLK
77
I/O
(5)
The pins VDSYS and DVSYS must be connected externally on board for proper device operation. Submit Documentation Feedback 17

TERMINAL NAME NO. PN 78 I/O General-purpose digital I/O ADC10_A clock output Test mode select General-purpose digital I/O ACLK clock output Test clock Reset input active low Non-maskable interrupt input Spy-Bi-Wire data input/output I/O (1) DESCRIPTION
PJ.2/ADC10CLK/TMS
PJ.3/ACLK/TCK
79
I/O
RST/NMI/SBWTDIO
80
I/O
18
SHORT-FORM DESCRIPTION CPU

The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations, other than program-flow instructions, are performed as register operations in conjunction with seven addressing modes for source operand and four addressing modes for destination operand. The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-toregister operation execution time is one cycle of the CPU clock. Four of the registers, R0 to R3, are dedicated as program counter, stack pointer, status register, and constant generator, respectively. The remaining registers are general-purpose registers. Peripherals are connected to the CPU using data, address, and control buses, and can be handled with all instructions.
Program Counter Stack Pointer Status Register Constant Generator General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register PC/R0 SP/R1 SR/CG1/R2 CG2/R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
Instruction Set
The instruction set consists of the original 51 instructions with three formats and seven address modes and additional instructions for the expanded address range. Each instruction can operate on word and byte data. Table 7 shows examples of the three types of instruction formats; Table 8 shows the address modes.
Table 7. Instruction Word Formats

INSTRUCTION WORD FORMAT Dual operands, source-destination Single operands, destination only Relative jump, un/conditional ADD CALL JNE R8 EXAMPLE R4,R5 R4 + R5 R5 PC (TOS), R8 PC Jump-on-equal bit = 0 OPERATION
Table 8. Address Mode Descriptions

ADDRESS MODE Register Indexed Symbolic (PC relative) Absolute Indirect Indirect autoincrement Immediate (1) S = source, D = destination S (1) + + + + + + + D (1) + + + + SYNTAX MOV Rs,Rd MOV X(Rn),Y(Rm) MOV EDE,TONI MOV & MEM, & TCDAT MOV @Rn,Y(Rm) MOV @Rn+,Rm MOV #X,TONI MOV @R10,Tab(R6) MOV @R10+,R11 MOV #45,TONI EXAMPLE MOV R10,R11 MOV 2(R5),6(R6) OPERATION R10 R11 M(2+R5) M(6+R6) M(EDE) M(TONI) M(MEM) M(TCDAT) M(R10) M(Tab+R6) M(R10) R11 R10 + 2 R10 #45 M(TONI)
19
Operating Modes
The MSP430 has one active mode and seven software selectable low-power modes of operation. An interrupt event can wake up the device from any of the low-power modes, service the request, and restore back to the low-power mode on return from the interrupt program. The following seven operating modes can be configured by software: Active mode (AM) All clocks are active Low-power mode 0 (LPM0) CPU is disabled ACLK and SMCLK remain active, MCLK is disabled FLL loop control remains active Low-power mode 1 (LPM1) CPU is disabled FLL loop control is disabled ACLK and SMCLK remain active, MCLK is disabled Low-power mode 2 (LPM2) CPU is disabled MCLK and FLL loop control and DCOCLK are disabled DCO's dc-generator remains enabled ACLK remains active Low-power mode 3 (LPM3) CPU is disabled MCLK, FLL loop control, and DCOCLK are disabled DCO's dc-generator is disabled ACLK remains active Low-power mode 4 (LPM4) CPU is disabled ACLK is disabled MCLK, FLL loop control, and DCOCLK are disabled DCO's dc-generator is disabled Crystal oscillator is stopped Complete data retention Low-power mode 3.5 (LPM3.5) Internal regulator disabled No RAM retention, Backup RAM retained I/O pad state retention RTC clocked by low-frequency oscillator Wakeup from RST/NMI, RTC_C events, Ports P1 and P2 Low-power mode 4.5 (LPM4.5) Internal regulator disabled No RAM retention, Backup RAM retained RTC is disabled I/O pad state retention Wakeup from RST/NMI, Ports P1 and P2
20
Interrupt Vector Addresses

The interrupt vectors and the power-up start address are located in the address range 0FFFFh to 0FF80h. The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence. Table 9. Interrupt Sources, Flags, and Vectors of MSP430F67xx Configurations
INTERRUPT SOURCE System Reset Power-Up External Reset Watchdog Timeout, Key Violation Flash Memory Key Violation System NMI PMM Vacant Memory Access JTAG Mailbox User NMI NMI Oscillator Fault Flash Memory Access Violation Supply Switch Watchdog Timer_A Interval Timer Mode eUSCI_A0 Receive/Transmit eUSCI_B0 Receive/Transmit ADC10_A SD24_B Timer TA0 Timer TA0 eUSCI_A1 Receive/Transmit eUSCI_A2 Receive/Transmit Auxiliary Supplies DMA Timer TA1 Timer TA1 I/O Port P1 Timer TA2 Timer TA2 I/O Port P2 Timer TA3 Timer TA3 LCD_C RTC_C INTERRUPT FLAG SYSTEM INTERRUPT WORD ADDRESS PRIORITY
WDTIFG, KEYV (SYSRSTIV) (1) (2)
Reset
0FFFEh
63, highest
SVMLIFG, SVMHIFG, DLYLIFG, DLYHIFG, VLRLIFG, VLRHIFG, VMAIFG, JMBNIFG, JMBOUTIFG (SYSSNIV) (1) (3)
(Non)maskable
0FFFCh
62
NMIIFG, OFIFG, ACCVIFG, AUXSWNMIFG (SYSUNIV) (1) (3)
(Non)maskable
0FFFAh
61
WDTIFG UCA0RXIFG, UCA0TXIFG (UCA0IV) (1) (4) UCB0RXIFG, UCB0TXIFG (UCB0IV)

(1) (4)
Maskable Maskable Maskable Maskable Maskable Maskable Maskable Maskable Maskable Maskable Maskable Maskable Maskable
(1) (4)
0FFF8h 0FFF6h 0FFF4h 0FFF2h 0FFF0h 0FFEEh 0FFECh 0FFEAh 0FFE8h 0FFE6h 0FFE4h 0FFE2h 0FFE0h 0FFDEh 0FFDCh 0FFDAh 0FFD8h 0FFD6h 0FFD4h 0FFD2h 0FFD0h
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40
ADC10IFG0, ADC10INIFG, ADC10LOIFG, ADC10HIIFG, ADC10TOVIFG, ADC10OVIFG (ADC10IV) (1) (4) SD24_B Interrupt Flags (SD24IV) (1) (4) TA0CCR0 CCIFG0 (4) TA0CCR1 CCIFG1, TA0CCR2 CCIFG2, TA0IFG (TA0IV) (1) (4) UCA1RXIFG, UCA1TXIFG (UCA1IV)
(1) (4)
UCA2RXIFG, UCA2TXIFG (UCA2IV) (1) (4) Auxiliary Supplies Interrupt Flags (AUXIV) TA1CCR0 CCIFG0 (4) TA1CCR1 CCIFG1, TA1IFG (TA1IV) (1) (4) P1IFG.0 to P1IFG.7 (P1IV) TA2CCR0 CCIFG0 (4) TA2CCR1 CCIFG1, TA2IFG (TA2IV) (1) (4) P2IFG.0 to P2IFG.7 (P2IV) TA3CCR0 CCIFG0 (4) TA3CCR1 CCIFG1, TA3IFG (TA3IV) (1) (4) LCD_C Interrupt Flags (LCDCIV) (1) (4) RTCOFIFG, RTCRDYIFG, RTCTEVIFG, RTCAIFG, RT0PSIFG, RT1PSIFG (RTCIV) (1) (4)
(1) (4) (1) (4)
DMA0IFG, DMA1IFG, DMA2IFG (DMAIV) (1) (4)
Maskable Maskable Maskable Maskable Maskable Maskable Maskable Maskable
(1) (2) (3) (4)
Multiple source flags A reset is generated if the CPU tries to fetch instructions from within peripheral space or vacant memory space. (Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot disable it. Interrupt flags are located in the module. Submit Documentation Feedback 21
Table 9. Interrupt Sources, Flags, and Vectors of MSP430F67xx Configurations (continued)

INTERRUPT SOURCE INTERRUPT FLAG SYSTEM INTERRUPT WORD ADDRESS 0FFCEh Reserved Reserved (5) 0FF80h (5) PRIORITY 39 0, lowest
Reserved interrupt vectors at addresses are not used in this device and can be used for regular program code if necessary. To maintain compatibility with other devices, it is recommended to reserve these locations.
Memory Organization
Table 10. Memory Organization
MSP430F6730 MSP430F6720 Main Memory (flash) Main: Interrupt vector Main: code memory Bank 3 Bank 2 Bank 1 Bank 0 RAM Total Size Sector 3 Sector 2 Sector 1 Sector 0 Info A Info B Information memory (flash) Info C Info D BSL 3 BSL 2 BSL 1 BSL 0 Peripherals Total Size 16kB 00FFFFh to 00FF80h not available not available not available 16kB 00FFFFh to 00C000h 1kB not available not available not available 1kB 001FFFh to 001C00h 128 B 0019FFh to 001980h 128 B 00197Fh to 001900h 128 B 0018FFh to 001880h 128 B 00187Fh to 001800h 512 B 0017FFh to 001600h 512 B 0015FFh to 001400h 512 B 0013FFh to 001200h 512 B 0011FFh to 001000h 4 KB 000FFFh to 0h MSP430F6731 MSP430F6721 32kB 00FFFFh to 00FF80h not available not available 16kB 00FFFFh to 00C000h 16kB 00BFFFh to 008000h 2kB not available not available not available 2kB 0023FFh to 001C00h 128 B 0019FFh to 001980h 128 B 00197Fh to 001900h 128 B 0018FFh to 001880h 128 B 00187Fh to 001800h 512 B 0017FFh to 001600h 512 B 0015FFh to 001400h 512 B 0013FFh to 001200h 512 B 0011FFh to 001000h 4 KB 000FFFh to 0h MSP430F6733 MSP430F6723 64kB 00FFFFh to 00FF80h not available not available 32kB 013FFFh to 00C000h 32kB 00BFFFh to 004000h 4kB not available not available 2kB 002BFFh to 002400h 2kB 0023FFh to 001C00h 128 B 0019FFh to 001980h 128 B 00197Fh to 001900h 128 B 0018FFh to 001880h 128 B 00187Fh to 001800h 512 B 0017FFh to 001600h 512 B 0015FFh to 001400h 512 B 0013FFh to 001200h 512 B 0011FFh to 001000h 4 KB 000FFFh to 0h
Bootstrap loader (BSL) memory (flash)
22
MSP430F6734 MSP430F6724 Main Memory (flash) Main: Interrupt vector Main: code memory Bank 3 Bank 2 Bank 1 Bank 0 RAM Total Size Sector 3 Sector 2 Sector 1 Sector 0 Info A Info B Information memory (flash) Info C Info D BSL 3 BSL 2 Bootstrap loader (BSL) memory (flash) BSL 1 BSL 0 Peripherals Total Size 96kB 00FFFFh to 00FF80h not available 32kB 01BFFFh to 014000h 32kB 013FFFh to 00C000h 32kB 00BFFFh to 004000h 4kB not available not available 2kB 002BFFh to 002400h 2kB 0023FFh to 001C00h 128 B 0019FFh to 001980h 128 B 00197Fh to 001900h 128 B 0018FFh to 001880h 128 B 00187Fh to 001800h 512 B 0017FFh to 001600h 512 B 0015FFh to 001400h 512 B 0013FFh to 001200h 512 B 0011FFh to 001000h 4 KB 000FFFh to 0h
MSP430F6735 MSP430F6725 128kB 00FFFFh to 00FF80h 32kB 023FFFh to 01C000h 32kB 01BFFFh to 014000h 32kB 013FFFh to 00C000h 32kB 00BFFFh to 004000h 4kB not available not available 2kB 002BFFh to 002400h 2kB 0023FFh to 001C00h 128 B 0019FFh to 001980h 128 B 00197Fh to 001900h 128 B 0018FFh to 001880h 128 B 00187Fh to 001800h 512 B 0017FFh to 001600h 512 B 0015FFh to 001400h 512 B 0013FFh to 001200h 512 B 0011FFh to 001000h 4 KB 000FFFh to 0h
MSP430F6736 MSP430F6726 128kB 00FFFFh to 00FF80h 32kB 023FFFh to 01C000h 32kB 01BFFFh to 014000h 32kB 013FFFh to 00C000h 32kB 00BFFFh to 004000h 8kB 2kB 003BFFh to 003400h 2kB 0033FFh to 002C00h 2kB 002BFFh to 002400h 2kB 0023FFh to 001C00h 128 B 0019FFh to 001980h 128 B 00197Fh to 001900h 128 B 0018FFh to 001880h 128 B 00187Fh to 001800h 512 B 0017FFh to 001600h 512 B 0015FFh to 001400h 512 B 0013FFh to 001200h 512 B 0011FFh to 001000h 4 KB 000FFFh to 0h
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Bootstrap Loader (BSL)

The BSL enables users to program the flash memory or RAM using various serial interfaces. Access to the device memory via the BSL is protected by an user-defined password. BSL entry requires a specific entry sequence on the RST/NMI/SBWTDIO and TEST/SBWTCK pins. For complete description of the features of the BSL and its implementation, see MSP430 Programming via the Bootstrap Loader (BSL) (SLAU319). Table 11. UART BSL Pin Requirements and Functions
DEVICE SIGNAL RST/NMI/SBWTDIO TEST/SBWTCK P3.0 P3.1 VCC VSS BSL FUNCTION Entry sequence signal Entry sequence signal Data transmit Data receive Power supply Ground supply
JTAG Operation
JTAG Standard Interface The MSP430 family supports the standard JTAG interface which requires four signals for sending and receiving data. The JTAG signals are shared with general-purpose I/O. The TEST/SBWTCK pin is used to enable the JTAG signals. In addition to these signals, the RST/NMI/SBWTDIO is required to interface with MSP430 development tools and device programmers. The JTAG pin requirements are shown in Table 12. For further details on interfacing to development tools and device programmers, see the MSP430 Hardware Tools User's Guide (SLAU278) and MSP430 Programming Via the JTAG Interface (SLAU320). Table 12. JTAG Pin Requirements and Functions
DEVICE SIGNAL PJ.3/ACLK/TCK PJ.2/ADC10CLK/TMS PJ.1/MCLK/TDI/TCLK PJ.0/SMCLK/TDO TEST/SBWTCK RST/NMI/SBWTDIO VCC VSS Direction IN IN IN OUT IN IN FUNCTION JTAG clock input JTAG state control JTAG data input/TCLK input JTAG data output Enable JTAG pins External reset Power supply Ground supply
Spy-Bi-Wire Interface In addition to the standard JTAG interface, the MSP430 family supports the two-wire Spy-Bi-Wire interface. SpyBi-Wire can be used to interface with MSP430 development tools and device programmers. The Spy-Bi-Wire interface pin requirements are shown in Table 13. For further details on interfacing to development tools and device programmers, see the MSP430 Hardware Tools User's Guide (SLAU278) and MSP430 Programming Via the JTAG Interface (SLAU320). Table 13. Spy-Bi-Wire Pin Requirements and Functions
DEVICE SIGNAL TEST/SBWTCK RST/NMI/SBWTDIO VCC VSS Direction IN IN, OUT FUNCTION Spy-Bi-Wire clock input Spy-Bi-Wire data input/output Power supply Ground supply
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Flash Memory
The flash memory can be programmed via the JTAG port, Spy-Bi-Wire (SBW), the BSL, or in-system by the CPU. The CPU can perform single-byte, single-word, and long-word writes to the flash memory. Features of the flash memory include: Flash memory has n segments of main memory and four segments of information memory (A to D) of 128 bytes each. Each segment in main memory is 512 bytes in size. Segments 0 to n may be erased in one step, or each segment may be individually erased. Segments A to D can be erased individually, or as a group with segments 0 to n. Segments A to D are also called information memory. Segment A can be locked separately.
RAM Memory
The RAM memory is made up of n sectors. Each sector can be completely powered down to save leakage, however all data is lost. Features of the RAM memory include: RAM memory has n sectors of 2k bytes each. Each sector 0 to n can be complete disabled; however, data retention is lost. Each sector 0 to n automatically enters low-power retention mode when possible.
Backup RAM Memory

The Backup RAM provides a limited number of bytes of RAM that are retained during LPMx.5. This Backup RAM is part of Backup subsystem in MSP430F67xx that operates on dedicated power supply AUXVCC3.There are 8 bytes of Backup RAM available in this device. It can be wordwise accessed via the registers BAKMEM0, BAKMEM1, BAKMEM2, and BAKMEM3. The Backup RAM registers can not be accessed by CPU when the high side SVS is disabled by user.
Peripherals
Peripherals are connected to the CPU through data, address, and control buses and can be handled using all instructions. For complete module descriptions, see the MSP430x5xx and MSP430x6xx Family User's Guide (SLAU208). Oscillator and System Clock The Unified Clock System (UCS) module includes support for a 32768-Hz watch crystal oscillator, an internal very-low-power low-frequency oscillator (VLO), an internal trimmed low-frequency oscillator (REFO), and an integrated internal digitally-controlled oscillator (DCO). The UCS module is designed to meet the requirements of both low system cost and low power consumption. The UCS module features digital frequency locked loop (FLL) hardware that, in conjunction with a digital modulator, stabilizes the DCO frequency to a programmable multiple of the selected FLL reference frequency. The internal DCO provides a fast turn-on clock source and stabilizes in 3 s (typical). The UCS module provides the following clock signals: Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal, the internal low-frequency oscillator (VLO), or the trimmed low-frequency oscillator (REFO). Main clock (MCLK), the system clock used by the CPU. MCLK can be sourced by same sources made available to ACLK. Sub-Main clock (SMCLK), the subsystem clock used by the peripheral modules. SMCLK can be sourced by same sources made available to ACLK. ACLK/n, the buffered output of ACLK, ACLK/2, ACLK/4, ACLK/8, ACLK/16, ACLK/32.
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Power Management Module (PMM) The PMM includes an integrated voltage regulator that supplies the core voltage to the device and contains programmable output levels to provide for power optimization. The PMM also includes supply voltage supervisor (SVS) and supply voltage monitoring (SVM) circuitry, as well as brownout protection. The brownout circuit is implemented to provide the proper internal reset signal to the device during power-on and power-off. The SVS/SVM circuitry detects if the supply voltage drops below a user-selectable level and supports both supply voltage supervision (the device is automatically reset) and supply voltage monitoring (the device is not automatically reset). SVS and SVM circuitry is available on the primary supply and core supply. Auxiliary Supply System The auxiliary supply system provides the possibility to operate the device from auxiliary supplies when the primary supply fails.There are two auxililary supplies AUXVCC1 and AUXVCC2 supported in MSP430F67xx. This module supports automatic and manual switching from primary supply to auxiliary suppllies while maintaining full functionality. It allows threshold based monitoring of primary and auxiliary supplies. The device can be started from primary supply or AUXVCC1, whichever is higher. Auxiliary supply system enables internal monitoring of voltage levels on primary and auxiliary supplies using ADC10_A. Also this module implements simple charger for backup supplies. Backup Subsystem The Backup subsystem operates on a dedicated power supply AUXVCC3. This subsystem includes lowfrequency oscillator (XT1), Real-Time Clock module, and Backup RAM. The functionality of Backup subsystem is retained during LPM3.5. The Backup susb-system module registers can not be accessed by CPU when the high side SVS is disabled by user. It is necessary to keep the high side SVS enabled with SVSHMD = 1 and SVSMHACE = 0 to turn off the low-frequency oscillator (XT1) in LPM4. Digital I/O There are up to nine 8-bit I/O ports implemented. For 100 pin options, Ports P1 to P8 are complete. P9 is reduced to 4-bit I/O. For 80 pin options, Ports P1 to P6 are complete. P7, P8 and P9 are completely removed. Port PJ contains four individual I/O pins, common to all devices. All I/O bits are individually programmable. Any combination of input, output and interrupt conditions is possible. Pullup or pulldown on all ports is programmable. Programmable drive strength on all ports. Edge-selectable interrupt and LPM3.5, LPM4.5 wakeup input capability available for all bits of ports P1 and P2. Read-write access to port-control registers is supported by all instructions. Ports can be accessed byte-wise (P1 through P9) or word-wise in pairs (PA through PE).
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Port Mapping Controller The port mapping controller allows flexible and reconfigurable mapping of digital functions to P1, P2, and P3. Table 14. Port Mapping, Mnemonics and Functions
VALUE 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31(0FFh) (1) (1) PxMAPy MNEMONIC PM_NONE PM_UCA0RXD PM_UCA0SOMI PM_UCA0TXD PM_UCA0SIMO PM_UCA0CLK PM_UCA0STE PM_UCA1RXD PM_UCA1SOMI PM_UCA1TXD PM_UCA1SIMO PM_UCA1CLK PM_UCA1STE PM_UCA2RXD PM_UCA2SOMI PM_UCA2TXD PM_ UCA2SIMO PM_UCA2CLK PM_UCA2STE PM_UCB0SIMO PM_UCB0SDA PM_UCB0SOMI PM_UCB0SCL PM_UCB0CLK PM_UCB0STE PM_TA0.0 PM_TA0.1 PM_TA0.2 PM_TA1.0 PM_TA1.1 PM_TA2.0 PM_TA2.1 PM_TA3.0 PM_TA3.1 PM_TACLK PM_RTCCLK PM_SDCLK PM_SD0DIO PM_SD1DIO PM_SD2DIO PM_ANALOG INPUT PIN FUNCTION None OUTPUT PIN FUNCTION DVSS
eUSCI_A0 UART RXD (direction controlled by eUSCI Input) eUSCI_A0 SPI slave out master in (direction controlled by eUSCI) eUSCI_A0 UART TXD (direction controlled by eUSCI Output) eUSCI_A0 SPI slave in master out (direction controlled by eUSCI) eUSCI_A0 clock input/output (direction controlled by eUSCI) eUSCI_A0 SPI slave transmit enable (direction controlled by eUSCI) eUSCI_A1 UART RXD (direction controlled by eUSCI Input) eUSCI_A1 SPI slave out master in (direction controlled by eUSCI) eUSCI_A1 UART TXD (direction controlled by eUSCI Output) eUSCI_A1 SPI slave in master out (direction controlled by eUSCI) eUSCI_A1 clock input/output (direction controlled by eUSCI) eUSCI_A1 SPI slave transmit enable (direction controlled by eUSCI) eUSCI_A2 UART RXD (direction controlled by eUSCI Input) eUSCI_A2 SPI slave out master in (direction controlled by eUSCI) eUSCI_A2 UART TXD (direction controlled by eUSCI Output) eUSCI_A2 SPI slave in master out (direction controlled by eUSCI) eUSCI_A2 clock input/output (direction controlled by eUSCI) eUSCI_A2 SPI slave transmit enable (direction controlled by eUSCI) eUSCI_B0 SPI slave in master out (direction controlled by eUSCI) eUSCI_B0 I2C data (open drain and direction controlled by eUSCI) eUSCI_B0 SPI slave out master in (direction controlled by eUSCI) eUSCI_B0 I2C clock (open drain and direction controlled by eUSCI) eUSCI_B0 clock input/output (direction controlled by eUSCI) eUSCI_B0 SPI slave transmit enable (direction controlled by eUSCI) TA0 CCR0 capture input CCI0A TA0 CCR1 capture input CCI1A TA0 CCR2 capture input CCI2A TA1 CCR0 capture input CCI0A TA1 CCR1 capture input CCI1A TA2 CCR0 capture input CCI0A TA2 CCR1 capture input CCI1A TA3 CCR0 capture input CCI0A TA3 CCR1 capture input CCI1A Timer_A clock input to TA0, TA1, TA2, TA3 None TA0 CCR0 compare output Out0 TA0 CCR1 compare output Out1 TA0 CCR2 compare output Out2 TA1 CCR0 compare output Out0 TA1 CCR1 compare output Out1 TA2 CCR0 compare output Out0 TA2 CCR1 compare output Out1 TA3 CCR0 compare output Out0 TA3 CCR1 compare output Out1 None RTC_C clock output
SD24_B bit stream clock input/output (direction controlled by SD24_B) SD24_B converter-0 bit stream data input/output (direction controlled by SD24_B) SD24_B converter-1 bit stream data input/output (direction controlled by SD24_B) SD24_B converter-2 bit stream data input/output (direction controlled by SD24_B) Disables the output driver as well as the input Schmitt-trigger to prevent parasitic cross currents when applying analog signals.
The value of the PM_ANALOG mnemonic is set to 0FFh. The port mapping registers are only 5 bits wide and the upper bits are ignored resulting in a read out value of 31. Submit Documentation Feedback 27
Table 15. Default Mapping

PIN NAME PZ P1.0/PM_TA0.0/ VeREF-/A2 P1.1/PM_TA0.1/ VeREF+/A1 P1.2/PM_UCA0RXD/ PM_UCA0SOMI/A0 PN P1.0/PM_TA0.0/ VeREF-/A2 P1.1/PM_TA0.1/ VeREF+/A1 P1.2/PM_UCA0RXD/ PM_UCA0SOMI/A0 PxMAPy MNEMONIC PM_TA0.0 PM_TA0.1 INPUT PIN FUNCTION TA0 CCR0 capture input CCI0A TA0 CCR1 capture input CCI1A OUTPUT PIN FUNCTION TA0 CCR0 compare output Out0 TA0 CCR1 compare output Out1
PM_UCA0RXD, PM_UCA0SOMI
eUSCI_A0 UART RXD (direction controlled by eUSCI input), eUSCI_A0 SPI slave out master in (direction controlled by eUSCI) eUSCI_A0 UART TXD (direction controlled by eUSCI output), eUSCI_A0 SPI slave in master out (direction controlled by eUSCI) eUSCI_A1 UART RXD (direction controlled by eUSCI input), eUSCI_A1 SPI slave out master in (direction controlled by eUSCI) eUSCI_A1 UART TXD (direction controlled by eUSCI output), eUSCI_A1 SPI slave in master out (direction controlled by eUSCI) eUSCI_A0 clock input/output (direction controlled by eUSCI) eUSCI_B0 clock input/output (direction controlled by eUSCI) eUSCI_B0 SPI slave out master in (direction controlled by eUSCI), eUSCI_B0 I2C clock (open drain and direction controlled by eUSCI) eUSCI_B0 SPI slave in master out (direction controlled by eUSCI), eUSCI_B0 I2C data (open drain and direction controlled by eUSCI) eUSCI_A2 UART RXD (direction controlled by eUSCI input), eUSCI_A2 SPI slave out master in (direction controlled by eUSCI) eUSCI_A2 UART TXD (direction controlled by eUSCI output), eUSCI_A2 SPI slave in master out (direction controlled by eUSCI) eUSCI_A1 clock input/output (direction controlled by eUSCI) eUSCI_A2 clock input/output (direction controlled by eUSCI) TA1 CCR0 capture input CCI0A TA1 CCR1 capture input CCI1A TA2 CCR0 capture input CCI0A TA2 CCR1 capture input CCI1A Timer_A clock input to TA0, TA1, TA2, TA3 TA0 CCR2 capture input CCI2A TA1 CCR0 compare output Out0 TA1 CCR1 compare output Out1 TA2 CCR0 compare output Out0 TA2 CCR1 compare output Out1 RTC_C clock output TA0 CCR2 compare output Out2
PM_UCA0TXD, PM_UCA0SIMO
P1.4/PM_UCA1RXD/ PM_UCA1SOMI/ LCDREF/R13
P1.4/PM_UCA1RXD/ PM_UCA1SOMI/ LCDREF/R13
P1.5/PM_UCA1TXD/ PM_UCA1SIMO/R23 P1.6/PM_UCA0CLK/ COM4 P1.7/PM_UCB0CLK/ COM5 P2.0/PM_UCB0SOMI/ PM_UCB0SCL/COM6
P1.5/PM_UCA1TXD/ PM_UCA1SIMO/R23 P1.6/PM_UCA0CLK/ COM4 P1.7/PM_UCB0CLK/ COM5 P2.0/PM_UCB0SOMI/ PM_UCB0SCL/COM6/S39
PM_UCA1TXD, PM_UCA1SIMO
PM_UCA0CLK PM_UCB0CLK
PM_UCB0SOMI, PM_UCB0SCL
P2.1/PM_UCB0SIMO/ PM_UCB0SDA/COM7
P2.1/PM_UCB0SIMO/ PM_UCB0SDA/COM7/S38
PM_UCB0SIMO, PM_UCB0SDA
P2.2/PM_UCA2RXD/ PM_UCA2SOMI
P2.2/PM_UCA2RXD/ PM_UCA2SOMI/S37
P2.3/PM_UCA2TXD/ PM_UCA2SIMO P2.4/PM_UCA1CLK P2.5/PM_UCA2CLK P2.6/PM_TA1.0 P2.7/PM_TA1.1 P3.0/PM_TA2.0 P3.1/PM_TA2.1 P3.2/PM_TACLK/ PM_RTCCLK P3.3/PM_TA0.2 P3.4/PM_SDCLK/S39 P3.5/PM_SD0DIO/S38 P3.6/PM_SD1DIO/S37 P3.7/PM_SD2DIO/S36
P2.3/PM_UCA2TXD/ PM_UCA2SIMO/S36 P2.4/PM_UCA1CLK/S35 P2.5/PM_UCA2CLK/S34 P2.6/PM_TA1.0/S33 P2.7/PM_TA1.1/S32 P3.0/PM_TA2.0/S31 P3.1/PM_TA2.1/S30 P3.2/PM_TACLK/ PM_RTCCLK/S29 P3.3/PM_TA0.2/S28 P3.4/PM_SDCLK/S27 P3.5/PM_SD0DIO/S26 P3.6/PM_SD1DIO/S25 P3.7/PM_SD2DIO/S24
PM_UCA2TXD, PM_UCA2SIMO PM_UCA1CLK PM_UCA2CLK PM_TA1.0 PM_TA1.1 PM_TA2.0 PM_TA2.1 PM_TACLK, PM_RTCCLK PM_TA0.2 PM_SDCLK PM_SD0DIO PM_SD1DIO PM_SD2DIO
SD24_B bit stream clock input/output (direction controlled by SD24_B) SD24_B converter-0 bit stream data input/output (direction controlled by SD24_B) SD24_B converter-1 bit stream data input/output (direction controlled by SD24_B) SD24_B converter-2 bit stream data input/output (direction controlled by SD24_B)
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System Module (SYS) The SYS module handles many of the system functions within the device. These include power on reset (POR) and power up clear (PUC) handling, NMI source selection and management, reset interrupt vector generators, boot strap loader entry mechanisms, as well as, configuration management (device descriptors). It also includes a data exchange mechanism via JTAG called a JTAG mailbox that can be used in the application. Table 16. System Module Interrupt Vector Registers
INTERRUPT VECTOR REGISTER INTERRUPT EVENT No interrupt pending Brownout (BOR) RST/NMI (POR) DoBOR (BOR) Wakeup from LPMx.5 (BOR) Security violation (BOR) SVSL (POR) SVSH (POR) SYSRSTIV, System Reset SVML_OVP (POR) SVMH_OVP (POR) DoPOR (POR) WDT timeout (PUC) WDT key violation (PUC) KEYV flash key violation (PUC) Reserved Peripheral area fetch (PUC) PMM key violation (PUC) Reserved No interrupt pending SVMLIFG SVMHIFG DLYLIFG DLYHIFG SYSSNIV, System NMI VMAIFG JMBINIFG JMBOUTIFG VLRLIFG VLRHIFG Reserved No interrupt pending NMIFG SYSUNIV, User NMI OFIFG ACCVIFG AUXSWNMIFG Reserved 019Ah 019Ch 019Eh WORD ADDRESS OFFSET 00h 02h 04h 06h 08h 0Ah 0Ch 0Eh 10h 12h 14h 16h 18h 1Ah 1Ch 1Eh 20h 22h to 3Eh 00h 02h 04h 06h 08h 0Ah 0Ch 0Eh 10h 12h 14h to 1Eh 00h 02h 04h 06h 08h 0Ah to 1Eh Lowest Highest Lowest Highest Lowest Highest PRIORITY
Watchdog Timer (WDT_A) The primary function of the watchdog timer (WDT_A) module is to perform a controlled system restart after a software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed in an application, the timer can be configured as an interval timer and can generate interrupts at selected time intervals.
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DMA Controller The DMA controller allows movement of data from one memory address to another without CPU intervention. For example, the DMA controller can be used to move data from the ADC10_A conversion memory to RAM. Using the DMA controller can increase the throughput of peripheral modules. The DMA controller reduces system power consumption by allowing the CPU to remain in sleep mode, without having to awaken to move data to or from a peripheral. Table 17. DMA Trigger Assignments (1)
Trigger 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 (1) DMA2IFG Channel 0 1 DMAREQ TA0CCR0 CCIFG TA0CCR2 CCIFG TA1CCR0 CCIFG Reserved TA2CCR0 CCIFG Reserved TA3CCR0 CCIFG Reserved Reserved Reserved Reserved Reserved SD24IFG Reserved Reserved UCA0RXIFG UCA0TXIFG UCA1RXIFG UCA1TXIFG UCA2RXIFG UCA2TXIFG UCB0RXIFG0 UCB0TXIFG0 ADC10IFG0 Reserved Reserved Reserved Reserved MPY ready DMA0IFG Reserved DMA1IFG 2
Reserved DMA triggers may be used by other devices in the family. Reserved DMA triggers do not cause any DMA trigger event when selected.
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CRC16 The CRC16 module produces a signature based on a sequence of entered data values and can be used for data checking purposes. The CRC16 module signature is based on the CRC-CCITT standard. Hardware Multiplier The multiplication operation is supported by a dedicated peripheral module. The module performs operations with 32-bit, 24-bit, 16-bit, and 8-bit operands. The module is capable of supporting signed and unsigned multiplication as well as signed and unsigned multiply and accumulate operations. Enhanced Universal Serial Communication Interface (eUSCI) The eUSCI module is used for serial data communication. The eUSCI module supports synchronous communication protocols such as SPI (3 or 4 pin) and I2C, and asynchronous communication protocols such as UART, enhanced UART with automatic baudrate detection, and IrDA. The eUSCI_An module supports for SPI (3 or 4 pin), UART, enhanced UART, or IrDA. The eUSCI_Bn module supports for SPI (3 or 4 pin) or I2C. Three eUSCI_A and one eUSCI_B module are implemented in MSP430F67xx devices. ADC10_A The ADC10_A module supports fast 10-bit analog-to-digital conversions. The module implements a 10-bit SAR core, sample select control, reference generator, and a conversion results buffer. A window comparator with a lower and upper limit allows CPU independent result monitoring with three window comparator interrupt flags. SD24_B The SD24_B module integrates up to three independent 24-bit sigma-delta A/D converters. Each converter is designed with a fully differential analog input pair and programmable gain amplifier input stage. The converters are based on second-order over-sampling sigma-delta modulators and digital decimation filters. The decimation filters are comb type filters with selectable oversampling ratios of up to 1024.
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TA0 TA0 is a 16-bit timer/counter (Timer_A type) with three capture/compare registers. TA0 can support multiple capture/compares, PWM outputs, and interval timing. TA0 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. Table 18. TA0 Signal Connections
DEVICE INPUT SIGNAL PM_TACLK ACLK (internal) SMCLK (internal) PM_TACLK PM_TA0.0 DVSS DVSS DVCC PM_TA0.1 ACLK (internal) DVSS DVCC PM_TA0.2 DVSS DVSS DVCC MODULE INPUT NAME TACLK ACLK SMCLK INCLK CCI0A CCI0B GND VCC CCI1A CCI1B CCR1 GND VCC CCI2A CCI2B GND VCC CCR2 TA2 PM_TA0.2 TA1 PM_TA0.1 ADC10_A (internal) ADC10SHSx = {1} SD24_B (internal) SD24SCSx = {1} CCR0 TA0 PM_TA0.0 Timer NA NA MODULE BLOCK MODULE OUTPUT SIGNAL DEVICE OUTPUT SIGNAL
TA1 TA1 is a 16-bit timer/counter (Timer_A type) with two capture/compare registers. TA1 can support multiple capture/compares, PWM outputs, and interval timing. TA1 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. Table 19. TA1 Signal Connections
DEVICE INPUT SIGNAL PM_TACLK ACLK (internal) SMCLK (internal) PM_TACLK PM_TA1.0 DVSS DVSS DVCC PM_TA1.1 ACLK (internal) DVSS DVCC MODULE INPUT NAME TACLK ACLK SMCLK INCLK CCI0A CCI0B GND VCC CCI1A CCI1B GND VCC CCR1 TA1 PM_TA1.1 CCR0 TA0 PM_TA1.0 Timer NA NA MODULE BLOCK MODULE OUTPUT SIGNAL DEVICE OUTPUT SIGNAL PZ
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DEVICE INPUT SIGNAL PM_TACLK ACLK (internal) SMCLK (internal) PM_TACLK PM_TA2.0 DVSS DVSS DVCC PM_TA2.1 ACLK (internal) DVSS DVCC MODULE INPUT NAME TACLK ACLK SMCLK INCLK CCI0A CCI0B GND VCC CCI1A CCI1B GND VCC CCR1 TA1 PM_TA2.1 SD24_B (internal) SD24SCSx = {2} CCR0 TA0 PM_TA2.0 Timer NA NA MODULE BLOCK MODULE OUTPUT SIGNAL DEVICE OUTPUT SIGNAL
DEVICE INPUT SIGNAL PM_TACLK ACLK (internal) SMCLK (internal) PM_TACLK PM_TA3.0 DVSS DVSS DVCC PM_TA3.1 ACLK (internal) DVSS DVCC MODULE INPUT NAME TACLK ACLK SMCLK INCLK CCI0A CCI0B GND VCC CCI1A CCI1B GND VCC CCR1 TA1 PM_TA3.1 SD24_B (internal) SD24SCSx = {3} CCR0 TA0 PM_TA3.0 ADC10_A (internal) ADC10SHSx = {2} Timer NA MODULE BLOCK MODULE OUTPUT SIGNAL DEVICE OUTPUT SIGNAL
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SD24_B Triggers Table 22 shows the input trigger connections to SD24_B converters from Timer_A modules and output trigger pulse connection from SD24_B to ADC10_A. Table 22. SD24_B Input/Output Trigger Connections
DEVICE INPUT SIGNAL MODULE INPUT SIGNAL TA0.1 (internal) TA2.1 (internal) TA3.1 (internal) SD24_B SD24SCSx = {1} SD24_B SD24SCSx = {2} SD24_B SD24SCSx = {3} SD24_B MODULE BLOCK MODULE OUTPUT SIGNAL Trigger Pulse DEVICE OUTPUT SIGNAL ADC10_A (internal) ADC10SHSx = {3}
ADC10_A Triggers Table 23 shows input trigger connections to ADC10_A from Timer_A modules and SD24_B. Table 23. ADC10_A Input Trigger Connections
DEVICE INPUT SIGNAL TA0.1 (internal) TA3.0 (internal) SD24_B trigger pulse (internal) MODULE INPUT SIGNAL ADC10_A ADC10SHSx = {1} ADC10_A ADC10SHSx = {2} ADC10_A ADC10SHSx = {3} ADC10_A MODULE BLOCK
Real-Time Clock (RTC_C) The RTC_C module can be configured for real-time clock (RTC) or calendar mode providing seconds, hours, day of week, day of month, month, and year. The RTC_C control and configuration registers are password protected to ensure clock integrity against runaway code. Calendar mode integrates an internal calendar that compensates for months with less than 31 days and includes leap year correction. The RTC_C also supports flexible alarm functions, offset calibration, and temperature compensation. The RTC_C on this device operates on dedicated AUXVCC3 supply and supports operation in LPM3.5. REF Voltage Reference The reference module (REF) is responsible for generation of all critical reference voltages that can be used by the various analog peripherals in the device. These include the ADC10_A, LCD_C, and SD24_B modules. LCD_C The LCD_C driver generates the segment and common signals required to drive a liquid crystal display (LCD). The LCD_C controller has dedicated data memories to hold segment drive information. Common and segment signals are generated as defined by the mode. Static, 2-mux, 3-mux, 4-mux, up to 8-mux LCDs are supported. The module can provide a LCD voltage independent of the supply voltage with its integrated charge pump. It is possible to control the level of the LCD voltage and thus contrast by software. The module also provides an automatic blinking capability for individual segments in static, 2-mux, 3-mux, and 4-mux modes. Embedded Emulation Module (EEM) (S Version) The Embedded Emulation Module (EEM) supports real-time in-system debugging. The S version of the EEM implemented on all devices has the following features: Three hardware triggers or breakpoints on memory access One hardware trigger or breakpoint on CPU register write access Up to four hardware triggers can be combined to form complex triggers or breakpoints One cycle counter Clock control on module level
34 Submit Documentation Feedback
Peripheral File Map Table 24. Peripherals

MODULE NAME Special Functions (see Table 25) PMM (see Table 26) Flash Control (see Table 27) CRC16 (see Table 28) RAM Control (see Table 29) Watchdog (see Table 30) UCS (see Table 31) SYS (see Table 32) Shared Reference (see Table 33) Port Mapping Control (see Table 34) Port Mapping Port P1 (see Table 35) Port Mapping Port P2 (see Table 36) Port Mapping Port P3 (see Table 37) Port P1/P2 (see Table 38) Port P3/P4 (see Table 39) Port P5/P6 (see Table 40) Port P7/P8 (see Table 41) (Port P7/P8 not available in MSP430F67xxIPN) Port P9 (Port P9 not available in MSP430F67xxIPN) (see Table 42) Port PJ (refer toTable 43) Timer TA0 (see Table 44) Timer TA1 (see Table 45) Timer TA2 (see Table 46) Timer TA3 (see Table 47) Backup Memory (see Table 48) RTC_C (see Table 49) 32-bit Hardware Multiplier (see Table 50) DMA General Control (see Table 51) DMA Channel 0 (see Table 52) DMA Channel 1 (see Table 53) DMA Channel 2 (see Table 54) eUSCI_A0 (see Table 55) eUSCI_A1 (see Table 56) eUSCI_A2 (see Table 57) eUSCI_B0 (see Table 58) ADC10_A (see Table 59) SD24_B(see Table 60) Auxiliary Supply (see Table 54) LCD_C (see Table 62) BASE ADDRESS 0100h 0120h 0140h 0150h 0158h 015Ch 0160h 0180h 01B0h 01C0h 01C8h 01D0h 01D8h 0200h 0220h 0240h 0260h 0280h 0320h 0340h 0380h 0400h 0440h 0480h 04A0h 04C0h 0500h 0500h 0500h 0500h 05C0h 05E0h 0600h 0640h 0740h 0800h 09E0h 0A00h OFFSET ADDRESS RANGE 000h - 01Fh 000h - 01Fh 000h - 00Fh 000h - 007h 000h - 001h 000h - 001h 000h - 01Fh 000h - 01Fh 000h - 001h 000h - 007h 000h - 007h 000h - 007h 000h - 007h 000h - 01Fh 000h - 00Bh 000h - 00Bh 000h - 00Bh 000h - 00Bh 000h - 01Fh 000h - 03Fh 000h - 03Fh 000h - 03Fh 000h - 03Fh 000h - 00Fh 000h - 01Fh 000h - 02Fh 000h - 00Fh 010h - 01Fh 020h - 02Fh 030h - 03Fh 000h - 01Fh 000h - 01Fh 000h - 01Fh 000h - 02Fh 000h - 01Fh 000h - 06Fh 000h - 01Fh 000h - 05Fh
35
Table 25. Special Function Registers (Base Address: 0100h)

REGISTER DESCRIPTION SFR interrupt enable SFR interrupt flag SFR reset pin control REGISTER SFRIE1 SFRIFG1 SFRRPCR 00h 02h 04h OFFSET
Table 26. PMM Registers (Base Address: 0120h)

REGISTER DESCRIPTION PMM Control 0 PMM control 1 SVS high side control SVS low side control PMM interrupt flags PMM interrupt enable PMM Power Mode 5 control register 0 REGISTER PMMCTL0 PMMCTL1 SVSMHCTL SVSMLCTL PMMIFG PMMIE PM5CTL0 00h 02h 04h 06h 0Ch 0Eh 10h OFFSET
Table 27. Flash Control Registers (Base Address: 0140h)

REGISTER DESCRIPTION Flash control 1 Flash control 3 Flash control 4 FCTL1 FCTL3 FCTL4 REGISTER 00h 04h 06h OFFSET
Table 28. CRC16 Registers (Base Address: 0150h)

REGISTER DESCRIPTION CRC data input CRC result REGISTER CRC16DI CRCINIRES 00h 04h OFFSET
Table 29. RAM Control Registers (Base Address: 0158h)

REGISTER DESCRIPTION RAM control 0 REGISTER RCCTL0 00h OFFSET
Table 30. Watchdog Registers (Base Address: 015Ch)

REGISTER DESCRIPTION Watchdog timer control REGISTER WDTCTL 00h OFFSET
Table 31. UCS Registers (Base Address: 0160h)

REGISTER DESCRIPTION UCS control 0 UCS control 1 UCS control 2 UCS control 3 UCS control 4 UCS control 5 UCS control 6 UCS control 7 UCS control 8 REGISTER UCSCTL0 UCSCTL1 UCSCTL2 UCSCTL3 UCSCTL4 UCSCTL5 UCSCTL6 UCSCTL7 UCSCTL8 00h 02h 04h 06h 08h 0Ah 0Ch 0Eh 10h OFFSET
36
Table 32. SYS Registers (Base Address: 0180h)

REGISTER DESCRIPTION System control Bootstrap loader configuration area JTAG mailbox control JTAG mailbox input 0 JTAG mailbox input 1 JTAG mailbox output 0 JTAG mailbox output 1 Bus Error vector generator User NMI vector generator System NMI vector generator Reset vector generator REGISTER SYSCTL SYSBSLC SYSJMBC SYSJMBI0 SYSJMBI1 SYSJMBO0 SYSJMBO1 SYSBERRIV SYSUNIV SYSSNIV SYSRSTIV 00h 02h 06h 08h 0Ah 0Ch 0Eh 18h 1Ah 1Ch 1Eh OFFSET
Table 33. Shared Reference Registers (Base Address: 01B0h)

REGISTER DESCRIPTION Shared reference control REGISTER REFCTL 00h OFFSET
Table 34. Port Mapping Controller (Base Address: 01C0h)

REGISTER DESCRIPTION Port mapping password register Port mapping control register REGISTER PMAPPWD PMAPCTL 00h 02h OFFSET
Table 35. Port Mapping for Port P1 (Base Address: 01C8h)

REGISTER DESCRIPTION Port P1.0 mapping register Port P1.1 mapping register Port P1.2 mapping register Port P1.3 mapping register Port P1.4 mapping register Port P1.5 mapping register Port P1.6 mapping register Port P1.7 mapping register REGISTER P1MAP0 P1MAP1 P1MAP2 P1MAP3 P1MAP4 P1MAP5 P1MAP6 P1MAP7 00h 01h 02h 03h 04h 05h 06h 07h OFFSET
Table 36. Port Mapping for Port P2 (Base Address: 01D0h)

37
Table 37. Port Mapping for Port P3 (Base Address: 01D8h)

Table 38. Port P1/P2 Registers (Base Address: 0200h)

REGISTER DESCRIPTION Port P1 input Port P1 output Port P1 direction Port P1 pullup/pulldown enable Port P1 drive strength Port P1 selection Port P1 interrupt vector word Port P1 interrupt edge select Port P1 interrupt enable Port P1 interrupt flag Port P2 input Port P2 output Port P2 direction Port P2 pullup/pulldown enable Port P2 drive strength Port P2 selection Port P2 interrupt vector word Port P2 interrupt edge select Port P2 interrupt enable Port P2 interrupt flag P1IN P1OUT P1DIR P1REN P1DS P1SEL P1IV P1IES P1IE P1IFG P2IN P2OUT P2DIR P2REN P2DS P2SEL P2IV P2IES P2IE P2IFG REGISTER 00h 02h 04h 06h 08h 0Ah 0Eh 18h 1Ah 1Ch 01h 03h 05h 07h 09h 0Bh 1Eh 19h 1Bh 1Dh OFFSET

REGISTER DESCRIPTION Port P3 input Port P3 output Port P3 direction Port P3 pullup/pulldown enable Port P3 drive strength Port P3 selection Port P4 input Port P4 output Port P4 direction Port P4 pullup/pulldown enable Port P4 drive strength Port P4 selection P3IN P3OUT P3DIR P3REN P3DS P3SEL P4IN P4OUT P4DIR P4REN P4DS P4SEL REGISTER 00h 02h 04h 06h 08h 0Ah 01h 03h 05h 07h 09h 0Bh OFFSET
38


Table 42. Port P9 Registers (Base Address: 0280h)

REGISTER DESCRIPTION Port P9 input Port P9 output Port P9 direction Port P9 pullup/pulldown enable Port P9 drive strength Port P9 selection P9IN P9OUT P9DIR P9REN P9DS P9SEL REGISTER 00h 02h 04h 06h 08h 0Ah OFFSET
Table 43. Port J Registers (Base Address: 0320h)

REGISTER DESCRIPTION Port PJ input Port PJ output Port PJ direction Port PJ pullup/pulldown enable Port PJ drive strength Port PJ selection PJIN PJOUT PJDIR PJREN PJDS PJSEL REGISTER 00h 02h 04h 06h 08h 0Ah OFFSET
39
Table 44. TA0 Registers (Base Address: 0340h)

REGISTER DESCRIPTION TA0 control Capture/compare control 0 Capture/compare control 1 Capture/compare control 2 TA0 counter register Capture/compare register 0 Capture/compare register 1 Capture/compare register 2 TA0 expansion register 0 TA0 interrupt vector REGISTER TA0CTL TA0CCTL0 TA0CCTL1 TA0CCTL2 TA0R TA0CCR0 TA0CCR1 TA0CCR2 TA0EX0 TA0IV 00h 02h 04h 06h 10h 12h 14h 16h 20h 2Eh OFFSET

REGISTER DESCRIPTION TA1 control Capture/compare control 0 Capture/compare control 1 TA1 counter register Capture/compare register 0 Capture/compare register 1 TA1 expansion register 0 TA1 interrupt vector REGISTER TA1CTL TA1CCTL0 TA1CCTL1 TA1R TA1CCR0 TA1CCR1 TA1EX0 TA1IV 00h 02h 04h 10h 12h 14h 20h 2Eh OFFSET


40
Table 48. Backup Memory Registers (Base Address: 0480h)

REGISTER DESCRIPTION Backup Memory 0 Backup Memory 1 Backup Memory 2 Backup Memory 3 REGISTER BAKMEM0 BAKMEM1 BAKMEM2 BAKMEM3 00h 02h 04h 06h OFFSET
Table 49. RTC_C Registers (Base Address: 04A0h)

REGISTER DESCRIPTION RTC control 0 RTC password RTC control 1 RTC control 3 RTC offset calibration RTC temperature compensation RTC prescaler 0 control RTC prescaler 1 control RTC prescaler 0 RTC prescaler 1 RTC interrupt vector word RTC seconds RTC minutes RTC hours RTC day of week RTC days RTC month RTC year RTC alarm minutes RTC alarm hours RTC alarm day of week RTC alarm days Binary-to-BCD conversion register BCD-to-Binary conversion register REGISTER RTCCTL0 RTCPWD RTCCTL1 RTCCTL3 RTCOCAL RTCTCMP RTCPS0CTL RTCPS1CTL RTCPS0 RTCPS1 RTCIV RTCSEC RTCMIN RTCHOUR RTCDOW RTCDAY RTCMON RTCYEAR RTCAMIN RTCAHOUR RTCADOW RTCADAY BIN2BCD BCD2BIN 00h 01h 02h 03h 04h 06h 08h 0Ah 0Ch 0Dh 0Eh 10h 11h 12h 13h 14h 15h 16h 18h 19h 1Ah 1Bh 1Ch 1Eh OFFSET
41
Table 50. 32-bit Hardware Multiplier Registers (Base Address: 04C0h)

REGISTER DESCRIPTION 16-bit operand 1 multiply 16-bit operand 1 signed multiply 16-bit operand 1 multiply accumulate 16-bit operand 1 signed multiply accumulate 16-bit operand 2 16 16 result low word 16 16 result high word 16 16 sum extension register 32-bit operand 1 multiply low word 32-bit operand 1 multiply high word 32-bit operand 1 signed multiply low word 32-bit operand 1 signed multiply high word 32-bit operand 1 multiply accumulate low word 32-bit operand 1 multiply accumulate high word 32-bit operand 1 signed multiply accumulate low word 32-bit operand 1 signed multiply accumulate high word 32-bit operand 2 low word 32-bit operand 2 high word 32 32 result 0 least significant word 32 32 result 1 32 32 result 2 32 32 result 3 most significant word MPY32 control register 0 MPY MPYS MAC MACS OP2 RESLO RESHI SUMEXT MPY32L MPY32H MPYS32L MPYS32H MAC32L MAC32H MACS32L MACS32H OP2L OP2H RES0 RES1 RES2 RES3 MPY32CTL0 REGISTER 00h 02h 04h 06h 08h 0Ah 0Ch 0Eh 10h 12h 14h 16h 18h 1Ah 1Ch 1Eh 20h 22h 24h 26h 28h 2Ah 2Ch OFFSET
Table 51. DMA General Control Registers (Base Address: 0500h)

REGISTER DESCRIPTION DMA module control 0 DMA module control 1 DMA module control 2 DMA module control 3 DMA module control 4 DMA interrupt vector REGISTER DMACTL0 DMACTL1 DMACTL2 DMACTL3 DMACTL4 DMAIV 00h 02h 04h 06h 08h 0Eh OFFSET
Table 52. DMA Channel 0 Registers (Base Address: 0500h)

REGISTER DESCRIPTION DMA channel 0 control DMA channel 0 source address low DMA channel 0 source address high DMA channel 0 destination address low DMA channel 0 destination address high DMA channel 0 transfer size REGISTER DMA0CTL DMA0SAL DMA0SAH DMA0DAL DMA0DAH DMA0SZ 10h 12h 14h 16h 18h 1Ah OFFSET
42


Table 55. eUSCI_A0 Registers (Base Address: 05C0h)

REGISTER DESCRIPTION eUSCI_A control word 0 eUSCI _A control word 1 eUSCI_A baud rate 0 eUSCI_A baud rate 1 eUSCI_A modulation control eUSCI_A status eUSCI_A receive buffer eUSCI_A transmit buffer eUSCI_A LIN control eUSCI_A IrDA transmit control eUSCI_A IrDA receive control eUSCI_A interrupt enable eUSCI_A interrupt flags eUSCI_A interrupt vector word REGISTER UCA0CTLW0 UCA0CTLW1 UCA0BR0 UCA0BR1 UCA0MCTLW UCA0STAT UCA0RXBUF UCA0TXBUF UCA0ABCTL UCA0IRTCTL UCA0IRRCTL UCA0IE UCA0IFG UCA0IV 00h 02h 06h 07h 08h 0Ah 0Ch 0Eh 10h 12h 13h 1Ah 1Ch 1Eh OFFSET
Table 56. eUSCI_A1 Registers (Base Address:05E0h)

REGISTER DESCRIPTION eUSCI_A control word 0 eUSCI _A control word 1 eUSCI_A baud rate 0 eUSCI_A baud rate 1 eUSCI_A modulation control eUSCI_A status eUSCI_A receive buffer eUSCI_A transmit buffer eUSCI_A LIN control eUSCI_A IrDA transmit control eUSCI_A IrDA receive control eUSCI_A interrupt enable
REGISTER UCA1CTLW0 UCA1CTLW1 UCA1BR0 UCA1BR1 UCA1MCTLW UCA1STAT UCA1RXBUF UCA1TXBUF UCA1ABCTL UCA1IRTCTL UCA1IRRCTL UCA1IE 00h 02h 06h 07h 08h 0Ah 0Ch 0Eh 10h 12h 13h 1Ah
OFFSET
43
Table 56. eUSCI_A1 Registers (Base Address:05E0h) (continued)

REGISTER DESCRIPTION eUSCI_A interrupt flags eUSCI_A interrupt vector word REGISTER UCA1IFG UCA1IV 1Ch 1Eh OFFSET
Table 57. eUSCI_A2 Registers (Base Address:0600h)

REGISTER DESCRIPTION eUSCI_A control word 0 eUSCI _A control word 1 eUSCI_A baud rate 0 eUSCI_A baud rate 1 eUSCI_A modulation control eUSCI_A status eUSCI_A receive buffer eUSCI_A transmit buffer eUSCI_A LIN control eUSCI_A IrDA transmit control eUSCI_A IrDA receive control eUSCI_A interrupt enable eUSCI_A interrupt flags eUSCI_A interrupt vector word REGISTER UCA2CTLW0 UCA2CTLW1 UCA2BR0 UCA2BR1 UCA2MCTLW UCA2STAT UCA2RXBUF UCA2TXBUF UCA2ABCTL UCA2IRTCTL UCA2IRRCTL UCA2IE UCA2IFG UCA2IV 00h 02h 06h 07h 08h 0Ah 0Ch 0Eh 10h 12h 13h 1Ah 1Ch 1Eh OFFSET
Table 58. eUSCI_B0 Registers (Base Address: 0640h)

REGISTER DESCRIPTION eUSCI_B control word 0 eUSCI_B control word 1 eUSCI_B bit rate 0 eUSCI_B bit rate 1 eUSCI_B status word eUSCI_B byte counter threshold eUSCI_B receive buffer eUSCI_B transmit buffer eUSCI_B I2C own address 0 eUSCI_B I2C own address 1 eUSCI_B I2C own address 2 eUSCI_B I2C own address 3 eUSCI_B received address eUSCI_B address mask eUSCI I2C slave address eUSCI interrupt enable eUSCI interrupt flags eUSCI interrupt vector word REGISTER UCB0CTLW0 UCB0CTLW1 UCB0BR0 UCB0BR1 UCB0STATW UCB0TBCNT UCB0RXBUF UCB0TXBUF UCB0I2COA0 UCB0I2COA1 UCB0I2COA2 UCB0I2COA3 UCB0ADDRX UCB0ADDMASK UCB0I2CSA UCB0IE UCB0IFG UCB0IV 00h 02h 06h 07h 08h 0Ah 0Ch 0Eh 14h 16h 18h 1Ah 1Ch 1Eh 20h 2Ah 2Ch 2Eh OFFSET
44
Table 59. ADC10_A Registers (Base Address: 0740h)

REGISTER DESCRIPTION ADC10_A Control register 0 ADC10_A Control register 1 ADC10_A Control register 2 ADC10_A Window Comparator Low Threshold ADC10_A Window Comparator High Threshold ADC10_A Memory Control Register 0 ADC10_A Conversion Memory Register ADC10_A Interrupt Enable ADC10_A Interrupt Flags ADC10_A Interrupt Vector Word REGISTER ADC10CTL0 ADC10CTL1 ADC10CTL2 ADC10LO ADC10HI ADC10MCTL0 ADC10MCTL0 ADC10IE ADC10IGH ADC10IV 00h 02h 04h 06h 08h 0Ah 12h 1Ah 1Ch 1Eh OFFSET
Table 60. SD24_B Registers (Base Address: 0800h)

REGISTER DESCRIPTION SD24_B Control 0 register SD24_B Control 1 register SD24_B Trigger Control register SD24_B Trigger OSR Control register SD24_B Trigger Preload register SD24_B interrupt flag register SD24_B interrupt enable register SD24_B Interrupt Vector register SD24_B converter 0 Control register SD24_B converter 0 Input Control register SD24_B converter 0 OSR Control register SD24_B converter 0 Preload register SD24_B converter 1 Control register SD24_B Converter 1 Input Control register SD24_B Converter 1 OSR Control register SD24_B Converter 1 Preload register SD24_B Converter 2 Control register SD24_B Converter 2 Input Control register SD24_B Converter 2 OSR Control register SD24_B Converter 2 Preload register SD24_B Converter 0 Conversion Memory Low Word register SD24_B Converter 0 Conversion Memory High Word regiser SD24_B Converter 1 Conversion Memory Low Word register SD24_B Converter 1 Conversion Memory High Word regiser SD24_B Converter 2 Conversion Memory Low Word register SD24_B Converter 2 Conversion Memory High Word regiser REGISTER SD24BCTL0 SD24BCTL1 SD24BTRGCTL SD24BTRGOSR SD24BTRGPRE SD24BIFG SD24BIE SD24BIV SD24BCCTL0 SD24BINCTL0 SD24BOSR0 SD24BPRE0 SD24BCCTL1 SD24BINCTL1 SD24BOSR1 SD24BPRE1 SD24BCCTL2 SD24BINCTL2 SD24BOSR2 SD24BPRE2 SD24BMEML0 SD24BMEMH0 SD24BMEML1 SD24BMEMH1 SD24BMEML2 SD24BMEMH2 00h 02h 04h 06h 08h 0Ah 0Ch 0Eh 10h 12h 14h 16h 18h 1Ah 1Ch 1Eh 20h 22h 24h 26h 50h 52h 54h 56h 58h 5Ah OFFSET
45
Table 61. Auxiliary Supplies Registers (Base Address: 09E0h)

REGISTER DESCRIPTION Auxiliary Supply Control 0 register Auxiliary Supply Control 1 register Auxiliary Supply Control 2 register AUX2 Charger Control AUX3 Charger Control AUX ADC Control AUX Interrupt Flag AUX Interrupt Enable AUX Interrupt Vector Word REGISTER AUXCTL0 AUXCTL1 AUXCTL2 AUX2CHCTL AUX3CHCTL AUXADCCTL AUXIFG AUXIE AUXIV 00h 02h 04h 12h 14h 16h 1Ah 1Ch 1Eh OFFSET
Table 62. LCD_C Registers (Base Address: 0A00h)

REGISTER DESCRIPTION LCD_C control register 0 LCD_C control register 1 LCD_C blinking control register LCD_C memory control register LCD_C voltage control register LCD_C port control 0 LCD_C port control 1 LCD_C port control 2 LCD_C charge pump control register LCD_C interrupt vector Static and 2 to 4 mux modes LCD_C memory 1 LCD_C memory 2 LCD_C memory 20 LCD_C blinking memory 1 LCD_C blinking memory 2 LCD_C blinking memory 20 5 to 8 mux modes LCD_C memory 1 LCD_C memory 2 LCD_C memory 40 LCDM1 LCDM2 LCDM40 020h 021h 047h LCDM1 LCDM2 LCDM20 LCDBM1 LCDBM2 LCDBM20 020h 021h 033h 040h 041h 053h REGISTER LCDCCTL0 LCDCCTL1 LCDCBLKCTL LCDCMEMCTL LCDCVCTL LCDCPCTL0 LCDCPCTL1 LCDCPCTL2 LCDCCPCTL LCDCIV 000h 002h 004h 006h 008h 00Ah 00Ch 00Eh 012h 01Eh OFFSET
46
Absolute Maximum Ratings (1)

over operating free-air temperature range (unless otherwise noted)
Voltage applied at DVCC to DVSS Voltage applied to any pin (excluding VCORE) Diode current at any device pin Storage temperature range, Tstg
(3) (2)
-0.3 V to 4.1 V -0.3 V to VCC + 0.3 V 2 mA 55C to 150C 95C
Maximum junction temperature, TJ (1) (2) (3)
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages referenced to VSS. VCORE is for internal device usage only. No external DC loading or voltage should be applied. Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow temperatures not higher than classified on the device label on the shipping boxes or reels.
Recommended Operating Conditions

MIN PMMCOREVx = 0 VCC Supply voltage during program execution and flash programming. V(AVCC) = V(DVCC) = VCC (1) Supply voltage V(AVSS) = V(DVSS) = VSS Operating free-air temperature Operating junction temperature Recommended capacitor at VCORE Capacitor ratio of DVCC to VCORE PMMCOREVx = 0, 1.8 V VCC 3.6 V (default condition) fSYSTEM Processor frequency (maximum MCLK frequency) (2) (3) (see Figure 1) PMMCOREVx = 1, 2.0 V VCC 3.6 V PMMCOREVx = 2, 2.2 V VCC 3.6 V PMMCOREVx = 3, 2.4 V VCC 3.6 V ILOAD,
DVCCD
NOM
MAX 3.6 3.6 3.6 3.6
UNIT V V V V V C C nF
1.8 2.0 2.2 2.4 0 40 40 470 10
PMMCOREVx = 0, 1 PMMCOREVx = 0, 1, 2 PMMCOREVx = 0, 1, 2, 3
VSS TA TJ CVCORE CDVCC/ CVCORE
I version I version
85 85
8.0
0 0 0
12.0 20.0 25.0 20 20 20 10 5 5
MHz
Maximum load current that can be drawn from DVCC for core and IO (ILOAD = ICORE + IIO) Maximum load current that can be drawn from AUXVCC1 for core and IO (ILOAD = ICORE + IIO) Maximum load current that can be drawn from AUXVCC2 for core and IO (ILOAD = ICORE + IIO) Maximum load current that can be drawn from AVCC for analog modules (ILOAD = IModules) Maximum load current that can be drawn from AUXVCC1 for analog modules (ILOAD = IModules) Maximum load current that can be drawn from AUXVCC2 for analog modules (ILOAD = IModules)
mA mA mA mA mA mA
ILOAD,
AUX1D
ILOAD,
AUX2D
ILOAD,
AVCCA
ILOAD,
AUX1A
ILOAD,
AUX2A
(1) (2) (3)
It is recommended to power AVCC and DVCC from the same source. A maximum difference of 0.3 V between V(AVCC) and V(DVCC) can be tolerated during power up and operation. The MSP430 CPU is clocked directly with MCLK. Both the high and low phase of MCLK must not exceed the pulse width of the specified maximum frequency. Modules may have a different maximum input clock specification. Refer to the specification of the respective module in this data sheet.
47
25 3
System Frequency - MHz
20 2 12 1 8 1, 2 1, 2, 3 2, 3
0, 1
0, 1, 2
0, 1, 2, 3
0 1.8 2.0 2.2 2.4 3.6
Supply Voltage - V The numbers within the fields denote the supported PMMCOREVx settings.
Figure 1. Maximum System Frequency
Active Mode Supply Current Into VCC Excluding External Current

over recommended operating free-air temperature (unless otherwise noted) (1)
PARAMETER EXECUTION MEMORY VCC PMMCOREVx 1 MHz TYP 0 IAM,
Flash (4)
(2) (3)
FREQUENCY (fDCO = fMCLK = fSMCLK) 8 MHz TYP 2.10 2.39 2.65 2.82 0.22 1.10 1.30 1.45 1.55 1.22 1.90 2.15 2.30 2.10 3.55 3.80 4.0 4.70 5.30 mA MAX 2.30 3.54 3.94 4.20 3.90 6.54 6.96 7.23 8.65 9.54 mA 12 MHz TYP MAX 20 MHz TYP MAX 25 MHz TYP MAX UNIT MAX 0.36
0.32 0.36 0.39 0.42 0.20 0.22 0.24 0.26
Flash
3.0 V
1 2 3 0
IAM,
RAM
(5)
RAM
3.0 V
1 2 3
(1) (2) (3)
(4) (5)
All inputs are tied to 0 or to VCC. Outputs do not source or sink any current. The currents are characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external load capacitance are chosen to closely match the required 12.5 pF. Characterized with program executing typical data processing. fACLK = 32786 Hz, fDCO = fMCLK = fSMCLK at specified frequency. XTS = CPUOFF = SCG0 = SCG1 = OSCOFF = SMCLKOFF = 0. Active mode supply current when program executes in flash at a nominal supply voltage of 3.0V. Active mode supply current when program executes in RAM at a nominal supply voltage of 3 V.
48
Low-Power Mode Supply Currents (Into VCC) Excluding External Current

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) (2)
TEMPERATURE (TA) PARAMETER VCC 2.2 V 3.0 V 2.2 V 3.0 V PMMCOREVx -40C TYP ILPM0,1MHz ILPM2 Low-power mode 0 (3) (4) Low-power mode 2 (5) (4) 0 3 0 3 0 ILPM3,XT1LF Low-power mode 3, crystal mode (6) (4) 2.2 V 1 2 0 ILPM3,XT1LF Low-power mode 3, crystal mode (6) (4) 3.0 V 1 2 3 0 ILPM3,VLO Low-power mode 3, VLO mode (7) (4) 3.0 V 1 2 3 0 ILPM4 Low-power mode 4 (8) (4) 3.0 V 1 2 3 ILPM3.5 ILPM4.5 Low-power mode 3.5, RTC active on AUXVCC3 (9) Low-power mode 4.5
(10)
25C MAX TYP 78 89 6.2 7.4 1.7 1.9 2.0 2.5 2.7 2.9 2.9 1.7 1.8 1.9 1.9 1.6 1.6 1.7 1.7 0.80 1.24 0.78 2.05 1.05 2.2 2.4 2.0 3.5 2.2 3.1 MAX 87 99 9 10
60C TYP 81 93 6.9 8.4 2.5 2.7 2.9 3.3 3.5 3.7 3.7 2.4 2.5 2.7 2.7 2.3 2.4 2.5 2.5 0.90 1.43 0.90 MAX
85C TYP 84 98 9.4 11 4.9 5.2 5.5 5.5 5.8 6.1 6.1 4.5 4.7 4.9 5.0 4.4 4.5 4.8 4.8 1.30 1.87 1.20 2.71 1.85 12.2 12.7 11.1 14.0 11.5 12.7 MAX 96 110 17 19
UNIT
75 85 5.9 6.9 1.4 1.5 1.7 2.2 2.3 2.5 2.5 1.4 1.5 1.6 1.6 1.3 1.4 1.4 1.4 0.65 1.16 0.70
2.2V 3.0V 3.0V
A A
(1) (2)
All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current. The currents are characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external load capacitance are chosen to closely match the required 12.5 pF. (3) Current for watchdog timer clocked by SMCLK included. ACLK = low frequency crystal operation (XTS = 0, XT1DRIVEx = 0). CPUOFF = 1, SCG0 = 0, SCG1 = 0, OSCOFF = 0 (LPM0); fACLK = 32768 Hz, fMCLK = 0 MHz, fSMCLK = fDCO = 1 MHz (4) Current for brownout, high side supervisor (SVSH) normal mode included. Low side supervisor and monitors disabled (SVSL, SVML). High side monitor disabled (SVMH). RAM retention enabled. (5) Current for watchdog timer clocked by ACLK and RTC clocked by XT1 included. ACLK = low frequency crystal operation (XTS = 0, XT1DRIVEx = 0). CPUOFF = 1, SCG0 = 0, SCG1 = 1, OSCOFF = 0 (LPM2); fACLK = 32768 Hz, fMCLK = 0 MHz, fSMCLK = fDCO = 0 MHz; DCO setting = 1 MHz operation, DCO bias generator enabled. (6) Current for watchdog timer clocked by ACLK and RTC clocked by XT1 included. ACLK = low frequency crystal operation (XTS = 0, XT1DRIVEx = 0). CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3); fACLK = 32768 Hz, fMCLK = fSMCLK = fDCO = 0 MHz (7) Current for watchdog timer clocked by ACLK included. RTC is disabled (RTCHOLD=1). ACLK = VLO. CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3); fACLK = fVLO, fMCLK = fSMCLK = fDCO = 0 MHz (8) CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1 (LPM4); fDCO = fACLK = fMCLK = fSMCLK = 0 MHz (9) fDCO = fMCLK = fSMCLK = 0 MHz, fACLK = 32768 Hz, PMMREGOFF = 1, RTC active on AUXVCC3 supply (10) fDCO = fMCLK = fSMCLK = 0 MHz, fACLK = 0 Hz, PMMREGOFF = 1
49
Low-Power Mode With LCD Supply Currents (Into VCC) Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) (2)
Temperature (TA) PARAMETER Low-power mode 3 (LPM3) current, LCD 4mux mode, internal biasing, charge pump disabled (3) (4) Low-power mode 3 (LPM3) current, LCD 4mux mode, internal biasing, charge pump disabled (3) (4) VCC PMMCOREVx 0 2.2 V 1 2 0 3.0 V 1 2 3 0 2.2 V ILPM3 LCD,CP Low-power mode 3 (LPM3) current, LCD 4mux mode, internal biasing, charge pump enabled (3) (5) 1 2 0 3.0 V 1 2 3 (1) (2) (3) -40C TYP 2.4 2.5 2.6 2.8 2.9 3.1 3.1 ILPM3 LCD, int. bias MAX 25C TYP 2.9 3.1 3.3 3.2 3.4 3.6 3.6 3.8 3.9 4.0 4.0 4.1 4.2 4.2 A A 4.5 3.9 3.9 MAX 3.6 60C TYP 3.8 4.0 4.2 4.1 4.3 4.5 4.5 MAX 85C TYP 5.8 6.0 6.3 6.4 6.7 7.0 7.0 14.7 13.4 13.3 A MAX 12.2 A UNIT
ILPM3 LCD, int. bias
(4)
(5)
All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current. The currents are characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external load capacitance are chosen to closely match the required 12.5 pF. Current for watchdog timer clocked by ACLK and RTC clocked by XT1 included. ACLK = low-frequency crystal operation (XTS = 0, XT1DRIVEx = 0). CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3); fACLK = 32768 Hz, fMCLK = fSMCLK = fDCO = 0 MHz Current for brownout, high-side supervisor (SVSH) normal mode included. Low-side supervisor and monitors disabled (SVSL, SVML). High-side monitor disabled (SVMH). RAM retention enabled. LCDMx = 11 (4-mux mode), LCDREXT = 0, LCDEXTBIAS = 0 (internal biasing), LCD2B = 0 (1/3 bias), LCDCPEN = 0 (charge pump disabled), LCDSSEL = 0, LCDPREx = 101, LCDDIVx = 00011 (fLCD = 32768 Hz / 32 / 4 = 256 Hz) Even segments S0, S2, ... = 0 and odd segments S1, S3, ... = 1. No LCD panel load. LCDMx = 11 (4-mux mode), LCDREXT = 0, LCDEXTBIAS = 0 (internal biasing), LCD2B = 0 (1/3 bias), LCDCPEN = 1 (charge pump enabled), VLCDx = 1000 (VLCD = 3V,typ.), LCDSSEL = 0, LCDPREx = 101, LCDDIVx = 00011 (fLCD = 32768 Hz / 32 / 4 = 256 Hz) Even segments S0, S2, ... = 0 and odd segments S1, S3, ... = 1. No LCD panel load.
Schmitt-Trigger Inputs General Purpose I/O

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER VIT+ VIT Vhys RPull CI Positive-going input threshold voltage Negative-going input threshold voltage Input voltage hysteresis (VIT+ VIT) Pullup/pulldown resistor Input capacitance For pullup: VIN = VSS For pulldown: VIN = VCC VIN = VSS or VCC TEST CONDITIONS VCC 1.8 V 3V 1.8 V 3V 1.8 V 3V MIN 0.80 1.50 0.45 0.75 0.3 0.4 20 35 5 TYP MAX 1.40 2.10 1.00 1.65 0.85 1.0 50 UNIT V V V k pF
50
Inputs Ports P1 and P2 (1)

PARAMETER t(int) (1) (2) External interrupt timing (2) TEST CONDITIONS Port P1, P2: P1.x to P2.x, External trigger pulse width to set interrupt flag VCC 2.2 V/3 V MIN 20 MAX UNIT ns
Some devices may contain additional ports with interrupts. See the block diagram and terminal function descriptions. An external signal sets the interrupt flag every time the minimum interrupt pulse width t(int) is met. It may be set by trigger signals shorter than t(int).
Leakage Current General Purpose I/O

PARAMETER Ilkg(Px.y) (1) (2) High-impedance leakage current See TEST CONDITIONS
(1) (2)
VCC 1.8 V/3 V
MIN
MAX 50
UNIT nA
The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted. The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup/pulldown resistor is disabled.
Outputs General Purpose I/O (Full Drive Strength)

PARAMETER TEST CONDITIONS I(OHmax) = 3 mA (1) VOH High-level output voltage I(OHmax) = 10 mA (1) I(OHmax) = 5 mA
(1)
VCC 1.8 V 3V 1.8 V 3V
MIN VCC 0.25 VCC 0.60 VCC 0.25 VCC 0.60
MAX VCC VCC VCC VCC
UNIT
I(OHmax) = 15 mA (1) I(OLmax) = 3 mA (2) VOL Low-level output voltage I(OLmax) = 10 mA (3) I(OLmax) = 5 mA (2) I(OLmax) = 15 mA (3) (1) (2) (3)
VSS VSS + 0.25 VSS VSS + 0.60 VSS VSS + 0.25 VSS VSS + 0.60 V
The maximum total current, I(OHmax), for all outputs combined should not exceed 20 mA to hold the maximum voltage drop specified. See Recommended Operating Conditions for more details. The maximum total current, I(OLmax), for all outputs combined should not exceed 48 mA to hold the maximum voltage drop specified. The maximum total current, I(OLmax), for all outputs combined should not exceed 100 mA to hold the maximum voltage drop specified.
51
Typical Characteristics General Purpose I/O (Full Drive Strength)

HIGH-LEVEL OUTPUT CURRENT vs HIGH-LEVEL OUTPUT VOLTAGE
0 VCC = 1.8 V Full Drive Strength

0 VCC = 3 V Full Drive Strength -10
IOH High-Level Output Current mA
-5
-20
-10
-30
-15 TA = 85C
-40 TA = 85C -50 TA = 25C
-20 TA = 25C -25 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 VOH High-Level Output Voltage V
-60 0 0.5 1 1.5 2 2.5 3 VOH High-Level Output Voltage V
Figure 2. LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE

25

60
IOL Low-Level Output Current mA
20 TA = 25C TA = 85C 15
50 TA = 25C TA = 85C 40
30
10
20
5 VCC = 1.8 V Full Drive Strength 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 VOL Low-Level Output Voltage V
10 VCC = 3 V Full Drive Strength 0 0 0.5 1 1.5 2 2.5 3 VOL Low-Level Output Voltage V
Figure 4.
Figure 5.
52
Outputs General Purpose I/O (Reduced Drive Strength)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER TEST CONDITIONS I(OHmax) = 1 mA VOH High-level output voltage
(2)
VCC 1.8 V 3.0 V 1.8 V 3.0 V
MIN VCC 0.25 VCC 0.60 VCC 0.25 VCC 0.60
MAX VCC VCC VCC VCC
UNIT
I(OHmax) = 3 mA (2) I(OHmax) = 2 mA (2) I(OHmax) = 6 mA (2) I(OLmax) = 1 mA

(3)
VSS VSS + 0.25 VSS VSS + 0.60 VSS VSS + 0.25 VSS VSS + 0.60 V
VOL
Low-level output voltage
I(OLmax) = 3 mA (4) I(OLmax) = 2 mA (3) I(OLmax) = 6 mA (4)
(1) (2) (3) (4)
Selecting reduced drive strength may reduce EMI. The maximum total current, I(OHmax), for all outputs combined should not exceed 20 mA to hold the maximum voltage drop specified. See Recommended Operating Conditions for more details. The maximum total current, I(OLmax), for all outputs combined, should not exceed 48 mA to hold the maximum voltage drop specified. The maximum total current, I(OLmax), for all outputs combined, should not exceed 100 mA to hold the maximum voltage drop specified.
53
Typical Characteristics General Purpose I/O (Reduced Drive Strength)

0 VCC = 1.8 V Reduced Drive Strength -1
0 VCC = 3 V Reduced Drive Strength
-2 -3 -4 -5 TA = 85C -6 -7 TA = 25C -8 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 VOH High-Level Output Voltage V
-5
-10
-15 TA = 85C
-20 TA = 25C -25 0 0.5 1 1.5 2 2.5 3 VOH High-Level Output Voltage V

8 7 20 18 TA = 25C
TA = 25C 6 TA = 85C 5 4 3 2 1 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 VOL Low-Level Output Voltage V
16 TA = 85C 14 12 10 8 6 4 2 0 0 0.5 1 1.5 2 2.5 3 VOL Low-Level Output Voltage V VCC = 3 V Reduced Drive Strength
VCC = 1.8 V Reduced Drive Strength
Figure 8.
Figure 9.
54
Output Frequency General Purpose I/O

PARAMETER Port output frequency (with load) TEST CONDITIONS VCC = 1.8 V PMMCOREVx = 0 VCC = 3 V PMMCOREVx = 3 VCC = 1.8 V PMMCOREVx = 0 VCC = 3 V PMMCOREVx = 3 MIN MAX 16 MHz 25 16 MHz 25 UNIT
fPx.y
See
(1) (2)
fPort_CLK
Clock output frequency
ACLK SMCLK MCLK CL = 20 pF (2)
(1) (2)
A resistive divider with 2 R1 between VCC and VSS is used as load. The output is connected to the center tap of the divider. For full drive strength, R1 = 550 . For reduced drive strength, R1 = 1.6 k. CL = 20 pF is connected to the output to VSS. The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency.
Crystal Oscillator, XT1, Low-Frequency Mode (1)

PARAMETER Differential XT1 oscillator crystal current consumption from lowest drive setting, LF mode XT1 oscillator crystal frequency, LF mode TEST CONDITIONS fOSC = 32768 Hz, XTS = 0, XT1BYPASS = 0, XT1DRIVEx = 1, TA = 25C fOSC = 32768 Hz, XTS = 0, XT1BYPASS = 0, XT1DRIVEx = 2, TA = 25C fOSC = 32768 Hz, XTS = 0, XT1BYPASS = 0, XT1DRIVEx = 3, TA = 25C XTS = 0, XT1BYPASS = 0
(3)
VCC
MIN
TYP 0.075
MAX
UNIT
IDVCC.LF
3.0 V
0.170 0.290 32768 10 32.768 210 50
fXT1,LF0 fXT1,LF,SW
Hz kHz
XT1 oscillator logic-level square-wave input frequency, XTS = 0, XT1BYPASS = 1 (2) LF mode Oscillation allowance for LF crystals (4)
OALF
XTS = 0, XT1BYPASS = 0, XT1DRIVEx = 0, fXT1,LF = 32768 Hz, CL,eff = 6 pF XTS = 0, XT1BYPASS = 0, XT1DRIVEx = 1, fXT1,LF = 32768 Hz, CL,eff = 12 pF XTS = 0, XCAPx = 0 (6) XTS = 0, XCAPx = 1 XTS = 0, XCAPx = 2 XTS = 0, XCAPx = 3
k 300 2 5.5 8.5 12.0 pF
CL,eff
Integrated effective load capacitance, LF mode (5)
(1)
(2) (3) (4)
(5)
(6)
To improve EMI on the XT1 oscillator, the following guidelines should be observed. (a) Keep the trace between the device and the crystal as short as possible. (b) Design a good ground plane around the oscillator pins. (c) Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT. (d) Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins. (e) Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins. (f) If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins. When XT1BYPASS is set, XT1 circuits are automatically powered down. Input signal is a digital square wave with parametrics defined in the Schmitt-trigger Inputs section of this datasheet. Maximum frequency of operation of the entire device cannot be exceeded. Oscillation allowance is based on a safety factor of 5 for recommended crystals. The oscillation allowance is a function of the XT1DRIVEx settings and the effective load. In general, comparable oscillator allowance can be achieved based on the following guidelines, but should be evaluated based on the actual crystal selected for the application: (a) For XT1DRIVEx = 0, CL,eff 6 pF. (b) For XT1DRIVEx = 1, 6 pF CL,eff 9 pF. (c) For XT1DRIVEx = 2, 6 pF CL,eff 10 pF. (d) For XT1DRIVEx = 3, CL,eff 6 pF. Includes parasitic bond and package capacitance (approximately 2 pF per pin). Since the PCB adds additional capacitance, it is recommended to verify the correct load by measuring the ACLK frequency. For a correct setup, the effective load capacitance should always match the specification of the used crystal. Requires external capacitors at both terminals. Values are specified by crystal manufacturers. Submit Documentation Feedback 55
Crystal Oscillator, XT1, Low-Frequency Mode(1) (continued)

PARAMETER Duty cycle fFault,LF LF mode Oscillator fault frequency, LF mode (7) TEST CONDITIONS XTS = 0, Measured at ACLK, fXT1,LF = 32768 Hz XTS = 0 (8) fOSC = 32768 Hz, XTS = 0, XT1BYPASS = 0, XT1DRIVEx = 0, TA = 25C, CL,eff = 6 pF fOSC = 32768 Hz, XTS = 0, XT1BYPASS = 0, XT1DRIVEx = 3, TA = 25C, CL,eff = 12 pF VCC MIN 30 10 1000 3.0 V 500 ms TYP MAX 70 10000 UNIT % Hz
tSTART,LF
Startup time, LF mode
(7) (8)
Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag. Frequencies in between might set the flag. Measured with logic-level input frequency but also applies to operation with crystals.
Internal Very-Low-Power Low-Frequency Oscillator (VLO)

PARAMETER fVLO dfVLO/dT VLO frequency VLO frequency temperature drift Duty cycle (1) (2) TEST CONDITIONS Measured at ACLK Measured at ACLK Measured at ACLK
(1)
VCC 1.8 V to 3.6 V 1.8 V to 3.6 V 1.8 V to 3.6 V 1.8 V to 3.6 V
MIN 6
TYP 9.4 0.5 4
MAX 15
UNIT kHz %/C %/V
dfVLO/dVCC VLO frequency supply voltage drift
Measured at ACLK (2)
30
70
Calculated using the box method: (MAX(-40 to 85C) MIN(-40 to 85C)) / MIN(85C (40C)) Calculated using the box method: (MAX(1.8 to 3.6 V) MIN(1.8 to 3.6 V)) / MIN(1.8 to 3.6 V) / (3.6 V 1.8 V)
Internal Reference, Low-Frequency Oscillator (REFO)

PARAMETER IREFO REFO oscillator current consumption REFO frequency calibrated fREFO dfREFO/dT dfREFO/dVCC tSTART (1) (2) REFO absolute tolerance calibrated REFO frequency temperature drift Duty cycle REFO startup time TEST CONDITIONS TA = 25C Measured at ACLK Full temperature range TA = 25C Measured at ACLK (1) Measured at ACLK 40%/60% duty cycle VCC 1.8 V to 3.6 V 1.8 V to 3.6 V 1.8 V to 3.6 V 3V 1.8 V to 3.6 V 1.8 V to 3.6 V 1.8 V to 3.6 V 1.8 V to 3.6 V 40 0.01 1.0 50 25 60 MIN TYP 3 32768 3.5 1.5 MAX UNIT A Hz % % %/C %/V % s
REFO frequency supply voltage drift Measured at ACLK (2)
Calculated using the box method: (MAX(-40 to 85C) MIN(-40 to 85C)) / MIN(85C (40C)) Calculated using the box method: (MAX(1.8 to 3.6 V) MIN(1.8 to 3.6 V)) / MIN(1.8 to 3.6 V) / (3.6 V 1.8 V)
56
DCO Frequency
PARAMETER fDCO(0,0) fDCO(0,31) fDCO(1,0) fDCO(1,31) fDCO(2,0) fDCO(2,31) fDCO(3,0) fDCO(3,31) fDCO(4,0) fDCO(4,31) fDCO(5,0) fDCO(5,31) fDCO(6,0) fDCO(6,31) fDCO(7,0) fDCO(7,31) SDCORSEL SDCO Duty cycle dfDCO/dT dfDCO/dVCORE DCO frequency temperature drift DCO frequency voltage drift DCO frequency (0, 0) DCO frequency (0, 31) DCO frequency (1, 0) DCO frequency (1, 31) DCO frequency (2, 0) DCO frequency (2, 31) DCO frequency (3, 0) DCO frequency (3, 31) DCO frequency (4, 0) DCO frequency (4, 31) DCO frequency (5, 0) DCO frequency (5, 31) DCO frequency (6, 0) DCO frequency (6, 31) DCO frequency (7, 0) DCO frequency (7, 31) Frequency step between range DCORSEL and DCORSEL + 1 Frequency step between tap DCO and DCO + 1 TEST CONDITIONS DCORSELx = 0, DCOx = 0, MODx = 0 DCORSELx = 0, DCOx = 31, MODx = 0 DCORSELx = 1, DCOx = 0, MODx = 0 DCORSELx = 1, DCOx = 31, MODx = 0 DCORSELx = 2, DCOx = 0, MODx = 0 DCORSELx = 2, DCOx = 31, MODx = 0 DCORSELx = 3, DCOx = 0, MODx = 0 DCORSELx = 3, DCOx = 31, MODx = 0 DCORSELx = 4, DCOx = 0, MODx = 0 DCORSELx = 4, DCOx = 31, MODx = 0 DCORSELx = 5, DCOx = 0, MODx = 0 DCORSELx = 5, DCOx = 31, MODx = 0 DCORSELx = 6, DCOx = 0, MODx = 0 DCORSELx = 6, DCOx = 31, MODx = 0 DCORSELx = 7, DCOx = 0, MODx = 0 DCORSELx = 7, DCOx = 31, MODx = 0 SRSEL = fDCO(DCORSEL+1,DCO)/fDCO(DCORSEL,DCO) SDCO = fDCO(DCORSEL,DCO+1)/fDCO(DCORSEL,DCO) Measured at SMCLK fDCO = 1 MHz fDCO = 1 MHz
Typical DCO Frequency, VCC = 3.0 V, TA = 25C 100
MIN 0.07 0.70 0.15 1.47 0.32 3.17 0.64 6.07 1.3 12.3 2.5 23.7 4.6 39.0 8.5 60 1.2 1.02 40
TYP
MAX 0.20 1.70 0.36 3.45 0.75 7.38 1.51 14.0 3.2 28.2 6.0 54.1 10.7 88.0 19.6 135 2.3 1.12
UNIT MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz ratio ratio % %/C %/V
50 0.1 1.9
60
10
fDCO MHz
DCOx = 31
0.1
DCOx = 0
DCORSEL
Figure 10. Typical DCO Frequency
57
PMM, Brown-Out Reset (BOR)

PARAMETER V(DVCC_BOR_IT) V(DVCC_BOR_IT+) V(DVCC_BOR_hys) tRESET (1)
(1)
TEST CONDITIONS | dDVCC/dt | < 3 V/s | dDVCC/dt | < 3 V/s
MIN 0.80 60 2
TYP 1.30
MAX 1.45 1.50 250
UNIT V V mV s
BORH on voltage, DVCC falling level BORH off voltage, DVCC rising level BORH hysteresis Pulse length required at RST/NMI pin to accept a reset
Pulse much shorter than 2 s might trigger reset.
PMM, Core Voltage

PARAMETER VCORE3(AM) VCORE2(AM) VCORE1(AM) VCORE0(AM) VCORE3(LPM) VCORE2(LPM) VCORE1(LPM) VCORE0(LPM) Core voltage, active mode, PMMCOREV = 3 Core voltage, active mode, PMMCOREV = 2 Core voltage, active mode, PMMCOREV = 1 Core voltage, active mode, PMMCOREV = 0 Core voltage, low-current mode, PMMCOREV = 3 Core voltage, low-current mode, PMMCOREV = 2 Core voltage, low-current mode, PMMCOREV = 1 Core voltage, low-current mode, PMMCOREV = 0 TEST CONDITIONS 2.4 V DVCC 3.6 V 2.2 V DVCC 3.6 V 2.0 V DVCC 3.6 V 1.8 V DVCC 3.6 V 2.4 V DVCC 3.6 V 2.2 V DVCC 3.6 V 2.0 V DVCC 3.6 V 1.8 V DVCC 3.6 V MIN TYP 1.93 1.83 1.62 1.42 1.96 1.94 1.74 1.54 MAX UNIT V V V V V V V V
PMM, SVS High Side

PARAMETER I(SVSH) SVS current consumption TEST CONDITIONS SVSHE = 0, DVCC = 3.6 V SVSHE = 1, DVCC = 3.6 V, SVSHFP = 0 SVSHE = 1, DVCC = 3.6 V, SVSHFP = 1 SVSHE = 1, SVSHRVL = 0 V(SVSH_IT) SVSH on voltage level (1) SVSHE = 1, SVSHRVL = 1 SVSHE = 1, SVSHRVL = 2 SVSHE = 1, SVSHRVL = 3 SVSHE = 1, SVSMHRRL = 0 SVSHE = 1, SVSMHRRL = 1 SVSHE = 1, SVSMHRRL = 2 V(SVSH_IT+) SVSH off voltage level (1) SVSHE = 1, SVSMHRRL = 3 SVSHE = 1, SVSMHRRL = 4 SVSHE = 1, SVSMHRRL = 5 SVSHE = 1, SVSMHRRL = 6 SVSHE = 1, SVSMHRRL = 7 tpd(SVSH) t(SVSH) dVDVCC/dt (1) SVSH propagation delay SVSH on/off delay time DVCC rise time SVSHE = 1, dVDVCC/dt = 10 mV/s, SVSHFP = 1 SVSHE = 1, dVDVCC/dt = 1 mV/s, SVSHFP = 0 SVSHE = 0 1, SVSHFP = 1 SVSHE = 0 1, SVSHFP = 0 0 1.60 1.77 1.97 2.09 1.68 1.89 2.08 2.21 2.35 2.65 2.96 2.96 MIN TYP 0 200 1.5 1.65 1.84 2.04 2.16 1.74 1.95 2.14 2.27 2.41 2.72 3.04 3.04 2.5 20 12.5 100 1000 1.70 1.90 2.10 2.23 1.80 2.01 2.21 2.34 2.49 2.80 3.13 3.13 s s V/s V V MAX UNIT nA nA A
The SVSH settings available depend on the VCORE (PMMCOREVx) setting. Please refer to the Power Management Module and Supply Voltage Supervisor chapter in the MSP430x5xx Family User's Guide (SLAU208) on recommended settings and usage.
58
PMM, SVM High Side

PARAMETER I(SVMH) SVMH current consumption TEST CONDITIONS SVMHE = 0, DVCC = 3.6 V SVMHE = 1, DVCC = 3.6 V, SVMHFP = 0 SVMHE = 1, DVCC = 3.6 V, SVMHFP = 1 SVMHE = 1, SVSMHRRL = 0 SVMHE = 1, SVSMHRRL = 1 SVMHE = 1, SVSMHRRL = 2 SVMHE = 1, SVSMHRRL = 3 V(SVMH) SVMH on/off voltage level
(1)
MIN
TYP 0 200 1.5
MAX
UNIT nA nA A
1.68 1.89 2.08 2.21 2.35 2.65 2.96 2.96
1.74 1.95 2.14 2.27 2.41 2.72 3.04 3.04 3.79 2.5
1.80 2.01 2.21 2.34 2.49 2.80 3.13 3.13 V
SVMHE = 1, SVSMHRRL = 4 SVMHE = 1, SVSMHRRL = 5 SVMHE = 1, SVSMHRRL = 6 SVMHE = 1, SVSMHRRL = 7 SVMHE = 1, SVMHOVPE = 1 SVMHE = 1, dVDVCC/dt = 10 mV/s, SVMHFP = 1 SVMHE = 1, dVDVCC/dt = 1 mV/s, SVMHFP = 0 SVMHE = 0 1, SVMHFP = 1 SVMHE = 0 1, SVMHFP = 0
tpd(SVMH)
SVMH propagation delay
s 20 12.5 s 100
t(SVMH)
SVMH on/off delay time
(1)
The SVMH settings available depend on the VCORE (PMMCOREVx) setting. Refer to the Power Management Module and Supply Voltage Supervisor chapter in the MSP430x5xx Family User's Guide (SLAU208) on recommended settings and usage.
59
PMM, SVS Low Side

PARAMETER I(SVSL) SVSL current consumption TEST CONDITIONS SVSLE = 0, PMMCOREV = 2 SVSLE = 1, PMMCOREV = 2, SVSLFP = 0 SVSLE = 1, PMMCOREV = 2, SVSLFP = 1 SVSLE = 1, dVCORE/dt = 10 mV/s, SVSLFP = 1 SVSLE = 1, dVCORE/dt = 1 mV/s, SVSLFP = 0 SVSLE = 0 1, SVSLFP = 1 SVSLE = 0 1, SVSLFP = 0 MIN TYP 0 200 1.5 2.5 s 20 12.5 100 s MAX UNIT nA nA A
tpd(SVSL)
SVSL propagation delay
t(SVSL)
SVSL on/off delay time
PMM, SVM Low Side

PARAMETER I(SVML) SVML current consumption TEST CONDITIONS SVMLE = 0, PMMCOREV = 2 SVMLE = 1, PMMCOREV = 2, SVMLFP = 0 SVMLE = 1, PMMCOREV = 2, SVMLFP = 1 tpd(SVML) t(SVML) SVML propagation delay SVML on/off delay time SVMLE = 1, dVCORE/dt = 10 mV/s, SVMLFP = 1 SVMLE = 1, dVCORE/dt = 1 mV/s, SVMLFP = 0 SVMLE = 0 1, SVMLFP = 1 SVMLE = 0 1, SVMLFP = 0 MIN TYP 0 200 1.5 2.5 20 12.5 100 MAX UNIT nA nA A s s
Wake-Up from Low-Power Modes and Reset

PARAMETER tWAKE-UPFAST
TEST CONDITIONS PMMCOREV = SVSMLRRL = n (where n = 0, 1, 2, or 3), SVSLFP = 1 fMCLK 4 MHz 1 MHz < fMCLK < 4 MHz
MIN
TYP MAX UNIT 3 4 150 5 6 160 s
Wake-up time from LPM2, LPM3, or LPM4 to active mode (1)
tWAKE-UPSLOW
Wake-up time from PMMCOREV = SVSMLRRL = n (where n = 0, 1, 2, or 3), LPM2, LPM3 or LPM4 to SVSLFP = 0 active mode (2) Wake-up time from LPM4.5 to active mode (3) Wake-up time from RST or BOR event to active mode (3)
tWAKE-UPLPM4.5
ms
tWAKE-UPRESET
ms
(1)
(2)
(3)
This value represents the time from the wakeup event to the first active edge of MCLK. The wakeup time depends on the performance mode of the low side supervisor (SVSL) and low side monitor (SVML). Fastest wakeup times are possible with SVSLand SVML in full performance mode or disabled when operating in AM, LPM0, and LPM1. Various options are available for SVSLand SVML while operating in LPM2, LPM3, and LPM4. See the Power Management Module and Supply Voltage Supervisor chapter in the MSP430x5xx Family User's Guide (SLAU208). This value represents the time from the wakeup event to the first active edge of MCLK. The wakeup time depends on the performance mode of the low side supervisor (SVSL) and low side monitor (SVML). In this case, the SVSLand SVML are in normal mode (low current) mode when operating in AM, LPM0, and LPM1. Various options are available for SVSLand SVML while operating in LPM2, LPM3, and LPM4. See the Power Management Module and Supply Voltage Supervisor chapter in the MSP430x5xx Family User's Guide (SLAU208). This value represents the time from the wakeup event to the reset vector execution.
60
Auxiliary Supplies - Recommended Operating Conditions

MIN VCC Supply voltage range for all supplies at pins DVCC, AVCC, AUX1, AUX2, AUX3 PMMCOREVx = 0 VDSYS Digital system supply voltage range, VDSYS = VCC - RONILOAD PMMCOREVx = 1 PMMCOREVx = 2 PMMCOREVx = 3 VASYS CVCC,CAUX1/2 CVSYS CVCORE CAUX3 Analog system supply voltage range, VASYS = VCC - RON ILOAD Recommended capacitor at pins DVCC, AVCC, AUX1, AUX2 Recommended capacitor at pins VDSYS and VASYS Recommended capacitance at pin VCORE Recommended capacitor at pin AUX3 1.8 1.8 2.0 2.2 2.4 Refer to modules 4.7 4.7 0.47 0.47 NOM MAX 3.6 3.6 3.6 3.6 3.6 V F F F F V UNIT V
Auxiliary Supplies - AUX3 (Backup-Sub-System) Currents

PARAMETER IAUX3,RTCon IAUX3,RTCoff AUX3 current with RTC enabled AUX3 current with RTC disabled TEST CONDITIONS RTC and 32-kHz oscillator in backup-subsystem enabled RTC and 32-kHz oscillator in backup-subsystem disabled VCC 3V 3V TA 25C 85C 25C 85C MIN TYP MAX 0.83 0.95 110 165 UNIT A nA
Auxiliary Supplies - Auxiliary Supply Monitor

PARAMETER Average supply current for monitoring circuitry drawn from VDSYS TEST CONDITIONS LOCKAUX = 0, AUXMRx = 0, AUX0MD = 0, AUX1MD = 0, AUX2MD = 1, VDSYS = DVCC, VASYS = AVCC, Current measured at VDSYS pin LOCKAUX = 0, AUXMRx = 0, AUX0MD = 0, AUX1MD = 0, AUX2MD = 1, VDSYS = DVCC, VASYS = AVCC, AUXVCC1 = 3 V, Current measured at AUXVCC1 pin AUXLVLx = 0 AUXLVLx = 1 AUXLVLx = 2 VMonitor Auxiliary supply threshold level AUXLVLx = 3 AUXLVLx = 4 AUXLVLx = 5 AUXLVLx = 6 AUXLVLx = 7 1.67 1.87 2.06 2.19 2.33 2.63 2.91 2.91 1.74 1.95 2.14 2.27 2.41 2.72 3.02 3.02 VCC 3V MIN TYP MAX UNIT
ICC,Monitor
0.70
IMeas,Monitor
Average current drawn from monitored supply during measurement cycle
0.11
1.80 2.01 2.21 2.33 2.48 2.79 3.10 3.10 V
61
0.7 0.6 0.5
ICC, monitor A
0.4 0.3 0.2 0.1 0 1.8
2.2
2.4
2.6 2.8 VDSYS Voltage V
3.2
3.4
3.6
Figure 11. VDSYS Voltage vs ICC,Monitor

120 100 80 60 40 20 0 1.8
Imeas, monitor nA
2.0
2.2
2.4
2.6 2.8 AUXVCC1 Voltage V
3.0
3.2
3.4
3.6
Figure 12. AUXVCC1 Voltage vs IMeas,Monitor
Auxiliary Supplies - Switch On-Resistance

PARAMETER RON,DVCC RON,DAUX1 RON,DAUX2 RON,AVCC RON,AAUX1 RON,AAUX2 On-resistance of switch between DVCC and VDSYS On-resistance of switch between AUX1 and VDSYS On-resistance of switch between AUX2 and VDSYS On-resistance of switch between AVCC and VASYS On-resistance of switch between AUX1 and VASYS On-resistance of switch between AUX2 and VASYS TEST CONDITIONS ILOAD = ICORE + IIO = 10mA + 10mA = 20mA ILOAD = ICORE + IIO = 10mA + 10mA = 20mA ILOAD = ICORE + IIO = 10mA + 10mA = 20mA ILOAD = IModules = 10mA ILOAD = IModules = 5mA ILOAD = IModules = 5mA VCC MIN TYP MAX 5 5 5 5 20 20 UNIT
62
Auxiliary Supplies - Switching Time

PARAMETER tSwitch tRecover Time from occurence of trigger (SVM or software) to "new" supply connected to system supplies "Recovery time" after a switch over took place. During that time no further switching takes place. 200 TEST CONDITIONS VCC MIN TYP MAX 100 450 UNIT ns s
Auxiliary Supplies - Switch Leakage

PARAMETER ISW,Lkg IVmax TEST CONDITIONS VCC MIN TYP 50 450 MAX 100 730 UNIT nA nA Current into DVCC, AVCC, AUX1 or AUX2 Per supply (but not the highest if not selected supply) Current drawn from highest supply
Auxiliary Supplies - Auxiliary Supplies to ADC10_A

PARAMETER V3 Supply voltage divider V3 = VSupply/3 AUXADCRx = 0 RV3 Load resistance AUXADC = 1, ADC10ON = 1, INCH = 0Ch, Error of conversion result 1 LSB AUXADCRx = 1 AUXADCRx = 2 AUXADCRx = 0 AUXADCRx = 1 AUXADCRx = 2 1000 1000 1000 Sampling time required if V3 selected. TEST CONDITIONS VCC 1.8 V 3.0 V 3.6 V MIN 0.58 0.98 1.18 TYP 0.60 1.00 1.20 MAX 0.62 1.02 1.22 18 1.5 0.6 k k k ns ns ns V UNIT
tSample,V3
Auxiliary Supplies - Charge Limiting Resistor

PARAMETER RCHARGE Charge limiting resistor TEST CONDITIONS CHCx = 1 CHCx = 2 CHCx = 3 VCC 3V 3V 3V MIN TYP MAX 5 10 20 k UNIT
63
Timer_A
PARAMETER fTA Timer_A input clock frequency TEST CONDITIONS Internal: SMCLK, ACLK External: TACLK Duty cycle = 50% 10% All capture inputs. Minimum pulse width required for capture. VCC 1.8 V/ 3.0 V 1.8 V/ 3.0 V MIN TYP MAX 25 UNIT MHz
tTA,cap
Timer_A capture timing
20
ns
eUSCI (UART Mode) - Recommended Operating Conditions

PARAMETER feUSCI fBITCLK eUSCI input clock frequency BITCLK clock frequency (equals baud rate in MBaud) CONDITIONS Internal: SMCLK, ACLK External: UCLK Duty cycle = 50% 10% VCC MIN TYP MAX fSYSTEM 5 UNIT MHz
MHz
eUSCI (UART Mode)

PARAMETER TEST CONDITIONS UCGLITx = 0 tt UART receive deglitch time (1) UCGLITx = 1 UCGLITx = 2 UCGLITx = 3 (1) 2.0 V/3.0 V VCC MIN 10 30 50 70 TYP 15 50 80 120 MAX 25 85 150 200 ns UNIT
Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses are correctly recognized their width should exceed the maximum specification of the deglitch time.
eUSCI (SPI Master Mode) - Recommended Operating Conditions

PARAMETER feUSCI eUSCI input clock frequency CONDITIONS Internal: SMCLK, ACLK Duty cycle = 50% 10% VCC MIN TYP MAX fSYSTEM UNIT MHz
eUSCI (SPI Master Mode)

PARAMETER tSTE,LEAD tSTE,LAG STE lead time, STE active to clock STE lag time, Last clock to STE inactive TEST CONDITIONS UCSTEM = 0, UCMODEx = 01 or 10 UCSTEM = 1, UCMODEx = 01 or 10 UCSTEM = 0, UCMODEx = 01 or 10 UCSTEM = 1, UCMODEx = 01 or 10 UCSTEM = 0, UCMODEx = 01 or 10 tSTE,ACC STE access time, STE active to SIMO data out UCSTEM = 1, UCMODEx = 01 or 10 UCSTEM = 0, UCMODEx = 01 or 10 UCSTEM = 1, UCMODEx = 01 or 10 VCC 2.0 V/3.0 V 2.0 V/3.0 V 2.0 V/3.0 V 2.0 V/3.0 V 2.0 V 3.0 V 2.0 V 3.0 V 2.0 V 3.0 V 2.0 V 3.0 V 2.0 V 3.0 V 50 30 MIN 150 150 200 200 50 30 50 30 40 25 40 25 ns ns ns TYP MAX UNIT ns ns
tSTE,DIS
STE disable time, STE inactive to SIMO high impedance SOMI input data setup time
tSU,MI (1) 64
fUCxCLK = 1/2tLO/HI with tLO/HI = max(tVALID,MO(eUSCI) + tSU,SI(Slave), tSU,MI(eUSCI) + tVALID,SO(Slave)). For the slave's parameters tSU,SI(Slave) and tVALID,SO(Slave) refer to the SPI parameters of the attached slave. Submit Documentation Feedback
eUSCI (SPI Master Mode) (continued)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
PARAMETER tHD,MI tVALID,MO tHD,MO (2) (3) SOMI input data hold time SIMO output data valid time (2) SIMO output data hold time (3) UCLK edge to SIMO valid, CL = 20 pF CL = 20 pF TEST CONDITIONS VCC 2.0 V 3.0 V 2.0 V 3.0 V 2.0 V 3.0 V 0 0 MIN 0 0 9 5 TYP MAX UNIT ns ns ns
Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. See the timing diagrams in Figure 15 and Figure 16. Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the data on the SIMO output can become invalid before the output changing clock edge observed on UCLK. See the timing diagrams in Figure 15 and Figure 16.
UCMODEx = 01 STE UCMODEx = 10 1/fUCxCLK CKPL = 0 UCLK CKPL = 1 tLOW/HIGH tLOW/HIGH tSU,MI tHD,MI SOMI tSTE,LEAD tSTE,LAG
tSTE,ACC SIMO
tVALID,MO
tSTE,DIS
Figure 13. SPI Master Mode, CKPH = 0
65
UCMODEx = 01 STE UCMODEx = 10 1/fUCxCLK CKPL = 0 UCLK CKPL = 1 tLOW/HIGH tLOW/HIGH tSU,MI SOMI tSTE,LEAD tSTE,LAG
tHD,MI
tSTE,ACC SIMO
tVALID,MO
tSTE,DIS
Figure 14. SPI Master Mode, CKPH = 1
66
eUSCI (SPI Slave Mode)

PARAMETER tSTE,LEAD tSTE,LAG tSTE,ACC tSTE,DIS tSU,SI tHD,SI tVALID,SO tHD,SO (1) (2) (3) STE lead time, STE active to clock STE lag time, Last clock to STE inactive STE access time, STE active to SOMI data out STE disable time, STE inactive to SOMI high impedance SIMO input data setup time SIMO input data hold time SOMI output data valid time (2) SOMI output data hold time (3) UCLK edge to SOMI valid, CL = 20 pF CL = 20 pF TEST CONDITIONS VCC 2.0 V 3.0 V 2.0 V 3.0 V 2.0 V 3.0 V 2.0 V 3.0 V 2.0 V 3.0 V 2.0 V 3.0 V 2.0 V 3.0 V 2.0 V 3.0 V 24 16 2 1 2 2 55 32 MIN 4 3 0 0 46 24 38 25 TYP MAX UNIT ns ns ns ns ns ns ns ns
fUCxCLK = 1/2tLO/HI with tLO/HI = max(tVALID,MO(Master) + tSU,SI(eUSCI), tSU,MI(Master) + tVALID,SO(eUSCI)). For the master's parameters tSU,MI(Master) and tVALID,MO(Master) refer to the SPI parameters of the attached slave. Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. Refer to the timing diagrams in Figure 15 and Figure 16. Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. Refer to the timing diagrams inFigure 15 and Figure 16.
UCMODEx = 01 STE UCMODEx = 10 1/fUCxCLK CKPL = 0 UCLK CKPL = 1 tLOW/HIGH tLOW/HIGH tSU,SIMO tHD,SIMO SIMO tSTE,LEAD tSTE,LAG
tACC SOMI
tVALID,SOMI
tDIS
Figure 15. SPI Slave Mode, CKPH = 0
67
UCMODEx = 01 STE UCMODEx = 10 1/fUCxCLK CKPL = 0 UCLK CKPL = 1 tLOW/HIGH tLOW/HIGH tHD,SI tSU,SI SIMO tSTE,LEAD tSTE,LAG
tACC SOMI
tVALID,SO
tDIS
Figure 16. SPI Slave Mode, CKPH = 1
68
eUSCI (I2C Mode)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 17)
PARAMETER feUSCI fSCL tHD,STA tSU,STA tHD,DAT tSU,DAT tSU,STO eUSCI input clock frequency SCL clock frequency Hold time (repeated) START Setup time for a repeated START Data hold time Data setup time Setup time for STOP fSCL = 100 kHz fSCL > 100 kHz fSCL = 100 kHz fSCL > 100 kHz UCGLITx = 0 tSP Pulse duration of spikes suppressed by input filter UCGLITx = 1 UCGLITx = 2 UCGLITx = 3 UCCLTOx = 1 tTIMEOUT Clock low timeout UCCLTOx = 2 UCCLTOx = 3
tHD,STA SDA tLOW SCL tHIGH tSP tSU,STA tHD,STA
TEST CONDITIONS Internal: SMCLK, ACLK External: UCLK Duty cycle = 50% 10%
VCC
MIN
TYP
MAX fSYSTEM
UNIT MHz kHz s s s s s
2 V/3 V fSCL = 100 kHz fSCL > 100 kHz fSCL = 100 kHz fSCL > 100 kHz 2 V/3 V 2 V/3 V 2 V/3 V 2 V/3 V 2 V/3 V 2 V/3 V
0 5.1 1.5 5.1 1.4 0.4 5.0 1.3 5.2 1.7 75
400
220 120 60 35 30 33 37
tBUF
ns ns ns ns ms ms ms
2 V/3 V
35 30 20
2 V/3 V
tSU,DAT tHD,DAT
tSU,STO
Figure 17. I2C Mode Timing
LCD_C - Recommended Operating Conditions

PARAMETER VCC,LCD_C,CP en,3.6 VCC,LCD_C,CP en,3.3 VCC,LCD_C,int. bias VCC,LCD_C,ext.
bias
CONDITIONS LCDCPEN = 1, 0000 < VLCDx 1111 (charge pump enabled, VLCD 3.6 V) LCDCPEN = 1, 0000 < VLCDx 1100 (charge pump enabled, VLCD 3.3 V) LCDCPEN = 0, VLCDEXT = 0 LCDCPEN = 0, VLCDEXT = 0 LCDCPEN = 0, VLCDEXT = 1
MIN 2.2 2.0 2.4 2.4 2.0
NOM
MAX 3.6 3.6 3.6 3.6 3.6
UNIT V V V V V
Supply voltage range, charge pump enabled, VLCD 3.6 V Supply voltage range, charge pump enabled, VLCD 3.3 V Supply voltage range, internal biasing, charge pump disabled Supply voltage range, external biasing, charge pump disabled Supply voltage range, external LCD voltage, internal or external biasing, charge pump disabled External LCD voltage at LCDCAP/R33, internal or external biasing, charge pump disabled
VCC,LCD_C,VLCDEXT
VLCDCAP/R33
LCDCPEN = 0, VLCDEXT = 1
2.4
3.6
69
LCD_C - Recommended Operating Conditions (continued)

PARAMETER CLCDCAP fFrame fACLK,in CPanel VR33 VR23,1/3bias Capacitor on LCDCAP when charge pump enabled LCD frame frequency range ACLK input frequency range Panel capacitance Analog input voltage at R33 Analog input voltage at R23 Analog input voltage at R13 with 1/3 biasing Analog input voltage at R13 with 1/2 biasing Analog input voltage at R03 Voltage difference between VLCD and R03 External LCD reference voltage applied at LCDREF/R13 100-Hz frame frequency LCDCPEN = 0, VLCDEXT = 1 LCDREXT = 1, LCDEXTBIAS = 1, LCD2B = 0 LCDREXT = 1, LCDEXTBIAS = 1, LCD2B = 0 LCDREXT = 1, LCDEXTBIAS = 1, LCD2B = 1 R0EXT = 1 LCDCPEN = 0, R0EXT = 1 VLCDREFx = 01 2.4 VR13 VR03 + 2/3(VR33VR03) VR03 + 1/3(VR33VR03) VR03 + 1/2(VR33VR03) CONDITIONS LCDCPEN = 1, VLCDx > 0000 (charge pump enabled) fLCD = 2 mux fFRAME with mux = 1 (static), 2, 3, 4 up to 8 0 30 32 MIN NOM 4.7 MAX 10 100 40 10000 VCC+0 .2 VR33 UNIT F Hz kHz pF V V
VR13,1/3bias
VR03
VR23
VR13,1/2bias VR03 VLCD-VR03 VLCDREF/R13
VR03 VSS 2.4 0.8
VR33
V V
VCC+0 .2 1.2 1.5
V V
LCD_C Electrical Characteristics

PARAMETER VLCD LCD voltage TEST CONDITIONS VLCDx = 0000, VLCDEXT = 0 LCDCPEN = 1, VLCDx = 0001 LCDCPEN = 1, VLCDx = 0010 LCDCPEN = 1, VLCDx = 0011 LCDCPEN = 1, VLCDx = 0100 LCDCPEN = 1, VLCDx = 0101 LCDCPEN = 1, VLCDx = 0110 LCDCPEN = 1, VLCDx = 0111 LCDCPEN = 1, VLCDx = 1000 LCDCPEN = 1, VLCDx = 1001 LCDCPEN = 1, VLCDx = 1010 LCDCPEN = 1, VLCDx = 1011 LCDCPEN = 1, VLCDx = 1100 LCDCPEN = 1, VLCDx = 1101 LCDCPEN = 1, VLCDx = 1110 LCDCPEN = 1, VLCDx = 1111 ICC,Peak,CP tLCD,CP,on ICP,Load RLCD,Seg RLCD,COM Peak supply currents due to charge pump activities Time to charge CLCD when discharged Maximum charge pump load current LCD driver output impedance, segment lines LCD driver output impedance, common lines LCDCPEN = 1, VLCDx = 1111 CLCD = 4.7F, LCDCPEN = 01, VLCDx = 1111 LCDCPEN = 1, VLCDx = 1111 LCDCPEN = 1, VLCDx = 1000, ILOAD = 10A LCDCPEN = 1, VLCDx = 1000, ILOAD = 10A VCC 2.4 V to 3.6 V 2 V to 3.6 V 2 V to 3.6 V 2 V to 3.6 V 2 V to 3.6 V 2 V to 3.6 V 2 V to 3.6 V 2 V to 3.6 V 2 V to 3.6 V 2 V to 3.6 V 2 V to 3.6 V 2 V to 3.6 V 2 V to 3.6 V 2.2 V to 3.6 V 2.2 V to 3.6 V 2.2 V to 3.6 V 2.2 V 2.2 V 2.2 V 2.2 V 2.2 V 50 10 10 MIN TYP VCC 2.58 2.64 2.71 2.78 2.83 2.90 2.96 3.02 3.07 3.14 3.21 3.27 3.32 3.38 3.44 400 150 500 3.6 A ms A k k MAX UNIT V
70
SD24_B, Power Supply and Recommended Operating Conditions

MIN AVCC fSD VI VIC VID,FS Analog supply voltage Modulator clock frequency (1) Absolute input voltage range Common-mode input voltage range Differential full scale input voltage VID = VI,A+ - VI,ASD24GAINx = 1 SD24GAINx = 2 SD24GAINx = 4 VID Differential input voltage for specified performance (2) SD24GAINx = 8 SD24REFS = 1 SD24GAINx = 16 SD24GAINx = 32 SD24GAINx = 64 SD24GAINx = 128 CREF (1) (2) (3) VREF load capacitance
(3)
TYP
MAX 3.6 2.3 AVCC AVCC +VREF/GAIN
UNIT V MHz V V
AVCC = DVCC, AVSS = DVSS = 0 V
2.4 0.03 AVSS - 1V AVSS - 1V -VREF/GAIN 910 455 227 113 57 28 14 7 920 460 230 115 58 29 14.5 7.2 100
mV
SD24REFS = 1
nF
Modulator clock frequency: MIN = 32.768 kHz - 10% 30 kHz. MAX = 32.768 kHz 64 + 10% 2.3 MHz The full-scale range (FSR) is defined by VFS+ = +VREF/GAIN and VFS-= -VREF/GAIN: FSR = VFS+ - VFS-= 2*VREF/GAIN. If VREF is sourced externally, the analog input range should not exceed 80% of VFS+ or VFS-; i.e., VID = 0.8 VFS- to 0.8 VFS+. If VREF is sourced internally, the given VID ranges apply. There is no capacitance required on VREF. However, a capacitance of 100nF is recommended to reduce any reference voltage noise.
(1)
SD24_B, Analog Input

PARAMETER
TEST CONDITIONS SD24GAINx = 1 SD24GAINx = 2 SD24GAINx = 4 SD24GAINx = 8 SD24GAINx = 16 SD24GAINx = 32, 64, 128 SD24GAINx = 1
VCC
MIN
TYP 5 5 5 5 5 5
MAX
UNIT
CI
Input capacitance
pF
3V 3V 3V 3V 3V 3V 300 300
200 200 200 400 400 400 k k
ZI
Input impedance (Pin A+ or A- to AVSS)
fSD24 = 1MHz
SD24GAINx = 8 SD24GAINx = 32 SD24GAINx = 1
ZID
Differential input impedance (Pin A+ to pin A-)
fSD24 = 1MHz
SD24GAINx = 8 SD24GAINx = 32
(1)
All parameters pertain to each SD24_B converter.
71
1600 1400
Input Leakage Current nA
1200 1000 800 600 400 200 0 -200 -1 -0.5 0 0.5 1 Input Voltage V 1.5 2 2.5 3
Figure 18. Input Leakage Current vs Input Voltage (Modulator OFF)
SD24_B, Supply Currents

PARAMETER TEST CONDITIONS SD24GAIN: 1 SD24GAIN: 2 SD24GAIN: 4 ISD,256 Analog plus digital supply current per converter (reference not included) fSD24 = 1 MHz, SD24OSR = 256 SD24GAIN: 8 SD24GAIN: 16 SD24GAIN: 32 SD24GAIN: 64 SD24GAIN: 128 SD24GAIN: 1 ISD,512 Analog plus digital supply current per converter (reference not included) fSD24 = 2 MHz, SD24OSR = 512 SD24GAIN: 8 SD24GAIN: 32 VCC 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V MIN TYP 600 600 600 700 700 775 775 775 750 825 900 MAX 675 675 675 750 750 850 850 850 800 900 1000 A A UNIT
SD24_B, Performance
fSD24 = 1 MHz, SD24OSRx = 256, SD24REFS = 1
PARAMETER INL TEST CONDITIONS VCC 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V MIN -0.01 -0.01 -0.01 1 2 4 8 16 31.7 63.4 126.8 TYP MAX 0.01 0.01 0.01 % of FSR UNIT SD24GAIN: 1 Integral nonlinearity, endSD24GAIN: 8 point fit SD24GAIN: 32 SD24GAIN: 1 SD24GAIN: 2 SD24GAIN: 4 Gnom Nominal gain SD24GAIN: 8 SD24GAIN: 16 SD24GAIN: 32 SD24GAIN: 64 SD24GAIN: 128
72
SD24_B, Performance (continued)

PARAMETER EG Gain error (1) Gain error temperature coefficient (2), internal reference Gain error vs VCC
(3)
TEST CONDITIONS SD24GAIN: 1, with external reference (1.2 V) SD24GAIN: 8, with external reference (1.2 V) SD24GAIN: 32, with external reference (1.2 V)
VCC 3V 3V 3V 3V
MIN -1 -2 -2
TYP
MAX +1 +2 +2
UNIT %
EG/T
SD24GAIN: 1/8/32 (with internal reference) SD24GAIN: 1
50 ppm/C 0.15 0.15 0.4 %/V 2.3 0.73 0.18 -0.2 -0.5 -0.5 1 0.15 0.1 600 100 50 uV/V uV/C 0.2 0.5 0.5 % FS mV
EG/VCC
SD24GAIN: 8 SD24GAIN: 32 SD24GAIN: 1 (with Vdiff = 0V) 3V 3V 3V 3V 3V 3V 3V 3V 3V
EOS[V]
Offset error (4)
SD24GAIN: 8 SD24GAIN: 32 SD24GAIN: 1 (with Vdiff = 0V)
EOS[FS]
Offset error (4)
SD24GAIN: 8 SD24GAIN: 32 SD24GAIN: 1
EOS/T
Offset error temperature coefficient (5)
SD24GAIN: 8 SD24GAIN: 32 SD24GAIN: 1
EOS/VCC
Offset error vs VCC
(6)
SD24GAIN: 8 SD24GAIN: 32 SD24GAIN: 1 3V 3V 3V
-110 -110 -110 dB
CMRR,DC
Common mode rejection at DC (7)
SD24GAIN: 8 SD24GAIN: 32
(1) (2)
(3)
(4) (5)
(6)
(7)
The gain error EG specifies the deviation of the actual gain Gact from the nominal gain Gnom: EG = (Gact - Gnom)/Gnom. It covers process, temperature and supply voltage variations. The gain error temperature coefficient EG/ T specifies the variation of the gain error EG over temperature (EG(T) = (Gact(T) Gnom)/Gnom) using the box method (i.e. min. and max. values): EG/ T = (MAX(EG(T)) - MIN(EG(T) ) / (MAX(T) - MIN(T)) = (MAX(Gact(T)) - MIN(Gact(T)) / Gnom / (MAX(T) - MIN(T)) with T ranging from -40C to +85C. The gain error vs VCC coefficient EG/ VCC specifies the variation of the gain error EG over supply voltage (EG(VCC) = (Gact(VCC) Gnom)/Gnom) using the box method (i.e. min. and max. values): EG/ VCC = (MAX(EG(VCC)) - MIN(EG(VCC) ) / (MAX(VCC) - MIN(VCC)) = (MAX(Gact(VCC)) - MIN(Gact(VCC)) / Gnom / (MAX(VCC) MIN(VCC)) with VCC ranging from 2.4V to 3.6V. The offset error EOS is measured with shorted inputs in 2's complement mode with +100% FS = VREF/G and -100% FS = -VREF/G. Conversion between EOS [FS] and EOS [V] is as follows: EOS [FS] = EOS [V]G/VREF; EOS [V] = EOS [FS]VREF/G. The offset error temperature coefficient EOS/ T specifies the variation of the offset error EOS over temperature using the box method (i.e. min. and max. values): EOS/ T = (MAX(EOS(T)) - MIN(EOS(T) ) / (MAX(T) - MIN(T)) with T ranging from -40C to +85C. The offset error vs VCC EOS/ VCC specifies the variation of the offset error EOS over supply voltage using the box method (i.e. min. and max. values): EOS/ VCC = (MAX(EOS(VCC)) - MIN(EOS(VCC) ) / (MAX(VCC) - MIN(VCC)) with VCC ranging from 2.4V to 3.6V. The DC CMRR specifies the change in the measured differential input voltage value when the common mode voltage varies: DC CMRR = -20log(MAX/FSR) with MAX being the difference between the minium value and the maximum value measured when sweeping the common mode voltage (for example, calculating with 16-bits FSR = 65536 a maximum change by 1 LSB results in 20log(1/65536) -96 dB) . The DC CMRR is measured with both inputs connected to the common mode voltage (i.e. no differential input signal is applied), and the common mode voltage is swept from -1V to VCC. Submit Documentation Feedback 73
SD24_B, Performance (continued)

PARAMETER CMRR,50Hz Common mode rejection at 50 Hz (8) TEST CONDITIONS SD24GAIN: 1, fCM = 50 Hz, VCM = 930 mV SD24GAIN: 8, fCM = 50 Hz, VCM = 120 mV SD24GAIN: 32, fCM = 50 Hz, VCM = 30 mV SD24GAIN: 1, VCC = 3 V + 50 mV sin(2 fVcc t), fVcc = 50 Hz AC PSRR,ext AC power supply rejection ratio, external reference (9) SD24GAIN: 8, VCC = 3 V + 50 mV sin(2 fVcc t), fVcc = 50 Hz SD24GAIN: 32, VCC = 3 V + 50 mV sin(2 fVcc t), fVcc = 50 Hz SD24GAIN: 1, VCC = 3 V + 50 mV sin(2 fVcc t), fVcc = 50 Hz AC PSRR,int AC power supply rejection ratio, internal reference (9) SD24GAIN: 8, VVCC = 3 V + 50 mV sin(2 fVcc t), fVcc = 50 Hz SD24GAIN: 32, VCC = 3 V + 50 mV sin(2 fVcc t), fVcc = 50 Hz Crosstalk source: SD24GAIN: 1, Sine-wave with max. possible Vpp. fIN = 50 Hz, 100 Hz, Converter under test: SD24GAIN: 1 XT Crosstalk between converters (10) Crosstalk source: SD24GAIN: 1, Sine-wave with max. possible Vpp. fIN = 50 Hz, 100 Hz, Converter under test: SD24GAIN: 8 Crosstalk source: SD24GAIN: 1, Sine-wave with max. possible Vpp. fIN = 50 Hz, 100 Hz, Converter under test: SD24GAIN: 32 (8) 3V VCC 3V 3V 3V MIN TYP -110 -110 -110 -61 -77 -79 -61 -77 -79 -120 dB dB dB MAX UNIT
3V
-115
dB
3V
-100
The AC CMRR is the difference between a hypothetical signal with the amplitude and frequency of the applied common mode ripple applied to the inputs of the ADC and the actual common mode signal spur visible in the FFT spectrum: AC CMRR = Error Spur [dBFS] - 20log(VCM/1.2V/G) [dBFS] with a common mode signal of VCM sin(2 fCM t) applied to the analog inputs. The AC CMRR is measured with the both inputs connected to the common mode signal i.e. no differential input signal is applied. With the specified typical values the error spur is within the noise floor (as specified by the SINAD values). (9) The AC PSRR is the difference between a hypothetical signal with the amplitude and frequency of the applied supply voltage ripple applied to the inputs of the ADC and the actual supply ripple spur visible in the FFT spectrum: AC PSRR = Error Spur [dBFS] - 20log(50 mV / 1.2 V / G) [dBFS] with a signal of 50 mV sin(2 fVcc t) added to VCC. The AC PSRR is measured with the inputs grounded; that is, no analog input signal is applied. With the specified typical values the error spur is within the noise floor (as specified by the SINAD values). SD24GAIN: 1 Hypothetical signal: 20log(50 mV / 1.2 V / 1) = -27.6 dBFS SD24GAIN: 8 Hypothetical signal: 20log(50 mV / 1.2 V / 8) = -9.5 dBFS SD24GAIN: 32 Hypothetical signal: 20log(50 mV / 1.2 V / 32) = 2.5 dBFS (10) The crosstalk XT is specified as the tone level of the signal applied to the crosstalk source seen in the spectrum of the converter under test. It is measured with the inputs of the converter under test being grounded.
74
SD24_B, AC Performance
fSD24 = 1MHz, SD24OSRx = 256, SD24REFS = 1
PARAMETER SD24GAIN: 1 SD24GAIN: 2 SD24GAIN: 4 SINAD Signal-to-noise + distortion ratio SD24GAIN: 8 SD24GAIN: 16 SD24GAIN: 32 SD24GAIN: 64 SD24GAIN: 128 SD24GAIN: 1 THD Total Harmonic distiortion SD24GAIN: 8 SD24GAIN: 32 (1) fIN = 50Hz (1) fIN = 50Hz (1) TEST CONDITIONS VCC 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 73 82 MIN 85 TYP 87 86 85 84 80 74 68 62 100 90 80 dB dB MAX UNIT
The following voltages were applied to the SD24_B inputs: VI,A+(t) = 0 V + VPP/2 sin(2 fIN t) VI,A-(t) = 0 V - VPP/2 sin(2 fIN t) resulting in a differential voltage of VID = VI,A+(t) - VI,A-(t) = VPP sin(2 fIN t) with VPP being selected as the maximum value allowed for a given range (according to SD24_B recommended operating conditions).
fSD24 = 2MHz, SD24OSRx = 512, SD24REFS = 1
PARAMETER SD24GAIN: 1 SD24GAIN: 2 SD24GAIN: 4 SINAD Signal-to-noise + distortion ratio SD24GAIN: 8 SD24GAIN: 16 SD24GAIN: 32 SD24GAIN: 64 SD24GAIN: 128 (1) fIN = 50Hz (1) TEST CONDITIONS VCC 3V 3V 3V 3V 3V 3V 3V 3V MIN TYP 87 86 85 84 81 76 71 65 dB MAX UNIT
75
fSD24 = 32 kHz, SD24OSRx = 512, SD24REFS = 1
PARAMETER SD24GAIN: 1 SD24GAIN: 2 SD24GAIN: 4 SINAD Signal-to-noise + distortion ratio SD24GAIN: 8 SD24GAIN: 16 SD24GAIN: 32 SD24GAIN: 64 SD24GAIN: 128 (1) fIN = 12Hz (1) TEST CONDITIONS VCC 3V 3V 3V 3V 3V 3V 3V 3V MIN TYP 89 85 84 86 80 76 67 61 dB MAX UNIT
95 90 85
SINAD dB
80 75 70 65 60 55 32 64 128 SD24OSRx 256 512 1024
Figure 19. SINAD vs OSR (fSD24 = 1 MHz, SD24REFS = 1, SD24GAIN = 1)
76
90
85
80
SINAD dB
75
70
65
60 0.1
0.2
0.3
0.4
0.5 0.6 Vpp/Vref/Gain
0.7
0.8
0.9
Figure 20. SINAD vs VPP
SD24_B, External Reference Input

ensure correct input voltage range according to VREF
PARAMETER VREF(I) Input voltage IREF(I) Input current TEST CONDITIONS SD24REFS = 0 SD24REFS = 0 VCC 3V 3V MIN 1.0 TYP 1.20 MAX 1.5 50 UNIT V nA
10-Bit ADC, Power Supply and Input Range Conditions

PARAMETER AVCC V(Ax) Analog supply voltage Analog input voltage range (1) Operating supply current into AVCC terminal, REF module and reference buffer off Operating supply current into AVCC terminal, REF module on, reference buffer on Operating supply current into AVCC terminal, REF module off, reference buffer on Operating supply current into AVCC terminal, REF module off, reference buffer off CI Input capacitance TEST CONDITIONS AVCC and DVCC are connected together, AVSS and DVSS are connected together, V(AVSS) = V(DVSS) = 0 V All ADC10_A pins fADC10CLK = 5 MHz, ADC10ON =1, REFON = 0, SHT0 = 0, SHT1 = 0, ADC10DIV = 0, ADC10SREF = 00 fADC10CLK = 5 MHz, ADC10ON = 1, REFON = 1, SHT0 = 0, SHT1 = 0, ADC10DIV = 0, ADC10SREF = 01 fADC10CLK = 5 MHz, ADC10ON = 1, REFON = 0, SHT0 = 0, SHT1 = 0, ADC10DIV = 0, ADC10SREF = 10, VEREF = 2.5 V fADC10CLK = 5 MHz, ADC10ON = 1, REFON = 0, SHT0 = 0, SHT1 = 0, ADC10DIV = 0, ADC10SREF = 11, VEREF = 2.5 V Only one terminal Ax can be selected at one time from the pad to the ADC10_A capacitor array including wiring and pad. AVCC > 2 V, 0 V VAx AVCC 1.8 V < AVCC < 2 V, 0 V VAx AVCC 2.2 V 3V 3V VCC MIN 1.8 0 70 80 130 TYP MAX 3.6 AVCC 105 115 185 A UNIT V V
IADC10_A
3V
108
160
3V
74
105
2.2 V
3.5 36 96
pF
RI (1)
Input MUX ON resistance
The analog input voltage range must be within the selected reference voltage range VR+ to VR for valid conversion results. The external reference voltage requires decoupling capacitors. Two decoupling capacitors, 10 F and 100 nF, should be connected to VREF to decouple the dynamic current required for an external reference source if it is used for the ADC10_A. Also see the MSP430x5xx and MSP430x6xx Family User's Guide (SLAU208). Submit Documentation Feedback 77
10-Bit ADC, Timing Parameters

PARAMETER fADC10CLK fADC10OSC Internal ADC10_A oscillator (1) TEST CONDITIONS For specified performance of ADC10_A linearity parameters ADC10DIV = 0, fADC10CLK = fADC10OSC REFON = 0, Internal oscillator, 12 ADC10CLK cycles, 10-bit mode fADC10OSC = 4 MHz to 5 MHz External fADC10CLK from ACLK, MCLK or SMCLK, ADC10SSEL 0 tADC10ON tSample (1) (2) (3) (4) Turn on settling time of the ADC Sampling time See
(3)
VCC 2.2 V, 3 V 2.2 V, 3 V 2.2 V, 3 V
MIN 0.45 4.4 2.4
TYP 5 5.0
MAX 5.5 5.6 3.0
UNIT MHz MHz
tCONVERT
Conversion time
s
(2)
100 1.8 V 3V 3 1
ns s s
RS = 1000 , RI = 96 k, CI = 3.5 pF (4) RS = 1000 , RI = 36 k, CI = 3.5 pF (4)
The ADC10OSC is sourced directly from MODOSC inside the UCS. 12 ADC10DIV 1/fADC10CLK The condition is that the error in a conversion started after tADC10ON is less than 0.5 LSB. The reference and input signal are already settled. Approximately eight Tau (t) are needed to get an error of less than 0.5 LSB
78
10-Bit ADC, Linearity Parameters

PARAMETER EI ED EO EG ET Integral linearity error Differential linearity error Offset error Gain error Total unadjusted error TEST CONDITIONS 1.4 V (VeREF+ VeREF)min 1.6 V 1.6 V < (VeREF+ VeREF)min VAVCC (VeREF+ VeREF)min (VeREF+ VeREF), CVeREF+ = 20 pF (VeREF+ VeREF)min (VeREF+ VeREF), Internal impedance of source RS < 100 , CVREF+ = 20 pF (VeREF+ VeREF)min (VeREF+ VeREF), CVeREF+ = 20 pF (VeREF+ VeREF)min (VeREF+ VeREF), CVeREF+ = 20 pF VCC 2.2 V, 3 V 2.2 V, 3 V 2.2 V, 3 V 2.2 V, 3 V 2.2 V, 3 V 1.0 MIN TYP MAX 1.0 1.0 1.0 1.0 1.0 2.0 UNIT LSB LSB LSB LSB LSB
10-Bit ADC, External Reference

PARAMETER VeREF+ VeREF (VeREF+ VeREF) Positive external reference voltage input Negative external reference voltage input Differential external reference voltage input TEST CONDITIONS VeREF+ > VeREF VeREF+ > VeREF VeREF+ > VeREF
(2)
VCC
MIN 1.4 0 1.4
TYP
MAX AVCC 1.2 AVCC
UNIT V V V
(3)
(4)
IVeREF+ IVeREF
Static input current
1.4 V VeREF+ VAVCC , VeREF = 0 V, fADC10CLK = 5 MHz, ADC10SHTx = 0x0001, Conversion rate 200 ksps 1.4 V VeREF+ VAVCC , VeREF = 0 V, fADC10CLK = 5 MHz, ADC10SHTX = 0x1000, Conversion rate 20 ksps See
(5)
2.2 V, 3 V
8.5
26
2.2 V, 3 V
CVeREF+/(1) (2) (3) (4) (5)
Capacitance at VeREF+/- terminal
10
The external reference is used during ADC conversion to charge and discharge the capacitance array. The input capacitance, CI, is also the dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the recommendations on analog-source impedance to allow the charge to settle for 12-bit accuracy. The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced accuracy requirements. The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced accuracy requirements. The accuracy limits minimum external differential reference voltage. Lower differential reference voltage levels may be applied with reduced accuracy requirements. Two decoupling capacitors, 10 F and 100 nF, should be connected to VeREF to decouple the dynamic current required for an external reference source if it is used for the ADC10_A. Also see the MSP430x5xx and MSP430x6xx Family User's Guide (SLAU208).
79
REF, Built-In Reference

PARAMETER VREF+ Positive built-in reference voltage AVCC minimum voltage, Positive built-in reference active TEST CONDITIONS REFVSEL = {2} for 2.5 V, REFON = 1 REFVSEL = {1} for 2.0 V, REFON = 1 REFVSEL = {0} for 1.5 V, REFON = 1 REFVSEL = {0} for 1.5 V REFVSEL = {1} for 2.0 V REFVSEL = {2} for 2.5 V fADC10CLK = 5 MHz, REFON = 1, REFBURST = 0, REFVSEL = {2} for 2.5 V IREF+ Operating supply current into AVCC terminal (1) fADC10CLK = 5 MHz, REFON = 1, REFBURST = 0, REFVSEL = {1} for 2.0 V fADC10CLK = 5 MHz, REFON = 1, REFBURST = 0, REFVSEL = {0} for 1.5 V TCREF+ ISENSOR VSENSOR VMID tSENSOR(sample) tVMID(sample) PSRR_DC Temperature coefficient of built-in reference (2) Operating supply current into AVCC terminal See
(3)
VCC 3V 3V 2.2 V, 3 V
MIN 2.47 1.95 1.46 1.8 2.2 2.7
TYP 2.51 1.99 1.50
MAX 2.55 2.03 1.54
UNIT V
AVCC(min)
3V
23
30
3V
21
27
3V
19
25
A ppm/ C A mV
REFVSEL = {0, 1, 2}, REFON = 1 REFON = 1, ADC10ON = 1, INCH = 0Ah, TA = 30C REFON = 1, ADC10ON = 1, INCH = 0Ah, TA = 30C ADC10ON = 1, INCH = 0Bh, VMID is ~0.5 VAVCC REFON = 1, ADC10ON = 1, INCH = 0Ah, Error of conversion result 1 LSB ADC10ON = 1, INCH = 0Bh, Error of conversion result 1 LSB AVCC = AVCC (min) - AVCC(max) TA = 25 C REFVSEL = {0, 1, 2}, REFON = 1 AVCC = AVCC (min) - AVCC(max) TA = 25 C f = 1 kHz, Vpp = 100 mV REFVSEL = {0, 1, 2}, REFON = 1 AVCC = AVCC (min) - AVCC(max) REFVSEL = {0, 1, 2}, REFON = 0 1 SD24REFS = 1 SD24REFS = 0->1, CREF = 100 nF 3V 3V 1.137 2.2 V 3V 2.2 V 3V 2.2 V 3V 1.08 1.48 30 1
10 145 170 780 780 1.1 1.5
50 220 245
AVCC divider at channel 11 Sample time required if channel 10 is selected (4) Sample time required if channel 11 is selected (5) Power supply rejection ratio (dc)
1.12 1.52
V s s
120
300
V/V
PSRR_AC
Power supply rejection ratio (ac) Settling time of reference voltage (6) SD24_B internal reference voltage SD24_B internal reference turn-on time (7)
mV/V
tSETTLE VSD24REF tON (1) (2) (3) (4) (5) (6) (7)
75 1.151 200 1.165
s V s
The internal reference current is supplied via terminal AVCC. Consumption is independent of the ADC10ON control bit, unless a conversion is active. The REFON bit enables to settle the built-in reference before starting an A/D conversion. Calculated using the box method: (MAX(-40 to 85C) MIN(-40 to 85C)) / MIN(-40 to 85C)/(85C (40C)). The temperature sensor offset can be as much as 20C. A single-point calibration is recommended to minimize the offset error of the built-in temperature sensor. The typical equivalent impedance of the sensor is 51 k. The sample time required includes the sensor-on time tSENSOR(on). The on-time tVMID(on) is included in the sampling time tVMID(sample); no additional on time is needed. The condition is that the error in a conversion started after tREFON is 1 LSB. The condition is that SD24_B conversion started after tON should guarantee specified SINAD values for the selected Gain, OSR and fSD24.
80
Flash Memory
PARAMETER DVCC(PGM/ERASE) Program and erase supply voltage IPGM IERASE IMERASE, IBANK tCPT tRetention tWord tBlock, tBlock, tBlock, tErase fMCLK,MGR (1) (2)
0 1(N1) N
TEST CONDITIONS
MIN 1.8
TYP
MAX 3.6
UNIT V mA mA mA ms cycles years
Average supply current from DVCC during program Average supply current from DVCC during erase Average supply current from DVCC during mass erase or bank erase Cumulative program time Program/erase endurance Data retention duration Word or byte program time Block program time for first byte or word Block program time for each additional byte or word, except for last byte or word Block program time for last byte or word Erase time for segment erase, mass erase, and bank erase when available MCLK frequency in marginal read mode (FCTL4.MGR0 = 1 or FCTL4. MGR1 = 1) TJ = 25C See See See See See
(2) (2) (2) (2) (2)
5 8 5
See
(1)
16 104 100 64 49 37 55 23 0 85 65 49 73 32 1 105
s s s s ms MHz
The cumulative program time must not be exceeded when writing to a 128-byte flash block. This parameter applies to all programming methods: individual word- or byte-write and block-write modes. These values are hardwired into the flash controller's state machine.
JTAG and Spy-Bi-Wire Interface

PARAMETER fSBW tSBW,Low tSBW,
En
TEST CONDITIONS 2.2 V, 3 V 2.2 V, 3 V 2.2 V, 3 V
MIN 0 0.025
TYP
MAX 20 15 1
UNIT MHz s s s MHz k
Spy-Bi-Wire input frequency Spy-Bi-Wire low clock pulse length Spy-Bi-Wire enable time (TEST high to acceptance of first clock edge) (1) Spy-Bi-Wire return to normal operation time TCK input frequency for 4-wire JTAG (2) Internal pulldown resistance on TEST
tSBW,Rst fTCK Rinternal (1) (2)
15 2.2 V 3V 2.2 V, 3 V 0 0 45 60
100 5 10 80
Tools accessing the Spy-Bi-Wire interface need to wait for the minimum tSBW,En time after pulling the TEST/SBWTCK pin high before applying the first SBWTCK clock edge. fTCK may be restricted to meet the timing requirements of the module selected.
81
INPUT/OUTPUT SCHEMATICS Port P1, P1.0 and P1.1, Input/Output With Schmitt Trigger (MSP430F67xxIPZ and MSP430F67xxIPN)
Pad Logic to/from Reference
To ADC10_A INCHx = y
P1REN.x P1MAP.x = PMAP_ANALOG DVSS DVCC P1DIR.x from Port Mapping 0 1 Direction 0: Input 1: Output 0 1 1
P1OUT.x from Port Mapping P1SEL.x P1IN.x
0 1 P1DS.x 0: Low drive 1: High drive P1.0/PM_TA0.0/VeREF-/A2 P1.1/PM_TA0.1/VeREF+/A1
EN to Port Mapping D P1IE.x P1IRQ.x P1IFG.x EN Q Set
Bus Keeper
P1SEL.x P1IES.x
Interrupt Edge Select
Table 63. Port P1 (P1.0 and P1.1) Pin Functions (MSP430F67xxIPZ and MSP430F67xxIPN)
PIN NAME (P1.x) P1.0/PM_TA0.0/ VeREF-/A2 x 0 P1.0 (I/O) TA0.CCI0A TA0.TA0 VeREF-/A2 (2) P1.1/PM_TA0.1/ VeREF+/A1 1 P1.1 (I/O) TA0.CCI1A TA0.TA1 VeREF+/A1 (2) (1) (2) FUNCTION CONTROL BITS/SIGNALS (1) P1DIR.x I: 0; O: 1 0 1 X I: 0; O: 1 0 1 X P1SEL.x 0 1 1 1 0 1 1 1 P1MAPx X default default = 31 X default default = 31
X = Don't care Setting P1SEL.x bit together with P1MAPx = PM_ANALOG disables the output driver as well as the input Schmitt trigger.
82
Port P1, P1.2, Input/Output With Schmitt Trigger (MSP430F67xxIPZ and MSP430F67xxIPN)
Pad Logic To ADC10_A INCHx = y
0 1 P1DS.x 0: Low drive 1: High drive P1.2/PM_UCA0RXD/PM_UCA0SOMI/A0
EN to Port Mapping D P1IE.x P1IRQ.x P1IFG.x EN Q Set
Bus Keeper
P1SEL.x P1IES.x
Table 64. Port P1 (P1.2) Pin Functions (MSP430F67xxIPZ and MSP430F67xxIPN)

PIN NAME (P1.x) P1.2/PM_UCA0RXD/ PM_UCA0SOMI/A0 x 2 P1.2 (I/O) UCA0RXD/UCA0SOMI A0 (2) (1) (2) FUNCTION CONTROL BITS/SIGNALS (1) P1DIR.x I: 0; O: 1 X X P1SEL.x 0 1 1 P1MAPx X default = 31
83
Port P1, P1.3 to P1.5, Input/Output With Schmitt Trigger (MSP430F67xxIPZ and MSP430F67xxIPN)
to LCD_C
Pad Logic P1REN.x P1MAP.x = PMAP_ANALOG
DVSS DVCC
0 1 1
P1DIR.x from Port Mapping
0 1
Direction 0: Input 1: Output
0 1 P1DS.x 0: Low drive 1: High drive P1.3/PM_UCA0TXD/PM_UCA0SIMO/R03 P1.4/PM_UCA1RXD/PM_UCA1SOMI/LCDREF/R13 P1.5/PM_UCA1TXD/PM_UCA1SIMO/R23
EN to Port Mapping D
Bus Keeper
P1IE.x P1IRQ.x P1IFG.x EN Q Set
P1SEL.x P1IES.x
Table 65. Port P1 (P1.3 to P1.5) Pin Functions (MSP430F67xxIPZ and MSP430F67xxIPN)
PIN NAME (P1.x) P1.3/PM_UCA0TXD/ PM_UCA0SIMO/R03 x 3 P1.3 (I/O) UCA0TXD/UCA0SIMO R03 (2) P1.4/PM_UCA1RXD/ PM_UCA1SOMI/ LCDREF/R13 P1.5/PM_UCA1TXD/ PM_UCA1SIMO/R23 4 P1.4 (I/O) UCA1RXD/UCA1SOMI LCDREF/R13 (2) 5 P1.5 (I/O) UCA1TXD/UCA1SIMO R23 (2) (1) (2) FUNCTION CONTROL BITS/SIGNALS (1) P1DIR.x I: 0; O: 1 X X I: 0; O: 1 X X I: 0; O: 1 X X P1SEL.x 0 1 1 0 1 1 0 1 1 P1MAPx X default = 31 X default = 31 X default = 31
84
Port P1, P1.6 and P1.7 (MSP430F67xxIPZ and MSP430F67xxIPN), Port P2, P2.0 and P2.1 (MSP430F67xxIPZ Only) Input/Output With Schmitt Trigger
COM4 to COM7 from LCD_C Pad Logic
PyREN.x PyMAP.x = PMAP_ANALOG DVSS DVCC PyDIR.x from Port Mapping 0 1 Direction 0: Input 1: Output 0 1 1
PyOUT.x from Port Mapping PySEL.x PyIN.x
0 1 PyDS.x 0: Low drive 1: High drive P1.6/PM_UCA0CLK/COM4 P1.7/PM_UCB0CLK/COM5 P2.0/PM_UCB0SOMI/PM_UCB0SCL/COM6 P2.1/PM_UCB0SIMO/PM_UCB0SDA/COM7
Bus Keeper
PyIE.x PyIRQ.x PyIFG.x EN Q Set
PySEL.x PyIES.x
85
Table 66. Port P1 (P1.6 and P1.7) Pin Functions (MSP430F67xxIPZ and MSP430F67xxIPN)
CONTROL BITS/SIGNALS (1) PIN NAME (P1.x) P1.6/PM_UCA0CLK/COM4 x 6 P1.6 (I/O) UCA0CLK Output driver and input Schmitt trigger disabled COM4 P1.7/PM_UCB0CLK/COM5 7 P1.7 (I/O) UCB0CLK Output driver and input Schmitt trigger disabled COM5 (1) X = Don't care FUNCTION P1DIR.x I: 0; O: 1 X X X I: 0; O: 1 X X X P1SEL.x 0 1 1 X 0 1 1 X P1MAPx X default = 31 X X default = 31 X COM4,5 Enable Signal 0 0 0 1 0 0 0 1
Table 67. Port P2 (P2.0 and P2.1) Pin Functions (MSP430F67xxIPZ Only)
CONTROL BITS/SIGNALS (1) PIN NAME (P2.x) P2.0/PM_UCB0SOMI/ PM_UCB0SCL/COM6 x 0 P2.0 (I/O) UCB0SOMI/UCB0SCL Output driver and input Schmitt trigger disabled COM6 P2.1/PM_UCB0SIMO/ PM_UCB0SDA/COM7 1 P2.1 (I/O) UCB0SIMO/UCB0SDA Output driver and input Schmitt trigger disabled COM7 (1) X = Don't care FUNCTION P2DIR.x I: 0; O: 1 X X X I: 0; O: 1 X X X P2SEL.x 0 1 1 X 0 1 1 X P2MAPx X default = 31 X X default = 31 X COM6,7 Enable Signal 0 0 0 1 0 0 0 1
86
Port P2, P2.2 to P2.7, Input/Output With Schmitt Trigger (MSP430F67xxIPZ Only)
DVSS DVCC
0 1 1
0 1
0 1 P2DS.x 0: Low drive 1: High drive P2.2/PM_UCA2RXD/PM_UCA2SOMI P2.3/PM_UCA2TXD/PM_UCA2SIMO P2.4/PM_UCA1CLK P2.5/PM_UCA2CLK P2.6/PM_TA1.0 P2.7/PM_TA1.1
Bus Keeper
P2SEL.x P2IES.x
87
Table 68. Port P2 (P2.2 to P2.7) Pin Functions (MSP430F67xxIPZ Only)

PIN NAME (P2.x) P2.2/PM_UCA2RXD/ PM_UCA2SOMI x 2 P2.2 (I/O) UCA2RXD/UCA2SOMI Output driver and input Schmitt trigger disabled P2.3/PM_UCA2TXD/ PM_UCA2SIMO 3 P2.3 (I/O) UCA2TXD/UCA2SIMO Output driver and input Schmitt trigger disabled P2.4/PM_UCA1CLK 4 P2.4 (I/O) UCA1CLK Output driver and input Schmitt trigger disabled P2.5/PM_UCA2CLK 5 P2.5 (I/O) UCA2CLK Output driver and input Schmitt trigger disabled P2.6/PM_TA1.0 6 P2.6 (I/O) TA1.CC10A TA1.TA0 Output driver and input Schmitt trigger disabled P2.7/PM_TA1.1 7 P2.7 (I/O) TA1.CCI1A TA1.TA1 Output driver and input Schmitt trigger disabled (1) X = Don't care FUNCTION CONTROL BITS/SIGNALS (1) P2DIR.x I: 0; O: 1 X X I: 0; O: 1 X X I: 0; O: 1 X X I: 0; O: 1 X X I: 0; O: 1 0 1 X I: 0; O: 1 0 1 X P2SEL.x 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 1 0 1 1 1 P2MAPx X default = 31 X default = 31 X default = 31 X default = 31 X default default = 31 X default default = 31
88
DVSS DVCC
0 1 1
0 1
0 1 P3DS.x 0: Low drive 1: High drive P3.0/PM_TA2.0 P3.1/PM_TA2.1 P3.2/PM_TACLK/PM_RTCCLK P3.3/PM_TA0.2
Bus Keeper

PIN NAME (P3.x) P3.0/PM_TA2.0 x 0 P3.0 (I/O) TA2.CC10A TA2.TA0 Output driver and input Schmitt trigger disabled P3.1/PM_TA2.1 1 P3.1 (I/O) TA2.CCI1A TA2.TA1 Output driver and input Schmitt trigger disabled P3.2/PM_TACLK/ PM_RTCCLK 2 P3.2 (I/O) TACLK RTCCLK Output driver and input Schmitt trigger disabled P3.3/PM_TA0.2 3 P3.3 (I/O) TA0.CCI2A TA0.TA2 Output driver and input Schmitt trigger disabled (1) X = Don't care FUNCTION CONTROL BITS/SIGNALS (1) P3DIR.x I: 0; O: 1 0 1 X I: 0; O: 1 0 1 X I: 0; O: 1 0 1 X I: 0; O: 1 0 1 X P3SEL.x 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 P3MAPx X default default = 31 X default default = 31 X default default = 31 X default default = 31
89
Port P3, P3.4 to P3.7 , Input/Output With Schmitt Trigger (MSP430F67xxIPZ Only)
S39 to S37 LCDS39 to LCDS37 Pad Logic
0 1 P3DS.x 0: Low drive 1: High drive P3.4/PM_SDCLK/S39 P3.5/PM_SD0DIO/S38 P3.6/PM_SD1DIO/S37 P3.7/PM_SD2DIO/S36
Bus Keeper

PIN NAME (P3.x) P3.4/PM_SDCLK/S39 x 4 P3.4 (I/O) SDCLK Output driver and input Schmitt trigger disabled S39 P3.5/PM_SD0DIO/S38 5 P3.5 (I/O) SD0DIO Output driver and input Schmitt trigger disabled S38 P3.6/PM_SD1DIO/S37 6 P3.6 (I/O) SD1DIO Output driver and input Schmitt trigger disabled S37 P3.7/PM_SD2DIO/S36 7 P3.7 (I/O) SD2DIO Output driver and input Schmitt trigger disabled S36 (1) X = Don't care FUNCTION CONTROL BITS/SIGNALS (1) P3DIR.x I: 0; O: 1 X X X I: 0; O: 1 X X X I: 0; O: 1 X X X I: 0; O: 1 X X X P3SEL.x 0 1 1 X 0 1 1 X 0 1 1 X 0 1 1 X P3MAPx X default = 31 X X default = 31 X X default = 31 X X default = 31 X LCDS39...36 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1
90
Port P4, Port P5, Port P6, Port P7, Port P8, P8.0 to P8.3 Input/Output With Schmitt Trigger (MSP430F67xxIPZ Only)
Sz LCDSz Pad Logic
PyREN.x DVSS DVCC PyDIR.x 0 1 Direction 0: Input 1: Output 0 1 1
PyOUT.x DVSS PySEL.x PyIN.x
0 1 PyDS.x 0: Low drive 1: High drive Py.x/Sz
EN Not Used D
Bus Keeper
91

PIN NAME (P4.x) P4.0/S35 x 0 P4.0 (I/O) N/A DVSS S35 P4.1/S34 1 P4.1 (I/O) N/A DVSS S34 P4.2/S33 2 P4.2 (I/O) N/A DVSS S33 P4.3/S32 3 P4.3 (I/O) N/A DVSS S32 P4.4/S31 4 P4.4 (I/O) N/A DVSS S31 P4.5/S30 5 P4.5 (I/O) N/A DVSS S30 P4.6/S29 6 P4.6 (I/O) N/A DVSS S29 P4.7/S28 7 P4.7 (I/O) N/A DVSS S28 (1) X = Don't care FUNCTION CONTROL BITS/SIGNALS (1) P4DIR.x I: 0; O: 1 0 1 X I: 0; O: 1 0 1 X I: 0; O: 1 0 1 X I: 0; O: 1 0 1 X I: 0; O: 1 0 1 X I: 0; O: 1 0 1 X I: 0; O: 1 0 1 X I: 0; O: 1 0 1 X P4SEL.x 0 1 1 X 0 1 1 X 0 1 1 X 0 1 1 X 0 1 1 X 0 1 1 X 0 1 1 X 0 1 1 X LCDS35...28 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1
92

93

94

95

PIN NAME (P8.x) P8.0/S3 x 0 P8.0 (I/O) N/A DVSS S3 P8.1/S2 1 P8.1 (I/O) N/A DVSS S2 P8.2/S1 2 P8.2 (I/O) N/A DVSS S1 P8.3/S0 3 P8.3 (I/O) N/A DVSS S0 (1) X = Don't care FUNCTION CONTROL BITS/SIGNALS (1) P8DIR.x I: 0; O: 1 0 1 X I: 0; O: 1 0 1 X I: 0; O: 1 0 1 X I: 0; O: 1 0 1 X P8SEL.x 0 1 1 X 0 1 1 X 0 1 1 X 0 1 1 X LCDS3...0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1
96
P8REN.x Pad Logic
DVSS DVCC P8DIR.x 0 1 Direction 0: Input 1: Output
0 1 1
P8OUT.x
0 1 P8DS.x 0: Low drive 1: High drive P8.4/TA1.0 P8.5/TA1.1 P8.6/TA2.0 P8.7/TA2.1
Module X OUT
P8SEL.x P8IN.x
EN
Module X IN

PIN NAME (P8.x) P8.4/TA1.0 x 4 P8.4 (I/O) TA1.CCI0A TA1.TA0 P8.5/TA1.1 5 P8.5 (I/O) TA1.CCI1A TA1.TA1 P8.6/TA2.0 6 P8.6 (I/O) TA2.CCI0A TA2.TA0 P8.7/TA2.1 7 P8.7 (I/O) TA2.CCI1A TA2.TA1 FUNCTION CONTROL BITS/SIGNALS P8DIR.x I: 0; O: 1 0 1 I: 0; O: 1 0 1 I: 0; O: 1 0 1 I: 0; O: 1 0 1 P8SEL.x 0 1 1 0 1 1 0 1 1 0 1 1
97
Port P9, P9.0, Input/Output With Schmitt Trigger (MSP430F67xxIPZ Only)

P9REN.x Pad Logic
DVSS DVCC P9DIR.x 0 1 Direction 0: Input 1: Output
0 1 1
P9OUT.x
0 1 P9DS.x 0: Low drive 1: High drive P9.0/TACLK/RTCCLK
Module X OUT
P9SEL.x P9IN.x
EN
Module X IN
Table 77. Port P9 (P9.0) Pin Functions (MSP430F67xxIPZ Only)

PIN NAME (P9.x) P9.0/TACLK/RTCCLK x 0 P9.0 (I/O) TACLK RTCCLK FUNCTION CONTROL BITS/SIGNALS P9DIR.x I: 0; O: 1 0 1 P9SEL.x 0 1 1
98
Pad Logic
To ADC10 INCHx = y
P9REN.x
DVSS DVCC P9DIR.x
0 1 1
P9OUT.x P9DS.x 0: Low drive 1: High drive P9.1/A5 P9.2/A4 P9.3/A3
P9SEL.x P9IN.x Bus Keeper

PIN NAME (P9.x) P9.1/A5 P9.2/A4 P9.3/A3 x 1 2 3 P9.1 (I/O) A5
(2)
FUNCTION
CONTROL BITS/SIGNALS (1) P9DIR.x I: 0; O: 1 X I: 0; O: 1 X I: 0; O: 1 X P9SEL.x 0 1 0 1 0 1
P9.2 (I/O) A4 (2) P9.3 (I/O) A3

(2)
(1) (2)
X = Don't care Setting P9SEL.x bit disables the output driver as well as the input Schmitt trigger.
99
Port P2, P2.0 and P2.1, Input/Output With Schmitt Trigger (MSP430F67xxIPN Only)
S39, S38 LCDS39, LCDS38
COM6, COM7 from LCD_C Pad Logic
0 1 P2DS.x 0: Low drive 1: High drive P2.0/PM_UCB0SOMI/PM_UCB0SCL/COM6/S39 P2.1/PM_UCB0SIMO/PM_UCB0SDA/COM7/S38
Bus Keeper
P2SEL.x P2IES.x
100
Table 79. Port P2 (P2.0 and P2.1) Pin Functions (MSP430F67xxIPN Only)
CONTROL BITS/SIGNALS (1) PIN NAME (P2.x) x FUNCTION P2DIR.x I: 0; O: 1 X X X X I: 0; O: 1 X X X X P2SEL.x 0 1 1 X X 0 1 1 X X P2MAPx X default = 31 X X X default = 31 X X LCDS39, LCDS38 0 0 0 X 1 0 0 0 X 1 COM6,7 Enable Signal 0 0 0 1 0 0 0 0 1 0
P2.0/PM_UCB0SOMI/ PM_UCB0SCL/COM6/ S39
P2.0 (I/O) UCB0SOMI/UCB0SCL Output driver and input Schmitt trigger disabled COM6 S39
P2.1/PM_UCB0SIMO/ PM_UCB0SDA/COM7/ S38
P2.1 (I/O) UCB0SIMO/UCB0SDA Output driver and input Schmitt trigger disabled COM7 S38
(1)
X = Don't care
101
Port P2, P2.2 to P2.7 , Input/Output With Schmitt Trigger (MSP430F67xxIPN Only)
S37...S32 LCDS37...LCDS32 Pad Logic
0 1 P2DS.x 0: Low drive 1: High drive P2.2/PM_UCA2RXD/PM_UCA2SOMI/S37 P2.3/PM_UCA2TXD/PM_UCA2SIMO/S36 P2.4/PM_UCA1CLK/S35 P2.5/PM_UCA2CLK/S34 P2.6/PM_TA1.0/S33 P2.7/PM_TA1.1/S32
Bus Keeper
P2SEL.x P2IES.x
102
Table 80. Port P2 (P2.2 to P2.7) Pin Functions (MSP430F67xxIPN Only)

PIN NAME (P2.x) P2.2/PM_UCA2RXD/ PM_UCA2SOMI/S37 x 2 P2.2 (I/O) UCA2RXD/UCA2SOMI Output driver and input Schmitt trigger disabled S37 P2.3/PM_UCA2TXD/ PM_UCA2SIMO/S36 3 P2.3 (I/O) UCA2TXD/UCA2SIMO Output driver and input Schmitt trigger disabled S36 P2.4/PM_UCA1CLK/S35 4 P2.4 (I/O) UCA1CLK Output driver and input Schmitt trigger disabled S35 P2.5/PM_UCA2CLK/S34 5 P2.5 (I/O) UCA2CLK Output driver and input Schmitt trigger disabled S34 P2.6/PM_TA1.0/S33 6 P2.6 (I/O) TA1.CCI0A TA1.TA0 Output driver and input Schmitt trigger disabled S33 P2.7/PM_TA1.1/S32 7 P2.7 (I/O) TA1.CCI1A TA1.TA1 Output driver and input Schmitt trigger disabled S32 (1) X = Don't care FUNCTION CONTROL BITS/SIGNALS (1) P2DIR.x I: 0; O: 1 X X X I: 0; O: 1 X X X I: 0; O: 1 X X X I: 0; O: 1 X X X I: 0; O: 1 0 1 X X I: 0; O: 1 0 1 X X P2SEL.x 0 1 1 X 0 1 1 X 0 1 1 X 0 1 1 X 0 1 1 1 X 0 1 1 1 X P2MAPx X default = 31 X X default = 31 X X default = 31 X X default = 31 X X default default = 31 X X default default = 31 X LCDS37...32 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 1
103
Port P3, P3.0 to P3.7 , Input/Output With Schmitt Trigger (MSP430F67xxIPN Only)
S31 to S24 LCDS31 to LCDS24 Pad Logic
0 1 P3DS.x 0: Low drive 1: High drive P3.0/PM_TA2.0/S31 P3.1/PM_TA2.1/S30 P3.2/PM_TACLK/PM_RTCCLK/S29 P3.3/PM_TA0.2/S28 P3.4/PM_SDCLK/S27 P3.5/PM_SD0DIO/S26 P3.6/PM_SD1DIO/S25 P3.7/PM_SD2DIO/S24
Bus Keeper
104

PIN NAME (P3.x) P3.0/PM_TA2.0/S31 x 0 P3.0 (I/O) TA2.CCI0A TA2.TA0 Output driver and input Schmitt trigger disabled S31 P3.1/PM_TA2.1/S30 1 P3.1 (I/O) TA2.CCI1A TA2.TA1 Output driver and input Schmitt trigger disabled S30 P3.2/PM_TACLK/ PM_RTCCLK/S29 2 P3.2 (I/O) TACLK RTCCLK Output driver and input Schmitt trigger disabled S29 P3.3/PM_TA0.2/S28 3 P3.3 (I/O) TA0.CCI2A TA0.TA2 Output driver and input Schmitt trigger disabled S28 P3.4/PM_SDCLK/S27 4 P3.4 (I/O) SDCLK Output driver and input Schmitt trigger disabled S27 P3.5/PM_SD0DIO/S26 5 P3.5 (I/O) SD0DIO Output driver and input Schmitt trigger disabled S26 P3.6/PM_SD1DIO/S25 6 P3.6 (I/O) SD1DIO Output driver and input Schmitt trigger disabled S25 P3.7/PM_SD2DIO/S24 7 P3.7 (I/O) SD2DIO Output driver and input Schmitt trigger disabled S24 (1) X = Don't care FUNCTION CONTROL BITS/SIGNALS (1) P3DIR.x I: 0; O: 1 0 1 X X I: 0; O: 1 0 1 X X I: 0; O: 1 0 1 X X I: 0; O: 1 0 1 X X I: 0; O: 1 X X X I: 0; O: 1 X X X I: 0; O: 1 X X X I: 0; O: 1 X X X P3SEL.x 0 1 1 1 X 0 1 1 1 X 0 1 1 1 X 0 1 1 1 X 0 1 1 X 0 1 1 X 0 1 1 X 0 1 1 X P3MAPx X default default = 31 X X default default = 31 X X default default = 31 X X default default = 31 X X default = 31 X X default = 31 X X default = 31 X X default = 31 X LCDS31...24 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1
105
Port P4, Port P5, Port P6, Input/Output With Schmitt Trigger (MSP430F67xxIPN Only)
Sz LCDSz Pad Logic
PyREN.x DVSS DVCC PyDIR.x 0 1 Direction 0: Input 1: Output 0 1 1
PyOUT.x DVSS PySEL.x PyIN.x
0 1 PyDS.x 0: Low drive 1: High drive Py.x/Sz
EN Not Used D
Bus Keeper
106

107

108

109
Port J, J.0, JTAG pin TDO, Input/Output With Schmitt Trigger or Output
Pad Logic PJREN.x
DVSS PJDIR.x DVCC 0 1 DVCC
0 1 1
PJOUT.x From JTAG SMCLK
00 01 10 11 PJDS.0 0: Low drive 1: High drive PJ.0/SMCLK/TDO
PJSEL.x From JTAG PJIN.x EN D Bus Holder
Port J, J.1 to J.3, JTAG pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output
Pad Logic PJREN.x
DVSS DVCC PJDIR.x DVSS 0 1
0 1 1
PJOUT.x From JTAG MCLK/ADC10CLK/ACLK
00 01 10 11 PJDS.x 0: Low drive 1: High drive PJ.1/MCLK/TDI/TCLK PJ.2/ADC10CLK/TMS PJ.3/ACLK/TCK
PJSEL.x From JTAG PJIN.x EN To JTAG D Bus Holder
110
Table 85. Port PJ (PJ.0 to PJ.3) Pin Functions

CONTROL BITS/ SIGNALS (1) PIN NAME (PJ.x) x PJ.0 (I/O) (2) SMCLK TDO PJ.1/MCLK/TDI/TCLK 1
(3)
FUNCTION
PJDIR.x I: 0; O: 1 1 X I: 0; O: 1 1 X I: 0; O: 1 1 X I: 0; O: 1 1 X
PJSEL.x 0 1 X 0 1 X 0 1 X 0 1 X
JTAG Mode Signal 0 0 1 0 0 1 0 0 1 0 0 1
PJ.0/SMCLK/TDO
PJ.1 (I/O) (2) MCLK TDI/TCLK

(3) (4)
PJ.2/ADC10CLK/TMS
PJ.2 (I/O) (2) ADC10CLK TMS

(3) (4) (2)
PJ.3/ACLK/TCK
PJ.3 (I/O) ACLK TCK

(3) (4)
(1) (2) (3) (4)
X = Don't care Default condition The pin direction is controlled by the JTAG module. In JTAG mode, pullups are activated automatically on TMS, TCK, and TDI/TCLK. PJREN.x are don't care.
111
DEVICE DESCRIPTORS (TLV)

Table 86 and Table 87 list the complete contents of the device descriptor tag-length-value (TLV) structure for each device type. Table 86. MSP430F673x Device Descriptor Table
Description Info Block Info length CRC length CRC value Device ID Device ID Hardware revision Firmware revision Die Record Die Record Tag Die Record length Lot/Wafer ID Die X position Die Y position Test results ADC10 Calibration ADC10 Calibration Tag ADC10 Calibration length ADC Gain Factor ADC Offset ADC 1.5-V Reference Temp. Sensor 30C ADC 1.5-V Reference Temp. Sensor 85C ADC 2.0-V Reference Temp. Sensor 30C ADC 2.0-V Reference Temp. Sensor 85C ADC 2.5-V Reference Temp. Sensor 30C ADC 2.5-V Reference Temp. Sensor 85C Address 01A00h 01A01h 01A02h 01A04h 01A05h 01A06h 01A07h 01A08h 01A09h 01A0Ah 01A0Eh 01A10h 01A12h 01A14h 01A15h 01A16h 01A18h 01A1Ah 01A1Ch 01A1Eh 01A20h 01A22h 01A24h Size bytes 1 1 2 1 1 1 1 1 1 4 2 2 2 1 1 2 2 2 2 2 2 2 2 F6736PZ F6736PN Value 06h 06h per unit 6Ch 81h per unit per unit 08h 0Ah per unit per unit per unit per unit 13h 10h per unit per unit per unit per unit per unit per unit per unit per unit F6735PZ F6735PN Value 06h 06h per unit 6Bh 81h per unit per unit 08h 0Ah per unit per unit per unit per unit 13h 10h per unit per unit per unit per unit per unit per unit per unit per unit F6734PZ F6734PN Value 06h 06h per unit 6Ah 81h per unit per unit 08h 0Ah per unit per unit per unit per unit 13h 10h per unit per unit per unit per unit per unit per unit per unit per unit F6733PZ F6733PN Value 06h 06h per unit 65h 80h per unit per unit 08h 0Ah per unit per unit per unit per unit 13h 10h per unit per unit per unit per unit per unit per unit per unit per unit F6731PZ F6731PN Value 06h 06h per unit 63h 80h per unit per unit 08h 0Ah per unit per unit per unit per unit 13h 10h per unit per unit per unit per unit per unit per unit per unit per unit F6730PZ F6730PN Value 06h 06h per unit 62h 80h per unit per unit 08h 0Ah per unit per unit per unit per unit 13h 10h per unit per unit per unit per unit per unit per unit per unit per unit
112
Table 87. MSP430F672x Device Descriptor Table

Description Info Block Info length CRC length CRC value Device ID Device ID Hardware revision Firmware revision Die Record Die Record Tag Die Record length Lot/Wafer ID Die X position Die Y position Test results ADC10 Calibration ADC10 Calibration Tag ADC10 Calibration length ADC Gain Factor ADC Offset ADC 1.5-V Reference Temp. Sensor 30C ADC 1.5-V Reference Temp. Sensor 85C ADC 2.0-V Reference Temp. Sensor 30C ADC 2.0-V Reference Temp. Sensor 85C ADC 2.5-V Reference Temp. Sensor 30C ADC 2.5-V Reference Temp. Sensor 85C Address 01A00h 01A01h 01A02h 01A04h 01A05h 01A06h 01A07h 01A08h 01A09h 01A0Ah 01A0Eh 01A10h 01A12h 01A14h 01A15h 01A16h 01A18h 01A1Ah 01A1Ch 01A1Eh 01A20h 01A22h 01A24h Size bytes 1 1 2 1 1 1 1 1 1 4 2 2 2 1 1 2 2 2 2 2 2 2 2 F6726PZ F6726PN Value 06h 06h per unit 6Fh 81h per unit per unit 08h 0Ah per unit per unit per unit per unit 13h 10h per unit per unit per unit per unit per unit per unit per unit per unit F6725PZ F6725PN Value 06h 06h per unit 6Eh 81h per unit per unit 08h 0Ah per unit per unit per unit per unit 13h 10h per unit per unit per unit per unit per unit per unit per unit per unit F6724PZ F6724PN Value 06h 06h per unit 6Dh 81h per unit per unit 08h 0Ah per unit per unit per unit per unit 13h 10h per unit per unit per unit per unit per unit per unit per unit per unit F6723PZ F6723PN Value 06h 06h per unit 61h 80h per unit per unit 08h 0Ah per unit per unit per unit per unit 13h 10h per unit per unit per unit per unit per unit per unit per unit per unit F6721PZ F6721PN Value 06h 06h per unit 59h 80h per unit per unit 08h 0Ah per unit per unit per unit per unit 13h 10h per unit per unit per unit per unit per unit per unit per unit per unit F6720PZ F6720PN Value 06h 06h per unit 58h 80h per unit per unit 08h 0Ah per unit per unit per unit per unit 13h 10h per unit per unit per unit per unit per unit per unit per unit per unit
113
REVISION HISTORY
REVISION SLAS731 SLAS731A Production Data release Changed the SYSRSTIV, System Reset Interrupt Event at offset 1Ch to Reserved in Table 16. Changed LPM3 current in Features. Changed limits for ILPM0,1MHz, ILPM2, and ILPM3,XT1LF in Low-Power Mode Supply Currents (Into VCC) Excluding External Current. Changed limits for ILPM3,LCD,int. bias in Low-Power Mode With LCD Supply Currents (Into VCC) Excluding External Current. Corrected values in "x" column in Table 70. COMMENTS
114
PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device MSP430F6720IPN MSP430F6720IPNR MSP430F6720IPZ MSP430F6720IPZR MSP430F6721IPN MSP430F6721IPNR MSP430F6721IPZ MSP430F6721IPZR MSP430F6723IPN MSP430F6723IPNR MSP430F6723IPZ MSP430F6723IPZR MSP430F6724IPN MSP430F6724IPNR MSP430F6724IPZ MSP430F6724IPZR MSP430F6725IPN Status
(1)
Package Type Package Drawing LQFP LQFP LQFP LQFP LQFP LQFP LQFP LQFP LQFP LQFP LQFP LQFP LQFP LQFP LQFP LQFP LQFP PN PN PZ PZ PN PN PZ PZ PN PN PZ PZ PN PN PZ PZ PN
Pins 80 80 100 100 80 80 100 100 80 80 100 100 80 80 100 100 80
Package Qty 119 1000 90 1000 119 1000 90 1000 119 1000 90 1000 119 1000 90 1000 119
Eco Plan
(2)
Lead/ Ball Finish
MSL Peak Temp
(3)
Samples (Requires Login)
ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE
Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br)
CU NIPDAU Level-3-260C-168 HR CU NIPDAU Level-3-260C-168 HR CU NIPDAU Level-3-260C-168 HR CU NIPDAU Level-3-260C-168 HR CU NIPDAU Level-3-260C-168 HR CU NIPDAU Level-3-260C-168 HR CU NIPDAU Level-3-260C-168 HR CU NIPDAU Level-3-260C-168 HR CU NIPDAU Level-3-260C-168 HR CU NIPDAU Level-3-260C-168 HR CU NIPDAU Level-3-260C-168 HR CU NIPDAU Level-3-260C-168 HR CU NIPDAU Level-3-260C-168 HR CU NIPDAU Level-3-260C-168 HR CU NIPDAU Level-3-260C-168 HR CU NIPDAU Level-3-260C-168 HR CU NIPDAU Level-3-260C-168 HR
Addendum-Page 1
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Orderable Device MSP430F6725IPNR MSP430F6725IPZ MSP430F6725IPZR MSP430F6726IPN MSP430F6726IPNR MSP430F6726IPZ MSP430F6726IPZR MSP430F6730IPN MSP430F6730IPNR MSP430F6730IPZ MSP430F6730IPZR MSP430F6731IPN MSP430F6731IPNR MSP430F6731IPZ MSP430F6731IPZR MSP430F6733IPN MSP430F6733IPNR MSP430F6733IPZ
Status
(1)
Package Type Package Drawing LQFP LQFP LQFP LQFP LQFP LQFP LQFP LQFP LQFP LQFP LQFP LQFP LQFP LQFP LQFP LQFP LQFP LQFP PN PZ PZ PN PN PZ PZ PN PN PZ PZ PN PN PZ PZ PN PN PZ
Pins 80 100 100 80 80 100 100 80 80 100 100 80 80 100 100 80 80 100
Package Qty 1000 90 1000 119 1 90 1000 119 1000 90 1000 119 1000 90 1000 90 1000 90
Eco Plan
(2)
Lead/ Ball Finish
MSL Peak Temp
(3)
ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE
Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br)
CU NIPDAU Level-3-260C-168 HR CU NIPDAU Level-3-260C-168 HR CU NIPDAU Level-3-260C-168 HR CU NIPDAU Level-3-260C-168 HR CU NIPDAU Level-3-260C-168 HR CU NIPDAU Level-3-260C-168 HR CU NIPDAU Level-3-260C-168 HR CU NIPDAU Level-3-260C-168 HR CU NIPDAU Level-3-260C-168 HR CU NIPDAU Level-3-260C-168 HR CU NIPDAU Level-3-260C-168 HR CU NIPDAU Level-3-260C-168 HR CU NIPDAU Level-3-260C-168 HR CU NIPDAU Level-3-260C-168 HR CU NIPDAU Level-3-260C-168 HR CU NIPDAU Level-3-260C-168 HR CU NIPDAU Level-3-260C-168 HR CU NIPDAU Level-3-260C-168 HR
Addendum-Page 2
www.ti.com
21-Apr-2012
Orderable Device MSP430F6733IPZR MSP430F6734IPN MSP430F6734IPNR MSP430F6734IPZ MSP430F6734IPZR MSP430F6735IPN MSP430F6735IPNR MSP430F6735IPZ MSP430F6735IPZR MSP430F6736CY MSP430F6736CYS MSP430F6736IPN MSP430F6736IPNR MSP430F6736IPZ MSP430F6736IPZR
Status
(1)
Package Type Package Drawing LQFP LQFP LQFP LQFP LQFP LQFP LQFP LQFP LQFP DIESALE LQFP LQFP LQFP LQFP PZ PN PN PZ PZ PN PN PZ PZ Y YS PN PN PZ PZ
Pins 100 80 80 100 100 80 80 100 100 0 0 80 80 100 100
Package Qty 1000 119 1000 90 1000 119 1000 90 1000 1 1 119 1000 90 1000
Eco Plan
(2)
Lead/ Ball Finish
MSL Peak Temp
(3)
ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE PREVIEW ACTIVE ACTIVE ACTIVE ACTIVE
Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) TBD TBD Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br)
CU NIPDAU Level-3-260C-168 HR CU NIPDAU Level-3-260C-168 HR CU NIPDAU Level-3-260C-168 HR CU NIPDAU Level-3-260C-168 HR CU NIPDAU Level-3-260C-168 HR CU NIPDAU Level-3-260C-168 HR CU NIPDAU Level-3-260C-168 HR CU NIPDAU Level-3-260C-168 HR CU NIPDAU Level-3-260C-168 HR Call TI Call TI Call TI Call TI
PREVIEW WAFERSALE
CU NIPDAU Level-3-260C-168 HR CU NIPDAU Level-3-260C-168 HR CU NIPDAU Level-3-260C-168 HR CU NIPDAU Level-3-260C-168 HR
(1)
The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 3
www.ti.com
21-Apr-2012
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 4
MECHANICAL DATA
MTQF010A JANUARY 1995 REVISED DECEMBER 1996
PN (S-PQFP-G80)
0,27 0,17 41
PLASTIC QUAD FLATPACK
0,50 60
0,08 M
61
40
80
0,13 NOM 21
1 9,50 TYP 12,20 SQ 11,80 14,20 SQ 13,80 1,45 1,35
20
Gage Plane
0,25 0,05 MIN 0 7
0,75 0,45
Seating Plane 1,60 MAX 0,08 4040135 / B 11/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
MECHANICAL DATA
MTQF013A OCTOBER 1994 REVISED DECEMBER 1996
PZ (S-PQFP-G100)
PLASTIC QUAD FLATPACK
0,50 75 51
0,27 0,17
0,08 M
76
50
100
26
0,13 NOM
1 12,00 TYP 14,20 SQ 13,80 16,20 SQ 15,80 1,45 1,35
25 Gage Plane
0,05 MIN
0,25 0 7
0,75 0,45 Seating Plane
1,60 MAX
0,08
4040149 /B 11/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TIs terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TIs standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. 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TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would reasonably be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products and any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may be provided by TI. Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in such safety-critical applications. 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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright 2012, Texas Instruments Incorporated

Mixed Signal Microcontroller: Features

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MSP430F673x MSP430F672x

www.ti.com SLAS731A DECEMBER 2011 REVISED APRIL 2012

MIXED SIGNAL MICROCONTROLLER

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Table 2. Ordering Information (1)

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Functional Block Diagram, MSP430F673xIPZ, MSP430F672xIPZ

I/O Ports P1/P2 28 I/Os Interrupt & Wakeup PA 116 I/Os

I/O Ports P3/P4 28 I/Os

I/O Ports P5/P6 28 I/Os

I/O Ports P7/P8 28 I/Os

I/O Ports P9 14 I/O

CPUXV2 and Working Registers (25MHz)

REF Reference 1.5V, 2.0V, 2.5V

JTAG/ SBW Interface/ Port PJ

TA0 Timer_A 3 CC Registers

TA1 TA2 TA3 Timer_A 2 CC Registers

eUSCI_A0 eUSCI_A1 eUSCI_A2 (UART, IrDA,SPI)

eUSCI_B0 (SPI, I2C)

Functional Block Diagram, MSP430F673xIPN, MSP430F672xIPN

I/O Ports P1/P2 28 I/Os Interrupt & Wakeup PA 116 I/Os

I/O Ports P3/P4 28 I/Os

I/O Ports P5/P6 28 I/Os

CPUXV2 and Working Registers (25MHz)

REF Reference 1.5V, 2.0V, 2.5V

TA0 Timer_A 3 CC Registers

JTAG/ SBW Interface/ Port PJ

TA1 TA2 TA3 Timer_A 2 CC Registers

eUSCI_A0 eUSCI_A1 eUSCI_A2 (UART, IrDA,SPI)

eUSCI_B0 (SPI, I2C)

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Pin Designation, MSP430F673xIPZ

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Table 3. Pinout Differences Between MSP430F673xIPZ and MSP430F672xIPZ (1)

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Pin Designation, MSP430F673xIPN

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Table 4. Pinout Differences Between MSP430F673xIPN and MSP430F672xIPN (1)

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Table 5. Terminal Functions, MSP430F67xxIPZ

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Table 5. Terminal Functions, MSP430F67xxIPZ (continued)

P8.5/TA1.1 COM0 COM1 COM2 COM3 P1.6/PM_UCA0CLK/COM4

P2.2/PM_UCA2RXD/ PM_UCA2SOMI P2.3/PM_UCA2TXD/ PM_UCA2SIMO

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Table 5. Terminal Functions, MSP430F67xxIPZ (continued)

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Table 5. Terminal Functions, MSP430F67xxIPZ (continued)

P6.0/S19 DVSYS (5) DVSS P6.1/S18

Table 5. Terminal Functions, MSP430F67xxIPZ (continued)

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