3 Testability Design

Technical University Tallinn, ESTONIA
Design for Testability

Outline
Ad Hoc Design for Testability Techniques
Method of test points
Multiplexing and demultiplexing of test points
Time sharing of I/O for normal working and testing modes
Partitioning of registers and large combinational circuits
Scan-Path Design
Scan-path design concept
Controllability and observability by means of scan-path
Full and partial serial scan-paths
Non-serial scan design
Classical scan designs

Method of Test Points:
Block 1 Block 2
Block 1 is not observable,
Block 2 is not controllable
Block 1 Block 2
1- controllability:
CP = 0 - normal working mode
CP = 1 - controlling Block 2
with signal 1
1
CP
Improving controllability and observability:
Block 1 Block 2
0- controllability:
CP = 1 - normal working mode
CP = 0 - controlling Block 2
with signal 0
&
CP
OP
OP
Method of Test Points:
Block 1 Block 2
Block 1 is not observable,
Block 2 is not controllable
Block 1
Block 2
1
CP1
Improving controllability:

Block 1 Block 2
Normal working mode:
CP1 = 0, CP2 = 1
Controlling Block 2 with 1:
CP1 = 1, CP2 = 1
CP2 = 0
MUX
CP1
&
CP2
CP2
Normal working mode:
CP2 = 0
CP1 = 1, CP2 = 1
CP1 = 0, CP2 = 1
Multiplexing monitor points:
OUT
0
1
2
n
-1
x
1

x
n

x
2

MUX
To reduce the number of
output pins for observing
monitor points,
multiplexer can be used:
2
n
observation points are
replaced by a single
output and n inputs to
address a selected
observation point
Disadvantage:
Only one observation
point can be observed at
a time

Advantage: (n + 1) << 2
n

Number of additional pins: (n + 1)
Number of observable points: [2
n
]
Multiplexing monitor points:
OUT
0
1
2
n
-1
c
MUX
monitor points,
multiplexer can be used:
inputs, a counter (or a
shift register) can be used
to drive the address lines
of the multiplexer
Disadvantage:
Only one observation
point can be observed at
a time

Counter
Advantage: 2 << 2
n

Number of additional pins: 2
Nmber of observable points: [2
n
]
Demultiplexer for implementing control points:
0
1
2
n
-1
DMUX
input pins for controlling
testpoints, demultiplexer
and a latch register can
be used.
Disadvantage:
N clock times are required
between test vectors to
set up the proper control
values

x
CP1
CP2
CPN
x
1

x
2

x
n

Advantage: (n + 1) << N
Number of additional pins: (n + 1)
Number of control points: 2
n-1
< N s 2
n
Demultiplexer for implementing control points:
0
1
2
n
-1
c
DMUX
To reduce the number of input
pins for controlling testpoints,
demultiplexer and a latch
register can be used.
inputs for addressing, a
counter (or a shift register) can
be used to drive the address
lines of the demultiplexer
Counter
x
CP1
CP2
CPN
Number of control points: N

Advantage: 2 << N
Disadvantage:
N clock times are required
between test vectors to set up
the proper control values
Time-sharing of outputs for monitoring
monitor points, time-
sharing of working
outputs can be
introduced: no additional
outputs are needed
inputs, again counter or
shift register can be used
if needed
Original
circuit
MUX

Advantage: 1 << N
Time-sharing of inputs for controlling
0
1
N
DMUX
CP1
CP2
CPN
input pins for controlling
test points, time-sharing
of working inputs can be
introduced.
inputs for driving the
address lines of
demultiplexer, counter or
shift register can be used
if needed
Normal
input
lines

Advantage: 1 << N
Example: DFT with MUX-s and DMUX-s
CP1
CP2
CP3
CP4
Given a circuit:
- CP1 and CP2 are not controllable
- CP3 and CP4 are not observable
DFT task: Improve the testability by using a single control input, no
additional inputs/outputs allowed
1
2
3
4
1
2
3
4
CP1
CP2
CP3
CP4
1
2
3
4
1
2
3
4
Given a circuit:
CP3 and CP4 are not observable
Improving the observability
MUX
MUX
0
0
1
1
T
T
0
1
Mode
Test
Norm.
MUX
0
1
Coding:
Result: A single pin T is needed
CP1
CP2
CP3
CP4
Given a circuit: CP1 and CP2 are not controllable Improving the controllability
MUX
MUX
FF
FF
DMUX
DMUX
1
2
3
4
T
0
0
0
0
1
1
1
1
1
2
3
4
Counter
Decoder
Q
00
01
Mode
Contr
Test
Norm.
10
DMUX MUX
1 1
0
x
0 1
Coding:
Result:
A single pin T
is needed
Q
x
3

y
1

z
3

z
2

z
1

F
1

F
2

F
3

F
4

z
4

CP1
CP 2
CP
MUX 1
FF
DMUX
1
2
3
0
0
1
1
1
2
3
Counter
Decoder
MUX 2
0
1
2
CP1
CP 2
CP4
3
MUX 1
FF
DMUX
1
2
3
T
0
0
1
1
1
2
3
Counter
Decoder
MUX 2
0
1
2
4
4 3
00
0 01
Mode
Contr
Test
010
DMUX
MUX 1
1 1
0
x
0 1
MUX 2
0
x
0
0 1 1
1 0 1
100
1 0 2
Q
00 0
0
Norm
010
MUX 1
1 1
0
x
0 1
MUX 2
0
x
0
0
1 0 1
100
1 0 2
101
1 0 3
10
1 0
x
2

x
1

Obs
Obs
Obs
Result:
A single
pin T
is needed
Q
Examples of good candidates for control points:
control, address, and data bus lines on bus-structured designs
enable/hold inputs of microprocessors
enable and read/write inputs to memory devices
clock and preset/clear inputs to memory devices (flip-flops, counters, ...)
data select inputs to multiplexers and demultiplexers
control lines on tristate devices
Examples of good candidates for observation points:
stem lines associated with signals having high fanout
global feedback paths
redundant signal lines
outputs of logic devices having many inputs (multiplexers, parity generators)
outputs from state devices (flip-flops, counters, shift registers)
address, control and data busses
Fault redundancy and testability
1
&
&
&
1
&
x
1

x
2

&
x
4

x
3

y
0
) (
2
4 3 4 2 1 1
c
c
v v v =
x
y
x x x x x x y
Faults at x
2
not
testable
0
1
1
1
&
&
&
1
&
x
1

x
2

&
x
4

x
3

y
0
1
0
3 4 1 4 3 4 1
x x x x x x x y v v = v v =
Redundant gates are removed:
Fault at x
12
not testable
x
12

x
11

Remaining
gate
Redundancy should be avoided:
If a redundant fault occurs, it may invalidate
some test for nonredundant faults
Redundant faults cause difficulty in
calculating fault coverage
Much test generation time can be spent in
trying to generate a test for a redundant fault
Redundancy intentionally added:
To eliminate hazards in combinational
circuits
To achieve high reliability (using error
detecting circuits)
Logical redundancy:
1
&
&
&
1
1
01
10
01
1
1
Hazard control circuitry:
Redundant AND-gate
Fault 0 not testable
0
T
Additional control input added:
T = 1 - normal working mode
T = 0 - testing mode
Fault redundancy:
Error control circuitry:
Decoder

1
E = 1 if decoder is fault-free
Fault 1 not testable
No
error
Testable error control circuitry:
Decoder

1
Additional control input added:
T 0 - normal working mode
T = 1 - testing mode
Error
detected
T
Partitioning of registers (counters):
C REG 1
REG 2
IN IN OUT OUT
CL CL
C
REG 1
REG 2
IN
IN OUT
OUT
CL
CL
&
&
&
&
CP: Tester Data
CP: Data Inhibit
CP: Clock Inhibit
CP: Tester Clock
&
&
CP: Tester Data
CP: Data Inhibit
OP
16 bit counter divided
into two 8-bit counters:
Instead of 2
16
= 65536
clocks, 2x2
8
= 512
clocks needed
If tested in parallel, only
256 clocks needed
Partitioning of large combinational circuits:
C1
C2
DMUX1
C1
MUX1 MUX2
DMUX2
C2
MUX3
MUX4
The time complexity of
test generation and
fault simulation grows
faster than a linear
function of circuit size
Partioning of large
circuits reduces these
costs
I/O sharing of normal
and testing modes is
used
Three modes can be
chosen:
- normal mode
- testing C1
- testing C2 (bolded
lines)
How many additional inputs are needed?
Scan-Path Design
Combinational
circuit
IN OUT
R
Scan-IN
Scan-OUT
1
&
&
q
q
Scan-IN
T
T D
C
Scan-OUT
q
q
The complexity of testing is a function
of the number of feedback loops and
their length
The longer a feedback loop, the more
clock cycles are needed to initialize
and sensitize patterns
Scan-register is a aregister with
both shift and parallel-load capability
T = 0 - normal working mode
T = 1 - scan mode
Normal mode : flip-flops are
connected to the combinational circuit
Test mode: flip-flops are
disconnected from the combinational
circuit and connected to each other to
form a shift register
Scan-Path Design and Testability
OUT
MUX
DMUX
IN
SCAN
OUT
SCAN
IN
Two possibilities for improving
controllability/observability
Parallel Scan-Path
Combinational
circuit
IN OUT
R1
Scan-IN 1
Scan-OUT 1
R2
Scan-IN 2
Scan-OUT 2
In parallel scan path
flip-flops can be
organized in more than
one scan chain
Advantage: time +
Disadvantage: # pins |
Partial Scan-Path
Combinational
circuit
IN OUT
R1
Scan-IN
Scan-OUT
R2
In partial scan
instead of
full-scan,
it may be
advantageous
to scan
only some
of the flip-flops
Example:
counter even
bits joined in the
scan-register

Partial Scan Path

M
3
e
+
M
1
a
*
M
2
b
-
-
R
1
IN
-
-
-
c
d
y
1
y
2 y
3
y
4
y
4
y
3
y
1
R
1
+ R
2
IN + R 2
R
1
* R
2
IN* R
2
y
2
R
2
0
1
2
0
1
0
1
0
1
#
0
R
2
IN
R
1
2
3
Hierarhical test generation with Scan-Path:
Control Part
R
2
Bus
Scan-In
Scan-Out
Data Part
Testing with Minimal DFT

M
3
e
+
M
1
a
*
M
2
b
-
-
R
1
IN
-
-
-
c
d
y
1
y
2 y
3
y
4
y
4
y
3
y
1
R
1
+ R
2
IN + R 2
R
1
* R
2
IN* R
2
y
2
R
2
0
1
2
0
1
0
1
0
1
#
0
R
2
IN
R
1
2
3
Hierarhical test generation with Scan-Path:
Control Part
R
2
Bus
Scan-In
Scan-Out
Data Part
Random Access Scan
Combinational
circuit
IN OUT
R q
q
&
Scan-IN
Scan-CL
Scan-OUT
DC
DC
X-Address
Y-Address
In random access
scan each flip-flop
in a logic network
is selected
individually by an
address for control
and observation of
its state
Example:
Delay fault testing
Higherarchical TPG: Behavioral Model
C = A+B
A = A*C
C = B
2
A = AvC
Behaviour model:
E(0)
L=0
1
0
0
T = T-1
T=0

1
1
A = F
D = B
E = B
0
q
3
q
4
q
5
q
2
F = F+D
C = F
A = A * (A + B) v B
2

Detailed data-flow graph:
C = A+B
T = 2
L = 9
q
1
q
0
BEGIN
D = R(D)
E = L(E)
L = L-1

D = A
E = C
F = 0

Higherarchical TPG: Digital System
Higherarchical TPG: Decision Diagram
Higherarchical TPG: Decision Diagram
No Testvektor Jlgitavad registrid
LT AB A C E
Testitavad
funktsioonid
Testi pikkus
(vektoreid/takte)
1 11 AB
A v R(A)
R(A) L(A+B)
R,L,v,+
8/5 = 40
2 x1 AB A*(A+B) Muutuja L 1/(2+16*2) = 34
3 xx AB
A*(A+B)vB
2
Muutuja T 1/(33+34) = 67

Kokku pakitud testprogramm:
Selection of Test Points
Test point selection approaches
Improving testability for any set of pseudo-random patterns
(Pseudorandom BIST)
Testability measures are used to characterize the controllability and
observability of the circuit
Improving testability for a given sequence of vectors
(Functional BIST)
Methods that are used:
logic simulation,
fault simulation,
estimation of controllability and observability values,
path tracing

Reference
Result

Go/NoGo
UUT
Reference
Result

Go/NoGo
UUT
Signature
Traditional
functional
testing
HW
overhead
Functional
BIST
Reference
Signature

Go/NoGo
UUT
Test
generator
Normal
operation
Random BIST vs Functional BIST
HW
overhead
Random test set
Deterministic
functional test set
Random
BIST
Method: Simulation of given test patterns
Identification of the faults that are detected
The remaining faults are classified as
A: Faults that were not excited
B: Faults at gate inputs that were excited but not propagated to the gate output
C: Faults that were excited but not propagated to circuit output
The faults A and B require control points for their detection
The faults C may be detected by observation points only
Control points selection should be carried out before observation
points selection

Classification of Not-Detected Faults
1
1
&
1
x
1

x
2

x
3

x
4

x
5

y
Always 1 0
Class A:
Fault x
3
1 is not
activated
Class B:
Faults at x
5
are not
propagated
through the gate
0
1
0
Class C:
Faults at x
1
are not
propagated to the output
Classes
A and B
need
controllability
Class C needs
either
controllability
or
observability
Classification of faults
1
&
&
1
x
1

x
2

x
3

x
4

x
5

a
b
c
y

No
Test patterns Fault table
Inputs
Intern.
points
Inputs
Intern.
points
1 2 3 4 5
a b c
1 2 3 4 5
a b c
1
0 0 1 0 1 0 0 0 1 1 - 1 - 1 1 1
2
0 1 0 1 1 1 0 1 - - - 0 0 - - 0
3
0 1 0 1 0 1 0 0 - - 1 - 1 - 1 1
Given test:
Not detected faults:
A x
1
/0: x
1
= 1 is missing
A b /0: b

= 1 is missing
B x
3
/0: x
3
a = 11 is missing
B a /0: x
3
a = 11 is missing
C x
2
/0: x
1
x
2
= 01 OK
x
1
/0 x
2
/0 x
3
/0 a /0 b /0
Class Faults Missing signals
1
&
&
1
x
1

x
2

x
3

x
4

x
5

a
b
c
y

No
Inputs
Intern.
points
Inputs
Intern.
points
1 2 3 4 5
a b c
1 2 3 4 5
a b c
1
0 0 1 0 1 0 0 0 1 1 - 1 - 1 1 1
2
0 1 0 1 1 1 0 1 - - - 0 0 - - 0
3
0 1 0 1 0 1 0 0 - - 1 - 1 - 1 1
Given test:
A x
1
/0: x
1
= 1 is missing
A b /0: b

= 1 is missing
B x
3
/0: x
3
a = 11 is missing
B a /0: x
3
a = 11 is missing
C x
2
/0: x
1
x
2
= 01 OK
x
1
/0 x
2
/0 x
3
/0 a /0 b /0
1
&
&
1
x
1

x
2

x
3

x
4

x
5

a
b
c
y

No
Inputs
Intern.
points
Inputs
Intern.
points
1 2 3 4 5
a b c
1 2 3 4 5
a b c
1
0 0 1 0 1 0 0 0 1 1 - 1 - 1 1 1
2
0 1 0 1 1 1 0 1 - - - 0 0 - - 0
3
0 1 0 1 0 1 0 0 - - 1 - 1 - 1 1
Given test:
A x
1
/0: x
1
= 1 is missing
A b /0: b

= 1 is missing
B x
3
/0: x
3
a = 11 is missing
B a /0: x
3
a = 11 is missing
C x
2
/0: x
1
x
2
= 01 OK
x
1
/0 x
2
/0 x
3
/0 a /0 b /0
1
&
&
1
x
1

x
2

x
3

x
4

x
5

a
b
c
y

No
Inputs
Intern.
points
Inputs
Intern.
points
1 2 3 4 5
a b c
1 2 3 4 5
a b c
1
0 0 1 0 1 0 0 0 1 1 - 1 - 1 1 1
2
0 1 0 1 1 1 0 1 - - - 0 0 - - 0
3
0 1 0 1 0 1 0 0 - - 1 - 1 - 1 1
Given test:
A x
1
/0: x
1
= 1 is missing
A b /0: b

= 1 is missing
B x
3
/0: x
3
a = 11 is missing
B a /0: x
3
a = 11 is missing
C x
2
/0: x
1
x
2
= 01 OK
x
1
/0 x
2
/0 x
3
/0 a /0 b /0
1
&
&
1
x
1

x
2

x
3

x
4

x
5

a
b
c
y

No
Inputs
Intern.
points
Inputs
Intern.
points
1 2 3 4 5
a b c
1 2 3 4 5
a b c
1
0 0 1 0 1 0 0 0 1 1 - 1 - 1 1 1
2
0 1 0 1 1 1 0 1 - - - 0 0 - - 0
3
0 1 0 1 0 1 0 0 - - 1 - 1 - 1 1
Given test:
A x
1
/0: x
1
= 1 is missing
A b /0: b

= 1 is missing
B x
3
/0: x
3
a = 11 is missing
B a /0: x
3
a = 11 is missing
C x
2
/0: x
1
x
2
= 01 OK,
Path activation is missing
x
1
/0 x
2
/0 x
3
/0 a /0 b /0
Identification of candidate control points
1. The reason of the low controllability of y=1 is high fan-in
&
.
.
.
x
1

x
2

x
n

n >> 1
y
The candidate control points are
lines x
k
in the fan-in of y with
controllability values that may be
changed to obtain a desired
change in the controllability values
at y
Question: x
k
or y as a candidate?
To control testing of other inputs
x-s should be the candidates
1
x
k

T = 1
Low C
1
High C
1
Selection of Test Points: Procedure
1. Selection of control points:
Once control point candidates are identified for the faults A and B, a
minimum number of control points (CP) can be identified
This can be formulated as a minimum coverage problem where a
minimum CPs are selected such that at least one CP candidate is
included for each fault in A and B

F1 F2 F3 F4 F5 F6 F7 F8 F9
CP1
1 1 1
CP2
1 1 1 1 1
CP3
1 1 1
CP4
1 1 1 1
CP5
1 1 1 1
Control
point
candidates
Faults
Selected
control
points
Selection of Test Points: Procedure
2. Selection of observation points
Once the CPs are selected, the given test patterns are augmented to
accommodate the additional inputs assotiated with the CPs and
fault simulation is performed
The fault class C is updated
For each fault, in C the circuit lines to which the effect of the fault
propagates, are identified as a potential observation point candidates
A minimum covering problem is formulated and solved to find the
observation points to be added

DMUX Control
CP1
CP2
CPN
Test
Fault
class C
updated
F1 F2 F3 F4 F5 F6 F7 F8 F9
CP1
1 1 1
CP2
1 1 1 1 1
CP3
1 1 1
CP4
1 1 1 1
CP5
1 1 1 1
Minimization of control points
New fault simulation
Test point coverage:
1
&
&
1
x
1

x
2

x
3

x
4

x
5

a
b
c
y
x
1
/0
x
3
/0
a /0
b /0
Class A: x
1
/0, b

/0
Class B: x
3
/0, a

/0,

Not detected faults
x
1
/0 x
3
/0 a /0 b

/0

Potential
control
points
x
1
=1 + + + +
x
3
=1 + + +
a

=1 + + +
b

=1 +

No
Test patterns
Inputs
Intern.
points
1 2 3 4 5
a b c
1
0 0 1 0 1 0 0 0
2
0 1 0 1 1 1 0 1
3
0 1 0 1 0 1 0 0
To be selected
Minimization of test points:
Insertion of Test Points
Selected test points:
Class A: x
1
/0 x
1
=1 (control point)
Class C: x
2
/0 (observable point)

No
Test patterns
Inputs
Intern.
points
1 2 3 4 5
a b c
1
0 0 1 0 1 0 0 0
2
0 1 0 1 1 1 0 1
3
0 1 0 1 0 1 0 0
T
1
=1
y
This
pattern is
to be
repeated
with
T
1
=1
1
&
&
1
x
1

x
2

x
3

x
4

x
5

a
b
c
y
x
1
/0
x
3
/0
a /0
b /0
To be observed
x
2
/0
Corrected circuit:
&
&
1 x
3

x
4

x
5

a
b
c
1
x
1

x
2

x
1
/0
x
2
/0
T
1
=1

T
2
T
2

1
Two test points:
Minimization of monitoring points:
To reduce the number of output
pins for observing monitor points,
exor gates can be used:
OUT
0
1
2
n
-1
c
MUX
Counter
OUT

Space and time
compaction
Space
Time
With MUX
With EXOR
MUX
EXOR
Additional
outputs
Without MUX
Minimization of monitor points:
To reduce the number of output
pins for observing monitor points,
signature analyzers can be used:
OUT
0
1
2
n
-1
c
MUX
Counter
SA
SCAN OUT
SCAN IN
With SA
Space
Time
With MUX
With EXOR
MUX
EXOR
Additional
outputs
Additional time
compaction
Boundary Scan Standard
Boundary Scan Architecture
TDO
internal
logic
T
A
P
TDO
TMS
TCK
TDI
BSC
TDI
Data_out
Data_in
TDO
TDO
TDI
internal
logic
internal
logic
internal
logic
internal
logic
T
A
P
T
A
P
TMS
TCK
T
A
P
T
A
P
Boundary Scan Architecture
Device ID. Register
Bypass Register
Instruction Register (IR)
TDI
TDO
B
o
u
n
d
a
r
y

Scan
R
e
g
i
s
t
e
r
s

Internal
logic
Data
Registers
Boundary Scan Cell
From
last
cell
Update DR
To next cell
Q
Q
SET
CLR
D
Clock DR
Test/Normal
1
0
Q
Q
SET
CLR
D
0
1
From system pin
Q
Q
SET
CLR
D
Q
Q
SET
CLR
D
Shift DR
To
system
logic
Used at the input or output pins
Boundary Scan Working Modes
SAMPLE mode:
Get snapshot of normal chip output signals
PRELOAD mode:
Put data on boundary scan chain before next instruction
Extest instruction:
Test off-chip circuits and board-level interconnections

INTEST instruction
Feeds external test patterns in and shifts responses out
Bypass instruction:
Bypasses the
corresponding chip
using 1-bit register
To TDO
From TDI
Shift DR
Clock DR
Q
Q
D
SET
CLR
IDCODE instruction:
Connects the component device identification register serially
between TDI and TDO in the Shift-DR TAP controller state
Allows board-level test controller or external tester to read out
component ID
Required whenever a J EDEC identification register is included
in the design
TDO
TDI
Version Part Number Manufacturer ID 1
4-bits
Any format
16-bits
Any format
11-bits
Coded form of JEDEC
Fault Diagnosis with Boundary Scan
Short
Open
1
0
0
0
0
1
Assume stuck-at-0
Assume wired AND
Short
Open
10
00
00
01
11
Assume stuck-at-0
00
00
00
Assume wired AND
Kautz showed in 1974 that a sufficient condition to detect any pair of
short circuited nets was that the horizontal codes must be unique
for all nets. Therefore the test length is ]log
2
(N)[
Short
Open
101
000
001
011
110
Assume stuck-at-0
001
001
001
Assume wired AND
All 0-s and all 1-s are forbidden codes because of stuck-at faults
Therefore the final test length is ]log
2
(N+2)[
Short
Open
0 101
0 000
0 001
0 011
1 110
Assume stuck-at-0
1 001
0 001
1 001
Assume wired AND
To improve the diagnostic resolution we have to add one bit more

Synthesis of Testable Circuits
2 1 3 1
x x x x y + =
1
&
&
x
1

x
3

x
2

y
x
1
x
2
x
3
y

&
&
2 1 3 1
x x x x y + =
Test generation:
0 1 1 0 1 0 0 0
1 0 0 1 0 1 1 0
1 1 0 0 0 0 1 1
0 0 1 1 1 1 1 1
4 test patterns are needed
2 1 3 1
x x x x y + =
1
&
&
x
1

x
3

x
2

y
&
&
x
1
x
2
x
3

y
&
&

Here:
Only 3 test patterns are needed
010
010
110
110
110
101
Here:
4 test patterns are needed
Two implementations
for the same circuit:
First assignment
3 2 1 7 2 1 6 3 1 5 1 4 3 2 3 2 2 3 1 0
x x x c x x c x x c x c x x c x c x c c y =
Calculation of constants:
2 1 3 1
x x x x y + =
f
i
x
1
x
2
x
3
y E

f
0
0 0 0 1 1 C
0
= f
0

f
1
0 0 1 0 1 C
1
= f
0

f
1
f
2
0 1 0 1 0 C
2
= f
0

f
2
f
3
0 1 1 0 0 C
3
= f
0

f
1

f
2

f
3
f
4
1 0 0 0 1 C
4
= f
0

f
4
f
5
1 0 1 0 1 C
5
= f
0

f
1

f
4

f
5
f
6
1 1 0 1 1 C
6
= f
0

f
2

f
4

f
6
f
7
1 1 1 1 0 C
3
= f
0

f
1

f
2

f
3

f
4

f
5

f
6

f
5
2 1 3 1 1 3
1 x x x x x x y =
Given:
New:
Test generation method:
2 1 3 1 1 3
1 x x x x x x y =
x
1
x
2
x
3

y
&
&

011
011
110
110
110
101
x
1
x
2
x
3

0 0 0
1 1 1
0 1 1
1 0 1
1 1 0

&
1
&
0
0
& 1
Roles of test patterns:
Testability as a trade-off
Amusing testability:
Theorem: You can test an arbitrary digital system by only 3 test patterns
if you design it approprietly
&
011
101
001
&
011
101
001
&
?
&
011
101
001
1
010
&
011
101
001
Solution: System FSM Scan-Path CC NAND
Proof:

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Technical University Tallinn, ESTONIA

Design for Testability

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