CPU Structure and Function

Arithmetic Logic Unit

Control Unit
Control Registers
Datapath
(Stalling, Chapter 12)

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CPU Component
■ Arithmetic Logic Unit (ALU)
– Complementor
– Adder
– Shifter
■ Control logic
– Hardwired/Microprogram
■ Temporary storage
– General purpose registers
– Specialized purpose registers

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CPU Overview
■ ALU
– Actual computation or
processing data
■ Control logic
– Control movement of data
and instructions into and
out of CPU
– Control operations of CPU
■ Registers
– Storage location for
intermediate data

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Detail View of CPU

■ Internal CPU bus

to transfer data
between registers
and ALU

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Register Organization
■ Registers form the highest level of the memory hierarchy.
– Small set of high speed storage locations
– Temporary storage for data and control information
■ Two types of registers:
– User-visible
May be referenced by assembly-level instructions and are thus “visible”
to the user.
– Control and status registers
Used to control the operation of the CPU.
Most are not visible to the user.

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User-visible Registers
■ General purpose registers
– Can be assigned a variety of functions.
– Ideally, they are defined orthogonally to the operations within the instructions.
– Can be used for addressing functions
■ Data registers
– These registers only hold data and cannot be employed in the calculation of an
operand address.
■ Address registers
– These registers only hold address information.
– Examples: general purpose address registers, segment pointers, stack pointers,
index registers.

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… User-visible Registers
■ Condition codes or Flags
– Bits set by the processor hardware as a result of operations
– Collected as status/flag register. Can be accessed by a
program but not changed directly
– Examples:
• sign flag
• zero flag
• overflow flag
• carry flag
– Bit values are used as the basis for conditional jump
instructions.

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Flags Affected by Arithmetic Operations
■ The ALU has a number of status flags that reflect the
outcome of arithmetic (and bitwise) operations
– based on the contents of the destination operand
■ Essential flags:
– Zero flag : set when destination equals zero
– Sign flag : set when destination is negative
– Carry flag : set when unsigned value is out of range
– Overflow flag : set when signed value is out of range

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Flags: Further Explanation
■ Zero flag is set (1) when the result of an operation produces zero in
the destination operand.
■ Sign flag is set (1) when the destination operand is negative. The
flag is clear (0) when the destination is positive.
■ Carry flag is set when the result of an operation generates an
unsigned value that is out of range (too big or too small for the
destination operand).
■ Overflow flag is set when the signed result of an operation is invalid
or out of range.

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Example 1: Flags Registers
■ Assuming that the system uses even parity
■ The following operation:
06 h 00000110
+ 54 h 01010100
5A h => 01011010

Carry flag : 0 Sign flag : 0

Auxiliary carry flag: 0 Parity flag: 1
Zero flag: 0 Overflow flag: 0

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 Design Trade Off:
General Purpose and Specialized Registers

■ General purpose registers maximize flexibility in

instruction design.
■ Special purpose registers permit implicit register
specification in instructions – reduces register field size
in an instruction.
■ No clear “best” design approach.

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How many registers are enough? (Number of
Registers)
■ More registers permit more operands to be held within
the CPU -- reducing memory bandwidth requirements to
some extent.
■ More registers cause an increase in the field sizes
needed to specify registers in an instruction word.
■ Most machines use 8-32 registers.

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How big (wide) ? (Register Length)
■ Address registers should be wide enough to hold the
longest address!
■ Data registers should be wide enough to hold most data
types.
■ Would not want to use 64-bit registers if the vast majority
of data operations used 16 and 32-bit operands.
■ Related to width of memory data bus.
■ Concatenate registers together to store longer formats.

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Control and Status Registers
■ Registers that are used during fetching, decoding and
execution of instructions
■ Many are not visible to the user/programmer
■ Some are visible but can not be (easily) modified to
instructions executed in operating system mode

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 Typical Control and Status Registers
Registers Functions
Program counter (PC)/ Points to the next instruction to be executed.
Instruction pointer (IP)
Instruction register (IR) Contains the instruction being executed.
Memory address register Contains the address of the next memory
(MAR) access.
Memory data/buffer register Contains the current data fetched from
(MBR) memory.
Program status word(s) Superset of condition code register.
(PSW) or FLAGS or Interrupt masks, supervisory modes, etc.
EFLAGS Status information.

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Example Microprocessor Register Organizations

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ALU
■ Consist of functional units
– Arithmetic operations: +, -, *, /
– Boolean operations: OR, AND, NOT, ExOR
– Comparision operations: <, >, =…
– Co-processor for mathematical operations, floating point operations
■ RISC (Reduced Instruction Set Computers)
– Have more than one functional units
■ Functional units can also be implemented using pipeline
architecture (pipeline concept will be discussed later).

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ALU Input and Output Components

Control Unit PSW/EFLAGS/FLAGS

ALU

Registers Registers

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Control Unit (CU)

Memory
Data
Transfer

Control
Input Input Output Output
Unit
Process

ALU

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CU Operations
■ Synchronize all activities in the computer.
■ Generate control signals and transfer them to related components
using the control bas.
■ Decide responses based on the control signals received from other
computer components.
■ Execute instructions by generating control signals based on the
instructions.
■ Control and manage all data transfer between CPU, memory and
I/O.
■ All activities are synchronized based on the timing of the clock.

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Control Signals of CU
Instruction Register (IR)

Decoder

…….
Flags
Signal from other Control Control signals to other
:
system components Unit CPU components
Clock

Control signals to other components outside CPU

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… Control Signals of CU

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Implementation of CU
■ Hardwired
– Sequential circuits
– Generating fixed sequence of control signals
– Implemented using standard digital logic design
– Pro: fast and small (total number of components)
– Con: changes of CU is difficult, requires a new
implementation
– Used in RISC system

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… Implementation of CU

■ Microprogramming
– The values of the control signal for each task are
stored in a control memory
– Control memory is accessed sequentially
– Pro: systematic, easy for modification
– Con: required more components, slow

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Execution of Instruction
■ We have learnt that instructions are executed
sequentially.
■ The process of the execution of an instruction consists of
several steps which is referred to as instruction cycle.
■ Each step in the instruction cycle consists of several
sequence smaller steps known as micro-operation.

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Instruction Cycle
Flow of data and information between registers during the
instruction cycle varies from processor to processor.

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Stages in Instruction Cycle

■ Fetch the instruction

■ Decode it Fetch Cycle
■ Fetch operands, if required
■ Perform the operation
■ Store results, if required Execute Cycle
■ Recognize pending interrupts

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Micro-Operations
■ Every step of the instruction cycle consist of micro-
operation(s) that are executed at specified time.
■ Every micro-operations is activated and control based on
the signals from the control unit.
■ Example of micro-operations:
– Transferring data from one register to another
– Activating the functional unit of ALU
■ Conventional format using register transfer language
(RTL)
– Example: PC  PC +1

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Instruction Cycle: Fetch Cycle
■ 4 registers are involved: PC, MAR, MBR and IR
■ The fetch cycle can be written symbolically using RTL as
t1: MAR  PC
t2: MBR  [MAR]
PC  PC + 1
t3: IR  MBR

t1, t2, t3 is the timing sequence

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… Fetch Cycle
■ t1: Content of PC that points to the next address of the instruction to
be executed is loaded to MAR and transferred to memory on the
address bus. Next, CU will activate the read signal of the memory.
■ t2: Instruction is accessed from the memory and transfer to CPU on
the data bus. This instruction will be loaded into MBR. At the same
time, PC will be incremented so as to point to the next instruction to
be executed.
■ t3: Instruction in MBR is loaded into IR. The opcode of the
instruction will be decoded and translated so as to determine the
micro-operations for the particular instruction.

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… Fetch Cycle
Address Data Control
Bus Bus Bus

PC MAR
Main
CU
Memory
IR MBR

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Indirect Cycle
■ Involve with fetching data from memory before initiating
the execute cycle.
■ Example: ADD AX, [2400]
■ In this cycle, the operand bits of the instruction that is in
IR are transferred to MAR. The read control line is
activated and the data associated with the address will
be read and transfer to MDR.
t1 : MAR  IR [operand]
t2 : MBR  Memory [MAR]

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… Indirect Cycle
Address Data Control
Bas Bas Bas

PC MAR

Main
CU Memory

IR MBR

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Instruction Cycle: Execute Cycle
■ The opcode of the instruction in IR will be decoded and related
control signals will be generated.

Type of opcode Operation

Processor-memory data transfer between CPU and main memory
Processor I/O Data transfer between CPU and I/O module
Data processing Some arithmetic or logical operation on data
Control Alteration of sequence of operations e.g. jump
Combination of above

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Example of Instruction Execution
■ ADD AX, BX
CU will generate signal to ALU (adder) for the
addition of the content of two registers, AX and BX
and store the result in AX.
■ JMP NEXT
(branch to the instruction at location NEXT )
CU will activate the path from MBR to MAR for the
transfer of the address in the operand field (of the
current instruction in IR) to fetch the next instruction.

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Example 2:

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Example 3: MOV AX, NUM
Fetch Cycle Address Data Control
Bas Bas Bas

PC MAR Memory

CU

IR MBR

ACC

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… Example 3
Clock PC MAR MBR IR ACC µoperation
t0 100 - - - - [PC] = 100
t1 100 100 - - - fetch cycle: MAR  PC;
t2 101 100 4450 - - MDR  MEM[MAR]; PC 
PC +1;
t3 101 100 4450 4450 - IR  MBR
t4 101 450 4450 4450 - indirect cycle:
MAR MDR[operand];
t5 101 450 000A 4450 - MBR  MEM[MAR];
t6 101 450 000A 4450 000A execution cycle:
ACC  MBR;

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Interrupt
■ The mechanism by which other system modules may interrupt the
normal processing of the CPU.
■ These devices are 1-10 orders of magnitude slower than the CPU
– CPU can waste vast amounts of processing cycles waiting for these slow
devices to perform their tasks
■ Interrupts let the CPU execute its normal instruction sequence and
pause to service the external devices only when they signal (the
interrupts) that they are ready for the CPU’s attention.
■ The processor and the O/S are responsible for recognizing an
interrupt, suspending the user program, servicing the interrupt, and
then resuming the user program.

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Cause for Interrupts
■ Mechanism by which other modules (e.g. I/O) may interrupt
normal sequence of processing
■ Program
– e.g. overflow, division by zero
■ Timer
– Generated by internal processor timer
– Used in pre-emptive multi-tasking
■ I/O
– from I/O controller
■ Hardware failure
– e.g. memory parity error

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Transfer of Control via Interrupts

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Interrupt Cycle
■ Interrupts are processed in an interrupt cycle within the
overall instruction cycle.
■ At the end of an instruction cycle (operand storage step),
check to see if any interrupts are pending.
■ If there aren’t any, proceed with the next instruction.
■ If there are, then:
– Suspend execution of the program and save its “state”.
– Jump to the interrupt service routine (ISR) and resume the “normal”
instruction cycle.
– When the ISR is completed, restore the state of the program and resume
its operation.

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Multiple Interrupts
■ Disable interrupts
– Processor will ignore further interrupts whilst processing one
interrupt
– Interrupts remain pending and are checked after first interrupt has
been processed
– Interrupts handled in sequence as they occur
■ Define priorities
– Low priority interrupts can be interrupted by higher priority
interrupts
– When higher priority interrupt has been processed, processor
returns to previous interrupt

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Transfer of Control with Multiple Interrupts

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Instruction Cycle with Interrupts

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Summary of Instruction Cycle

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Instruction Cycle (with Interrupts) -
State Diagram

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