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LEAKAGE POWER OPTIMIZED
SEQUENTIAL CIRCUITS FOR USE

IN NANOSCALE VLSI SYSTEMS
Abstract :
i. As the density and operating speed of CMOS VLSI
chips increases, leakage power dissipation
becomes more and more significant. Therefore it
is necessary to reduce the leakage power of
portable battery operated devices.
ii. This paper proposes three power reduction
techniques such as transistor stacking, self-
adjustable voltage level circuit and reverse body
bias for use in sequential circuits like D flip-flops
and shift register.
iii. This work analyses the power of three different
implementations of D flip-flops using pass
transistors, transmission gates and gate diffusion
input gates.
d
iv. All the designs are simulated with and without the
application of leakage reduction techniques and the
readings are presented. Also two bit, four bit and eight
bit shift registers are simulated with stack and reverse
body bias leakage reduction techniques.
v. The circuits are simulated with MOSFET models of
level 54 using HSPICE in 65 nm process technology with
a supply voltage of 1 volt. Simulation results show that
the proposed pass transistor based D flip-flop circuit has
the least leakage power dissipation.
vi. In the case of shift registers the combined stack and
reverse body bias method gives minimum leakage power
of 19.51nW, 32.16nW and 98.34nW for two bit, four bit
and eight bit shift registers respectively.
1.Introduction
• Increasing demand for mobile electronic devices such as cellular
phones, laptop computers and personal digital assistants
requires the use of power efficient VLSI circuits.
• To minimize the power consumption and to increase the battery
life time, the supply voltage Vdd has been scaled down
continuously. But the propagation delay Tpd of a circuit is
inversely proportional to the square of the difference between
the supply voltage Vdd and the threshold voltage Vt of the
transistors.
• So scaling down the supply voltage, without scaling down the
threshold voltage increases the propagation delay. However the
threshold voltage scaling results in substantial increase of sub-
threshold leakage current, which increases the leakage or static
power dissipation of the VLSI circuits . Leakage power
dissipation is the power dissipated by the circuit when it is in
sleep mode or standby mode. Leakage power is given by [1]
Introduction contd…
• This power dominates dynamic power especially in
deep submicron circuits and also in circuits that
remains in idle mode for a long time such as cell
phones. Therefore in this paper the focus is on the
reduction of leakage power dissipation. The leakage
current consists of various components, such as sub-
threshold leakage, gate leakage, reverse-biased
junction leakage, gate-induced drain leakage [3].
Among these, sub-threshold leakage and gate leakage
are dominant. The sub-threshold leakage current of a
MOS device can be modeled as follows [2]:
• Isubth=I0 exp[(Vgs-Vt) / (n VT) ] [1- exp (-Vds/VT)] -----
(2)
• And I0=ueff Cox (W/L)VT2 ------(3)
2.Related Work
In [4] Hamid et al. proposes a conventional data-retention
scheme which uses a balloon latch applied to a transmission
gate flip-flop. In this the balloon latch and some switches which
are not in the critical paths use high threshold voltage
transistors to reduce their leakage power. This scheme requires
extra data-preserving balloon latches and complicated timing
for transferring data back and forth between balloon latches
and flip- flops on any transition from power down to active
mode and vice versa.
In [5] David Levacq designed an ultra low power flip-flop using
two ultra-low leakage diodes and analysis of master slave
latches and flip-flops is discussed in [6].
In [7] Linfeng et al. proposes a new transmission gate flip-flop
based on dual threshold CMOS technique to reduce it’s leakage
power. In this low threshold transistors are assigned to critical
paths of the circuits to enhance the performance, while high
Related work contd….
• In [8] Morgenstein et al. describes the

implementation of D flip –flop using GDI
gates. The analysis of single edge triggered flip
flops is presented by D. Markovic et al. in [9]
and Nedovic et al. in [10] describes the design
of dual edge triggered flip-flops. Sagi Fisher et
al. in [11] proposes two architectures for
implementing flip-flop cells by integrating a
GDI multiplexer in their design.
3. CMOS Implementation of D flip
flops
• In this section three different implementations
of D flip-flops in CMOS logic are presented.
The D flip-flop
• combines a pair of master and slave D latch.
• Can be done
Fig.D flip flop using pass transistors
Fig1.D flip flop using pass transistors

Fig2.D flip flop using Transmission gates
the design – II that uses transmission gates and inverters [12]. At the negative edge of the
clock,
transmission gates T1 and T4 are ON and transmission gates T2 and T3 are OFF.
Fig3.D flip flop using Gate Diffusion Gates(GDI)
design –III with master-slave connection of two GDI D-latches [8]. In this the body gates are
responsible for the state of the circuit. These gates are controlled by the clock (clk) signal and
create two alternative paths.
4. Proposed Leakage Current
Reduction Techniques
• Leakage current control using transistor stack
• Self-adjustable voltage level circuit
• Reverse body bias (RBB)
1. Leakage current control using
transistor stack
• If natural stacking not
posible
Self-adjustable voltage level circuit
SAL contd….
• . During the standby mode
• (SL=1), it provides slightly lower supply voltage to the
load circuit through the weakly ON NMOS transistors
• (N1, N2, N3, ---Nm). So the voltage applied to the load
circuit is given by
• V=V dd-Vn (4)
• where Vn
• is the voltage drop of m weakly ON NMOS transistors.
The drain to source voltage V dsn of the OFF NMOS in
stand mode is expressed as
• Vdsn=VL-Vss=VL (5)
Reverse body bias
(RBB)
• This is an effective approach to reduce leakage power. In this
method, when the circuit enters the standby mode, RBB is applied
to increase the threshold voltage Vt of the transistors and this
decreases the sub-threshold leakage current. Vt is related to the
reverse bias voltage between the source and body Vsb by the
following equation [15]:
• Vt = Vto + gamma{(sqrt(2pif+Vsb)-sqrt(2pif)} (6)
• where Vto is the zero bias Vt for Vsb = 0volt, f is a physical
parameter and is a fabrication-process parameter. Modification of
Vt can be achieved by changing |Vsb| .This method can be either
applied at the full chip level or a finer granularity. The advantage of
this method is that it can be implemented without incurring any
delay penalty. The key issue is that the range of threshold
adjustment is limited, which in turn limits the amount of leakage
reduction.
Simulation Results and Discussion
• In this work three designs of D flip-flops have been implemented in 65 nm
CMOS process technology. The leakage power dissipation of the above circuit
are compared with and without the power reduction techniques. The net lists
of the circuits are extracted and simulated with BSIM4 models of MOSFET
[16]. The simulations are done in HSPICE with a supply voltage of 1 volt, at a
temperature of 27º C with a load capacitance of 50fF.
• The figure 6 shows the input-output waveforms of D flip-flop. The simulation
results of D flip-flop with and without transistor stacking technique is
presented in table 1. In this the leakage power reduction is more (13.05%) in D
flip-flop designed using transmission gates.
• Table 2 shows the leakage power reduction using SAL technique and the
reduction is maximum (34.67%) in transmission gate based D flip-flop. The
design of D flip flops using pass transistors gives the minimum leakage curren
and using this flip flop 2-bit, 4-bit and 8-bit shift registers are implemented.
The leakage power of the shift registers are compared with and without the
stack and reverse body bias reduction techniques.
• The simulation results are shown in table 3 and for the shift registers the
combined effect of RBB and stack method gives the least leakage power.
Figure 7 shows the percentage reduction of leakage power in flip flops and
figure 8 shows the leakage power in shift registers.
Conclusion
Table 1&2 Leakage power of D flip-
flops with stacking&with SAL
DFF circuit Pleak(nw) Pleak(nw) %reduction in
Without With stack P leak
stack
Pass transistors 16.42 14.95 8.95

Transmission gates 29.65 25.78 13.05
Gdi 25.74 23.06 10.41
Dff circuit Pleak(nw) Pleak (nw) %reduction in p leak

Without sal with sal
Pass transistors 16.42 13.46 18.03
Transmission gates 29.65 19.37 34.67
Gdi 25.74 20.94 18.64

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LEAKAGE POWER OPTIMIZED

SEQUENTIAL CIRCUITS FOR USE

• In [8] Morgenstein et al. describes the

Fig1.D flip flop using pass transistors

Pass transistors 16.42 14.95 8.95

Dff circuit Pleak(nw) Pleak (nw) %reduction in p leak

Transmission gates 29.65 19.37 34.67

Gdi 25.74 20.94 18.64

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