COMPUTER ORGANIZATION

AND
ARCHITECTURE
(KCS 302)

Topic: UNIT 2

Jyoti Guglani
Department of Computer Science & Engineering
IMS ENGINEERING COLLEGE
Dr. A.P.J. Abdul Kalam Technical University,
Lucknow
S= A`B`C + A`BC`+AB`C`+ABC
= (A`B` + AB) C + (A`B+AB`) C`
= (A`B +AB`)` C + (A`B+AB`) C`
= (A EXOR B)` C + (A EXOR B)C`
Let A EXOR B is Z
S = Z`C + ZC`
= Z EXOR C
S = (A EXOR B) EXOR C

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Cout = A`BC + AB`C + ABC`+ABC
= A`BC + AB`C + ABC`+ABC + ABC
= ( A`+A) BC + AB`C + ABC` + ABC
= BC + AB`C + ABC` + ABC + ABC
= BC + (B`+B) AC + (C`+C) AB
= BC + AC + AB
FULL ADDER
 Karnaugh Map/K-Map
 Karnaugh Map is a:
 - Rectangle divided into 2n cells with each cell corresponding to an n-variable truth
table value.
 - Each cell is associated with a Minterm or maxterm
 An output(function) value for each input value associated with a minterm is written
in the cell representing the minterm → 1-cell, maxterm → 0-cell
 Each Minterm or maxterm is identified by a decimal number whose binary
representation is identical to the binary interpretation of the input values of the
minterm or maxterm.

Computer Organization
 K-Map
Reduction Rule

To reduce the Boolean expression, first we have

to mark pairs, quads and octets.
Pair – remove one variable
Quad – remove two variables
Octet – remove three variables

Note – To get the optimum reduction, priority is given

to octet first, then quad and then pair.

Computer Organization
 Two-Variable Map

x2 x1
x1 0 1 x2 0 1
0 1 0 2
0 m0 m1 0 m0 m2
2 3
OR 1 3
1 m2 m3 1 m1 m3

NOTE: ordering of variables is IMPORTANT for f(x1,x2), x1 is the row, x2 is the column.

Cell 0 represents x1’x2’; Cell 1 represents x1’x2; etc. If a minterm is present in the function,
then a 1 is placed in the corresponding cell.
Any two adjacent cells in the map differ by ONLY one variable, which appears
complemented in one cell and un complemented in the other- (Gray Code)

Computer Organization
 2-Variable Map -- Example

 f(x1,x2) = x1’x2’+ x1’x2 + x1x2’

= m0 + m 1 + m 2

 1s placed in K-map for specified

minterms m0, m1, m2

 Grouping (ORing) of 1s allows

simplification

Computer Organization
 Three-Variable Map

yz
x 00 01 11 10
0 1 3 2
0 m0 m1 m3 m2
4 5 7 6
1 m4 m5 m7 m6

Note: variable ordering is (x,y,z); yz specifies column, x specifies row.

-Each cell is adjacent to three other cells (left or right or top or bottom or edge
wrap)
Notice the code sequence: 00 01 11 10 – a Gray code

Computer Organization
C out =A`BC + AB`C + ABC`+ABC
Drawback of Ripple carry Adder and
can be overcome by Look ahead Carry
Adder
In ripple carry adders, for each adder block, the two bits
that are to be added are available instantly. However, each
adder block waits for the carry to arrive from its previous
block. So, it is not possible to generate the sum and carry
of any block until the input carry is known. The next block
waits for the carry from the previous block. So there will
be a considerable time delay which is carry propagation
delay.
A carry look-ahead adder reduces the propagation delay
by providing the carry to all adder circuit at the same time.
Look Ahead Carry Adder
Advantages –
The propagation delay is reduced.
It provides the fastest addition logic.

Disadvantages –
The Carry Look-ahead adder circuit gets complicated
as the number of variables increase.
The circuit is costlier as it involves more number of
hardware.
Look Ahead Carry Generator/Adder
Let us now consider two new variables, Carry Generate (Gi) and Carry Propagate (Pi).
Pi = Ai ⊕ Bi
G = A . B
i i i

The output is given as;

Si = Pi ⊕ Ci
We can calculate the output carry C1, C2, C3, and C4 using the above derived equations as:
Ci+1 = Gi + Pi Ci
When i=0;
C1 = G0 + P0C0
When i = 1;
C2 = G1 + P1C1 = G1 + P1 (G0 + P0C0)
When i = 2;
C3 = G2 + P2C2 = G2 + P2 (G1 + P1 (G0 + P0C0) )
When I = 3:
C4 = G3 + P3C3 = G3 + P3 (G2 + P2 (G1 + P1 (G0 + P0C0) ))

Thus, Carry C1, C2, C3 and C4 depends on C0. As soon as C0 generate all carries are generated at
the same so the problem of Propagation delay of Rippler adder circuit overcomes by this circuit.
4 Bit Adder / Subtractor Circuit
A Binary Adder-Subtractor is one which is capable
of both addition and subtraction of binary numbers in
one circuit itself.
EX OR gate property that if one input is 1 than other
input is complemented and get at the output of gate.
And if one input is 0 than other input as it is at the
output of
A gate B Output
0 0 0
0 1 1
1 0 1
1 1 0
When M=0 it act as ADDER Circuit and when M=1 it act as
SUBSTRACTOR Circuit
BOOTH’S ALGORITHM OF MULTIPLICATION

Booth’s algorithm for two complements multiplication:

1.Multiplier and multiplicand are placed in the Q and M register respectively.
2.Result for this will be stored in the A and Q registers.
3.Initially, A and Q-1 register will be 0.
4.Multiplication of a number is done in a cycle.
5.A 1-bit register Q-1 is placed right of the least significant bit Q0 of the
register Q.
6.In each of the cycle, Q0 and Q-1 bits will be checked.
1. If Q0 and Q-1 are 11 or 00 then the bits of A, Q and Q-1 are shifted to
the right by 1 bit.
2. If the value is shown 01 then multiplicand is added to A. After
addition, A, Q0, Q-1 register are shifted to the right by 1 bit.
3. If the value is shown 10 then multiplicand is subtracted from A. After
subtraction A, Q0, Q-1 register is shifted to the right by 1 bit.
Answer is AQ : 00010101
Answer is 2’s Complement of AQ with negative sign : - 00010101
Booth : -7 × 3

A Q Q-1 M Operation
0000 0011 0 1001
0111 0011 0 1001 A= A-M
0011 1001 1 1001 ASR
0001 1100 1 1001 ASR
1010 1100 1 1001 A=A+M
1101 0110 0 1001 ASR
1110 1011 0 1001 ASR

The Answer is 2’s complement of AQ with negative sign

:
- 00010101
Booth : -7 × -3

A Q Q-1 M Operation
0000 1101 0 1001
0111 1101 0 1001 A= A-M
0011 1110 1 1001 ASR
1100 1110 1 1001 A=A+M
1110 0111 0 1001 ASR
0101 0111 0 1001 A=A-M
0010 1011 1 1001 ASR
0001 0101 1 1001 ASR

The Answer is AQ : 00010101

Example: Let us multiply (-6) and (2) using Booth’s algorithm.
Solution: (6)10 = (0110)2
As it is given multiplicand, M= (-6)10 =2’s complement of 0110 = 1010
Multiplier, Q= (2)10 = 0010

A Q Q-1 M Operation
0000 0010 0 1010
0000 0001 0 1010 ASR
0110 0001 0 1010 A=A-M
0011 0000 1 1010 ASR
1101 0000 1 1010 A=A+M
1110 1000 0 1010 ASR
1111 0100 0 1010 ASR

Answer is 2’s complement of AQ with negative sign : - 00001100

 ARRAY MULIPLIER

An array multiplier is a digital circuit used for multiplying two binary numbers by
employing an array of full adders and half adders. This array is used for the nearly
simultaneous addition of the various product terms involved. To form the various
product terms, an array of AND gates is used before the Adder array.

A full adder has three input lines and two output lines, where we use this as a
basic building block of an array multiplier. The following is the example of a
4×4 array multiplier. The leftmost bit is the LSB bit of partial product.

The advantages of array multiplier are,

Minimum complexity
Easily scalable
Easily pipelined
Regular shape, easy to place and route

The disadvantages of array multiplier are as follows,

High power consumption
More digital gates resulting in large areas.
RESTORING DIVISION METHOD
Dividend (Q) – 11 Divisor (M) - 3
A Q M Operation
00000 1011 00011
00001 011_ 00011 SL
11110 011_ A=A-M
11110 0110 Q0=0
00001 0110 A=A+M
00010 110_ SL
11111 110_ A=A-M
11111 1100 Qo=0
00010 1100 A=A+M
00101 100_ SL
00010 100_ A=A-M
00010 1001 Qo=1
00101 001_ SL
00010 001_ A=A-M
00010 0011 Qo=1
Remainder Quotient ANSWER
Non-Restoring Division Method
Dividend (Q) – 11 Divisor (M) - 3

A Q M Operation
00000 1011 00011
00001 011_ 00011 SL
11110 011_ A=A-M
11110 0110 Qo=0
11100 110_ SL
11111 110_ A=A+M
11111 1100 Qo=0
11111 100_ SL
00010 100_ A=A+M
00010 1001 Qo=1
00101 001_ SL
00010 001_ A=A-M
00010 0011 Qo=1
Remainder Quotient Answer
 Basic Gates: NOT

 NOT Gate: complement of Input

 Can be written as NOTA / A’

Logic diagram Truth Table

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 Basic Gates: AND
 AND Gate: output is high ,when all the inputs are
high.
 Can be written as (A • B) / (AB)

Logic diagram Truth Table

 Note: AND Gate follows Associative and Commutative laws.

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 Basic Gates: OR

OR Gate: Output is high when any one or all inputs

are high.
 Can be written as (A + B)
Logic diagram Truth Table

 Note: AND Gate follows Associative and Commutative laws .

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 Arithmetic Gates - XOR Gate
EXCLUSIVE-OR(commonly written as XOR) in XOR gate the output of an XOR
gate is true only when exactly one of its inputs is true.
XOR-(A’B+AB’)

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 Arithmetic Gates - XNOR Gate
EXCLUSIVE-NOR(commonly written as XNOR) is the NOT of XOR
gate. i.e. the logic gate that obtained by complementing the output
of an XOR gate. XNOR=(A’B+AB’)’ = AB + A`B`

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 Universal Gates: NAND

 NAND Gate: Compliment of AND Gate.

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 Universal Gates: NOR
 NOR Gate: Compliment of OR Gate.
Logic diagram Truth Table

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Answer is 10.00111 * 2-¹
Answer is 10001100 * 2 -³
Floating Point Division
1.0000 * 2² / 1.0100 *2³ = 0.1101 * 2-¹

In Division Exponents are Subtracted and Mantissa are

Divided.
Exponents : 2 – 3 = -1
Mantissa : 1.0000/1.0100 = 1/ 1.25 = 0.8 = 0.1101

Answer is 0.1101 * 2-¹

 Arithmetic Logic Unit
An arithmetic logic unit (ALU) is a digital circuit used to
perform arithmetic and logic operations. It represents the
fundamental building block of the central processing unit
(CPU) of a computer. Modern CPUs contain very powerful and
complex ALUs. In addition to ALUs, modern CPUs contain a
control unit (CU).
It is having Arithmetic Circuit block for arithmetic operations
such as addition, subtraction, transfer, increment , decrement etc.
It is having Logic circuit block to perform logical operations such
as AND,OR,NOT and EX-OR.
At a time either arithmetic or logical operation will be performed
and that will be selected by selection lines of 4:1 Multiplexer.
ALU Circuit Description
S3 S2 will select the operations

S3 S2 Operation
0 0 Arithmetic
0 1 Logical
1 0 Shift Right
1 1 Shift Left

A and B are the input numbers and S1 S0 are the select

lines of Multiplexers of Arithmetic and logic circuit
Unit.
THANK YOU
STUDENTS

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