article

A Systematic Design Space Exploration of MPSoC Based on Synchronous Data Flow Specification

Authors:

Choonseung Lee,

Soonhoi HaAuthors Info & Claims

Journal of Signal Processing Systems, Volume 58, Issue 2

Pages 193 - 213

https://doi.org/10.1007/s11265-009-0351-6

Published: 01 February 2010 Publication History

Abstract

The design space exploration (DSE) problem addressed in this paper is to find out Multi-Processor System-on-Chip architectures for a given multi-task signal processing application aiming to minimize the system cost while satisfying the real-time constraints. It involves the following three sub-problems: selecting processing elements, mapping an application to the processing elements, and determining the communication architecture. The proposed approach consists of two inner design loops: one is a cosynthesis loop that determines the selection of PEs and the mapping of a given application to the PEs, and the other is a communication architecture synthesis loop to find the hierarchical shared bus architecture. We specify an application with a synchronous data flow (SDF) model of computation that has well-matched semantics with the algorithmic function flow in DSP applications. To solve the problem, we need to compare the estimated performance of design points and choose the best ones. The common method of simulation-based performance estimation is too time-consuming to explore the wide design space. Thanks to the analytical properties of the SDF model, the performance estimation can be done without HW/SW cosimulation in both loops. A global feedback from the communication architecture synthesis step to the cosynthesis step forms the proposed DSE framework. We use a real-life application, 4-channel Digital Video Recorder (DVR) that is a multi-task example, as well as randomly generated graphs to show the viability of the proposed approach.

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Cited By

Smirnov FReimann FTeich JGlaß M(2018)Automatic Optimization of the VLAN Partitioning in Automotive Communication NetworksACM Transactions on Design Automation of Electronic Systems10.1145/327812024:1(1-23)Online publication date: 21-Dec-2018
https://dl.acm.org/doi/10.1145/3278120
Smirnov FReimann FTeich JHan ZGlaß M(2018)Automatic Optimization of Redundant Message Routings in Automotive NetworksProceedings of the 21st International Workshop on Software and Compilers for Embedded Systems10.1145/3207719.3207725(90-99)Online publication date: 28-May-2018
https://dl.acm.org/doi/10.1145/3207719.3207725
Li ZPark HMalik AWang KSalcic ZKuzmin BGla MTeich J(2017)Using design space exploration for finding schedules with guaranteed reaction times of synchronous programs on multi-core architectureJournal of Systems Architecture: the EUROMICRO Journal10.1016/j.sysarc.2016.12.00374:C(30-45)Online publication date: 1-Mar-2017
https://dl.acm.org/doi/10.1016/j.sysarc.2016.12.003
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A Systematic Design Space Exploration of MPSoC Based on Synchronous Data Flow Specification
1. General and reference
  1. Cross-computing tools and techniques

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Published In

cover image Journal of Signal Processing Systems

Journal of Signal Processing Systems Volume 58, Issue 2

Feb 2010

157 pages

ISSN:1939-8018

EISSN:1939-8115

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Copyright © Copyright © 2010 Springer Science+Business Media, LLC.

Publisher

Kluwer Academic Publishers

United States

Publication History

Published: 01 February 2010

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Cited By

Smirnov FReimann FTeich JGlaß M(2018)Automatic Optimization of the VLAN Partitioning in Automotive Communication NetworksACM Transactions on Design Automation of Electronic Systems10.1145/327812024:1(1-23)Online publication date: 21-Dec-2018
https://dl.acm.org/doi/10.1145/3278120
Smirnov FReimann FTeich JHan ZGlaß M(2018)Automatic Optimization of Redundant Message Routings in Automotive NetworksProceedings of the 21st International Workshop on Software and Compilers for Embedded Systems10.1145/3207719.3207725(90-99)Online publication date: 28-May-2018
https://dl.acm.org/doi/10.1145/3207719.3207725
Li ZPark HMalik AWang KSalcic ZKuzmin BGla MTeich J(2017)Using design space exploration for finding schedules with guaranteed reaction times of synchronous programs on multi-core architectureJournal of Systems Architecture: the EUROMICRO Journal10.1016/j.sysarc.2016.12.00374:C(30-45)Online publication date: 1-Mar-2017
https://dl.acm.org/doi/10.1016/j.sysarc.2016.12.003
Cilardo AFusella E(2016)Design automation for application-specific on-chip interconnectsIntegration, the VLSI Journal10.1016/j.vlsi.2015.07.01752:C(102-121)Online publication date: 1-Jan-2016
https://dl.acm.org/doi/10.1016/j.vlsi.2015.07.017
Graf SReimann FGlaß MTeich JMarculescu RNicolescu G(2014)Towards scalable symbolic routing for multi-objective networked embedded system design and optimizationProceedings of the 2014 International Conference on Hardware/Software Codesign and System Synthesis10.1145/2656075.2656102(1-10)Online publication date: 12-Oct-2014
https://dl.acm.org/doi/10.1145/2656075.2656102
Jia ZBautista TNúñez APimentel AThompson M(2013)A system-level infrastructure for multidimensional MP-SoC design space co-explorationACM Transactions on Embedded Computing Systems10.1145/2536747.253674913:1s(1-26)Online publication date: 6-Dec-2013
https://dl.acm.org/doi/10.1145/2536747.2536749
Sundari B(2012)Design space exploration of deeply nested loop 2D filtering and 6 level FSBM algorithm mapped onto systolic arrayVLSI Design10.1155/2012/2684022012(15-15)Online publication date: 1-Jan-2012
https://dl.acm.org/doi/10.1155/2012/268402
Leary GChe WChatha KGroeneveld PSciuto DHassoun S(2012)System-level synthesis of memory architecture for stream processing sub-systems of a MPSoCProceedings of the 49th Annual Design Automation Conference10.1145/2228360.2228481(672-677)Online publication date: 3-Jun-2012
https://dl.acm.org/doi/10.1145/2228360.2228481
Kwon SHa S(2010)Serialized parallel code generation framework for MPSoCACM Transactions on Design Automation of Electronic Systems10.1145/1698759.169876115:2(1-27)Online publication date: 2-Mar-2010
https://dl.acm.org/doi/10.1145/1698759.1698761

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