article

Transactional memory

Author:

Håkan GrahnAuthors Info & Claims

Journal of Parallel and Distributed Computing, Volume 70, Issue 10

Pages 993 - 1008

https://doi.org/10.1016/j.jpdc.2010.06.006

Published: 01 October 2010 Publication History

Abstract

Current and future processor generations are based on multicore architectures where the performance increase comes from an increasing number of cores on a chip. In order to utilize the performance potential of multicore architectures the programs also need to be parallel, but writing parallel programs is a non-trivial task. Transactional memory tries to ease parallel program development by providing atomic and isolated execution of code sequences, enabling software composability and protected access to shared data. In addition, transactional memory has the ability to execute atomic code sequences in parallel as long as no data conflicts occur. Transactional memory implementation proposals exist for both hardware and software, as well as hybrid solutions. This special issue on transactional memory introduces transactional memory as a concept, presents an overview of some of the most important approaches so far, and finally, includes five articles that advances the state-of-the-art in transactional memory research.

References

[1]

M. Abadi, A. Birrell, T. Harris, M. Isard, Semantics of transactional memory and automatic mutual exclusion, in: Proc. of the 35th ACM SIGPLAN-SIGACT Symp. on Principles of Programming Languages, 2008, pp. 63-74.

Digital Library

[2]

M. Abadi, T. Harris, M. Mehrara, Transactional memory with strong atomicity using off-the-shelf memory protection hardware, in: Proc. of the 14th ACM Symp. on Principles and Practice of Parallel Programming, 2009, pp. 185-196.

Digital Library

[3]

Adl-Tabatabai, A.-R., Lewis, B.T., Menon, V., Murphy, B.R., Saha, B. and Shpeisman, T., Compiler and runtime support for efficient Software Transactional Memory. In: Proc. of the 2006 Conf. on Programming Language Design and Implementation, pp. 26-37.

[4]

C.S. Ananian, K. Asanovic, B.C. Kuszmaul, C.E. Leiserson, S. Lie, Unbounded transactional memory, in: Proc. of the 11th Int'l Symp. on High-Performance Computer Architecture, 2005, pp. 316-327.

Digital Library

[5]

K. Asanovic, R. Bodik, B.C. Catanzaro, J.J. Gebis, P. Husbands, K. Keutzer, D.A. Patterson, W.L. Plishker, J. Shalf, S.W. Williams, K.A. Yelick, The landscape of parallel computing research: a view from Berkeley, Tech. Rep. UCB/EECS-2006-183, EECS Department, University of California, Berkeley, Dec. 2006.

[6]

L. Baugh, N. Neelakantam, C. Zilles, Using hardware memory protection to build a high-performance, strongly-atomic hybrid transactional memory, in: Proc. of the 35th Int'l Symp. on Computer Architecture, 2008, pp. 115-126.

Digital Library

[7]

Bloom, B.H., Space/time trade-offs in hash coding with allowable errors. Communications of the ACM. v13 i7. 422-426.

[8]

C. Blundell, J. Devietti, E.C. Lewis, M.M.K. Martin, Making the fast case common and the uncommon case simple in unbounded transactional memory, in: Proc. of the 34th Int'l Symp. on Computer Architecture, 2007, pp. 24-34.

Digital Library

[9]

C. Blundell, E.C. Lewis, M.M.K. Martin, Deconstructing transactions: the subtleties of atomicity, in: Fourth Annual Workshop on Duplicating, Deconstructing, and Debunking, 2005.

[10]

Blundell, C., Lewis, E.C. and Martin, M.M.K., Subtleties of transactional memory atomicity semantics. IEEE Computer Architecture Letters. v5 i2.

[11]

J. Bobba, N. Goyal, M.D. Hill, M.M. Swift, D.A. Wood, TokenTM: efficient execution of large transactions with hardware transactional memory, in: Proc. of the 35th Int'l Symp. on Computer Architecture, 2008, pp. 127-138.

Digital Library

[12]

J. Bobba, R. Rajwar, M. Hill, Transactional memory bibliography, http://www.cs.wisc.edu/trans-memory/biblio/index.html, 2010.

[13]

C. Cao Minh, M. Trautmann, J. Chung, A. McDonald, N. Bronson, J. Casper, C. Kozyrakis, K. Olukotun, An effective hybrid transactional memory system with strong isolation guarantees, in: Proc. of the 34th Int'l Symp. on Computer Architecture, 2007, pp. 69-80.

[14]

L. Ceze, J. Tuck, C. Cascaval, J. Torrellas, Bulk disambiguation of speculative threads in multiprocessors, in: Proc. of the 33rd Int'l Symp. on Computer Architecture, 2006, pp. 227-238.

[15]

L. Ceze, J. Tuck, P. Montesinos, J. Torrellas, BulkSC: bulk enforcement of sequential consistency, in: Proc. of the 34th Int'l Symp. on Computer Architecture, 2007, pp. 278-289.

[16]

H. Chafi, J. Casper, B.D. Carlstrom, A. McDonald, C. Cao Minh, W. Baek, C. Kozyrakis, K. Olukotun, A scalable, non-blocking approach to transactional memory, in: Proc. of the 13th Int'l Symp. on High-Performance Computer Architecture, 2007, pp. 97-108.

Digital Library

[17]

Chang, A. and Mergen, M.F., 801 storage: architecture and programming. ACM Transactions on Computer Systems. v6 i1. 28-50.

[18]

Chaudhry, S., Cypher, R., Ekman, M., Karlsson, M., Landin, A., Yip, S., Zeffer, H. and Tremblay, M., Rock: a high-performance sparc CMT processor. IEEE Micro. v29 i2. 6-16.

[19]

Chung, J., Cao Minh, C., McDonald, A., Skare, T., Chafi, H., Carlstrom, B.D., Kozyrakis, C. and Olukotun, K., Tradeoffs in transactional memory virtualization. In: Proc. of the 12th Int'l Conf. on Architectural Support for Programming Languages and Operating Systems, pp. 371-381.

[20]

Colvin, R. and Dongol, B., A general technique for proving lock-freedom. Science of Computer Programming. v74 i3. 143-165.

[21]

Damron, P., Fedorova, A., Lev, Y., Luchangco, V., Moir, M. and Nussbaum, D., Hybrid transactional memory. In: Proc. of the 12th Int'l Conf. on Architectural Support for Programming Languages and Operating Systems, pp. 336-346.

[22]

D. Dice, M. Herlihy, D. Lea, Y. Lev, V. Luchangco, W. Mesard, M. Moir, K. Moore, D. Nussbaum, Applications of the Adaptive Transactional Memory test platform, in: 3rd ACM SIGPLAN Workshop on Transactional Computing, 2008.

[23]

Dice, D., Lev, Y., Moir, M. and Nussbaum, D., Early experience with a commercial hardware transactional memory implementation. In: Proc. of the 14th Int'l Conf. on Architectural Support for Programming Languages and Operating Systems, pp. 157-168.

[24]

Dice, D., Shalev, O. and Shavit, N., Transactional Locking II. In: Lecture Notes in Computer Science, vol. 4167. pp. 194-208.

[25]

D. Dice, N. Shavit, What really makes transactions faster? in: Proc. of the First ACM SIGPLAN Workshop on Languages, Compilers, and Hardware Support for Transactional Computing, 2006.

[26]

D. Dice, N. Shavit, Understanding tradeoffs in Software Transactional Memory, in: Proc. of the 2007 Int'l Symp. on Code Generation and Optimization, 2007, pp. 21-33.

Digital Library

[27]

Dragojević, A., Guerraoui, R. and Kapalka, M., Stretching transactional memory. In: Proc. of the 2009 ACM SIGPLAN Conf. on Programming Language Design and Implementation, pp. 155-165.

[28]

Dubois, M., Skeppstedt, J. and Strenström, P., Essential misses and data traffic in coherence protocols. Journal of Parallel and Distributed Computing. v29 i2. 108-125.

[29]

Eggers, S. and Katz, R., The effect of sharing on the cache and bus performance of parallel programs. In: Proc. of the 3rd Int'l Conf. on Architectural Support for Programming Languages and Operating Systems, pp. 230-242.

[30]

P. Felber, C. Fetzer, T. Riegel, Dynamic performance tuning of Word-Based Software Transactional Memory, in: Proc. of the 13th ACM SIGPLAN Symp. on Principles and Practice of Parallel Programming, 2008, pp. 237-246.

Digital Library

[31]

Felber, P., Gramoli, V. and Guerraoui, R., Elastic transactions. In: LNCS, vol. 5805. pp. 93-107.

[32]

K. Fraser, Practical lock-freedom, Ph.D. Thesis, Cambridge University Computer Laboratory, also available as Technical Report UCAM-CL-TR-579, February 2004.

[33]

Gharachorloo, K., Gupta, A. and Hennessy, J., Two techniques to enhance the performance of memory consistency models. In: Architecture, vol. I. pp. I:355-364.

[34]

Gniady, C. and Falsafi, B., Speculative sequential consistency with little custom storage. In: Proc. of the 11th Int'l Conf. on Parallel Architectures and Compilation Techniques, pp. 179-188.

[35]

C. Gniady, B. Falsafi, T.N. Vijaykumar, Is SC+ILP=RC? in: Proc. of the 26th Int'l Symp. on Computer Architecture, 1999, pp. 162-171.

[36]

J.E. Gottschlich, D.A. Connors, DracoSTM: a practical C++ approach to Software Transactional Memory, in: LCSD '07: Proc. of the 2007 Symp. on Library-Centric Software Design, 2007, pp. 52-66.

Digital Library

[37]

R. Guerraoui, M. Herlihy, B. Pochon, Toward a theory of transactional contention managers, in: Proc. of the 24th ACM Symp. on Principles of Distributed Computing, 2005, pp. 258-264.

[38]

R. Guerraoui, M. Herlihy, B. Pochon, Polymorphic contention management, in: Proc. of the 19th Int'l Symp. on Distributed Computing, 2005, pp. 303-323.

[39]

Hammond, L., Carlstrom, B.D., Wong, V., Chen, M., Kozyrakis, C. and Olukotun, K., Transactional coherence and consistency: simplifying parallel hardware and software. IEEE Micro. v24 i6. 92-103.

[40]

Hammond, L., Carlstrom, B.D., Wong, V., Hertzberg, B., Chen, M., Kozyrakis, C. and Olukotun, K., Programming with transactional coherence and consistency (TCC). In: Proc. of the 11th Int'l Conf. on Architectural Support for Programming Languages and Operating Systems, pp. 1-13.

[41]

L. Hammond, V. Wong, M. Chen, B.D. Carlstrom, J.D. Davis, B. Hertzberg, M.K. Prabhu, H. Wijaya, C. Kozyrakis, K. Olukotun, Transactional memory coherence and consistency, in: Proc. of the 31st Int'l Symp. on Computer Architecture, 2004, pp. 102-113.

[42]

Harris, T. and Fraser, K., Language support for lightweight transactions. In: Object-Oriented Programming, Systems, Languages, and Applications, pp. 388-402.

[43]

Harris, T., Plesko, M., Shinnar, A. and Tarditi, D., Optimizing memory transactions. In: Proc. of the 2006 Conf. on Programming Language Design and Implementation, pp. 14-25.

[44]

M. Herlihy, Impossibility and universality results for wait-free synchronization, in: Proc. of the Seventh ACM Symp. on Principles of Distributed Computing, 1988, pp. 276-290.

Digital Library

[45]

Herlihy, M., Wait-free synchronization. ACM Transactions on Computer Systems. v13 i1. 124-149.

[46]

Herlihy, M., Luchangco, V. and Moir, M., Obstruction-free synchronization: double-ended queues as an example. In: Proc. of the 23rd Int'l Conf. on Distributed Computing Systems, pp. 522-529.

[47]

Herlihy, M., Luchangco, V. and Moir, M., A flexible framework for implementing Software Transactional Memory. In: Proc. of the 21st ACM SIGPLAN Conf. on Object-Oriented Programming Systems, Languages, and Applications, pp. 253-262.

[48]

M. Herlihy, V. Luchangco, M. Moir, W.N. Scherer III, Software Transactional Memory for dynamic-sized data structures, in: Proc. of the 22nd Symp. on Principles of Distributed Computing, 2003, pp. 92-101.

[49]

M. Herlihy, J.E.B. Moss, Transactional memory: architectural support for lock-free data structures, in: Proc. of the 20th Int'l Symp. on Computer Architecture, 1993, pp. 289-300.

[50]

Hofmann, O.S., Rossbach, C.J. and Witchel, E., Maximum benefit from a minimal HTM. In: Proc. of the 14th Int'l Conf. on Architectural Support for Programming Languages and Operating Systems, pp. 145-156.

[51]

S.A.R. Jafri, M. Thottethodi, T.N. Vijaykumar, LiteTM: reducing transactional state overhead, in: Proc. of the 16th Int'l Symp. on High-Performance Computer Architecture, 2010, pp. 81-92.

[52]

Knight, T.F., An architecture for mostly functional languages. In: LFP '86: Proc. of the ACM Lisp and Functional Programming Conference, pp. 105-112.

[53]

S. Kumar, M. Chu, C. Hughes, P. Kundu, A. Nguyen, Hybrid transactional memory, in: Proc. of the 11th ACM SIGPLAN Symp. on Principles and Practice of Parallel Programming, 2006, pp. 209-220.

Digital Library

[54]

Lamport, L., How to make a multiprocessor computer that correctly executes multiprocess programs. IEEE Transactions on Computers. v28 i9. 690-691.

[55]

Lamport, L., Time, clocks, and the ordering of events in a distributed system. Communications of the ACM. v21 i7. 558-565.

[56]

Larus, J.R. and Rajwar, R., Transactional Memory. 2007. Morgan & Claypool Publishers.

[57]

Y. Lev, V. Luchangco, V. Marathe, M. Moir, D. Nussbaum, M. Olszewski, Anatomy of a scalable Software Transactional Memory, in: TRANSACT¿'09: 4th Workshop on Transactional Computing, 2009.

[58]

Y. Lev, J.-W. Maessen, Split Hardware Transactions: true nesting of transactions using best-effort hardware transactional memory, in: Proc. of the 13th ACM SIGPLAN Symp. on Principles and Practice of Parallel Programming, 2008, pp. 197-206.

[59]

Y. Lev, M. Moir, D. Nussbaum, PhTM: phased transactional memory, in: Workshop on Transactional Computing (TRANSACT), 2007.

[60]

Lupon, M., Magklis, G. and Gonzalez, A., FASTM: a log-based hardware transactional memory with fast abort recovery. In: Proc. of the 18th Int'l Conf. on Parallel Architectures and Compilation Techniques, pp. 293-302.

Digital Library

[61]

V.J. Marathe, W.N. Scherer III, M.L. Scott, Design tradeoffs in modern Software Transactional Memory systems, in: Proc. of the 7th Workshop on Languages, Compilers, and Run-time Systems for Scalable Systems, 2004, pp. 1-7.

[62]

Marathe, V.J., Scherer III, W.N. and Scott, M.L., Adaptive Software Transactional Memory. In: Lecture Notes in Computer Science, vol. 3724. pp. 354-368.

[63]

V.J. Marathe, M.F. Spear, C. Heriot, A. Acharya, D. Eisenstat, W.N. Scherer III, M.L. Scott, Lowering the overhead of Software Transactional Memory, in: Proc. of the ACM SIGPLAN Workshop on Transactional Computing, 2006.

[64]

Marathe, V.J., Spear, M.F. and Scott, M.L., Scalable techniques for transparent privatization in Software Transactional Memory. In: Proc. of the 37th Int'l Conf. on Parallel Processing, pp. 67-74.

Digital Library

[65]

McDonald, A., Carlstrom, B.D., Chung, J., Cao Minh, C., Chafi, H., Kozyrakis, C. and Olukotun, K., Transactional memory: the hardware-software interface. IEEE Micro, Special Issue on Top Picks from Architecture Conferences. v27 i1. 67-76.

[66]

A. McDonald, J. Chung, D.C. Brian, C. Cao Minh, H. Chafi, C. Kozyrakis, K. Olukotun, Architectural semantics for practical transactional memory, in: Proc. of the 33rd Int'l Symp. on Computer Architecture, 2006, pp. 53-65.

[67]

McDonald, A., Chung, J., Chafi, H., Cao Minh, C., Carlstrom, B.D., Hammond, L., Kozyrakis, C. and Olukotun, K., Characterization of TCC on chip-multiprocessors. In: PACT '05: Proc. of the 14th Int'l Conf. on Parallel Architectures and Compilation Techniques, pp. 63-74.

Digital Library

[68]

McDougall, R., Extreme software scaling. Queue. v3 i7. 36-46.

[69]

Moir, M., Moore, K. and Nussbaum, D., The Adaptive Transactional Memory test platform: a tool for experimenting with transactional code for Rock. In: 3rd ACM SIGPLAN Workshop on Transactional Computing, ACM Press.

[70]

K.E. Moore, J. Bobba, M.J. Moravan, M.D. Hill, D.A. Wood, LogTM: Log-based Transactional Memory, in: Proc. of the 12th Int'l Symp. on High-Performance Computer Architecture, 2006, pp. 254-265.

[71]

Moravan, M.J., Bobba, J., Moore, K.E., Yen, L., Hill, M.D., Liblit, B., Swift, M.M. and Wood, D.A., Supporting nested transactional memory in LogTM. In: Proc. of the 12th Int'l Conf. on Architectural Support for Programming Languages and Operating Systems, pp. 359-370.

[72]

Olukotun, K. and Hammond, L., The future of microprocessors. Queue. v3 i7. 26-29.

[73]

Pagh, R. and Rodler, F.F., Cuckoo hashing. In: Lecture Notes in Computer Science, vol. 2161. pp. 121-133.

[74]

Pagh, R. and Rodler, F.F., Cuckoo hashing. Journal of Algorithms. v51 i2. 122-144.

[75]

Petrank, E., Musuvathi, M. and Steesngaard, B., Progress guarantee for parallel programs via bounded lock-freedom. In: Proc. of the 2009 ACM SIGPLAN Conf. on Programming Language Design and Implementation, pp. 144-154.

[76]

Rajwar, R. and Goodman, J.R., Transactional lock-free execution of lock-based programs. In: Proc. of the 10th Int'l Conf. on Architectural Support for Programming Languages and Operating Systems, pp. 5-17.

[77]

Rajwar, R. and Goodman, J.R., Transactional execution: toward reliable, high-performance multithreading. IEEE Micro. v23 i6. 117-125.

[78]

R. Rajwar, J.R. Goodman, Speculative lock elision: enabling highly concurrent multithreaded execution, in: Proc. of the 34th ACM/IEEE Int'l Symp. on Microarchitecture, 2001, pp. 294-305.

[79]

R. Rajwar, M. Herlihy, K. Lai, Virtualizing transactional memory, in: Proc. of the 32nd Int'l Symp. on Computer Architecture, 2005, pp. 494-505.

Digital Library

[80]

Ramadan, H.E., Rossbach, C.J., Porter, D.E., Hofmann, O.S., Bhandari, A. and Witchel, E., MetaTM/TxLinux: transactional memory for an operating system. In: Proc. of the 34th Int'l Symp. on Computer Architecture, ACM. pp. 92-103.

[81]

Ramadan, H.E., Rossbach, C.J., Porter, D.E., Hofmann, O.S., Bhandari, A. and Witchel, E., MetaTM/TxLinux: transactional memory for an operating system. IEEE Micro. v28 i1. 42-51.

[82]

P. Ranganathan, V.S. Pai, S.V. Adve, Using speculative retirement and larger instruction windows to narrow the performance gap between memory consistency models, in: Proc. of the 9th ACM Symp. on Parallel Algorithms and Architectures, 1997, pp. 199-210.

[83]

Riegel, T., Felber, P. and Fetzer, C., A lazy snapshot algorithm with eager validation. In: Lecture Notes in Computer Science, vol. 4167. pp. 284-298.

[84]

T. Riegel, C. Fetzer, P. Felber, Time-based transactional memory with scalable time bases, in: Proc. of the 19th ACM Symp. on Parallelism in Algorithms and Architectures, 2007, pp. 221-228.

[85]

T. Riegel, C. Fetzer, P. Felber, Snapshot isolation for Software Transactional Memory, in: Proc. of the First ACM SIGPLAN Workshop on Languages, Compilers, and Hardware Support for Transactional Computing, 2006.

[86]

B. Saha, A.-R. Adl-Tabatabai, R.L. Hudson, C. Cao Minh, B. Hertzberg, McRT-STM: a high performance Software Transactional Memory system for a multi-core runtime, in: Proc. of the 11th ACM SIGPLAN Symp. on Principles and Practice of Parallel Programming, 2006, pp. 187-197.

[87]

D. Sanchez, L. Yen, M.D. Hill, K. Sankaralingam, Implementing signatures for transactional memory, in: Proc. of the 40th IEEE/ACM Int'l Symp. on Microarchitecture, 2007, pp. 123-133.

[88]

W.N. Scherer III, M.L. Scott, Contention management in dynamic Software Transactional Memory, in: Proc. of the ACM PODC Workshop on Concurrency and Synchronization in Java Programs, 2004.

[89]

W.N. Scherer III, M.L. Scott, Advanced contention management for dynamic Software Transactional Memory, in: Proc. of the 24th ACM Symp. on Principles of Distributed Computing, 2005, pp. 240-248.

[90]

N. Shavit, D. Touitou, Software Transactional Memory, in: Proc. of the 14th ACM Symp. on Principles of Distributed Computing, 1995, pp. 204-213.

[91]

Shpeisman, T., Menon, V., Adl-Tabatabai, A.-R., Balensiefer, S., Grossman, D., Hudson, R.L., Moore, K.F. and Saha, B., Enforcing isolation and ordering in STM. In: Proc. of the 2007 ACM SIGPLAN Conf. on Programming Language Design and Implementation, pp. 78-88.

[92]

A. Shriraman, S. Dwarkadas, M.L. Scott, Flexible decoupled transactional memory support, in: Proc. of the 35th Int'l Symp. on Computer Architecture, 2008, pp. 139-150.

Digital Library

[93]

A. Shriraman, M.F. Spear, H. Hossain, V. Marathe, S. Dwarkadas, M.L. Scott, An integrated hardware-software approach to flexible transactional memory, in: Proc. of the 34th Int'l Symp. on Computer Architecture, 2007, pp. 104-115.

Digital Library

[94]

M.F. Spear, L. Dalessandro, V.J. Marathe, M.L. Scott, A comprehensive strategy for contention management in Software Transactional Memory, in: Proc. of the 14th ACM Symp. on Principles and Practice of Parallel Programming, 2009, pp. 141-150.

Digital Library

[95]

M.F. Spear, V.J. Marathe, L. Dalessandro, M.L. Scott, Privatization techniques for Software Transactional Memory, in: Proc. of the 26th ACM Symp. on Principles of Distributed Computing, 2007.

Digital Library

[96]

Stone, J.M., Stone, H.S., Heidelberger, P. and Turek, J., Multiple reservations and the oklahoma update. IEEE Parallel & Distributed Technology. v1 i4. 58-71.

[97]

Sutter, H. and Larus, J., Software and the concurrency revolution. Queue. v3 i7. 54-62.

[98]

F. Tabba, M. Moir, J.R. Goodman, A.W. Hay, C. Wang, NZTM: Nonblocking Zero-Indirection Transactional Memory, in: Proc. of the 21st Symp. on Parallelism in Algorithms and Architectures, 2009, pp. 204-213.

[99]

F. Tabba, C. Wang, J.R. Goodman, M. Moir, NZTM: Nonblocking, Zero-Indirection Transactional Memory, in: Workshop on Transactional Computing (TRANSACT), 2007.

[100]

Thiebaut, D. and Stone, H.S., Footprints in the cache. ACM Transactions on Computer Systems. v5 i4. 305-329.

[101]

S. Tomić, C. Perfumo, C. Kulkarni, A. Armejach, A. Cristal, O. Unsal, T. Harris, M. Valero, EazyHTM: eager-lazy hardware transactional memory, in: Proc. of the 42nd Int'l Symp. on Microarchitecture, 2009, pp. 145-155.

[102]

Tremblay, M. and Chaudhry, S., A third-generation 65 nm 16-core 32-thread plus 32-scout-thread CMT SPARC processor. In: Proc. of the 2008 IEEE Int'l Solid-State Circuits Conference, pp. 82-83.

[103]

L. Yen, J. Bobba, M.M. Marty, K.E. Moore, H. Volos, M.D. Hill, M.M. Swift, D.A. Wood, LogTM-SE: decoupling hardware transactional memory from caches, in: Proc. of the 13th Int'l Symp. on High-Performance Computer Architecture, 2007, pp. 261-272.

[104]

Zhou, P., Qin, F., Liu, W., Zhou, Y. and Torrellas, J., iWatcher: simple, general architectural support for software debugging. IEEE Micro. v24 i6. 50-56.

Cited By

Pasqualin DDiener MDu Bois APilla M(2021)Sharing-Aware Data Mapping in Software Transactional MemoryEmbedded Computer Systems: Architectures, Modeling, and Simulation10.1007/978-3-031-04580-6_32(481-492)Online publication date: 4-Jul-2021
https://dl.acm.org/doi/10.1007/978-3-031-04580-6_32
Pasqualin DDiener MDu Bois APilla M(2020)Characterizing the Sharing Behavior of Applications Using Software Transactional MemoryBenchmarking, Measuring, and Optimizing10.1007/978-3-030-71058-3_1(3-21)Online publication date: 15-Nov-2020
https://dl.acm.org/doi/10.1007/978-3-030-71058-3_1
Mokhtar HHussein NDesai BBernardino JAlmeida ADesai B(2014)A novel mechanism for enhancing software transactional memoryProceedings of the 18th International Database Engineering & Applications Symposium10.1145/2628194.2628212(278-283)Online publication date: 7-Jul-2014
https://dl.acm.org/doi/10.1145/2628194.2628212

Recommendations

Unbounded page-based transactional memory
Proceedings of the 2006 ASPLOS Conference

Exploiting thread level parallelism is paramount in the multicore era. Transactions enable programmers to expose such parallelism by greatly simplifying the multi-threaded programming model. Virtualized transactions (unbounded in space and time) are ...
Unbounded page-based transactional memory
Proceedings of the 2006 ASPLOS Conference

Exploiting thread level parallelism is paramount in the multicore era. Transactions enable programmers to expose such parallelism by greatly simplifying the multi-threaded programming model. Virtualized transactions (unbounded in space and time) are ...
Unbounded page-based transactional memory
Proceedings of the 2006 ASPLOS Conference

Exploiting thread level parallelism is paramount in the multicore era. Transactions enable programmers to expose such parallelism by greatly simplifying the multi-threaded programming model. Virtualized transactions (unbounded in space and time) are ...

Comments

Information & Contributors

Information

Published In

cover image Journal of Parallel and Distributed Computing

Journal of Parallel and Distributed Computing Volume 70, Issue 10

October, 2010

94 pages

ISSN:0743-7315

Issue’s Table of Contents

Copyright © Elsevier Inc. © 2010.

Publisher

Academic Press, Inc.

United States

Publication History

Published: 01 October 2010

Author Tags

Qualifiers

Article

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

3
Total Citations
View Citations
0
Total Downloads

Downloads (Last 12 months)0
Downloads (Last 6 weeks)0

Reflects downloads up to 04 Sep 2024

Other Metrics

View Author Metrics

Citations

Cited By

Pasqualin DDiener MDu Bois APilla M(2021)Sharing-Aware Data Mapping in Software Transactional MemoryEmbedded Computer Systems: Architectures, Modeling, and Simulation10.1007/978-3-031-04580-6_32(481-492)Online publication date: 4-Jul-2021
https://dl.acm.org/doi/10.1007/978-3-031-04580-6_32
Pasqualin DDiener MDu Bois APilla M(2020)Characterizing the Sharing Behavior of Applications Using Software Transactional MemoryBenchmarking, Measuring, and Optimizing10.1007/978-3-030-71058-3_1(3-21)Online publication date: 15-Nov-2020
https://dl.acm.org/doi/10.1007/978-3-030-71058-3_1
Mokhtar HHussein NDesai BBernardino JAlmeida ADesai B(2014)A novel mechanism for enhancing software transactional memoryProceedings of the 18th International Database Engineering & Applications Symposium10.1145/2628194.2628212(278-283)Online publication date: 7-Jul-2014
https://dl.acm.org/doi/10.1145/2628194.2628212

View Options

View options

Get Access

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

Media

Figures

Other

Tables

View Issue’s Table of Contents