Indirect test architecture for SoC testing

A generic model for test architectures in the core-based system-on-chip (SoC) designs consists of source/sink, wrapper, and test access mechanism (TAM). Current test architectures for digital cores assume a direct connection between the core and the tester. In these architectures, the tester establishes a physical link between itself and the core, such that it can directly control the core's design-for-testability (DFT), such as the scan chains or primary inputs. This direct connection undermines the modularity in the generic test architecture by tightly coupling its elements. In this paper, we propose a network-oriented indirect and modular architecture (NIMA) for postfabrication test in an SoC design methodology. In NIMA, test stimuli and expected results for digital cores are first compiled into new formats and subsequently encapsulated into packets. These packets are augmented with control and address bits such that they can autonomously be transmitted to their destination through a switching fabric. Owing to the indirect nature of the connection, embedded autonomous blocks at each core are used to apply the test to the core and compare the test results with expected values. This indirect access to the core decouples test data processing at the core from its communication providing the basis for flexible and modular test design and programming. Moreover, NIMA facilitates remote-access of single or multiple testers to an SoC, and enables the sending of test data to an SoC in-field in order to test the chip in its target system. Finally, NIMA serves in contributing toward the development of new test architectures that benefit from network-centric SoCs. We present a first implementation of NIMA when applied to a number of SoC benchmarks.