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QDI decomposed DIMS method featuring homogeneous/heterogeneous data encoding

Published: 15 September 2011 Publication History

Abstract

The delay-insensitive minterm synthesis (DIMS) method facilitates a robust two-level asynchronous implementation of dual-rail encoded arbitrary combinational logic. However for multilevel realization, logic decomposition becomes indispensable. In this context, this paper describes an elegant technique of performing quasi-delay-insensitive logic decomposition based on set theoretic principles. This includes consideration of generic homogeneous and heterogeneous delay-insensitive data encoding schemes within the purview of the DIMS approach. Through the proposed set theory based logic decomposition rules, it is shown how any combinational logic specification that comprises any number of concurrent inputs can be synthesized in a multilevel fashion on the basis of the DIMS method without compromising on circuit robustness.

References

[1]
J. Sparso, and J. Staunstrup, "Delay-insensitive multi-ring structures," Integration, the VLSI Journal, vol. 15, pp. 313-340, 1993.
[2]
Ligthart, K. Fant, R. Smith, A. Taubin and A. Kondratyev, "Asynchronous design using commercial HDL synthesis tools," Proc. 6th International Symp. on Advanced Research in Asynchronous Circuits and Systems, pp. 114-125, 2000.
[3]
Y. Zhou, D. Sokolov and A. Yakovlev, "Cost-aware synthesis of asynchronous circuits based on partial acknowledgement," Proc. IEEE/ACM International Conf. on Computer-Aided Design, pp. 158-163, 2006.
[4]
Jeong and S.M. Nowick, "Optimization of robust asynchronous circuits by local input completeness relaxation," Proc. Asia and South Pacific Design Automation Conference, pp. 622-627, 2007.
[5]
C.L Seitz, "System Timing," in Introduction to VLSI Systems, C. Mead and L. Conway (Eds.), pp. 218- 262, Addison-Wesley, Reading, MA, 1980.
[6]
A. Kondratyev, M. Kishinevsky, B. Lin, P. Vanbekbergen and A. Yakovlev, "Basic gate implementation of speed-independent circuits," Proc. 31st ACM/IEEE Design Automation Conference, pp. 56- 62, 1994.
[7]
T.S. Anantharaman, "A delay insensitive regular expression recognizer," IEEE VLSI Technical Bulletin, vol. 1, no. 2, pp. 3-15, 1986.
[8]
A.J. Martin, "Compiling communicating processes into delay-insensitive VLSI circuits," Distributed Computing, vol. 1, no. 4, pp. 226-234, December 1986.
[9]
A.J. Martin, "The limitation to delay-insensitivity in asynchronous circuits," Proc. 6th MIT Conf. on Advanced Research in VLSI, pp. 263-278, MIT Press, 1990.
[10]
A.J. Martin and P. Prakash, "Asynchronous nano-electronics: preliminary investigation," Proc. 14th IEEE International Symp. on Asynchronous Circuits and Systems, pp. 58-68, 2008.
[11]
V.I. Varshavsky (Ed.), Self-Timed Control of Concurrent Processes: The Design of Aperiodic Logical Circuits in Computers and Discrete Systems, Chapter 4: Aperiodic Circuits, pp. 77-85, (Translated from the Russian by Alexandre V. Yakovlev), Kluwer Academic Publishers, 1990.
[12]
I. Newman, "On read-once Boolean functions," in M.S. Paterson (Ed.), Boolean Function Complexity, pp. 25-34, London Mathematical Society Lecture Note Series 169, Cambridge University Press, 1992.

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cover image Guide Proceedings
ICANCM'11/ICDCC'11: Proceedings of the 2011 international conference on applied, numerical and computational mathematics, and Proceedings of the 2011 international conference on Computers, digital communications and computing
September 2011
239 pages
ISBN:9781618040305

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World Scientific and Engineering Academy and Society (WSEAS)

Stevens Point, Wisconsin, United States

Publication History

Published: 15 September 2011

Author Tags

  1. DIMS method
  2. asynchronous logic design
  3. combinational logic
  4. delay-insensitive codes
  5. logic decomposition
  6. quasi-delay-insensitivity

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