Article

Gain-based technology mapping for discrete-size cell libraries

Authors:

Yosinori Watanabe,

Alex Kondratyev,

Malgorzata Marek-SadowskaAuthors Info & Claims

DAC '03: Proceedings of the 40th annual Design Automation Conference

Pages 574 - 579

https://doi.org/10.1145/775832.775979

Published: 02 June 2003 Publication History

Abstract

In this paper we describe a technology mapping technique based on the logical effort theory [13]. First, we appropriately characterize a given standard cell library and extract from it a set of cell classes. Each cell-class is assigned a constant-delay model and corresponding load-bounds, which define the conditions of the delay model's validity. Next, we perform technology mapping using the classes determined in the first step. We propose several effective area-optimization heuristics which allow us to apply our algorithm directly to general graphs. Experimental results show that our gain-based mapping algorithm achieves reduced delay with less area, compared to the mapper in SIS [15]. By adjusting the constant delay model associated with each class, we determine the area-delay trade-off curve. We achieve the best area-delay trade-off using a design-specific constant delay models.

References

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Cited By

Liu JNi LLi XZhou MChen LLi XZhao QMa S(2023)AiMap: Learning to Improve Technology Mapping for ASICs via Delay Prediction2023 IEEE 41st International Conference on Computer Design (ICCD)10.1109/ICCD58817.2023.00059(344-347)Online publication date: 6-Nov-2023
https://doi.org/10.1109/ICCD58817.2023.00059
KAWAGUCHI JMASHIKO HKOHIRA Y(2016)Technology Mapping Method Using Integer Linear Programming for Low Power Consumption and High Performance in General-Synchronous FrameworkIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences10.1587/transfun.E99.A.1366E99.A:7(1366-1373)Online publication date: 2016
https://doi.org/10.1587/transfun.E99.A.1366
Amelifard BFallah FPedram M(2009)Low-power fanout optimization using multi threshold voltages and multi channel lengthsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2009.201399228:4(478-489)Online publication date: 1-Apr-2009
https://dl.acm.org/doi/10.1109/TCAD.2009.2013992
Show More Cited By

Index Terms

Gain-based technology mapping for discrete-size cell libraries
1. Applied computing
  1. Arts and humanities
    1. Architecture (buildings)
      1. Computer-aided design
  2. Physical sciences and engineering
    1. Engineering
      1. Computer-aided design

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Information & Contributors

Information

Published In

cover image ACM Conferences

DAC '03: Proceedings of the 40th annual Design Automation Conference

June 2003

1014 pages

ISBN:1581136889

DOI:10.1145/775832

General Chair:
Ian Getreu
Ambric Inc., Portland, OR
,
Program Chairs:
Limor Fix
Intel Semiconductors Ltd., Haifa, Israel
,
Luciano Lavagno
Cadence Berkeley Labs., Berkeley, CA

Copyright © 2003 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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New York, NY, United States

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Published: 02 June 2003

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DAC03: 2003 40th Annual Design Automation Conference

June 2 - 6, 2003

CA, Anaheim, USA

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DAC '03 Paper Acceptance Rate 152 of 628 submissions, 24%;

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

Liu JNi LLi XZhou MChen LLi XZhao QMa S(2023)AiMap: Learning to Improve Technology Mapping for ASICs via Delay Prediction2023 IEEE 41st International Conference on Computer Design (ICCD)10.1109/ICCD58817.2023.00059(344-347)Online publication date: 6-Nov-2023
https://doi.org/10.1109/ICCD58817.2023.00059
KAWAGUCHI JMASHIKO HKOHIRA Y(2016)Technology Mapping Method Using Integer Linear Programming for Low Power Consumption and High Performance in General-Synchronous FrameworkIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences10.1587/transfun.E99.A.1366E99.A:7(1366-1373)Online publication date: 2016
https://doi.org/10.1587/transfun.E99.A.1366
Amelifard BFallah FPedram M(2009)Low-power fanout optimization using multi threshold voltages and multi channel lengthsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2009.201399228:4(478-489)Online publication date: 1-Apr-2009
https://dl.acm.org/doi/10.1109/TCAD.2009.2013992
Singh AOrshansky M(2008)Logic synthesis for reducing leakage power consumption under workload uncertaintyProceedings of the 12th WSEAS international conference on Circuits10.5555/1576429.1576496(351-355)Online publication date: 22-Jul-2008
https://dl.acm.org/doi/10.5555/1576429.1576496
Karandikar SSapatnekar S(2008)Technology Mapping Using Logical Effort for Solving the Load-Distribution ProblemIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2007.90706727:1(45-58)Online publication date: 1-Jan-2008
https://dl.acm.org/doi/10.1109/TCAD.2007.907067
(2007)Congestion Optimization During Technology Mapping and Logic SynthesisRouting Congestion in VLSI Circuits: Estimation and Optimization10.1007/0-387-48550-3_6(189-229)Online publication date: 2007
https://doi.org/10.1007/0-387-48550-3_6
Singh AMani MPuri ROrshansky MSentovich E(2006)Gain-based technology mapping for minimum runtime leakage under input vector uncertaintyProceedings of the 43rd annual Design Automation Conference10.1145/1146909.1147046(522-527)Online publication date: 24-Jul-2006
https://dl.acm.org/doi/10.1145/1146909.1147046
Stamenkovic Z(2006)System-on-Chip Design: Engineering or Art2006 25th International Conference on Microelectronics10.1109/ICMEL.2006.1650978(372-379)Online publication date: 2006
https://doi.org/10.1109/ICMEL.2006.1650978
Karandikar SSapatnekar S(2005)Fast comparisons of circuit implementationsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2005.86272713:12(1329-1339)Online publication date: 1-Dec-2005
https://dl.acm.org/doi/10.1109/TVLSI.2005.862727
Karandikar SSapatnekar S(2004)Logical effort based technology mappingProceedings of the 2004 IEEE/ACM International conference on Computer-aided design10.1109/ICCAD.2004.1382611(419-422)Online publication date: 7-Nov-2004
https://dl.acm.org/doi/10.1109/ICCAD.2004.1382611

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