Article

Optimality study of logic synthesis for LUT-based FPGAs

Authors:

Kirill MinkovichAuthors Info & Claims

FPGA '06: Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays

February 2006

Pages 33 - 40

https://doi.org/10.1145/1117201.1117207

Published: 22 February 2006 Publication History

Abstract

FPGA logic synthesis and technology mapping have been studied extensively over the past 15 years. However, progress within the last few years has slowed considerably (with some notable exceptions). It seems natural to then question whether the current logic synthesis and technology mapping algorithms for FPGA designs are producing near-optimal solutions. Although there are many empirical studies that compare different FPGA synthesis/mapping algorithms, little is known about how far these algorithms are from the optimal (recall that both logic optimization and technology mapping problems are NP-hard if we consider area optimization in addition to delay/depth optimization). In this paper we present a novel method for constructing arbitrarily large circuits that have known optimal solutions after technology mapping. Using these circuits and their derivatives (called LEKO and LEKU, respectively), we show that although leading FPGA technology mapping algorithms can produce close to optimal solutions, the results from the entire logic synthesis flow (logic optimization + mapping) are far from optimal. The best industrial and academic FPGA synthesis flows are around 140 times larger in terms of area on average, and in some cases as much as 500 times larger on LEKU examples. These results clearly indicate that there is much room for further research and improvement in FPGA synthesis.

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https://doi.org/10.1109/TNANO.2023.3326199
Zhang QQu PSun SYu EYan W(2022)Design of Full Digital Signal Generator and FIR Digital Filter System Based on FPGA2022 41st Chinese Control Conference (CCC)10.23919/CCC55666.2022.9901637(4501-4506)Online publication date: 25-Jul-2022
https://doi.org/10.23919/CCC55666.2022.9901637
Józwiak LGawłowski DSlusarczyk A(2018)Benchmarking in digital circuit design automationWSEAS Transactions on Circuits and Systems10.5555/1482050.14820657:4(287-310)Online publication date: 21-Dec-2018
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Index Terms

Optimality study of logic synthesis for LUT-based FPGAs
1. Hardware
  1. Integrated circuits
    1. Logic circuits

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cover image ACM Conferences

FPGA '06: Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays

February 2006

248 pages

ISBN:1595932925

DOI:10.1145/1117201

General Chair:
Steve Wilton
University of British Columbia, Canada
,
Program Chair:
André DeHon
California Institute of Technology, USA

Copyright © 2006 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 22 February 2006

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FPGA06

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FPGA06: ACM/SIGDA International Symposium on Field Programmable Gate Arrays

February 22 - 24, 2006

California, Monterey, USA

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Overall Acceptance Rate 125 of 627 submissions, 20%

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Cited By

Zhang TJiang HLiu WLombardi FLiu LKo SHan J(2023)A Survey of Majority Logic Designs in Emerging Nanotechnologies for ComputingIEEE Transactions on Nanotechnology10.1109/TNANO.2023.332619922(732-739)Online publication date: 2023
https://doi.org/10.1109/TNANO.2023.3326199
Zhang QQu PSun SYu EYan W(2022)Design of Full Digital Signal Generator and FIR Digital Filter System Based on FPGA2022 41st Chinese Control Conference (CCC)10.23919/CCC55666.2022.9901637(4501-4506)Online publication date: 25-Jul-2022
https://doi.org/10.23919/CCC55666.2022.9901637
Józwiak LGawłowski DSlusarczyk A(2018)Benchmarking in digital circuit design automationWSEAS Transactions on Circuits and Systems10.5555/1482050.14820657:4(287-310)Online publication date: 21-Dec-2018
https://dl.acm.org/doi/10.5555/1482050.1482065
Nunna KMehdipour FYoshimura MMurakami K(2012)Methodology for early estimation of hierarchical routing resources in 3D FPGAs2012 IEEE/IFIP 20th International Conference on VLSI and System-on-Chip (VLSI-SoC)10.1109/VLSI-SoC.2012.7332103(213-218)Online publication date: Oct-2012
https://doi.org/10.1109/VLSI-SoC.2012.7332103
Nunna KMehdipour FYoshimura MMurakami K(2012)Methodology for early estimation of hierarchical routing resources in 3D FPGAs2012 IEEE/IFIP 20th International Conference on VLSI and System-on-Chip (VLSI-SoC)10.1109/VLSI-SoC.2012.6379032(213-218)Online publication date: Oct-2012
https://doi.org/10.1109/VLSI-SoC.2012.6379032
Rajavel SAkoglu AStok LDutt NHassoun S(2011)MO-packProceedings of the 48th Design Automation Conference10.1145/2024724.2024908(818-823)Online publication date: 5-Jun-2011
https://dl.acm.org/doi/10.1145/2024724.2024908
Rajavel SAkoglu A(2011)An analytical energy model to accelerate FPGA logic architecture investigation2011 International Conference on Field-Programmable Technology10.1109/FPT.2011.6132683(1-8)Online publication date: Dec-2011
https://doi.org/10.1109/FPT.2011.6132683
Rice JKent K(2009)Case studies in determining the optimal field programmable gate array design for computing highly parallelisable problemsIET Computers & Digital Techniques10.1049/iet-cdt.2008.00423:3(247)Online publication date: 2009
https://doi.org/10.1049/iet-cdt.2008.0042
Hu YShih VMajumdar RHe LFix L(2008)FPGA area reduction by multi-output function based sequential resynthesisProceedings of the 45th annual Design Automation Conference10.1145/1391469.1391478(24-29)Online publication date: 8-Jun-2008
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Jozwiak LChojnacki ASlusarczyk A(2008)High-Quality Circuit Synthesis for Modern Technologies9th International Symposium on Quality Electronic Design (isqed 2008)10.1109/ISQED.2008.4479720(168-173)Online publication date: Mar-2008
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