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Combinational logic synthesis for LUT based field programmable gate arrays

Authors:

Jason Cong and

Yuzheng DingAuthors Info & Claims

ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 1, Issue 2

Pages 145 - 204

https://doi.org/10.1145/233539.233540

Published: 01 April 1996 Publication History

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Abstract

The increasing popularity of the field programmable gate-array (FPGA) technology has generated a great deal of interest in the algorithmic study and tool development for FPGA-specific design automation problems. The most widely used FPGAs are LUT based FPGAs, in which the basic logic element is a K-input one-output lookup-table (LUT) that can implement any Boolean function of up to K variables. This unique feature of the LUT has brought new challenges to logic synthesis and optimization, resulting in many new techniques reported in recent years. This article summarizes the research results on combinational logic synthesis for LUT based FPGAs under a coherent framework. These results were dispersed in various conference proceedings and journals and under various formulations and terminologies. We first present general problem formulations, various optimization objectives and measurements, then focus on a set of commonly used basic concepts and techniques, and finally summarize existing synthesis algorithms and systems. We classify and summarize the basic techniques into two categories, namely, logic optimization and technology mapping, and describe the existing algorithms and systems in terms of how they use the classified basic techniques. A comprehensive list of references is compiled in the attached bibliography.

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Combinational logic synthesis for LUT based field programmable gate arrays
1. Applied computing
  1. Arts and humanities
    1. Architecture (buildings)
      1. Computer-aided design
  2. Physical sciences and engineering
    1. Engineering
      1. Computer-aided design
2. Hardware

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Reviews

Reviewer: Arun Ektare

Research related to the design of logic circuits, both combination al and sequential, has been very productive. The variety of integrated chips (ICs) available to realize combinational functions is fairly large and ranges from basic gates to multiplexers, programmable logic arrays (PLAs), and so on. This variety has given rise to many computer-aided design algorithms, which are scattered in research journals but only sporadically described in textbooks. The currently popular IC in logic synthesis is the field-programmable gate array (FPGA) with look-up table (LUT). A K -input 1-output LUT can realize any Boolean function of up to K variables. This feature has spurred research activity, resulting in a vast literature on LUT FPGA-based algorithms. The authors have made a major contribution to the literature by writing this survey paper, summarizing the work done until very recently. The authors concentrate on combinational logic design, not the sequential logic design for which some references are given in the text. The basic techniques are described using a coherent theoretical framework. The synthesis is described in two steps, which involve logic optimization (transforming a gate-level network to a more suitable form) and technology mapping (in which the network is transformed for a target technology). The paper begins with a section devoted to summarizing problem formulation and representation, which makes substantial use of graph theory. The representations include sum-of products and binary-decision diagrams. The next section, on logic optimization, describes techniques to transform a multilevel logic network into a form more suitable for FPGA. Next comes a section on technology mapping, which describes how the network obtained using the methods in the previous section is transformed into LUT FPGAs. The criteria used to do this include area, depth, and delay minimizations. This detailed section encapsulates all of the techniques available. I highly recommend this paper for research students and for the curious. People starting to work on a research problem often need a concise survey paper that lists relevant publications. This paper fits the bill. For those in industry, it may prove to be a source of useful algorithms. The paper also helps theoreticians and practitioners appreciate the state of the art. My only concern is that this paper is not necessarily a tutorial, since it assumes a certain background.

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cover image ACM Transactions on Design Automation of Electronic Systems

ACM Transactions on Design Automation of Electronic Systems Volume 1, Issue 2

April 1996

156 pages

ISSN:1084-4309

EISSN:1557-7309

DOI:10.1145/233539

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Association for Computing Machinery

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ACM Journals for the Design of Smart and Connected Systems

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Published: 01 April 1996

Published in TODAES Volume 1, Issue 2

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Structural gate decomposition for depth-optimal technology mapping in LUT-based FPGA designs

Flexible multi-mode embedded floating-point unit for field programmable gate arrays

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