Location via proxy:   [ UP ]  
[Report a bug]   [Manage cookies]                
skip to main content
10.1145/1127908.1127913acmconferencesArticle/Chapter ViewAbstractPublication PagesglsvlsiConference Proceedingsconference-collections
Article

Threshold/majority logic synthesis and concurrent error detection targeting nanoelectronic implementations

Published: 30 April 2006 Publication History
  • Get Citation Alerts
  • Abstract

    Many nanometer-scale devices have been proposed and fabricated recently. Several can implement threshold and majority logic efficiently. Research has also begun on design methodologies to keep pace with the development of these devices. Specifically, a threshold logic synthesis tool (TELS) and a majority/minority logic synthesis tool (MALS) have been developed recently. In this paper, we discuss several factorization methods to enhance the efficacy of these two tools significantly. We then augment the design methodology to allow the tools to produce totally self-checking (TSC) circuits which can efficiently implement concurrent error detection. Such circuits can be used to detect run-time errors. Two schemes are used to synthesize TSC circuits - one based on the Berger code and the other on the parity code. We compare and contrast these two schemes. Experimental results establish the effectiveness of the proposed approaches.

    References

    [1]
    D. Goldhaber-Gordon et al., "Overview of nanoelectronic devices," Proc. IEEE, vol. 85, no. 4, pp. 521--540, Apr. 1997.
    [2]
    R. Waser, Nanoelectronics and Information Technology: Advanced Electronic Materials and Novel Devices. Weinheim, Germany: Wiley-VCH, 2003.
    [3]
    J. C. Ellenbogen, "A brief overview of nanoelectronic devices," in Government Microelectronics Applications Conf., Jan. 1998, pp. 13--16.
    [4]
    H. S. P. Wong, "Beyond the conventional transistor," IBM J. Res. Develop., vol. 46, no. 2/3, pp. 133--168, Mar./May 2002.
    [5]
    K. J. Chen, K. Maezawa, and M. Yamamoto, "InP-based high-performance monostable-bistable transition logic elements (MOBILE's) using integrated multiple-input resonant-tunneling devices," IEEE Electron Device Lett., vol. 17, no. 3, pp. 127--129, Mar. 1996.
    [6]
    J. P. Sun, G. I. Haddad, P. Mazumder, and J. N. Schulman, "Resonant tunneling diodes: Models and properties," Proc. IEEE, vol. 86, no. 4, pp. 641--661, Apr. 1998.
    [7]
    P. Mazumder et al., "Digital circuit applications of resonant tunneling devices," Proc. IEEE, vol. 86, no. 4, pp. 664--686, Apr. 1998.
    [8]
    R. H. Mathews et al., "A new RTD-FET logic family," Proc. IEEE, vol. 87, no. 4, pp. 596--605, Apr. 1999.
    [9]
    K. Maezawa, H. Matsuzaki, M. Yamamoto, and T. Otsuji, "High-speed and low-power operation of a resonant tunneling logic gate MOBILE," IEEE Electron Device Lett., vol. 19, no. 3, pp. 80--82, Mar. 1998.
    [10]
    C. Pacha et al., "Resonant tunneling device logic circuits," University of Dortmund and Gerhard-Mercator University of Duisburg, Tech. Rep., July 1999.
    [11]
    P. D. Tougaw and C. S. Lent, "Logical devices implemented using quantum cellular automata," J. Applied Physics, vol. 75, no. 3, pp. 1811--1817, Feb. 1994.
    [12]
    M. T. Niemier and P. M. Kogge, "Exploring and exploiting wire-level pipelining in emerging technologies," in Proc. Int. Symp. Computer Architecture, June 2001, pp. 166--177.
    [13]
    A. O. Orlov et al., "Realization of a functional cell for quantum-dot cellular automata," Science, vol. 277, pp. 928--930, Aug. 1997.
    [14]
    H. Iwamura, M. Akazawa, and Y. Amemiya, "Single-electron majority logic circuits," IEICE Trans. Electron., vol. E-81C, pp. 42--48, Jan. 1998.
    [15]
    H. A. Fahmy and R. A. Kiehl, "Complete logic family using tunneling-phase-logic devices," in Proc. Int. Conf. Microelectronics, Nov. 1999, pp. 22--24.
    [16]
    R. Zhang, P. Gupta, L. Zhong, and N. K. Jha, "Threshold network synthesis and optimization and its application to nanotechnologies," IEEE Trans. Computer-Aided Design, vol. 24, no. 1, pp. 107--118, Jan. 2005.
    [17]
    R. Zhang, P. Gupta, and N. K. Jha, "Synthesis of majority and minority networks and its applications to QCA, TPL and SET based nanotechnologies," in Proc. Int. Conf. VLSI Design, Jan. 2005, pp. 229--234.
    [18]
    D. K. Pradhan, Fault-Tolerant Computer System Design. Englewood Cliffs, NJ: Prentice-Hall, 1996.
    [19]
    S. Muroga, Threshold Logic and its Applications. New York, NY: John Wiley, 1971.
    [20]
    Z. Yu, R. W. Dutton, and R. A. Kiehl, "Circuit/device modeling at the quantum level," IEEE Trans. Electron Devices, vol. 47, no. 10, pp. 1819--1825, Oct. 2000.
    [21]
    Z. Kohavi, Switching and Finite Automata Theory. New York, NY: McGraw-Hill, 1978.
    [22]
    G. D. Hachtel and F. Somenzi, Logic Synthesis and Verification Algorithms. Norwell, MA: Kluwer Academic Publishers, 1998.
    [23]
    N. K. Jha and S.-J. Wang, "Design and synthesis of self-checking VLSI circuits," IEEE Trans. Computer-Aided Design, vol. 12, no. 6, pp. 878--887, June 1993.
    [24]
    K. De, C. Natarajan, D. Nair, and P. Banerjee, "RSYN: A system for automated synthesis of reliable multilevel circuits," IEEE Trans. VLSI Systems, vol. 2, no. 6, pp. 186--195, June 1994.
    [25]
    S. M. Kia and S. Parameswaran, "Design automation of self checking circuits," in Proc. European Design Automation Conf., 1994, pp. 252--257.
    [26]
    T. R. N. Rao, G. L. Feng, M. S. Kolluru, and J. C. Lo, "Novel totally self-checking Berger code checker designers based on generalized Berger code partitioning," IEEE Trans. Computers, vol. 42, no. 8, pp. 1020--1024, Aug. 1993.
    [27]
    R. K. Brayton, G. D. Hachtel, and A. L. Sangiovanni-Vincentelli, "Multilevel logic synthesis," Proc. IEEE, vol. 78, no. 2, pp. 264--300, Feb. 1990.
    [28]
    E. M. Sentovich et al., "Sequential circuit design using synthesis and optimization," in Proc. Int. Conf. Computer Design, Oct. 1992, pp. 328--333.
    [29]
    R. K. Brayton, R. Rudell, A. Sangiovanni-Vincentelli, and A. R. Wang, "MIS: A multiple-level logic optimization system," IEEE Trans. Computer-Aided Design, vol. CAD-6, no. 6, pp. 1062--1081, Nov. 1987.
    [30]
    M. A. Marouf and A. D. Friedman, "Design of self-checking checkers for Berger codes," in Proc. Int. Symp. Fault-Tolerant Comput., June 1978, pp. 179--184.
    [31]
    R. Lisanke, "Logic synthesis and optimization benchmarks," Microelectronics Center of North Carolina, Tech. Rep., 1988.
    [32]
    E. J. McCluskey, "Design techniques for testable embedded error checkers," IEEE Computer, vol. 23, no. 7, pp. 84--88, July 1990.

    Cited By

    View all
    • (2013)Multi-objective optimization of QCA circuits with multiple outputs using genetic programmingGenetic Programming and Evolvable Machines10.1007/s10710-012-9173-614:1(95-118)Online publication date: 1-Mar-2013
    • (2012)Error Rate Estimation for Defective Circuits via Ones CountingACM Transactions on Design Automation of Electronic Systems10.1145/2071356.207136417:1(1-14)Online publication date: 1-Jan-2012
    • (2011)Logic Minimization of QCA Circuits Using Genetic AlgorithmsSoft Computing in Industrial Applications10.1007/978-3-642-20505-7_35(393-403)Online publication date: 2011
    • Show More Cited By

    Index Terms

    1. Threshold/majority logic synthesis and concurrent error detection targeting nanoelectronic implementations

        Recommendations

        Comments

        Information & Contributors

        Information

        Published In

        cover image ACM Conferences
        GLSVLSI '06: Proceedings of the 16th ACM Great Lakes symposium on VLSI
        April 2006
        450 pages
        ISBN:1595933476
        DOI:10.1145/1127908
        Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

        Sponsors

        Publisher

        Association for Computing Machinery

        New York, NY, United States

        Publication History

        Published: 30 April 2006

        Permissions

        Request permissions for this article.

        Check for updates

        Qualifiers

        • Article

        Conference

        GLSVLSI06
        Sponsor:
        GLSVLSI06: Great Lakes Symposium on VLSI 2006
        April 30 - May 1, 2006
        PA, Philadelphia, USA

        Acceptance Rates

        Overall Acceptance Rate 312 of 1,156 submissions, 27%

        Contributors

        Other Metrics

        Bibliometrics & Citations

        Bibliometrics

        Article Metrics

        • Downloads (Last 12 months)0
        • Downloads (Last 6 weeks)0
        Reflects downloads up to 28 Jul 2024

        Other Metrics

        Citations

        Cited By

        View all
        • (2013)Multi-objective optimization of QCA circuits with multiple outputs using genetic programmingGenetic Programming and Evolvable Machines10.1007/s10710-012-9173-614:1(95-118)Online publication date: 1-Mar-2013
        • (2012)Error Rate Estimation for Defective Circuits via Ones CountingACM Transactions on Design Automation of Electronic Systems10.1145/2071356.207136417:1(1-14)Online publication date: 1-Jan-2012
        • (2011)Logic Minimization of QCA Circuits Using Genetic AlgorithmsSoft Computing in Industrial Applications10.1007/978-3-642-20505-7_35(393-403)Online publication date: 2011
        • (2008)Design Methods for Misaligned and Mispositioned Carbon-Nanotube Immune CircuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2008.200327827:10(1725-1736)Online publication date: 1-Oct-2008

        View Options

        Get Access

        Login options

        View options

        PDF

        View or Download as a PDF file.

        PDF

        eReader

        View online with eReader.

        eReader

        Media

        Figures

        Other

        Tables

        Share

        Share

        Share this Publication link

        Share on social media