research-article

Analysis of SystemC actor networks for efficient synthesis

Authors:

Christian Zebelein,

Joachim Keinert,

Christian Haubelt,

Shuvra S. BhattacharyyaAuthors Info & Claims

ACM Transactions on Embedded Computing Systems (TECS), Volume 10, Issue 2

Article No.: 18, Pages 1 - 34

https://doi.org/10.1145/1880050.1880054

Published: 07 January 2011 Publication History

Abstract

Applications in the signal processing domain are often modeled by dataflow graphs. Due to heterogeneous complexity requirements, these graphs contain both dynamic and static dataflow actors. In previous work, we presented a generalized clustering approach for these heterogeneous dataflow graphs in the presence of unbounded buffers. This clustering approach allows the application of static scheduling methodologies for static parts of an application during embedded software generation for multiprocessor systems. It systematically exploits the predictability and efficiency of the static dataflow model to obtain latency and throughput improvements. In this article, we present a generalization of this clustering technique to dataflow graphs with bounded buffers, therefore enabling synthesis for embedded systems without dynamic memory allocation. Furthermore, a case study is given to demonstrate the performance benefits of the approach.

References

[1]

Abdi, S., Peng, J., Yu, H., Shin, D., Gerstlauer, A., Doemer, R., and Gajski, D. 2003. System-on-Chip Environment (SCE Version 2.2.0 beta): Tutorial. University of California, Irvine, CA. Tech. rep. CECS-TR-03-41.

[2]

Baird, M. 2005. IEEE Standard 1666-2005 SystemC Language Reference Manual. IEEE, Los Alamitos, CA.

[3]

Baleani, M., Ferrari, A., Mangeruca, L., Sangiovanni-Vincentelli, A., Freund, U., Schlenker, E., and Wolff, H.-J. 2005. Correct-by-construction transformations across design environments for model-based embedded software development. In Proceedings of the Conference on Design, Automation and Test in Europe. IEEE, Los Alamitos, CA.

Digital Library

[4]

Bhattacharya, B. and Bhattacharyya, S. 2000. Parameterized dataflow modeling of DSP systems. In Proceedings of the International Conference on Acoustics, Speech, and Signal Processing. IEEE, Los Alamitos, CA, 1948--1951.

Digital Library

[5]

Bhattacharyya, S. S., Buck, J. T., Ha, S., and Lee, E. A. 1995. Generating compact code from dataflow specifications of multi-rate signal processing algorithms. IEEE Trans. Circuits Syst. 42, 3, 138--150.

[6]

Bhattacharyya, S. S. and Lee, E. A. 1993. Scheduling synchronous dataflow graphs for efficient looping. J. VLSI Signal Process. Syst. 6, 3, 271--288.

Digital Library

[7]

Bhattacharyya, S. S., Leupers, R., and Marwedel, P. 2000. Software synthesis and code generation for signal processing systems. IEEE Trans. Circuits Syst. 47, 9.

[8]

Bhattacharyya, S. S., Murthy, P., and Lee, E. 1997. APGAN and RPMC: Complementary heuristics for translating DSP block diagrams into efficient software implementations. J. Des. Autom. Embedded Syst.

[9]

Bhattacharyya, S. S. and Murthy, P. K. 1995. Optimal parenthesization of lexical orderings for dsp block diagrams. In Proceedings of the International Workshop on Signal Processing. IEEE, Los Alamitos, CA, 177--186.

[10]

Bilsen, G., Engels, M., Lauwereins, R., and Peperstraete, J. 1996. Cyclo-static dataflow. IEEE Trans. Signal Process. 44, 2, 397--408.

Digital Library

[11]

Buck, J. and Vaidyanathan, R. 2000. Heterogeneous modeling and simulation of embedded systems in el greco. In Proceedings of the 8th International Workshop on Hardware/Software Co-Design. ACM, New York, 142--146.

Digital Library

[12]

Buck, J. T. 1993. Scheduling dynamic dataflow graphs with bounded memory using the token flow model. Ph.D. thesis, Department of Electrical Engineering and Computer Sciences, University of California at Berkeley.

Digital Library

[13]

Choi, C. and Ha, S. 1997. Software synthesis for dynamic data flow graph. In Proceedings of the International Workshop on Rapid System Prototyping. IEEE, Los Alamitos, CA.

Digital Library

[14]

de Kock, E. A., Essink, G., Smits, W. J. M., van der Wolf, P., Brunel, J.-Y., Kruijtzer, W. M., Lieverse, P., and Vissers, K. A. 2000. YAPI: Application modeling for signal processing systems. In Proceedings of the Design Automation Conference. IEEE, Los Alamitos, CA, 402--405.

Digital Library

[15]

Edwards, S. A. and Tardieu, O. 2005. SHIM: A deterministic model for heterogeneous embedded systems. In Proceedings of International Conference on Embedded Software. ACM, New York, 264--272.

Digital Library

[16]

Falk, J., Keinert, J., Haubelt, C., Teich, J., and Bhattacharyya, S. 2008. A generalized static dataflow clustering algorithm for MPSoC scheduling of multimedia applications. In Proceedings of the 8th International Conference on Embedded Software. ACM, New York.

Digital Library

[17]

FZI Research Center for Information Technology. 2007. KaSCPar—Karlsruhe SystemC Parser Suite. http://www.fzi.de/sim/kascpar.html.

[18]

Geilen, M. and Basten, T. 2004. Reactive process networks. In Proceedings of the 4th International Conference on Embedded Software.ACM, New York, 137--146.

Digital Library

[19]

Grötker, T., Liao, S., Martin, G., and Swan, S. 2002. System Design with SystemC. Kluwer Academic Publishers, The Netherlands.

Digital Library

[20]

Hsu, C. and Bhattacharyya, S. S. 2007. Cycle-breaking techniques for scheduling synchronous dataflow graphs. Tech. rep. UMIACS-TR-2007-12, Institute for Advanced Computer Studies, University of Maryland at College Park.

[21]

Hsu, C., Ko, M., and Bhattacharyya, S. S. 2005. Software synthesis from the dataflow interchange format. In Proceedings of the International Workshop on Software and Compilers for Embedded Systems. Springer-Verlag, Berlin, 37--49.

Digital Library

[22]

Jerraya, A. A., Bouchhim, A., and Pétrot, F. 2006. Programming models and HW-SW interfaces abstraction for multi-processor SoC. In Proceedings of the Design Automation Conference. IEEE, Los Alamitos, CA, 280--285.

Digital Library

[23]

Kahn, G. 1974. The semantics of simple language for parallel programming. In Proceedings of the Congress. 471--475.

[24]

Kangas, T., Kukkala, P., Orsila, H., Salminen, E., Hännikäinen, M., Hämäläinen, T. D., Riihimäki, J., and Kuusilinna, K. 2006. UML-based multiprocessor SoC design framework. ACM Trans. Embedded Comput. Syst. 5, 2, 281--320.

Digital Library

[25]

Keinert, J., Streubühr, M., Schlichter, T., Falk, J., Gladigau, J., Haubelt, C., Teich, J., and Meredith, M. 2009. SYSTEMCODESIGNER—an automatic ESL synthesis approach by design space exploration and behavioral synthesis for streaming applications. Trans. Des. Autom. Electr. Syst. 14, 1, 1--23.

Digital Library

[26]

Kianzad, V. and Bhattacharyya, S. S. 2006. Efficient techniques for clustering and scheduling onto embedded multiprocessors. IEEE Trans. Parallel Distrib. Syst. 17, 7, 667--680.

Digital Library

[27]

Lee, E. A. 2004. Overview of the Ptolemy project. Tech. rep. ucb/erl m03/25. Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA.

[28]

Lee, E. A. and Messerschmitt, D. G. 1987. Synchronous data flow. Proc. IEEE 75, 9, 1235--1245.

[29]

Lee, E. A. and Sangiovanni-Vincentelli, A. 1998. A framework for comparing models of computation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17, 12, 1217--1229.

Digital Library

[30]

Patel, H. D. and Shukla, S. K. 2005. Towards a heterogeneous simulation kernel for system- level models: A SystemC kernel for synchronous dataflow models. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24, 1261--1271.

Digital Library

[31]

Pino, J. L., Bhattacharyya, S. S., and Lee, E. A. 1995. A hierarchical multiprocessor scheduling system for dsp applications. In Proceedings of the Conference on Signals, Systems, and Computers. IEEE, Los Alamitos, CA, 122--126.

Digital Library

[32]

Sgroi, M., Lavagno, L., Watanabe, Y., and Sangiovanni-Vincentelli, A. 1999. Quasi-static scheduling of embedded software using equal conflict nets. In Proceedings of the 20th International Conference Application and Theory of Petri Nets. Springer, Berlin.

Digital Library

[33]

Strehl, K., Thiele, L., Gries, M., Ziegenbein, D., Ernst, R., and Teich, J. 2001. FunState—an internal design representation for codesign. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 9, 4, 524--544.

Digital Library

[34]

Stuijk, S., Geilen, M., and Basten, T. 2006a. Exploring trade-offs in buffer requirements and throughput constraints for synchronous dataflow graphs. In Proceedings of the 43rd Annual Conference on Design Automation. ACM, New York, 899--904.

Digital Library

[35]

Stuijk, S., Geilen, M., and Basten, T. 2006b. SDF3: SDF for free. In Proceedings of the 6th International Conference on Application of Concurrency to System Design. IEEE, Los Alamitos, CA, 276--278.

Digital Library

[36]

Thompson, M., Nikolov, H., Stefanov, T., Pimentel, A., Erbas, C., Polstra, S., and Deprettere, E. 2007. A framework for rapid system-level exploration, synthesis, and programming of multimedia MP-SoCs. In Proceedings of the 5^th International Conference on Hardware/Software Codesign and System Synthesis. IEEE, Los Alamitos, CA, 9--14.

Digital Library

[37]

Wiggers, M. H., Bekooij, M. J. G., and Smit, G. J. M. 2007. Efficient computation of buffer capacities for cyclo-static dataflow graphs. In Proceedings of the 44th Annual Conference on Design Automation. ACM, New York, 658--663.

Digital Library

[38]

Zebelein, C., Falk, J., Haubelt, C., and Teich, J. 2008. Classification of general dataflow actors into known models of computation. In Proceedings of the 6th International Conference on Formal Methods and Models for Co-Design. ACM, New York, 119--128.

[39]

Ziegenbein, D., Richter, K., Ernst, R., Thiele, L., and Teich, J. 2002. SPI—a system model for heterogeneously specified embedded systems. IEEE Trans. Very Large Scale Integr. (VLSI) Syst.

Digital Library

Cited By

Cedersjö GJanneck J(2019)TÿchoACM Transactions on Embedded Computing Systems10.1145/336269218:6(1-25)Online publication date: 14-Dec-2019
https://doi.org/10.1145/3362692
Letras MFalk JSchwarzer TTeich J(2019)On the Analytic Evaluation of Schedules via Max-Plus Algebra for DSE of Multi-Core ArchitecturesProceedings of the 22nd International Workshop on Software and Compilers for Embedded Systems10.1145/3323439.3323979(63-71)Online publication date: 27-May-2019
https://dl.acm.org/doi/10.1145/3323439.3323979
Schwarzer TFalk JMüller SLetras MHeidorn CWildermann STeich J(2019)Compilation of Dataflow Applications for Multi-Cores using Adaptive Multi-Objective OptimizationACM Transactions on Design Automation of Electronic Systems10.1145/331024924:3(1-23)Online publication date: 11-Mar-2019
https://dl.acm.org/doi/10.1145/3310249
Show More Cited By

Index Terms

Analysis of SystemC actor networks for efficient synthesis
1. Computing methodologies
  1. Parallel computing methodologies
    1. Parallel programming languages
2. Software and its engineering
  1. Software notations and tools
    1. General programming languages
      1. Language types
        Parallel programming languages

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cover image ACM Transactions on Embedded Computing Systems

ACM Transactions on Embedded Computing Systems Volume 10, Issue 2

December 2010

457 pages

ISSN:1539-9087

EISSN:1558-3465

DOI:10.1145/1880050

Issue’s Table of Contents

Copyright © 2011 ACM.

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ACM Journals for the Design of Smart and Connected Systems

Publication History

Published: 07 January 2011

Received: 01 September 2009

Accepted: 01 April 2009

Revised: 01 February 2009

Published in TECS Volume 10, Issue 2

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Cited By

Cedersjö GJanneck J(2019)TÿchoACM Transactions on Embedded Computing Systems10.1145/336269218:6(1-25)Online publication date: 14-Dec-2019
https://doi.org/10.1145/3362692
Letras MFalk JSchwarzer TTeich J(2019)On the Analytic Evaluation of Schedules via Max-Plus Algebra for DSE of Multi-Core ArchitecturesProceedings of the 22nd International Workshop on Software and Compilers for Embedded Systems10.1145/3323439.3323979(63-71)Online publication date: 27-May-2019
https://dl.acm.org/doi/10.1145/3323439.3323979
Schwarzer TFalk JMüller SLetras MHeidorn CWildermann STeich J(2019)Compilation of Dataflow Applications for Multi-Cores using Adaptive Multi-Objective OptimizationACM Transactions on Design Automation of Electronic Systems10.1145/331024924:3(1-23)Online publication date: 11-Mar-2019
https://dl.acm.org/doi/10.1145/3310249
Falk JNeubauer KHaubelt CZebelein CTeich J(2018)Integrated Modeling Using Finite State Machines and Dataflow GraphsHandbook of Signal Processing Systems10.1007/978-3-319-91734-4_23(825-864)Online publication date: 14-Oct-2018
https://doi.org/10.1007/978-3-319-91734-4_23
Letras MFalk JWildermann STeich J(2017)Automatic Conversion of Simulink Models to SysteMoC Actor NetworksProceedings of the 20th International Workshop on Software and Compilers for Embedded Systems10.1145/3078659.3078668(81-84)Online publication date: 12-Jun-2017
https://dl.acm.org/doi/10.1145/3078659.3078668
Falk JHaubelt CTeich JZebelein C(2017)SysteMoC: A Data-Flow Programming Language for CodesignHandbook of Hardware/Software Codesign10.1007/978-94-017-7358-4_4-2(1-39)Online publication date: 14-Sep-2017
https://doi.org/10.1007/978-94-017-7358-4_4-2
Falk JHaubelt CTeich JZebelein C(2017)SysteMoC: A Data-Flow Programming Language for CodesignHandbook of Hardware/Software Codesign10.1007/978-94-017-7358-4_4-1(1-39)Online publication date: 10-Apr-2017
https://doi.org/10.1007/978-94-017-7358-4_4-1
Falk JHaubelt CTeich JZebelein C(2017)SysteMoC: A Data-Flow Programming Language for CodesignHandbook of Hardware/Software Codesign10.1007/978-94-017-7267-9_4(59-97)Online publication date: 27-Sep-2017
https://doi.org/10.1007/978-94-017-7267-9_4
Cedersjo GJanneck J(2016)Processes and actors: Translating Kahn processes to dataflow with firing2016 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS)10.1109/SAMOS.2016.7818327(21-30)Online publication date: Jul-2016
https://doi.org/10.1109/SAMOS.2016.7818327
Schwarzer TFalk JGlaß MTeich JZebelein CHaubelt CCorporaal HStuijk S(2015)Throughput-optimizing Compilation of Dataflow Applications for Multi-Cores using Quasi-Static SchedulingProceedings of the 18th International Workshop on Software and Compilers for Embedded Systems10.1145/2764967.2764972(68-75)Online publication date: 1-Jun-2015
https://dl.acm.org/doi/10.1145/2764967.2764972
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