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Srivastava PSrivastava P(2022)Preliminary Considerations for Asynchronous Circuit DesignCompletion Detection in Asynchronous Circuits10.1007/978-3-031-18397-3_2(15-28)Online publication date: 16-Sep-2022
https://doi.org/10.1007/978-3-031-18397-3_2
Balasubramanian PYamashita S(2016)Area/latency optimized early output asynchronous full adders and relative-timed ripple carry addersSpringerPlus10.1186/s40064-016-2074-z5:1Online publication date: 12-Apr-2016
https://doi.org/10.1186/s40064-016-2074-z
Balasubramanian PMastorakis N(2011)QDI decomposed DIMS method featuring homogeneous/heterogeneous data encodingProceedings of the 2011 international conference on applied, numerical and computational mathematics, and Proceedings of the 2011 international conference on Computers, digital communications and computing10.5555/2047950.2047965(93-101)Online publication date: 15-Sep-2011
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Basic gate implementation of speed-independent circuits

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DAC '94: Proceedings of the 31st annual Design Automation Conference

June 1994

739 pages

ISBN:0897916530

DOI:10.1145/196244

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Michael Lorenzetti
Mentor Graphics Corp., Wilsonville, OR

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Srivastava PSrivastava P(2022)Preliminary Considerations for Asynchronous Circuit DesignCompletion Detection in Asynchronous Circuits10.1007/978-3-031-18397-3_2(15-28)Online publication date: 16-Sep-2022
https://doi.org/10.1007/978-3-031-18397-3_2
Balasubramanian PYamashita S(2016)Area/latency optimized early output asynchronous full adders and relative-timed ripple carry addersSpringerPlus10.1186/s40064-016-2074-z5:1Online publication date: 12-Apr-2016
https://doi.org/10.1186/s40064-016-2074-z
Balasubramanian PMastorakis N(2011)QDI decomposed DIMS method featuring homogeneous/heterogeneous data encodingProceedings of the 2011 international conference on applied, numerical and computational mathematics, and Proceedings of the 2011 international conference on Computers, digital communications and computing10.5555/2047950.2047965(93-101)Online publication date: 15-Sep-2011
https://dl.acm.org/doi/10.5555/2047950.2047965
Toms WEdwards D(2010)M-of-N Code Decomposition for Indicating Combinational LogicProceedings of the 2010 IEEE Symposium on Asynchronous Circuits and Systems10.1109/ASYNC.2010.12(15-25)Online publication date: 3-May-2010
https://dl.acm.org/doi/10.1109/ASYNC.2010.12
Toms WEdwards D(2009)Prime IndicantsProceedings of the 2009 15th IEEE Symposium on Asynchronous Circuits and Systems (async 2009)10.1109/ASYNC.2009.24(139-150)Online publication date: 17-May-2009
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Milton Sawasaki (2006)Externally Hazard-Free Implementations of Asynchronous Circuits32nd Design Automation Conference10.1109/DAC.1995.250058(718-724)Online publication date: Dec-2006
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Bill Lin (2006)Hierarchical Optimization of Asynchronous Circuits32nd Design Automation Conference10.1109/DAC.1995.250057(712-717)Online publication date: Dec-2006
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Jung SMyers C(2006)Direct synthesis of timed circuits from free-choice STGsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.98642221:3(275-290)Online publication date: 1-Nov-2006
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Carloni LMcMillan KSangiovanni-Vincentelli A(2006)Theory of latency-insensitive designIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.94530220:9(1059-1076)Online publication date: 1-Nov-2006
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Myers CRokicki TMeng T(2006)POSET timing and its application to the synthesis and verification of gate-level timed circuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.76672718:6(769-786)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.766727
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Basic circuits for multi-valued sequential logic

Automatic Synthesis of Gate-Level Speed-Independent Circuits

Decomposition and technology mapping of speed-independent circuits using Boolean relations

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Basic circuits for multi-valued sequential logic

Automatic Synthesis of Gate-Level Speed-Independent Circuits

Decomposition and technology mapping of speed-independent circuits using Boolean relations

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