Collecting signatures to model latency tolerance in high-level simulations of microthreaded cores

The current many-core architectures are generally evaluated using cycle-accurate simulations. However these detailed simulations of the architecture make the evaluation of large programs very slow. Since the focus in many-core architecture is shifting from the performance of individual cores to the overall behavior of the chip, high-level simulations are becoming necessary, which evaluate the same architecture at less detailed level and allow the designer to make quick and reasonably accurate design decisions. We have developed a high-level simulator for the design space exploration of the Microgrid, which is a many-core architecture comprised of many fine-grained multi-threaded cores. This simulator allows us to investigate mapping and scheduling strategies of families (i.e. groups of threads) in developing an operating environment for the Microgrid. The previous method to count and evaluate the workload in basic blocks was not accurate enough. The key problem was that with many concurrent threads the latency of certain instructions is hidden because of the multi-threaded nature of the core. This paper presents a technique to determine the execution time of different types of instructions with thread concurrency. We believe to achieve high accuracy in evaluating programs in the high-level simulator.