research-article

Open access

Benefits of selective packet discard in networks-on-chip

Authors:

Andreas Lankes,

Stefan Wallentowitz,

Andreas HerkersdorfAuthors Info & Claims

ACM Transactions on Architecture and Code Optimization (TACO), Volume 9, Issue 2

Article No.: 12, Pages 1 - 21

https://doi.org/10.1145/2207222.2207228

Published: 15 June 2012 Publication History

Abstract

Today, Network on Chip concepts principally assume inherent lossless operation. Considering that future nanometer CMOS technologies will witness increased sensitivity to all forms of manufacturing and environmental variations (e.g., IR drop, soft errors due to radiation, transient temperature induced timing problems, device aging), efforts to cope with data corruption or packet loss will be unavoidable. Possible counter measures against packet loss are the extension of flits with ECC or the introduction of error detection with retransmission.

We propose to make use of the perceived deficiency of packet loss as a feature. By selectively discarding stuck packets in the NoC, a proven practice in computer networks, all types of deadlocks can be resolved. This is especially advantageous for solving the problem of message-dependent deadlocks, which otherwise leads to high costs either in terms of throughput or chip area. Strict ordering, the most popular approach to this problem, results in a significant buffer overhead and a more complex router architecture. In addition, we will show that eliminating local network congestions by selectively discarding individual packets also can improve the effective throughput of the network. The end-to-end retransmission mechanism required for the reliable communication, then also provides lossless communication for the cores.

References

[1]

Benini, L. and Micheli, G. D. 2002. Networks on chips: A new soc paradigm. Computer 35, 1, 70--78.

Digital Library

[2]

Bjerregaard, T. and Mahadevan, S. 2006. A survey of research and practices of network-on-chip. ACM Comput. Surv. 38, 1, 1.

Digital Library

[3]

Borkar, S. 2005. Designing reliable systems from unreliable components: the challenges of transistor variability and degradation. IEEE Micro 25, 6, 10--16.

Digital Library

[4]

Borkar, S. 2010. The exascale challenge. In Proceedings of the International Symposium on VLSI Design Automation and Testing. 2--3.

[5]

Dally, W. and Towles, B. 2003. Principles and Practices of Interconnection Networks. Morgan Kaufmann Publishers Inc., San Francisco, CA.

Digital Library

[6]

Dally, W. J. and Seitz, C. L. 1987. Deadlock-free message routing in multiprocessor interconnection networks. IEEE Trans. Comput. 36, 5, 547--553.

Digital Library

[7]

Durand, Y., Bernard, C., and Lattard, D. 2005. Faust: On-chip distributed architecture for a 4g baseband modem soc. In Design & Reuse. IEEE Computer Society Press.

[8]

Fallin, C., Craik, C., and Mutlu, O. 2011. Chipper: A low-complexity bufferless deflection router. In Proceedings of the 17th IEEE International Symposium on High Performance Computer Architecture.

Digital Library

[9]

Floyd, S. and Jacobson, V. 1993. Random early detection gateways for congestion avoidance. IEEE/ACM Trans. Netw. 1, 397--413.

Digital Library

[10]

Frantz, A., Cassel, M., Kastensmidt, F., Cota, E., and Carro, L. 2007. Crosstalk- and seu-aware networks on chips. IEEE Des. Test Comput. 24, 4, 340--350.

Digital Library

[11]

Gebremichael-Tesfagiorgis, B., Vaandrager, F. W., Zhang, M., Goossens, K., Rijpkema, E., Ruadulescu, A., Borrione, D., and Paul, W. 2005. Deadlock prevention in sc thereal protocol. In Proceedings of the 13th IFIP WG Advanced Research Working Conference on Correct Hardware Design and Verification Methods.

Digital Library

[12]

Gomez, C., Gomez, M., Lopez, P., and Duato, J., D. 2008. BPS: A bufferless switching technique for NoCs. In Proceedings of the Workshop on Interconnection Network Architectures: 3rd International Conference on High-Performance Embedded Architectures and Compilers. 43--50.

[13]

Goossens, K., Dielissen, J., and Radulescu, A. 2005. Aethereal network on chip: Concepts, architectures, and implementations. IEEE Des. Test 22, 5, 414--421.

Digital Library

[14]

Gratz, P., Kim, C., McDonald, R., Keckler, S., and Burger, D. 2006. Implementation and evaluation of on-chip network architectures. In Proceedings of the International Conference on Computer Design (ICCD'06). 477--484.

[15]

Hansson, A., Goossens, A., and Radulescu, A. 2007. Avoiding message-dependent deadlock in network-based systems on chip. VLSI Des. 10.

[16]

Hayenga, M., Jerger, N. E., and Lipasti, M. 2009. Scarab: a single cycle adaptive routing and bufferless network. In Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture. ACM, New York, NY, 244--254.

Digital Library

[17]

Hoskote, Y., Vangal, S., Singh, A., Borkar, N., and Borkar, S. Sept.-Oct. 2007. A 5-gHz mesh interconnect for a teraflops processor. IEEE Micro 27, 5, 51--61.

Digital Library

[18]

Hu, J., Ogras, U. Y., and Marculescu, R. 2006. System-level buffer allocation for application-specific networks-on-chip router design. IEEE Trans Comput.-Aid. Des. Integr. Circ. Syst. 25, 12, 2919--2933.

Digital Library

[19]

Jantsch, A. and Tehunen H. 2003. Networks on Chip. Kluwer, Hingham, MA.

Digital Library

[20]

Kang, Y. H., Kwon, T.-J., and Draper, J. 2010. Fault-tolerant flow control in on-chip networks. In Proceedings of the 4th ACM/IEEE International Symposium on Networks-on-Chip (NOCS'10). IEEE Computer Society, Los Alamitos, CA, 79--86.

Digital Library

[21]

Kim, J., Liu, Z., and Chien, A. 1994. Compressionless routing: a framework for adaptive and fault-tolerant routing. In Proceedings of the 21st Annual International Symposium on Computer Architecture. 289--300.

Digital Library

[22]

Lai, M., Wang, Z., Gao, L., Lu, H., and Dai, K. 2008. A dynamically allocated virtual channel architecture with congestion awareness for on-chip routers. In Proceedings of the 45th Annual Design Automation Conference (DAC'08). ACM, New York, NY, 630--633.

Digital Library

[23]

Lankes, A., Wild, T., Herkersdorf, A., Sonntag, S., and Reinig, H. 2010. Comparison of deadlock recovery and avoidance mechanisms to approach message dependent deadlocks in on-chip networks. In Proceedings of the 4th ACM/IEEE International Symposium on Networks-on-Chip. 17--24.

Digital Library

[24]

Liu, J. and Delgado-Frias, J. 2006. A shared self-compacting buffer for network-on-chip systems. In Proceedings of the 49th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS'06), Vol. 2. 26--30.

[25]

Mitra, S., Narayanan, V., Spainhower, L., and Xie, Y. 2005. Robust system design from unreliable components. Tech. rep., International Symposium on Computer Architecture.

[26]

Moscibroda, T. and Mutlu, O. 2009. A case for bufferless routing in on-chip networks. In Proceedings of the 36th Annual International Symposium on Computer Architecture (ISCA'09). ACM, New York, NY, 196--207.

Digital Library

[27]

Murali, S., Theocharides, T., Vijaykrishnan, N., Irwin, M. J., Benini, L., and Micheli, G. D. 2005. Analysis of error recovery schemes for networks on chips. IEEE Des. Test 22, 5, 434--442.

Digital Library

[28]

Neishaburi, M. H. and Zilic, Z. 2009. Reliability aware noc router architecture using input channel buffer sharing. In Proceedings of the 19th ACM Great Lakes Symposium on VLSI (GLSVLSI '09). ACM, New York, NY, 511--516.

Digital Library

[29]

Park, D., Nicopoulos, C., Kim, J., Vijaykrishnan, N., and Das, C. R. 2006. Exploring fault-tolerant network-on-chip architectures. In Proceedings of the International Conference on Dependable Systems and Networks (DSN '06). IEEE, Los Alamitos, CA, 93--104.

Digital Library

[30]

Saastamoinen, I., Alho, M., and Nurmi, J. 2003. Buffer implementation for proteo network-on-chip. InProceedings of the International Symposium on Circuits and Systems (ISCAS'03).

[31]

Song, Y. H. and Pinkston, T. M. 2003. A progressive approach to handling message-dependent deadlock in parallel computer systems. IEEE Trans. Paral. Distrib. Syst. 14, 3, 259--275.

Digital Library

[32]

Su, W.-T., Shen, J.-S., and Hsiung, P.-A. 2011. Network-on-chip router design with buffer-stealing. In Proceedings of the 16th Asia and South Pacific Design Automation Conference (ASPDAC'11). IEEE Press, 160--164.

Digital Library

[33]

Wentzlaff, D., Griffin, P., Hoffmann, H., Bao, L., Edwards, B., Ramey, C., Mattina, M., Miao, C.-C., Brown III, J. F., and Agarwal, A. Sept.-Oct. 2007. On-chip interconnection architecture ofthe tile processor. IEEE Micro 27, 5, 15--31.

Digital Library

Cited By

Chang WTseng HKuo CCho YShin SKim SHung CHong J(2014)A traffic-balanced routing scheme for heat balance in 3D networks-on-chipProceedings of the 29th Annual ACM Symposium on Applied Computing10.1145/2554850.2554961(1437-1442)Online publication date: 24-Mar-2014
https://dl.acm.org/doi/10.1145/2554850.2554961
Vonbun MWallentowitz SFeilen MStechele WHerkersdorf A(2013)Evaluation of hop count advantages of network-coded 2D-mesh NoCs2013 23rd International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)10.1109/PATMOS.2013.6662166(134-141)Online publication date: Sep-2013
https://doi.org/10.1109/PATMOS.2013.6662166

Index Terms

Benefits of selective packet discard in networks-on-chip
1. Computer systems organization
  1. Architectures
    1. Distributed architectures
    2. Parallel architectures
      1. Interconnection architectures

Recommendations

Comparison of Deadlock Recovery and Avoidance Mechanisms to Approach Message Dependent Deadlocks in On-chip Networks
NOCS '10: Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip

With the transition from buses to on-chip networks in SoCs the problem of deadlocks in on-chip interconnects arises. Deadlocks can be caused by routing cycles in the network, or by message dependencies, even if the network itself is actually free of ...
Packet loss performance of selective cell discard schemes in ATM switches

In transport-layer protocols such as TCP over ATM networks, a packet is discarded when one or more cells of that packet are lost, and the destination node then requires its source to retransmit the corrupted packet. Therefore, once one of the cells ...
A performance model of partial packet discard and early packet discard schemes in ATM switches

In this paper, we develop a concise performance model of partial packet discard (PPD) and early packet discard (EPD) schemes in ATM switches. We study the performance of PPD and EPD with heterogeneous traffic sources. The sources included Poisson, and ...

Comments

Information & Contributors

Information

Published In

cover image ACM Transactions on Architecture and Code Optimization

ACM Transactions on Architecture and Code Optimization Volume 9, Issue 2

June 2012

177 pages

ISSN:1544-3566

EISSN:1544-3973

DOI:10.1145/2207222

Issue’s Table of Contents

Copyright © 2012 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 15 June 2012

Accepted: 01 March 2012

Revised: 01 October 2011

Received: 01 July 2011

Published in TACO Volume 9, Issue 2

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Research-article
Research
Refereed

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

2
Total Citations
View Citations
510
Total Downloads

Downloads (Last 12 months)49
Downloads (Last 6 weeks)9

Reflects downloads up to 03 Oct 2024

Other Metrics

View Author Metrics

Citations

Cited By

Chang WTseng HKuo CCho YShin SKim SHung CHong J(2014)A traffic-balanced routing scheme for heat balance in 3D networks-on-chipProceedings of the 29th Annual ACM Symposium on Applied Computing10.1145/2554850.2554961(1437-1442)Online publication date: 24-Mar-2014
https://dl.acm.org/doi/10.1145/2554850.2554961
Vonbun MWallentowitz SFeilen MStechele WHerkersdorf A(2013)Evaluation of hop count advantages of network-coded 2D-mesh NoCs2013 23rd International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)10.1109/PATMOS.2013.6662166(134-141)Online publication date: Sep-2013
https://doi.org/10.1109/PATMOS.2013.6662166

View Options

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Get Access

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Article

Media

Figures

Other

Tables

View Issue’s Table of Contents