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A Mapping-Scheduling Algorithm for Hardware Acceleration on Reconfigurable Platforms

Published: 04 July 2014 Publication History
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  • Abstract

    Reconfigurable platforms are a promising technology that offers an interesting trade-off between flexibility and performance, which many recent embedded system applications demand, especially in fields such as multimedia processing. These applications typically involve multiple ad-hoc tasks for hardware acceleration, which are usually represented using formalisms such as Data Flow Diagrams (DFDs), Data Flow Graphs (DFGs), Control and Data Flow Graphs (CDFGs) or Petri Nets. However, none of these models is able to capture at the same time the pipeline behavior between tasks (that therefore can coexist in order to minimize the application execution time), their communication patterns, and their data dependencies. This article proves that the knowledge of all this information can be effectively exploited to reduce the resource requirements and the timing performance of modern reconfigurable systems, where a set of hardware accelerators is used to support the computation. For this purpose, this article proposes a novel task representation model, named Temporal Constrained Data Flow Diagram (TCDFD), which includes all this information. This article also presents a mapping-scheduling algorithm that is able to take advantage of the new TCDFD model. It aims at minimizing the dynamic reconfiguration overhead while meeting the communication requirements among the tasks. Experimental results show that the presented approach achieves up to 75% of resources saving and up to 89% of reconfiguration overhead reduction with respect to other state-of-the-art techniques for reconfigurable platforms.

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    Published In

    cover image ACM Transactions on Reconfigurable Technology and Systems
    ACM Transactions on Reconfigurable Technology and Systems  Volume 7, Issue 2
    June 2014
    199 pages
    ISSN:1936-7406
    EISSN:1936-7414
    DOI:10.1145/2638850
    Issue’s Table of Contents
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Publication History

    Published: 04 July 2014
    Accepted: 01 November 2013
    Revised: 01 August 2013
    Received: 01 February 2013
    Published in TRETS Volume 7, Issue 2

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    Author Tags

    1. Mapping
    2. reconfigurable systems
    3. reconfiguration overheads
    4. runtime reconfiguration
    5. task scheduling

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    • (2020)Resource Partitioning and Application Scheduling with Module Merging on Dynamically and Partially Reconfigurable FPGAsElectronics10.3390/electronics90914619:9(1461)Online publication date: 7-Sep-2020
    • (2020)Sw/Hw Partitioning and Scheduling on Region-Based Dynamic Partial Reconfigurable System-on-ChipElectronics10.3390/electronics90913629:9(1362)Online publication date: 21-Aug-2020
    • (2020)Partitioning and Scheduling with Module Merging on Dynamic Partial Reconfigurable FPGAsACM Transactions on Reconfigurable Technology and Systems10.1145/340370213:3(1-24)Online publication date: 21-Aug-2020
    • (2019)Hybrid scheduling to enhance reliability of real-time tasks running on reconfigurable devicesThe Journal of Supercomputing10.1007/s11227-019-02976-676:6(4701-4730)Online publication date: 27-Aug-2019
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    • (2017)Using graph isomorphism for mapping of data flow applications on reconfigurable computing systemsMicroprocessors and Microsystems10.1016/j.micpro.2016.12.00851(343-355)Online publication date: Jun-2017
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