Research Interests:
Research Interests:
Research Interests:
Research Interests:
Cet article presente le module complementaire « Composants complexes FPGA » de deuxieme annee de DUT Genie Electrique et Informatique Industrielle (GEII). Ce module est compose de deux seances de cours magistraux, huit seances de travaux... more
Cet article presente le module complementaire « Composants complexes FPGA » de deuxieme annee de DUT Genie Electrique et Informatique Industrielle (GEII). Ce module est compose de deux seances de cours magistraux, huit seances de travaux diriges (TDs) et cinq seances de travaux pratiques (TPs) permettant aux etudiants d'approfondir leurs connaissances en VHDL. Durant les TD/TPs, le logiciel Quartus est utilise, ainsi que des cartes FPGAs DE1 d'Altera. Les TDs servent a se rememorer la syntaxe VHDL acquise en premiere annee pour les circuits combinatoires et sequentiels, ainsi qu'a apprehender la description hierarchique et des fonctionnalites non abordees en premiere annee (boucles, fonctions, parametres generiques, …). Apres deux TPs de « remise a niveau », les trois derniers TPs se focalisent sur l'utilisation de la sortie VGA des cartes avec pour but la programmation du jeu « Pong ».
Research Interests:
Research Interests:
Research Interests:
Research Interests:
Research Interests:
Research Interests:
Research Interests:
Research Interests:
Research Interests:
Research Interests:
Cet article presente le module complementaire « Composants complexes FPGA » de deuxieme annee de DUT Genie Electrique et Informatique Industrielle (GEII). Ce module est compose de deux seances de cours magistraux, huit seances de travaux... more
Cet article presente le module complementaire « Composants complexes FPGA » de deuxieme annee de DUT Genie Electrique et Informatique Industrielle (GEII). Ce module est compose de deux seances de cours magistraux, huit seances de travaux diriges (TDs) et cinq seances de travaux pratiques (TPs) permettant aux etudiants d'approfondir leurs connaissances en VHDL. Durant les TD/TPs, le logiciel Quartus est utilise, ainsi que des cartes FPGAs DE1 d'Altera. Les TDs servent a se rememorer la syntaxe VHDL acquise en premiere annee pour les circuits combinatoires et sequentiels, ainsi qu'a apprehender la description hierarchique et des fonctionnalites non abordees en premiere annee (boucles, fonctions, parametres generiques, …). Apres deux TPs de « remise a niveau », les trois derniers TPs se focalisent sur l'utilisation de la sortie VGA des cartes avec pour but la programmation du jeu « Pong ».
Research Interests:
The current trend to globalize the supply chain in the Integrated Circuits (ICs) industry has raised several security concerns including, among others, IC overproduction. Over the past years, logic locking has grown into a prominent... more
The current trend to globalize the supply chain in the Integrated Circuits (ICs) industry has raised several security concerns including, among others, IC overproduction. Over the past years, logic locking has grown into a prominent countermeasure to tackle this threat in particular. Logic locking consists of “locking” an IC with an added primary input, the so-called key, which, unless fed with the correct secret value, renders the ICs unusable. One of the first criteria ensuring the quality of a logic locking technique was the output corruption, i.e., the corruption at the outputs of a locked circuit, for any wrong key value. However, since the introduction of SAT-based attacks, resulting countermeasures have compromised this criterion in favor of a better resilience against such attacks. In this work, we propose SKG-Lock+, a Provably Secure Logic Locking scheme that can thwart SAT-based attacks while maintaining significant output corruption. We perform a comprehensive security an...
Research Interests:
Research Interests:
Research Interests:
Research Interests:
Outsourcing the fabrication process to low-cost locations has become a major trend in the Integrated Circuits (ICs) industry in the last decade. This trend raises the question about untrusted foundries in which an adversary can tamper... more
Outsourcing the fabrication process to low-cost locations has become a major trend in the Integrated Circuits (ICs) industry in the last decade. This trend raises the question about untrusted foundries in which an adversary can tamper with the circuit by inserting a malicious behavior in the ICs, referred to as Hardware Trojans (HTs). The serious impact of HTs in security applications and global economy brings extreme importance to detection as well as prevention techniques. In this paper, we introduce the idea of hardware modified dual modular redundancy (MODMOR): a prevention technique that aims at making the insertion of a stealthy HT more difficult, and at detecting it at run-time.
Research Interests:
Research Interests:
Energy consumption of IoT devices is a very important issue. For this reason, many techniques have been developed to allow IoT nodes to be aware of the amount of available energy. When energy is missing, the device halts and saves its... more
Energy consumption of IoT devices is a very important issue. For this reason, many techniques have been developed to allow IoT nodes to be aware of the amount of available energy. When energy is missing, the device halts and saves its state. One of those techniques is context saving, relying on the use of Non-Volatile Memories (NVM) to store and restore the state of the device. However, this information, as far as IoT devices deal with security, might be the target of attacks, including tampering and theft of confidential data. In this paper, we propose a SECure Context Saving (SECCS) approach that provides a context saving procedure and a hardware module easy to implement inside a System on Chip (SoC). This approach provides both confidentiality and integrity to all the CPU content saved into the target NVM.
Research Interests:
Research Interests:
Research Interests:
HAL is a multi-disciplinary open access archive for the deposit and dissemination of sci-entific research documents, whether they are pub-lished or not. The documents may come from teaching and research institutions in France or abroad,... more
HAL is a multi-disciplinary open access archive for the deposit and dissemination of sci-entific research documents, whether they are pub-lished or not. The documents may come from teaching and research institutions in France or abroad, or from public or private research centers. L’archive ouverte pluridisciplinaire HAL, est destinée au dépôt et a ̀ la diffusion de documents scientifiques de niveau recherche, publiés ou non, émanant des établissements d’enseignement et de recherche français ou étrangers, des laboratoires publics ou privés.
Research Interests:
Research Interests:
Research Interests: Computer Science and IEEE
Many techniques have been proposed in literature to cope with transient, permanent and malicious faults in computing systems. Among these techniques for reliability improvement and fault tolerance, Control Flow Checking allows covering... more
Many techniques have been proposed in literature to cope with transient, permanent and malicious faults in computing systems. Among these techniques for reliability improvement and fault tolerance, Control Flow Checking allows covering any fault affecting the part of the storing elements containing the executable program, as well as all the hardware components handling the program itself and its flow. In [1] the authors proposed a low-overhead solution implementing hardware based control flow monitoring technique. They suggested that control flow error detection could be also used as a solution for enhancing the security of a computing system, preventing the insertion of malicious code in an application. In this paper we present a technique to map a malicious program into another one without structure violation and thus bypassing the control flow detection method.
Research Interests:
Cet article presente une seance de travaux pratiques permettant a des etudiants d'IUT GEII (Genie Electrique et Informatique Industrielle) de decouvrir le fonctionnement du bus de communication I2C. Elle fait partie des enseignements... more
Cet article presente une seance de travaux pratiques permettant a des etudiants d'IUT GEII (Genie Electrique et Informatique Industrielle) de decouvrir le fonctionnement du bus de communication I2C. Elle fait partie des enseignements relatifs a la programmation avancee (en langage C) des microcontroleurs (2eme semestre de la premiere annee). Nous decrivons les principales etapes du TP et nous presentons egalement les resultats d'un sondage illustrant comment ce TP est percu par les etudiants.
Research Interests:
Cet article presente deux seances de Travaux Pratiques (TPs) du module Informatique du premier semestre de DUT Genie Electrique et Informatique Industrielle (GEII). Afin de susciter l'interet des etudiants et de les motiver dans... more
Cet article presente deux seances de Travaux Pratiques (TPs) du module Informatique du premier semestre de DUT Genie Electrique et Informatique Industrielle (GEII). Afin de susciter l'interet des etudiants et de les motiver dans l'apprentissage du langage C, ces TPs ont pour but de developper une version du jeu video Pong, propose par la societe Atari en 1972.
Hardware Trojans have become in the last decade a major threat in the Integrated Circuit industry. Many techniques have been proposed in the literature aiming at detecting such malicious modifications in fabricated ICs. For the most... more
Hardware Trojans have become in the last decade a major threat in the Integrated Circuit industry. Many techniques have been proposed in the literature aiming at detecting such malicious modifications in fabricated ICs. For the most critical circuits, prevention methods are also of interest. The goal of such methods is to prevent the insertion of a Hardware Trojan thanks to ad-hoc design rules. In this paper, we present a novel prevention technique based on approximation. An approximate logic circuit is a circuit that performs a possibly different but closely related logic function, so that it can be used for error detection or error masking where it overlaps with the original circuit. We will show how this technique can successfully detect the presence of Hardware Trojans, with a solution that has a smaller impact than triplication.
Research Interests:
Research Interests:
The outsourcing business model is dominating the semiconductor industry. Due to this loss of control over the design flow, several threats have become a major source of concern, including overproduction and IP overuse. For over a decade,... more
The outsourcing business model is dominating the semiconductor industry. Due to this loss of control over the design flow, several threats have become a major source of concern, including overproduction and IP overuse. For over a decade, several solutions have been proposed in the literature to counteract such threats. These solutions consist in hiding the behavior of the IPs/ICs until the design house securely unlocks them. This way, only unlocked IPs/ICs can be used properly while locked ones produce erroneous data. In this paper, we survey logic locking approaches and discuss locking quality in hiding expected behavior and in resisting to attacks.
Research Interests:
Research Interests:
Research Interests:
Research Interests:
Research Interests:
Research Interests:
Research Interests:
Research Interests:
Research Interests:
Research Interests:
Lors de la conception de chemins de donnees arithmetiques, l’utilisation de l’arithmetique classique (complement a 2) n’est pas toujours optimale en terme de performances. Recemment, il a ete propose d’utiliser d’autres formes... more
Lors de la conception de chemins de donnees arithmetiques, l’utilisation de l’arithmetique classique (complement a 2) n’est pas toujours optimale en terme de performances. Recemment, il a ete propose d’utiliser d’autres formes d’arithmetiques, telle que l’arithmetique redondante, conjointement aux systemes classiques. Cependant, la conception d’un chemin de donnees en redondant s’avere complexe pour un concepteur, d’ou l’utilite d’un cadre de conception ad-hoc. Ce papier presente une methode permettant d’automatiser le recours a plusieurs systemes arithmetiques dans la synthese d’architecture de chemins de donnees arithmetiques.
Research Interests:
This thesis presents the optimisation of data-paths thanks to the automatic incorporation of the redundant number system on VLSI conception flow, in order to make it more accessible. The work is divided into two parts. The goal of the... more
This thesis presents the optimisation of data-paths thanks to the automatic incorporation of the redundant number system on VLSI conception flow, in order to make it more accessible. The work is divided into two parts. The goal of the first part is to incorporate redundant and mixed operators and the knowledge in their usage to low level synthesis. The intrinsic good performances of those operators show the potential interest of such an approach. Three optimisation algorithms have been proposed, based on the choice of the notations used between arithmetical operators. The second part is dedicated to the conception environment in which the algorithmes are going to be used. This environment meets the needs of the arithmetic and provides a circuits description langage with a high level of abstraction. Those algorithms have been applied to several arithmetic circuits and the results confirm that the automatic incorporation of redundant arithmetic improves the performances with regard to...