Floating Point Arithmetic

This chapter is devoted to introducing the theories of interval algebra to people who are interested in applying the interval methods to uncertainty analysis in science and engineering. In view of this purpose, we shall introduce the key concepts of the algebraic theories of intervals that form the foundations of the interval techniques as they are now practised, provide a historical and epistemological background of interval mathematics and uncertainty in science and technology, and finally describe some typical applications that clarify the need for interval computations to cope with uncertainty in a wide variety of scientific disciplines.

Keywords. Interval mathematics, Uncertainty, Quantitative Knowledge, Reliability, Complex interval arithmetic, Machine interval arithmetic, Interval automatic differentiation, Computer graphics, Ray tracing, Interval root isolation.

Recommended Citation:

Hend Dawood. Interval Mathematics as a Potential Weapon against Uncertainty. In S. Chakraverty, editor, Mathematics of Uncertainty Modeling in the Analysis of Engineering and Science Problems. chapter 1, pages 1-38. IGI Global, Hershey, PA, 2014. ISBN 978-1-4666-4991-0.

The final publication is available at IGI Global via http://dx.doi.org/10.4018/978-1-4666-4991-0.ch001

Decimal data processing applications have grown exponentially in recent years thereby increasing the need to have hardware support for decimal arithmetic. In this paper, an improved architecture for efficient Binary Coded Decimal (BCD) addition/subtraction is presented that performs binary addition/subtraction without any extra hardware. The architecture works for both signed and unsigned numbers. The design is runtime reconfigurable and maximum utilization of the hardware is a feature of the architecture. Simulation results show that the proposed architecture is at least 32% better in terms of power-delay product than the existing designs.

This is a draft of a book about algorithms for performing arithmetic, and their implementation on modern computers. We are concerned with software more than hardware - we do not cover computer architecture or the design of computer hardware. Instead we focus on algorithms for efficiently performing arithmetic operations such as addition, multiplication and division, and their connections to topics such as modular arithmetic, greatest common divisors, the Fast Fourier Transform (FFT), and the computation of elementary and special functions. The algorithms that we present are mainly intended for arbitrary-precision arithmetic. They are not limited by the computer word size, only by the memory and time available for the computation. We consider both integer and real (floating-point) computations. The book is divided into four main chapters, plus an appendix. Our aim is to present the latest developments in a concise manner. At the same time, we provide a self-contained introduction for...

In mathematics and computer science, for a given real number, there are situations where we need to perform base number conversion. Floating point numbers are known for their very large and very small number representations such as beyond CPU 64-bit integer supporting range at the expense of loosely controlled accuracy. In Go, floating-point number conversion is only limited to Base-10 to Base-2 numbering representations. To convert into other base number representations like Base-8, Base-16, Base-9, the converter is currently unavailable. To support such conversion, there is a need to investigate a way to convert floating-point number from one base numbering representation to another. This paper first reviews floating-point number fundamentals like working mechanism in mathematics and computer science domains. The goal is to understand floating point number's role and working mechanisms. Then, the paper reviews its definitions, parts, requirements, tradeoff, and operating algorithms related to seek out available math functionalities in Go programming language. Next the paper derives and tests the base conversion algorithm based on the available resources. Lastly, the paper specifies its limitation based on the test results and concluded the derived algorithm.

This paper presents a new floating-point technology: Bounded Floating Point (BFP) that constrains inexact floating-point values by adding a new field to the standard floating point data structure. This BFP extension to standard floating point identifies the number of significant bits of the representation of an infinitely accurate real value, which standard floating point cannot. The infinitely accurate real value of the calculated result is bounded between a lower bound and an upper bound. Presented herein are multiple demonstrations of the BFP software model, which identifies the number of significant bits remaining after a calculation and displays only the number of significant decimal digits. These show that BFP can be used to pinpoint failure points. This paper analyzes the thin triangle area algorithm presented by Kahan and compares it to an earlier algorithm by Heron. BFP is also used to demonstrate zero detection and to correctly identify an otherwise unstable matrix.

Abstract. Given a Cylindrical Algebraic Decomposition of an implicit algebraic curve, visualizing distinct curve arcs is not as easy as it stands because, despite the absence of singularities in the interior, the arcs can pass arbitrary close to each other. We present an algorithm to visualize distinct connected arcs of an algebraic curve efficiently and precise (at a given resolution), irrespective of how close to each other they actually pass. Our hybrid method inherits the ideas of subdivision and curve-tracking methods. With an adaptive mixed-precision model we can render the majority of algebraic curves using floating-point arithmetic without sacrificing the exactness of the final result. The correctness and applicability of our algorithm is borne out by the success of our webdemo 1 presented in [10].

Abstract—Sparse matrix-vector multiplication (SpMV) is a common operation in numerical linear algebra and is the computational kernel of many scientific applications. It is one of the original and perhaps most studied targets for FPGA acceleration. Despite this, GPUs, which have ...

By using a combination of 32-bit and 64-bit floating point arithmetic, the performance of many dense and sparse linear algebra algorithms can be significantly enhanced while maintaining the 64-bit accuracy of the resulting solution. The approach presented here can apply not only to conventional processors but also to exotic technologies such as Field Programmable Gate Arrays (FPGA), Graphical Processing Units (GPU), and the Cell BE processor. Results on modern processor architectures and the Cell BE are presented.

Decimal data processing applications have grown exponentially in recent years thereby increasing the need to have hardware support for decimal arithmetic. In this paper, an improved architecture for efficient Binary Coded Decimal (BCD) addition/subtraction is presented that performs binary addition/subtraction without any extra hardware. The architecture works for both signed and unsigned numbers. The design is runtime reconfigurable and maximum utilization of the hardware is a feature of the architecture. Simulation results show that the proposed architecture is at least 32% better in terms of power-delay product than the existing designs.

A R T I C L E I N F O A B S T R A C T Article history: Received: 20 November, 2020 Accepted: 17 January, 2021 Online: 28 January, 2021 This paper presents a new floating-point technology: Bounded Floating Point (BFP) that constrains inexact floating-point values by adding a new field to the standard floating point data structure. This BFP extension to standard floating point identifies the number of significant bits of the representation of an infinitely accurate real value, which standard floating point cannot. The infinitely accurate real value of the calculated result is bounded between a lower bound and an upper bound. Presented herein are multiple demonstrations of the BFP software model, which identifies the number of significant bits remaining after a calculation and displays only the number of significant decimal digits. These show that BFP can be used to pinpoint failure points. This paper analyzes the thin triangle area algorithm presented by Kahan and compares it to an ea...

A new reorthogonalized block classical Gram--Schmidt algorithm is proposed that factorizes a full column rank matrix A into A=QR where Q is left orthogonal (has orthonormal columns) and R is upper triangular and nonsingular. With appropriate assumptions on the diagonal blocks of R, the algorithm, when implemented in floating point arithmetic with machine unit , produces Q and R such that I- Q^T Q _2 =O() and A-QR _2 =O( A _2). The resulting bounds also improve a previous bound by Giraud et al. [Num. Math., 101(1):87-100, 2005] on the CGS2 algorithm originally developed by Abdelmalek [BIT, 11(4):354--367, 1971]. Keywords: Block matrices, Q--R factorization, Gram-Schmidt process, Condition numbers, Rounding error analysis.

Recursive procedures used for sequential calculations of polynomial basis coefficients in discrete orthogonal moments produce unreliable results for high moment orders as a result of error accumulation. This paper demonstrates accurate reconstruction of arbitrary-size images using full-order (orders as large as the image size) Tchebichef and Krawtchouk moments by calculating polynomial coefficients directly from their definition formulas in hypergeometric functions and by creating lookup tables of these coefficients off-line. An ...

This paper discusses the design and development of a general-purpose programmable DSP subsystem packaged in a multichip module. The subsystem contains a 32-bit floating-point programmable DSP processor along with 256 K-byte of SRAM; 128 K-byte of FLASH memory, 10 K-gate FPGA and a 6-channel 12-bit ADC. The complete subsystem is interconnected on a 37 mm by 37 mm MCM-D substrate

In mathematics and computer science, for a given real number, there are situations where we need to perform base number conversion. Floating point numbers are known for their very large and very small number representations such as beyond CPU 64-bit integer supporting range at the expense of loosely controlled accuracy. In Go, floating-point number conversion is only limited to Base-10 to Base-2 numbering representations. To convert into other base number representations like Base-8, Base-16, Base-9, the converter is currently unavailable. To support such conversion, there is a need to investigate a way to convert floating-point number from one base numbering representation to another. This paper first reviews floating-point number fundamentals like working mechanism in mathematics and computer science domains. The goal is to understand floating point number's role and working mechanisms. Then, the paper reviews its definitions, parts, requirements, tradeoff, and operating algor...

Decimal data processing applications have grown exponentially in recent years thereby increasing the need to have hardware support for decimal arithmetic. In this paper, an improved architecture for efficient Binary Coded Decimal (BCD) addition/subtraction is presented that performs binary addition/subtraction without any extra hardware. The architecture works for both signed and unsigned numbers. The design is runtime reconfigurable and maximum utilization of the hardware is a feature of the architecture. Simulation results show that the proposed architecture is at least 32% better in terms of power-delay product than the existing designs.

Abstract: This work explores the feasibility of implementing a floating-point exponentiation unit on reconfigurable computing systems. A table-driven exponentiation unit was implemented using synthesizable VHDL. The project included creating pipelined submodules for ...