NAND Flash memory

TANOS charge trap flash (CTF) with Al2O3-Si3N4-SiO2 memory stack and TaN metal gate is a candidate technology to replace conventional floating gate technology for multi-level NAND applications beyond the 32nm node. The main drawbacks of TANOS to date are poor erase performance (in terms of speed and/or saturated level) as well as insufficient retention in the highest programmed state.

In spite of the mature cell structure, the memory controller architecture of Multi-level cell (MLC) NAND Flash memories is evolving fast in an attempt to improve the uncorrected/miscorrected bit error rate (UBER) and to provide a more flexible usage model where the performance-reliability trade-off point can be adjusted at runtime. However, optimization techniques in the memory controller architecture cannot avoid

Recently smart devices based on Android, one of operating systems, are widely used by many users. Such Android-based smart devices use NAND flash memory as storage media. In contrast to other file systems, EXT4 file system of Android has journaling feature. Simple Circular Buffer Structure and Algorithm used by journal feature does not cause performance degradation on hard disks. However, the authors found that, due to the characteristics of journal recording algorithm, performance of that journaling feature degrades on NAND flash memory. Specifically VPC (Valid Page Copy) occurs quite frequently. In this paper, the authors propose Doubly-Circular Buffer Structure and Algorithm to replace the Simple Circular Buffer Structure and Algorithm which causes performance degradation on NAND flash memory. Specifically, by deleting Journal Cold Pages early that will not be used later, we can reduce unnecessary VPCs and therefore improve the performance of smart devices using EXT4 file system on NAND flash memory.

The performance and lifetime of highperformance solid-state drives (SSDs) can be improved by data compression, which can reduce the amount of data physically transferred from/to flash memory. In this paper, we present our experience of building a high-performance solid-state drive using a hardware accelerated compression module called BlueZIP. In order to fully exploit the BlueZIP module, we devise a compression-aware flash translation layer (FTL), called CaFTL, which supports compressionaware address mapping and garbage collection for BlueZIP. For poorly compressed pages, CaFTL supports selective compression so that unnecessary compression can be avoided. We have implemented a complete SSD prototype with BlueZIP on an FPGA-based custom SSD platform and evaluated its effectiveness using realistic workloads. Our evaluation results show that BlueZIP can increase the lifetime of the SSD prototype by 26% as well as improve read and write performance by 20% and 27%, respectively, on aver...

This paper presents a new cell crosstalk effect in deca-nanometer nand Flash memories, making the data retention and erase transients of fresh cells dependent on the threshold-voltage level at which adjacent cells in the array are placed. In particular, a programmed cell is shown to display a larger threshold-voltage loss when its adjacent cells are in the erased than in the programmed state, with cells on the same bit line and word line having a similar impact on the acceleration of the threshold-voltage loss. The effect is explained by means of 3-D TCAD simulations, showing that a low threshold voltage for the adjacent cells increases the discharging tunneling current of the monitored cell for a fixed negative potential of its floating gate. This is due to a change of the electric field profile at the corners of the monitored cell active area when the potential of the floating gate of its neighboring cells is modified.

In recent years, many systems have employed NAND flash memory as storage devices because of its advantages of higher performance (compared to the traditional hard disk drive), high-density, random-access, increasing capacity, and falling cost. On the other hand, the performance of NAND flash memory is limited by its ¿erase-before-write¿ requirement. Log-based structures have been used to alleviate this problem by writing updated data to the clean space. Prior log-based methods, however, cannot avoid excessive erase operations when there are frequent updates, which quickly consume free pages, especially when some data are updated repeatedly. In this paper, we propose a hybrid architecture for the NAND flash memory storage, of which the log region is implemented using phase change random access memory (PRAM). Compared to traditional log-based architectures, it has the following advantages: (1) the PRAM log region allows in-place updating so that it significantly improves the usage efficiency of log pages by eliminating out-of-date log records; (2) it greatly reduces the traffic of reading from the NAND flash memory storage since the size of logs loaded for the read operation is decreased; (3) the energy consumption of the storage system is reduced as the overhead of writing and reading log data is decreased with the PRAM log region; (4) the lifetime of NAND flash memory is increased because the number of erase operations are reduced. To facilitate the PRAM log region, we propose several management policies. The simulation results show that our proposed methods can substantially improve the performance, energy consumption, and lifetime of the NAND flash memory storage1.

NAND flash memories are used in digital still cameras, cellular phones, MP3 players and various memory cards. As seen in the growing needs for applications such as solid-state drives and video camcoders, the market demands for larger-capacity storage has continuously increased ...

NAND flash memories are used in digital still cameras, cellular phones, MP3 players and various memory cards. As seen in the growing needs for applications such as solid-state drives and video camcoders, the market demands for larger-capacity storage has continuously increased and NAND flash memories are enabling a wide range of new applications. In such situations, to achieve larger capacity at low cost per bit, technical improvement in feature-size scaling, multi-bit per cell and area reduction are essential. To respond to such continuous requirements of cost reduction and density increase, 32 Gb 3 b/cell (D3) NAND flash memory with sub-35 nm CMOS process is developed. Introduction of sub-35 nm CMOS process and D3 technology doubles the capacity at almost the same chip area compared to previously published 43 nm 16 Gb 2 b/cell (D2) chip and about 80% chip area compared to previously published 56 nm 16 Gb D3 chip. The chip of size 9.215 x 12.247 mm2 = 112.86 mm2 enables the 32 Gb chip to fit in a microSD memory card. The chip architecture has 2 planes with 1.4 K blocks/plane, 1.5 MB block size and 8 KB page size. The block consists of 66 wordlines (WLs) containing 2 dummy WLs between select gates (SGs). All memory cells on the same WL have 3 pages and can be programmed and read simultaneously.

We investigate atmospheric neutron effects on floating gate cells in MLC NAND Flash memories. Loss of information is shown to occur especially at the highest program levels, but to an extent that does not challenge current error correction capabilities. We discuss the physical mechanisms and analyze scaling trends, which show a rapid increase in sensitivity for decreasing feature size. A

Page 1. Write Amplification Analysis in Flash-Based Solid State Drives ... ABSTRACT Write amplification is a critical factor limiting the random write performance and write endurance in storage devices based on NAND-flash memories such as solid-state drives (SSD). ...

... Chanik Park Jeong-Uk Kang Seon-Yeong Park Jin-Soo Kim ... is hereafter referred to as mem-ory “shadowing” (Figure 1(a)). The shadowing offers the best performance possible since all the code is executed in fast SDRAM memory, but copying overhead at boot-time contributes ...