TSMC

Indian fisheries are at a turning point. To date, Indian fisheries policies have emphasised production at the expense of allocation and, indeed, even effort restrictions. On the basis of original ethnographic data and secondary sources, we show how this has led to conflict between sectors and exacerbated pressures on marine living resources in the states of Tamil Nadu and Gujarat. We use a social justice approach to analyse this trend and to suggest possible alternative future paths of governance. These turn on the conviction that only with a new emphasis on allocation grounded in social justice can Indian fisheries governance foster fisheries that continue to sustain high levels of employment without further depleting their biological basis.

El paradigma hacia el que hoy nos dirigimos es el Internet de Todo, donde los objetos ya prescinden en gran medida de los humanos y se comunican entre sí. El soporte de este nuevo modelo de relaciones es el 5G, la tecnología de telecomunicaciones móviles de Quinta Generación.
El despliegue de la tecnología 5G produce una escalada en la competencia entre actores-proveedores-influencers centrales: los dos cardinales centros de poder de este tiempo, Estados Unidos y China, están disputándose el tablero global de esta nueva tecnología. Avanzan sobre el terreno blandiendo cada uno sus mejores armas para la conquista, ya sea a partir de la persuasión -en el interés de mantener el status quo relacionado con la seguridad internacional- o desde la seducción -de poseer las mejores herramientas para encarar la revolución tecnológica que se avecina-. En un plano subyacente existe la lucha entre la superioridad actual y una preeminencia naciente.
Los desarrollos computacionales, la aeronavegación, la era nuclear, la exploración espacial, y las telecomunicaciones, constituyen evidencias sobre cómo la geopolítica mundial evolucionó y evoluciona sobre capacidades tecnológicas aplicadas, tanto al ámbito civil como a la defensa y conquista militar. Sin estas razones, es imposible entender la revolución del Japón Meiji en el siglo XIX o el afán reformista de China en el siglo XX, la debacle de la ex URSS, la industrialización asiática, la modernidad europea y racional pulso conquistador colonial, o la actual competencia China-Estados Unidos.
En el Campo de Batalla de la Guerra Tecnológica del Siglo se presentan los Campeones y el Retador. Ya están dadas las Reglas del Juego. ¿Cómo se definirá la contienda?

Communication systems use the concept of transmitting information using the electrical distribution network as a communication channel. To enable the transmission data signal modulated on a carrier signal is superimposed on the electrical wires. Typical power lines are designed to handle 50/60 Hz of AC power signal; however they can carry the signals up to 500 KHz frequency. This work aims to aid transmission/reception of an audio signal in the spectrum from 300 Hz to 4000 Hz using PLCC on a tunable carrier frequency in the spectrum from 200 KHz to 500 KHz. For digital amplitude modulation the sampling rate of the carrier and the audio signal has to be matched. Tunable carrier generation can be achieved with Direct Digital Synthesizers at a desired sampling rate. DSP Sample rate conversion techniques are very useful to make the sampling circuits to work on their own sampling rates which are fine for the data/modulated-carrier signal's bandwidth. This also simplifies the complexity of the sampling circuits. Digital Up Conversion (DUC) and Digital Down Conversion (DDC) are DSP sample rate conversion techniques which refer to increasing and decreasing the sampling rate of a signal respectively. The objective was to design and implement low power ASIC of DUC and DDC designs at 65nm for PLCC. Low power implementation was carried out using Multi-VDD technique. MATLAB software models were used to understand the DUC and DDC designs. RTL to GDS flow was executed using Synopsys tools such as VCS, Design Compiler, IC Compiler and PrimeTime. Key milestones of this activity are RTL verification, synthesis, gate-level simulations, low power architecture definitions, physical implementation, ASIC signoff checks and postroute delay based simulations. Multi-VDD technique deployed on DUC and DDC helped to reduce the power consumption from 280.9uW to 198.07uW and from 176.26uW to 124.47uW respectively. DUC and DUC designs have met functionality at 64MHz clock frequency. Both the designs have passed postroute delay based simulations, static performance checks, power domain checks and TSMC's 65nm design rule checks.

In this research, we present a new method, termed F-Sign, for automatic extraction of unique signatures from malware files. F-Sign is primarily intended for high-speed network traffic filtering devices that are based on deep-packet inspection. Malicious executables are analyzed using two approaches: disassembly, utilizing IDA-Pro, and the application of a dedicated state machine in order to obtain the set of functions comprising the executables. The signature extraction process is based on a comparison with a common function repository. By eliminating functions appearing in the common function repository from the signature candidate list, F-Sign can minimize the risk of false-positive detection errors. To minimize false-positive rates even further, F-Sign proposes intelligent candidate selection using an entropy score to generate signatures. Evaluation of F-Sign was conducted under various conditions. The findings suggest that the proposed method can be used for automatically generating signatures that are both specific and sensitive.

Most Semantic Web technology-based applications need users to have a deep background on the formal underpinnings of ontology languages and some basic skills in these technologies. Generally, only experts in the field meet these requirements. In this paper, we present OWLPath, a natural language-query editor guided by multilanguage OWL-formatted ontologies. This application allows nonexpert users to easily create SPARQL queries that can be issued over most existing ontology storage systems. Our approach is a fully fledged solution backed with a proof-of-concept implementation and the empirical results of two challenging use cases: one in the domain of e-finance and the other in e-tourism.

This paper introduce a type-2 fuzzy function system for uncertainty modeling using evolutionary algorithms (ET2FF). The type-1 fuzzy inference systems (FISs) with fuzzy functions, which do not entail if ... then rule bases, have demonstrated better performance compared to traditional FIS. Nonetheless, the performance of these approaches is usually affected by their uncertain parameters. The proposed method implements a three-phase learning strategy to capture the uncertainties in fuzzy function systems induced by learning parameters, as well as fuzzy function structures. The improved fuzzy clustering initially finds hidden structures, and the genetic learning algorithm optimizes interval type-2 fuzzy sets to capture their optimum uncertainty interval. The proposed ET2FF architecture is evaluated using an extensive suite of real-life applications such as manufacturing process and financial market modeling. The results show that the proposed ET2FF method is comparable - if not superior - to earlier FIS in terms of generalization performance and robustness.

This paper introduce a type-2 fuzzy function system for uncertainty modeling using evolutionary algorithms (ET2FF). The type-1 fuzzy inference systems (FISs) with fuzzy functions, which do not entail if ... then rule bases, have demonstrated better performance compared to traditional FIS. Nonetheless, the performance of these approaches is usually affected by their uncertain parameters. The proposed method implements a three-phase learning strategy to capture the uncertainties in fuzzy function systems induced by learning parameters, as well as fuzzy function structures. The improved fuzzy clustering initially finds hidden structures, and the genetic learning algorithm optimizes interval type-2 fuzzy sets to capture their optimum uncertainty interval. The proposed ET2FF architecture is evaluated using an extensive suite of real-life applications such as manufacturing process and financial market modeling. The results show that the proposed ET2FF method is comparable - if not superior - to earlier FIS in terms of generalization performance and robustness.

Communication systems use the concept of transmitting information using the electrical distribution network as a communication channel. To enable the transmission data signal modulated on a carrier signal is superimposed on the electrical wires. Typical power lines are designed to handle 50/60 Hz of AC power signal; however they can carry the signals up to 500 KHz frequency. This work aims to aid transmission/reception of an audio signal in the spectrum from 300 Hz to 4000 Hz using PLCC on a tunable carrier frequency in the spectrum from 200 KHz to 500 KHz. For digital amplitude modulation the sampling rate of the carrier and the audio signal has to be matched. Tunable carrier generation can be achieved with Direct Digital Synthesizers at a desired sampling rate. DSP Sample rate conversion techniques are very useful to make the sampling circuits to work on their own sampling rates which are fine for the data/modulated-carrier signal’s bandwidth. This also simplifies the complexity of the sampling circuits. Digital Up Conversion (DUC) and Digital Down Conversion (DDC) are DSP sample rate conversion techniques which refer to increasing and decreasing the sampling rate of a signal respectively.

The objective was to design and implement low power ASIC of DUC and DDC designs at 65nm for PLCC. Low power implementation was carried out using Multi-VDD technique. MATLAB software models were used to understand the DUC and DDC designs. RTL to GDS flow was executed using Synopsys tools such as VCS, Design Compiler, IC Compiler and PrimeTime. Key milestones of this activity are RTL verification, synthesis, gate-level simulations, low power architecture definitions, physical implementation, ASIC signoff checks and postroute delay based simulations. Multi-VDD technique deployed on DUC and DDC helped to reduce the power consumption from 280.9uW to 198.07uW and from 176.26uW to 124.47uW respectively. DUC and DUC designs have met functionality at 64MHz clock frequency. Both the designs have passed postroute delay based simulations, static performance checks, power domain checks and TSMC’s 65nm design rule checks.