Service Manual For: Repair Technology Research Department /EDVD Feb.2004

BY: Grass Grass.Ren .
Ren
Repair Technology Research Department /EDVD Repair Technology Research Department /EDVD
Feb.2004
SERVICE MANUAL FOR
8050
8050 8050 N/B Maintenance N/B Maintenance
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1. Hardware Engineering Specification ..
1.1 Introduce .
1.2 System Overview .
1.3 System Hardware Parts ....
2. System View & Disassembly ..
2.1 System View ...
2.2 System Disassembly .
3. Definition & Location of Connectors / Switches Setting
4. Definition & Location of Major Component ..
5. Pin Description of Major Component..
5.1 Pentium4 (Willamette/Northwood) processor ...
5.2 Sis650 North Bridge .
5.3 Sis962 South Bridge .
6. System Block Diagram ..
7. Maintenance Diagnostics ..
7.1 Introduction
7.2 Debug Card
7.3 Error code ..
Contents
3
3
6
9
34
37
57
60
62
62
66
75
83
84
84
86
85
34
2
8. Trouble Shooting
8.1 No Power .
8.2 Battery Can not Be Charged .
8.3 No Display ..
8.4 External Monitor No Display ....
8.5 Memory Test Error .
8.6 Keyboard/Touch-pad Test Error ..
8.7 USB Port Test error..
8.8 Hard Disk Drive Test Error...
8.9 CD-ROM Test Error
8.10 Audio Test Failure..
8.11 LAN Test Error .
8.12 Modem Test Error .
8.13 Mini-PCI Test Error.. ...
8.14 Card Bus&Reader Test Error..
8.15 TV Encoder Test Failure .
8.16 IEEE1394 Test Failure ...
9. Spare Parts List .
10. System Exploded View
11. Circuit Diagram ..
12. Reference Material .
Contents
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90
95
97
103
105
107
109
111
113
115
118
120
122
124
126
128
141
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176
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1.1 Introduce
1. Engineer Hardware Specification
The MiTAC 8050 model is designed for Intel Banias processor with 400MHz FSB with Micro-FCPGA package.
It can support Banias 1.5G ~ 1.9GHz/Dothan 2.0GHz and above.
This system is based on PCI architecture and is fully compatible with IBM PC/AT specification, which has
standard hardware peripheral interface. The power management complies with Advanced Configuration and
Power Interface (ACPI) 2.0. It also provides easy configuration through CMOS setup, which is built in system
BIOS software and can be pop-up by pressing F2 key at system start up or warm reset. System also provides icon
LEDs to display system status, such as AC Power indicator, Battery Power indicator, Battery status indicator,
HDD,CD-ROM, NUM LOCK, CAP LOCK, SCROLL LOCK, RF on/off Card Reader indicator. It also equipped
with LAN, 56K Fax MODEM, 3 USB port, S-Video and audio line in/out , external microphone function.
The memory subsystem supports two expansion DDR SDRAM slot with unbuffered PC1600/PC2100 DDR-
SDRAM.
The Montara-GME GMCH Host Memory Controller integrates a high performance host interface for Intel
Banias processor, a high performance 2D/3D Graphic Engine, a high performance memory controller, Digital
Video port (DVOB & DVOC) interface, and Intel Hub interface Technology connecting with Intel 82801DBM
ICH4-M.
The Intel ICH4-M integrates three Universal Serial Bus 2.0 Host Controllers Interface (UHCI), the Audio
Controller with AC97 interface, the Ethernet includes a 32-bit PCI controller, the IDE Master/Slave controllers,
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and Intel Hub interface technology.
The MOBILITY M10 provides one of the fastest and most advanced 2D, 3D, and multimedia graphics2
performance for notebooks. Its architecture introduces the latest achievements in the graphics industry, which
enable the use of the progressive new features in upcoming applications, but without compromising performance.
ATIs support of support of DirectX 9 features, highly optimized Open GL support, and flexible memory
configurations allow implementations targeted at the gaming enthusiast, consumer, business and workstation
platforms.
The Realtek RTL8100C(L) is a highly integrated, cost-effective single-chip Fast Ethernet controller that provides
32-bit performance, PCI bus master capability, and full compliance with IEEE 802.3u 100Base-T specifications
and IEEE 802.3x Full Duplex Flow Control. It also supports the Advanced Configuration Power management
Interface (ACPI).
The VT6307L is a single chip PCI Host Controller for IEEE 1394-1995 Release 1.0 and IEEE 1394a P2000. It
implements the Link and PHY layers for IEEE 1394-1995 High Performance Serial Bus specification release 1.0
and 1394a P2000. It is compliant with 1394 Open HCI 1.0 and 1.1 with DMA engine support for high
performance data transfer via a 32-bit bus master PCEI host bus interface. The VT6307L supports 100, 200 and
400 Mbit/sec transmission via an integrated 2-port PHY. The VT6307L services two types of data packets:
asynchronous and isochronous(real time). The 1394 link core performs arbitration requesting, packet generation
and checking, and bus cycle master operations. It also has root node capability and performs retry operations.
The RICOH R5C592 CardBus/Media Reader controller functions as a single slot PCI to Cardbus bridge and also
PCI interface smart card and MS/SD/MMC flash card reader. The R5C592 provide one Cardbus slot and all reader
interface may operate simultaneously.
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The CH7011A is a display controller device which accepts a digital graphics input signal, and encodes and
transmits data to a TV output (analog composite, s-video or RGB). The device accepts data over one 12-bit wide
variable voltage data port which supports five different data format including RGB and YcrCb. The TV-Out
processor will perform non-interlace to interlace conversion with scaling and flicker filters, and encode the data
into any of the NTSC or PAL video standards. The scaling and flicker filter is adaptive and programmable to
enable superior text display. Eight graphics resolutions are supported up to 1024 X 768 with full vertical and
horizontal underscan capability in all modes. A high accuracy low jitter phase locked loop is integrated to create
outstanding video quality. Support is provided for Macrovision and RGB bypass mode which enable driving a
VGA CRT with the input data.
The W83L950D is a high performance microcontroller on-chip supporting functions optimized for embedded
control.These include ROM, RAM, four types of timers, a serial communication interface, optional IC bus
interface, host interface, A/D converter, D/A converter, I/O ports, and other functions needed in control system
configurations, so that compact, high performance systems can be implemented easily.
A full set of software drivers and utilities are available to allow advanced operating systems such as Windows ME,
Windows 2000 and Windows XP to take full advantage of the hardware capabilities. Features such as bus
mastering IDE, Plug and Play, Advanced Power Management (APM) with application restart, software-controlled
power shutdown.
Following chapters will have more detail description for each individual sub-systems and functions.
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1.2 System Overview(1)
Intel Mobile Pentium-M Processor 1.5G ~ 1.9GHz/Dothan 2.0GHz and above
-Thermal spec 35W TDP
Chip Set
Intel 855GME+ICH4
L2 Cache
1MB on-die for Pentium-M/ 2MB for Dothan
System BIOS
512KB Flash EPROM - include System BIOS, VGA BIOS - Plug&Play capability -ACPI
0MB DDR266/333 SDRAM memory on board
- 200pin DDR266/333 SDRAM SO-DIMM Memory Module
- Expandable to 1,024MB
- 1.25-inch height memory module supported
1.SMA
2.Reserve external VGA for Ati M10/M11
Optical drive
Combo / DVD-RW, DVD-RAM (12.7mm)
FDD
External USB I/F Option
2.5" 30GB / 40GB / 60GB / 80GB HDD(9.5mm) 4200rpm or 5400rpm
- Ultra DMA 100
15.4" Wide WXGA+ TFT
-Resolution: 1280x800
- 1 CCFT Typical 185cd/m2
-16.77 Million Colors with dithering
CPU
Memory
Video Controller
HDD
Display
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Continue to previous page
US/UK/Japanese keyboard layout(Use the Orignal KBD that other model used)
- 19mm key pitch / 3mm stroke
- Hot key spec: Fn+F1 : WirelessLAN ON/OFF, Fn+F3/E4 : Volume down/up, Fn+F5 :
LCD/CRT output change
Fn+F6/F7: Brightness up/down, Fn+F11: Display ON/OFF, Fn+F12: Standby
TouchPad (No scroll button)
TypeII x 1
-PCMCIA Standard Rev.2.1 , CardBus support , w/o ZV port
Built-in Sound system
- SCMS support - AC97 I/F
- 16-bit Sampling and Playback - 16-bit stereo - Full duplex supported - 3D sound supported
- AC-3 support
- Built-in 2W Woofer
- Built-in stereo speaker, Built-in microphone
- Sound Volume control by Hot-Key (Fn + F3 : Volume down, Fn + F4 : Volume up)
Card Reader
Support Mulit Card Reader
USB(2.0) x 3
IEEE1394 port x 1(4pins)
Mic-in(mono) x 1
Headphone-out(stereo)/SPDIFx 1
Keyboard
Pointing Device
Audio System
I/O Port
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Line-in x 1
TV-out (PAL/NTSC) x 1 (Macrovision supported)
RJ-45 LAN Jack x 1 (with cap) RJ-11Modem Jack x 1 (with cap)
Mini-PCI connetor (for WirelessLAN Card)
VGA port x 1 DC-in x 1
56Kbps(V.90) Fax Modem(MDC) and 100Base-TX LAN
Wireless LAN (IEEE802.11b, g,a/g)
Li-ion Battery 2200mAh(6-cell) - Battery Life: (TBD)
-RTC bckup battery(Lithium) Standard -Power-ON charge available
Power Supply
60W Universal AC Adapter(100-240V)
Safety Lock
Security Lock hole
Dimension
W353.8 x D250 x H25~32mm
Weight
(P)3.0kg
OS
Windows XP Home Service Pack 1
Accessories
TBD
Windows Logo
Support PC2001 Specification
- need to get the Logo for WindowsXP Home, WHQL Certified
EMI:CE/FCC/UL/TUV, BSMI/CCC(TBD)
Wireless:CE/FCC,WiFi, PTT:CE/FCC, USB:USB2.0 Logo, Energy Star, Harmonic Noise
regulations
Communication
Battery
EMI / Safety / Regulation
Continue to previous page
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1.3.1 Intel Banias processors in Micro-FCPGA package.
Intel Banias Processors with 478 pins Micro-FCPGA package.
The first Intel mobile processor with the Intel NetBurst micro-architecture which features include hyper-pipelined
technology, a rapid execution engine, a 400MHz system, an execution trace cache, advanced dynamic execution,
advanced transfer cache, enhanced floating point and multi-media unit, and Streaming SIMD Extensions 2
(SSE2).
The Streaming SIMD Extensions 2 (SSE2) enable break-through levels of performance in multimedia applications
including 3-D graphics, video decoding/encoding, and speech recognition.
Use Source-Synchronous Transfer (SST) of address and data to improve performance by transferring data four
times per bus clock.
Support Enhanced Intel SpeedStep technology, which enables real-time dynamic switching of the voltage and
frequency between two performance modes.
1.3.2 Clock Generator
System frequency synthesizer: ICS950810 Programmable output frequency, divider ratios, output rise/fall time,
1.3 System Hardware Parts
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1.3.3 Montara-GME GMCH IGUI 3D Graphic DDR/SDR Chipset
output skew. Programmable spread percentage for EMI control. Watchdog timer technology to reset system if
system malfunctions. Programmable watchdog safe frequency. Support I2C Index read/write and block read/write
operations. Use external 14.318MHz crystal.
Montara-GME GMCH IGUI Host Memory Controller integrates a high performance host interface for Intel
Banias processor, a high performance 2D/3D Graphic Engine, a high performance memory controller, an AGP 4X
interface, and Intel I/O Hub architecture INTEL 82801DBM ICH4-M.
Montara-GME GMCH Host Interface features the AGTL & AGTL+ compliant bus driver technology with
integrated on-die termination to support Intel Banias processors. Montara-GME GMCH provides a 12-deep In-
Order-Queue to support maximum outstanding transactions up to 12. It integrated a high performance 2D/3D
Graphic Engine, Video Accelerator and Advanced Hardware Acceleration MPEGI/MPEGII Video Decoder for
the Intel Banias series based PC systems. It also integrates a high performance 2.1GB/s DDR266 Memory
controller to sustain the bandwidth demand from the integrated GUI or external AGP master, host processor, as
well as the multi I/O masters. In addition to integrated GUI, Montara-GME GMCH also can support external AGP
slot with AGP 1X/2X/4X capability and Fast Write Transactions. A high bandwidth and mature Intel I/O Hub
architecture is incorporated to connect Montara-GME GMCH and INTEL 82801DBM ICH4-Mtogether. Intel
I/O Hub architecture is developed into three layers, the Multi-threaded I/O Link Layer delivering 1.2GB
bandwidth to connect embedded DMA Master devices and external PCI masters to interface to Multi-threaded I/O
Link layer, the Multi-threaded I/O Link Encoder/Decoder in INTEL 82801DBM ICH4-M to transfer data w/ 533
MB/s bandwidth
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Features
Processor/Host Bus Support
from/to Multi-threaded I/O Link layer to/from Montara-GME GMCH, and the Multi-threaded I/O Link
Encoder/Decoder in Montara-GME GMCH to transfer data w/ 533 MB/s from/to Multi-threaded I/O Link layer
to/from INTEL 82801DBM ICH4-M.
An Unified Memory Controller supporting DDR266 DRAM is incorporated, delivering a high performance data
transfer to/from memory subsystem from/to the Host processor, the integrated graphic engine or external AGP
master, or the I/O bus masters. The memory controller also supports the Suspend to RAM function by retaining
the CKE# pins asserted in ACPI S3 state in which only AUX source deliver power. The Montara-GME GMCH
adopts the Shared Memory Architecture, eliminating the need and thus the cost of the frame buffer memory by
organizing the frame buffer in the system memory. The frame buffer size can be allocated from 8MB to 64MB.
Intel Banias processor
Support host bus Dynamic Bus Inversion (DBI)
2X Address, 4X data
Supports system bus at 400MT/s (100 MHz) Supports 64-bit host bus addressing
8-deep In-Order-Queue
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AGTL+ bus driver technology with integrated GTL termination resistors and low voltage operation
(1.05V)
Supports Enhanced Intel Speed Step TM Technology (EIST) and Geyserville III
Support for DPWR# signal to Banias processor for PSB power management
Memory System
Directly supports one DDR channel, 64-bts wide (72-b with ECC).
Supports 200-MHz and 266-MHz DDR devices with max of 2 Double-Sided SO-DIMMs(4 rows populated)
with unbuffered PC1600/PC2100 DDR(with ECC).
Supports 128-Mb, 256-Mb and 512-Mbit technologies providing maximum capacity of 1-GB with only x 16
devices.
All supported devices have 4 banks.
Supports up to 16 simultaneous open pages.
Supports page sizes of 2KB, 4KB, 8KB, and 16KB. Page size is individually selected for every row. UMA
support only.
System Interrupt
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Supports 8259 and Processor
System Bus interrupt delivery mechanism
Supports interrupts signaled as upstream Memory Writes from PCI and Hub interface
MSI sent to the CPU through the system Bus
From IOxAPIC in ICH4-M
Provides redirection for upstream interrupts to the System Bus
Video Stream Decoder
Improved HW Motion Compensation for MPEG2
All format decoder (18 ATSC formats) supported Dynamic Bob and Weave support for Video Streams
Software DVD at 60 fields/second and 30 frames/second full screen
Support for 720x480 pixel resolution DVD quality encoding at low CPU utilization Video Overlay
Single high quality scalable overlay and second Sprite to support second overlay
Multiple overlay functionality provided via Arithmetic Stretch Blt
Direct YUV from Overlay to TV-out
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Independent Gamma Correction
Independent Brightness / Contrast / Saturation
Independent Tint / Hue support
Destination Color keying
Source Chroma keying
Maximum source resolution of 1920x1080 pixels
Maximum overlay clock of 133 MHz/200 MHz provides a pixel resolution up to 1600x1200@ 60Hz or
1280x1024@ 85 Hz
Analog Display Support 350 MHz integrated 24-bit RAMDAC that can drive a standard progressive scan
analog monitor up to 1800x1350 @ 85 Hz accompanying I2C and DDC channels provided through
multiplexed interface hot plug and display support
Dual independent pipe with single display support Simultaneous: Same images and native display timings on
each display device
DVO (DVOB) support
Digital video out port DVOB with 165-MHz dot clock on 12-bit interface
L Display
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- Variety of DVO devices channel
- Compliant with DVI Specification 1.0, thereby providing support for a flat panel up to 2048x1536 pixel
resolution, or digital CRT up to 1920x1080 pixel resolution
1.3.4 I/O Controller Hub : INTEL 82801DBM
The INTEL 82801DBM ICH4-M integrates three Universal Serial Bus 2.0 Host Controllers, the Audio Controller
with AC 97 Interface, the IDE Master/Slave controllers, and Intel I/O Hub architecture. The PCI to LPC Bridge,
I/O Advanced Programmable Interrupt Controller, legacy system I/O and legacy power management
functionalities are integrated as well.
The integrated Universal Serial Bus Host Controllers features Dual Independent UHCI Compliant Host controllers
with six USB ports delivering 480 Mb/s bandwidth and rich connectivity. Besides, Legacy USB devices as well as
over current detection are also implemented.
The Integrated AC97 v2.3 compliance Audio Controller that features a 7-channels of audio speaker out and HSP
v.90 modem support. Additionally, the AC97 interface supports 4 separate SDATAIN pins that is capable of
supporting multiple audio codecs with one separate modemcodec.
The integrated IDE Master/Slave controllers features Dual Independent IDE channels supporting PIO mode
transfers up to 16 Mbytes/sec and Ultra DMA 33/66/100. It provides two separate data paths for the dual IDE
channels that sustain the high data transfer rate in the multitasking environment.
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INTEL 82801DBM ICH4-M supports 6 PCI masters and complies with PCI 2.2 specification. It also incorporates
the legacy system I/O like: two 82C37 compatible DMA controllers, Channels 0-3 are hardwired to 8 bit, three
8254 compatible programmable 16-bit counters channels 5-7, hardwired keyboard controller and PS2 mouse
interface(not use in MiTAC 8050 model), Real Time clock with 512Bytes CMOS SRAM and two 82C59
compatible Interrupt controllers. Besides, the I/O APIC managing up to 14 interrupts with both Serial and FSB
interrupt delivery modes is supported.
The integrated power management module incorporates the ACPI 1.0b compliance functions, the APM 1.2
compliance functions, and the PCI bus power management interface spec. v1.1. Numerous power-up events and
power down events are also supported. 21 general purposed I/O pins are provided to give an easy to use logic for
specific application. In addition, the INTEL 82801DBM ICH4-M supports Deeper Sleep power state for Intel
Mobile processor.
A high bandwidth and mature Intel I/O Hub architecture is incorporated to connect Montara and Intel
82801DBM ICH4-M Hub interface together. Intel I/O Hub architecture is developed.
1.3.5 Introducing MOBILITY M10 (Option)
The MOBILITY M10 provides one of the fastest and most advanced 2D, 3D, and multimedia graphics
performance for notebooks. Its architecture introduces the latest achievements in the graphics industry, which
enable the use of the progressive new features in upcoming applications, but without compromising performance.
ATIs support of DirectX 9 features, highly optimized OpenGL support, and flexible memory configurations
allow implementations targeted at the gaming enthusiast, consumer, business and workstation platforms.
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L SMARTSHADER2.0 Advanced Shader Technology
Provides complete hardware-accelerated support for the new DirectX 9 programmable shader model,
enabling more complex and realistic texture and lighting effects than ever before.
Significant improvement over first-generation shaders introduced in DirectX 8, with a much more
powerful and intuitive instruction set. Offers full support for this feature in OpenGL applications.
L MOOTHVISION2.0 Flexible Anti-Aliasing and Anisotropic Filtering
2x/4x/6x full-scene anti-aliasing modes
Adaptive algorithm with programmable sample patterns
2x/4x/8x/16x anisotropic filtering modes
Adaptive algorithm with bi-linear (performance) and tri-linear (quality) options
Incorporates support for DDR SDRAM/SGRAM.
Features key items from ATIs third generation HYPER ZIII technology that conserves memory
bandwidth for improved performance in demanding applications.
L High Performance Memory Support
L Dual Display Support
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Leading-edge technology, fully optimized with HYDRA VISION, flexibly supports multiple
combinations of notebook LCD, traditional CRT monitors, flat panel displays and TV.
Features Dual Channel DVI support.
230MHz LVDS transmitter supports LCD panels up to QXGA (2048x1536) resolution.
Integrated 165MHz TMDS transmitter supports external flat panels up to UXGA (1600x1200) resolution.
High performance DAC speeds of 400MHz.
Features in Detail
L VIDEO Acceleration
M10 allows the integration of industry leading digital video features, including advanced de-interlacing
algorithms for unprecedented video quality and integrated digital TV decode capability. Includes
programmable,independent gamma control for the video overlay.
New FULLSTREAMtechnology removes blocky artifacts from streaming and Internet video and
provides sharper image quality.
Integrated general purpose xDCT engine (capable of performing both forward and inverse discrete cosine
transform) and motion compensation (MC) support for the acceleration of MPEG encoding and decoding
as well as DV (digital video) encoding and decoding.
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The CH7011 is a Display controller device which accepts a digital graphics input signal, and encodes and
transmits data to a TV output (analog composite, s-video or RGB). The device accepts data over one 12-bit wide
variable voltage data port which supports five different data formats including RGB and YCrCb.The TV-Out
processor will perform non-interlace to interlace conversion with scaling and flicker filters, and encode the data
into any of the NTSC or PAL video standards. The scaling and flicker filter is adaptive and programmable to
enable superior text display. Eight graphics resolutions are supported up to 1024 by 768 with full vertical and
horizontal underscan capability in all modes. A high accuracy low jitter phase locked loop is integrated to create
outstanding video quality. Support is provided for Macrovisionand RGB bypass mode which enables driving a
VGA CRT with the input data.
Features
TV output supporting up to 1024x768 graphics resolutions
Macro vision7.X copy protection support
Programmable digital interface supports RGB and YCrCb
True scale rendering engine supports under scan in all TV output resolutions
Enhanced text sharpness and adaptive flicker removal with up to 7 lines of filtering
Support for all NTSC and PAL formats
1.3.6 TV CH7011
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Provides CVBS, S-Video and SCART (RGB) outputs
TV connection detect
Programmable power management
10-bit video DAC outputs
Fully programmable through serial port
Complete Windows and DOS driver support
Low voltage interface support to graphics device
The ALC655 is a 16-bit, full duplex AC'97 2.3 compatible six channels audio CODEC designed for PC
multimedia systems,including host/soft audio and AMR/CNR based designs. The ALC655 incorporates
proprietary converter technology to meet performance requirements on PC99/2001 systems. The ALC655
CODEC provides three pairs of stereo outputs with 5-Bitvolume controls, a mono output, and multiple stereo and
mono inputs, along with flexible mixing, gain and mute functions to provide a complete integrated audio solution
for PCs. The digital interface circuitry of the ALC655 CODEC operates from a 3.3V power supply for use in
notebook and PC applications. The ALC655 integrates 50mW/20ohm headset audio amplifiers at Front-Out and
Surr-Out, built-in 14.318M 24.576MHz PLL and PCBEEP generator, those can save BOM costs. The ALC655
1.3.7 AC97 AUDIO SYSTEM: Advance Logic, Inc, ALC655
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also supports the S/PDIF input and output function, which can offer easy connection of PCs to consumer
electronic products, such as AC3 decoder/speaker and mini disk devices. ALC655 supports host/soft audio from
Intel ICHx chipsets as well as audio controller based VIA/SIS/ALI/AMD/nVIDIA/ATI chipset. Bundled Windows
series drivers (Win XP/ME/2000/98/NT), EAX/Direct Sound 3D/ I3DL2/ A3D compatible sound effect utilities
(supporting Karaoke, 26-kind of environment sound emulation,10-band equalizer), HRTF 3D positional audio and
Sensaura3D (optional) provide an excellent entertainment package and game experience for PC users. Besides,
ALC655 includes Realteks impedance sensing techniques that makes device load on outputs and inputs can be
detected.
Meets performance requirements for audio on PC99/2001 systems
Meets Microsoft WHQL/WLP 2.0 audio requirements
16-bit Stereo full-duplex CODEC with 48KHz sampling rate
Compliant with AC97 2.3 specifications
- Front-Out, Surround-Out, MIC-In and LINE In Jack Sensing
- 14.318MHz- 24.576MHz PLL to save crystal
- 12.288MHz BITCLK input can be consumed
- Integrated PCBEEP generator to save buzzer
- Interrupt capability
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Three analog line-level stereo inputs with 5-bit volume control: LINE_IN, CD, AUX
High quality differential CD input
Two analog line-level mono input: PCBEEP,PHONE-IN
Two software selectable MIC inputs
A dedicated Front-MIC input for front panel applications (software selectable)
Boost preamplifier for MIC input shared with Center and LFE output
Both Front-out and Surround-Out built-in
LINE Input shared with surround output;
MIC 50mW/20 amplifier
1.3.8 MDC:PCTEL MODEM DAUGHTER CARD PCT2303W (ASKEY
V1456VQL-P1)
The PCT2303W chipset is designed to meet the demand of this emerging worldwide AMR/MDC market. Theof
PC-TELs well proven PCT2303W chipset and the HSP56TM MR software modem driver allows systems
manufactures to implement modem functions in PCs at a lower bill of materials (BOM) while maintaining higher
system performance.
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PC-TEL has streamlined the traditional modem into the Host Signal Processing (HSP) solution. Operating with
the Pentium class processors, HSP becomes part of the host computers system software. It requires less power to
operate and less physical space than standard modem solutions. PC-TELs HSP modem is an easily integrated,
cost-effective communications solution that is flexible enough to carry you into the future.
The PCT2303W chip set is an integrated direct access arrangement (DAA) and Codec that provides a
programmable line interface to meet international telephone line requirements. The PCT2303W chip set is
available in two 16-pin small outline packages (AC97 interface on PCT303A and phone-line interface on
PCT303W). The chip set eliminates the need for an AFE, an isolation transformer, relays, opto-isolators, and 2-to
4-wire hybrid. The PCT2303W chip set dramatically reduces the number of discrete components and cost
required to achieve compliance with international regulatory requirements. The PCT2303W complies with
AC97 Interface specification Rev. 2.1.
The chip set is fully programmable to meet world-wide telephone line interface requirements including those
described by CTR21, NET4, JATE, FCC, and various country-specific PTT specifications. The programmable
parameters of the PCT2303W chip set include AC termination, DC termination, ringer impedance, and ringer
threshold. The PCT2303W chip set has been designed to meet stringent world-wide requirements for out-of-band
energy, billing-tone immunity, lightning surges, and safety requirements.
Features
Virtual com port with a DTE throughout up to 460.8Kbps.
G3 Fax compatible
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Codec/DAA Features
AC97 2.1 compliant
86dB dynamic range TX/RX paths
2-4-wire hybrid
Integrated ring detector
High voltage isolation of 4000V
Support for Caller ID
Compliant with FCC Part68, CTR21, Net4 and JATE
Low power standby
Low profile SOIC package 16 pins 10x3x1.55mm
Low power consumption
10mA @ 3.3V operation
Auto dial and auto answer
Ring detection
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Standard Features
Data ITU-T V.90 (56Kbps), V.34 (4.8Kbps TO 33.6 Kbps), V.32 bis (4.8Kbps to 14.4Kbps), V.22 bis (1.2 bps
to 2.4 Kbps), V.21 and Bell 103 and 212A(300 to 1200 bps) modulation protocol.
Data Compression ITU-T V.42bis MNP Class 5
Error Correction ITU-T V.42 LAPM MNP 2-4
Fax ITU-T V. 17, V.29, V.27ter, V.21, Channel 2, Group 3, EIA Class I
1mA @ 3.3V power down
Integrated modemcodec
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1.3.9 IEEE1394 VT6307L (Option)
1.3.9.1 Overview
The VT6307 IEEE 1394 OHCI Host Controller provides high performance serial connectivity. It implements the
Link and Phy layers for IEEE 1394-1995 High Performance Serial Bus specification release 1.0 and 1394a-2000.
It is compliant with 1394 Open HCI 1.0 and 1.1 with DMA engine support for high performance data transfer via
a 32-bit bus master PCI host bus interface. The VT6307 supports 100, 200 and 400 M bit/sec transmission via an
integrated 2-port PHY. The VT6307 services two types of data packets: asynchronous and isochronous (real time).
The 1394 link core performs arbitration requesting, packet generation and checking, and bus cycle master
operations. It also has root node capability and performs retry operations. The VT6307 is ready to provide
industry-standard IEEE 1394 peripheral connections for desktop and mobile PC platforms. Support for the
VT6307 is built into Microsoft Windows 98, Windows ME, Windows 2000, and Windows XP.
32 bit CRC generator and checker for receive and transmit data
On-chip isochronous and asynchronous receive and transmit FIFOs for packets (2K for general receive plus
2K for isochronous transmit plus 2K for asynchronous transmit)
8 isochronous transmit contexts
4 isochronous receive contexts
1.3.9.2. Features
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3-deep physical post-write queue
2-deep physical response queue
Dual buffer mode enhancements
Skip Processing enhancements
Block Read Request handling
Ack_tardy processing
L Firmware Hub for Intel 810, 810E, 815, 815E,815EP, 820, 840, 850 Chipsets
L Flexible Erase Capability
1.3.10 System Flash Memory (BIOS)
Uniform 4 K Byte Sectors
Uniform 16 K Byte overlay blocks for SST49LF002A
Uniform 64 K Byte overlay blocks for SST49LF004ATop boot block protection
16 K Byte for SST49LF002A
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5-signal communication interface supporting byte Read and Write
33 MHz clock frequency operation
WP# and TBL# pins provide hardware write protect for entire chip and/or top Boot Block
Block Locking Register for all blocks
Standard SDP Command Set
Data# Polling and Toggle Bit for End-of-Write detection
5 GPI pins for system design flexibility
4 ID pins for multi-chip selection
L Single 3.0-3.6V Read and Write Operations
L Superior Reliability
L Firmware Hub Hardware Interface Mode
64 K Byte for SST49LF004A
Chip-Erase for PP Mode
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JEDEC-standard 200-pin, small-outline, dual in-line memory module (SODIMM)
Utilizes 200 Mb/s and 266 Mb/s DDR SDRAM components
64MB (8 Meg x 64 [H]); 128MB (16 Meg x 64, [H] and [HD]); 256MB (32 Meg x 64 [HD]); 512MB
(64Meg x 64 [HD])
VDD= VDDQ= +2.5V 0.2V
VDDSPD = +2.2V to +5.5V
2.5V I/O (SSTL_2 compatible)
Commands entered on each positive CK edge
DQS edge-aligned with data for READs; center-aligned with data for WRITEs
Internal, pipelined double data rate (DDR) architecture; two data accesses per clock cycle Bidirectional data
strobe (DQS) transmitted/received with datai.e.,source-synchronous data capture
Differential clock inputs (CK and CK# - can be multiple clocks, CK0/CK0#, CK1/CK1#, etc.)
1.3.11 Memory System
1.3.11.1 64MB, 128MB, 256MB, 512MB (x64) 200-Pin DDR SDRAM SODIMM
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Four internal device banks for concurrent operation
Selectable burst lengths: 2, 4, or 8
Auto precharge option
Auto Refresh and Self Refresh Modes
15.6s (MT4VDDT864H, MT8VDDT1664HD), 7.8125s (MT4VDDT1664H, MT8VDDT3264HD,
MT8VDDT6464HD) maximum average periodic refresh interval
Serial Presence Detect (SPD) with EEPROM
Fast data transfer rates PC2100 or PC1600
Selectable READ CAS latency for maximum compatibility
Gold-plated edge contacts
1.3.12 PHY: 3.3-V 10Base-T/100Base-TX Integrated PHY Ceiver ,The ICS1893
is a low-power, physical-layer device (PHY)
General
The Realtek RTL8100C(L) is a highly integrated, cost-effective single-chip Fast Ethernet controller that provides
32-bit performance, PCI bus master capability, and full compliance with IEEE 802.3u 100Base-T specifications
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and IEEE 802.3x Full Duplex Flow Control. It also supports the Advanced Configuration Power management
Interface (ACPI), PCI power management for modern operating systems that are capable of Operating System
Directed Power Management (OSPM) to achieve the most efficient power management possible.The
RTL8100C(L) does not support CardBus mode as the RTL8139C does. In addition to the ACPI feature, the
RTL8100C(L) also supports remote wake-up (including AMD Magic Packet, LinkChg, and Microsoft wake-
upframe) in both ACPI and APM environments. The RTL8100C(L) is capable of performing an internal reset
through the application of auxiliary power. When auxiliary power is applied and the main power remains off, the
RTL8100C(L) is ready and waiting for the Magic Packet or Link Change to wake the system up. Also, the
LWAKE pin provides 4 different output signals including active high, active low, positive pulse, and negative
pulse. The versatility of the RTL8100C(L) LWAKE pin provides motherboards with Wake-On-LAN (WOL)
functionality. The RTL8100C(L) also supports Analog Auto-Power-down, that is, the analog part of the
RTL8100C(L) can be shut down temporarily according to user requirements or when the RTL8100C(L) is in a
power down state with the wakeup function disabled.In addition, when the analog part is shut down and the Isolate
B pin is low (i.e. the main power is off), then both the analog and digital parts stop functioning and the power
consumption of the RTL8100C(L) will be negligible. The RTL8100C(L) also supports an auxiliary power
auto-detect function, and will auto-configure related bits of their own PCI power management registers in
PCI configuration space.
128 pin QFP/LQFP
Integrated Fast Ethernet MAC, Physical chip and transceiver in one chip
10 Mb/s and 100 Mb/s operation
Supports 10 Mb/s and 100 Mb/s N-way Auto-negotiation operation
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- Compliant to PCI Revision 2.2Supports PCI clock 16.75MHz-40MHz
- Supports PCI target fast back-to-back transaction
- Provides PCI bus master data transfers and PCI
- Memory space or I/O space mapped data transfers of RTL8100C(L)'s operational registers
- Supports PCI VPD (Vital Product Data)
- Supports ACPI, PCI power management
Supports 25MHz crystal or 25MHz OSC as the internal
Clock source. The frequency deviation of either crystal or OSC must be within 50 PPM.
Compliant to PC99/PC2001 standard
Supports Wake-On-LAN function and remote wake-up (Magic Packet*, LinkChg and Microsoft wake-
up frame)
Supports 4 Wake-On-LAN (WOL) signals (active high, active low, positive pulse, and negative pulse)
Supports auxiliary power-on internal reset, to be ready for remote wake-up when main power still
remains off
PCI local bus single-chip Fast Ethernet controller
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Supports auxiliary power auto-detect, and sets the related capability of power management registers in PCI
configuration space.
Includes a programmable, PCI burst size and early Tx/Rx threshold. Supports a 32-bit general-purpose
timer with the external PCI clock as clock source, to generate timer-interrupt
Contains two large (2Kbyte) independent receive and transmit FIFOs
Advanced power saving mode when LAN function or wakeup function is not used
Uses 93C46 (64*16-bit EEPROM) to store resource configuration, ID parameter, and VPD data.
Supports LED pins for various network activity indications
Supports loopback capability
Half/Full duplex capability
Supports Full Duplex Flow Control (IEEE 802.3x)
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2.1 System View

2.1.1 Front View
Line Out Connector
1394 Jack
MIC In Connector
Line In Connector
2.1.2 Left-side View
USB Ports *1
RJ-11 Connector
VGA Port
Ventilation Openings
S-Video Port
SD Card Slot
O
O
O
OO
O
Top Cover Latch
OO
O
O
O
O O
RJ-45 Connector
PCMCIA Card Socket
2. System View and Disassembly
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2.1.3 Right-side View
2.1.4 Rear View
Kensington Lock
Power Connector
CD-ROM/DVD-ROM Drive
USB Port*2
O O
O
O
O
Kensington Lock
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2.1.5 Bottom View
Hard Disk Drive

DDR SDRAM Card
Wireless Card
2.1.6 Top-open View
LCD Screen
Device LED Indicators

Keyboard
Stereo Speaker Set
Power Button
Battery Park
CPU
Touch Pad
Hard Disk Drive Indicator
Battery Power Charging Indicator
O
O
O
O
O
O
Stereo Speaker Set

O
O
O
O
O
O
O
O
O
Power Indicator
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2.2 System Disassembly
The section discusses at length each major component for disassembly/reassembly and show corresponding
illustrations.Use the chart below to determine the disassembly sequence for removing components from the
notebook.
NOTE: Before you start to install/replace these modules, disconnect all peripheral devices and make sure the
notebook is not turned on or connected to AC power.
Modular Components
LCD Assembly Components
Base Unit Components
NOTEBOOK
2.2.1 Battery Pack
2.2.2 Keyboard
2.2.3 CPU
2.2.4 HDD Module
2.2.5 DVD-ROM Drive
2.2.6 Wireless Card
2.2.7 Modem Card
2.2.8 DDR-SDRAM
2.2.9 LCD Assembly
2.2.10 LCD Panel
2.2.11 Inverter Board
2.2.12 System Board
2.2.13 Touch Pad
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1. Replace the battery pack into the compartment. The battery pack should be correctly connected when you
hear a clicking sound.
2. Slide the release lever to the lock ( ) position.
2.2.1 Battery Pack
Disassembly
1. Carefully put the notebook upside down.
2. Slide the two release lever outwards to the unlock ( ) position (), while take the battery pack out of the
compartment (). (Figure 2-1)
Figure 2-1 Remove the battery pack
Reassembly

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2.2.2 Keyboard
Disassembly
1. Remove the battery pack. (Refer to section 2.2.1 Disassembly)
2. Open the top cover.
3. Loosen the four latches locking the keyboard. (Figure 2-2)
4. Slightly lift up the keyboard and disconnect the cable from the mother board, then separate the keyboard.
(Figure 2-3)
Figure 2-2 Loosen the four latches Figure 2-3 Disconnect the cable
Reassembly
1. Reconnect the keyboard cable and fit the keyboard back into place with four latches.
2. Replace the battery pack. (Refer to section 2.2.1 reassembly)
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1. Remove the battery pack. (Refer to section 2.2.1 Disassembly)
2. Remove three screws fastening the heatsink cover. (Figure 2-4)
3. Remove three spring screws that secure the heatsink upon the CPU and disconnect the fans power cord
from system board. (Figure 2-5)
2.2.3 CPU
Disassembly
Figure 2-4 Remove three screws Figure 2-5 Free the heatsink
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Reassembly
1. Carefully, align the arrowhead corner of the CPU with the beveled corner of the socket, then insert CPU
pins into the holes. Tighten the screw by a flat screwdriver to locking the CPU.
2. Connect the fans power cord to the system board, fit the heatsink upon the CPU and secure with three
spring screws.
3. Replace the CPU cover and secure with three screws.
4. To remove the existing CPU, Loosen the screw by a flat screwdriver,upraise the CPU socket to unlock
the CPU. (Figure 2-6)
Figure 2-6 Remove the CPU
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2.2.4 HDD Module
Disassembly
1. Carefully put the notebook upside down. Remove the battery pack. (Refer to section 2.2.1 Disassembly)
2. Remove two screws fastening the HDD compartment cover. (Figure 2-7)
3. Remove the one screw and slide the HDD module out of the compartment. (Figure 2-8)
Figure 2-8 Remove HDD module Figure 2-7 Remove the HDD compartment cover
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4. Remove four screws to separate the hard disk drive from the bracket, remove four screws.
(Figure 2-9)
Reassembly
1. Attach the bracket to hard disk drive and secure with four screws.
2. Slide the HDD module into the compartment and secure with one screw.
3. Place the HDD compartment cover and secure with two screws.
Figure 2-9 Remove hard disk drive
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2.2.5 CD/DVD-ROM Drive
Disassembly
Figure 2-10 Remove one screw
2. Remove one screw fastening the CD/DVD-ROM drive. (Figure 2-10)
3. Push firmly to release the tray. Then gently pull out the CD/DVD-ROM drive by holding the tray that
pops out. (Figure 2-11)
Reassembly
1. Push the CD/DVD-ROM drive into the compartment and secure with one screw.
Figure 2-11 Remove the CD/DVD-
ROM drive
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2.2.6 Wireless Card
Disassembly
1. Carefully put the notebook upside down. Remove the battery pack. (Refer to sections 2.2.1 Disassembly)
2. Remove the two screws fastening the Mini PCI compartment cover. (Figure 2-12)
3. Disconnect the wireless cards antennae first (). Then pull the retaining clips outwards () and remove
the wireless card (). (Figure 2-13)
Figure 2-12 Remove two screws
Figure 2-13 Remove the Wireless card

Reassembly
1. To install the wireless card, match the wireless card 's notched part with the socket's projected part and firmly
insert it into the socket. Then push down until the retaining clips lock the wireless card into position. Then
sure that the antennae fully populated.
2. Tighten the screws to secure the wireless card compartment cover to the housing.
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2.2.7 Modem Card
Disassembly
2. Remove two screws fastening modem cards compartment cover. (Refer to steps 1-2 of section 2.2.6
Disassembly)
3. Remove two screws fastening the modem card. (Figure 2-14)
4. Lift up the modem card and disconnect the cord. (Figure 2-15)
Figure 2-14 Remove two screws Figure 2-15 Disconnect the cord
Reassembly
1. Reconnect the cord and fit the modem card.
2. Fasten the modem card by two screws.
3. Replace the modem cards compartment cover by two screws. (Refer to step 2 of section 2.2.6 reassembly).
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2.2.8 DDR-SDRAM
Disassembly
1. Carefully put the notebook upside down. And remove the battery pack. (See section 2.2.1 disassembly)
2. Remove two screws fastening the DDR compartment cover to access the SO-DIMM socket. (Figure 2-16)
Figure 2-16 Remove the cover Figure 2-17 Remove the SO-DIMM
3. Pull the retaining clips outwards () and remove the SO-DIMM (). (Figure 2-17)
Reassembly
1. To install the DDR, match the DDR's notched part with the socket's projected part and firmly insert the
SO-DIMM into the socket at 20-degree angle. Then push down until the retaining clips lock the DDR
into position.
2. Replace two screws to fasten the DDR compartment cover.
3. Replace the battery pack. (See section 2.2.1 reassembly)
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2.2.9 LCD ASSY
Disassembly
1. Remove the battery pack, keyboard,CPU, hard disk drive, CD/DVD-drive and wireless card.
(See sections 2.2.1,2.2.2, 2.2.3, 2.2.4, 2.2.5 and 2.2.6 Disassembly)
2. Remove the nineteen screws on the bottom of notebook. (Figure 2-18)
3. Remove the four screws that secure the hinge cover. (Figure 2-19)
Figure 2-18 Remove nineteen screws Figure 2-19 Remove four screws
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4. Remove the two screws and disconnect the touch pads cable, then free the top cover.(Figure 2-20)
5. Remove the two hinge covers. (Figure 2-21)
Figure 2-20 Free the Top cover Figure 2-21 Remove the hinge covers
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Figure 2-22 Remove the four screws and
Disconnect the two cables
Figure 2-23 Remove the eight screws
6. Disconnect the two cables and remove the four screws. (Figure 2-22)
7. Remove the eight screws. (Figure 2-23)
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8. Carefully pull the antenna wires out. Now you can lift up the LCD ASSY from base unit. (Figure 2-24)
Figure 2-24 Free the LCD ASSY
1. Attach the LCD assembly to the base unit and secure with four screws.
2. Rip the antenna wires back into Min-PCI compartment.
3. Reconnect the two cables to the system board. Screw the hinge covers by two screws.
4. Replace the shield and secure with eight screws.
5. Replace the top cover and secure with two screws. And reconnect the touch pads cable.
6. Upside down the notebook. secure the housing by nineteen screws and secure two screws in the rear.
7. Replace the Wireless card, CD/DVD-ROM, hard disk drive, CPU, keyboard and battery pack. (Refer to
sections 2.2.6, 2.2.5, 2.2.4, 2.2.3, 2.2.2 and 2.2.1 reassembly)
Reassembly
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2.2.10 LCD Panel
Disassembly
1. Remove the battery, keyboard, hard disk drive, CD/DVD-ROM drive and LCD assembly. (Refer to
section 2.2.1, 2.2.2, 2.2.4, 2.2.5 and 2.2.9 Disassembly)
2. Remove the two rubber pads and two screws on the corners of the panel. (Figure 2-25)
3. Insert a flat screwdriver to the lower part of the LCD cover and gently pry the frame out. Repeat the
process until the cover is completely separated from the housing.
4. Remove the twelve screws and disconnect the cable. (Figure 2-26)
Figure 2-26 Remove twelve screws and
disconnect the cable
Figure 2-25 Remove LCD cover
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Reassembly
1. Replace the cable to the LCD.
2. Attach the LCD panels bracket back to LCD panel and secure with six screws.
3. Replace the LCD panel into LCD housing.and reconnect two cables to inverter board and secure with two
screws.
4. Fasten the LCD panel by ten screws.
5. Fit the LCD cover and secure with two screws and rubber pads.
6. Replace the LCD assembly, CD/DVD-ROM drive, hard disk drive, keyboard, battery pack. (See sections
2.2.9, 2.2.5, 2.2.4, 2.2.2, and 2.2.1 reassembly)
Figure 2-28 Free the LCD panel
5. Remove the six screws that secure the LCD bracket. (Figure 2-27)
6. Disconnect the cable to free the LCD panel. (Figure 2-28)
Figure 2-27 Remove the six screws
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2.2.11 Inverter Board
Disassembly
1. Remove the battery, keyboard, hard disk drive, CD/DVD-ROM drive and LCD assembly. (Refer to
section 2.2.1, 2.2.2, 2.2.4, 2.2.5 and 2.2.9 Disassembly)
2. Remove the LCD cover and LCD panel. (Refer to the steps 1-4 of section 2.2.10 Disassembly )
3. Remove the one screw fastening the inverter board and disconnect the cable, Then free the inverter board.
(Figure 2-29)
Figure 2-29 Free the inverter board
Reassembly
1. Reconnect the cable. Fit the inverter board back into place and secure with one screw.
2. Replace the LCD Panel and LCD cover. (Refer to section 2.2.10 reassembly)
3. Replace the LCD assembly. (Refer to section 2.2.9 reassembly)
4. Replace the CD/DVD-ROM drive, hard disk drive, keyboard and battery pack. (Refer to sections 2.2.5,
2.2.4, 2.2.2 and 2.2.1 reassembly)
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1. Remove the battery, keyboard, hard disk drive, CD/DVD-ROM drive, Wireless card and LCD assembly.
(Refer to sections 2.2.1, 2.2.2, 2.2.4, 2.2.5, 2.2.6 and 2.2.9 Disassembly)
2. Remove the four screws that secure the system board and disconnect the two speakers cables. Then lift it
up from the housing. (Figure 2-30)
3. Disconnect the one speakers cables from the system board and remove the two screws, Then separate the
bracket and free the system board. (Figure 2-31)
2.2.12 System Board
Disassembly
Figure 2-30 Remove four screws and
disconnect the two cables Figure 2-31 Free the system board
Reassembly
1. Fit the bracket and secure with two screws .
2. Turn over the system board. Reconnect the speakers cords.
3. Replace the system board back into the housing and secure with four screws, then reconnect the cable.
4. Replace the LCD assembly, CD/DVD-ROM, HDD, keyboard and battery pack. (Refer to previous section
reassembly)
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2.2.13 Touch Pad
Disassembly
1. Remove the battery pack, keyboard, hard disk drive and CD/DVD-drive. (See sections 2.2.1,2.2.2 , 2.2.4 and
2.2.5 Disassembly)
2. Remove the top cover. (See steps 1-5 in section 2.2.9 Disassembly)
3. Remove the two screws and free the touch pad. (Figure 2-32).
Reassembly
1. Replace the touch pad and secure the two screws.
2. Replace the top cover. (Refer to the section in 2.2.9 reassembly)
3. Replace the battery pack, keyboard, hard disk drive and CD/DVD-drive. (See sections 2.2.1,2.2.2 ,
2.2.4 and 2.2.5 Disassembly).
Figure 2-32 Remove the two screws
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3. Definition & Location of Connectors / Switches
3.1 Mother Board - A
J1 : Inverter Board Connector
J2 : LCD panel connector
J3 : Internal Left Speaker Connector
J4 : Touch-pad Module Connector
J5 : Internal Key-board Connector
J6 : PCMCIA Card Connector
J7 : Internal Right Speaker Connector
SW2 : Power Button
SW4 : Left Button Switch of Touch-pad
SW5 : Right Button Switch of Touch-pad
J6
J2
J1
J3
J5
J4
J7
SW4
SW5
SW2
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3.2 Mother Board - B
PJ701 : AC Adaptor Connector
J701&J706 : USB Port Connector
J702 : CRT Connector
J703 : Battery Connector
J704 : External VGA Connector
J705 : Internal Subwoofer Speaker
J707: FAN Connector
J708 : CD-ROM IDE Connector
J709: Lan & Phone Lan Connector
J710 : RTC Battery Connector
J711&J712 : DDR SO-DIMM Module Socket
J713 : Mini-PCI Connector
J714 : Hard Disk Driver Connector
-----To next page-----
J706
PJ701
J701
J713
J
7
1
1
J
7
1
2
J705
J703
J708 J714
J710
J702 J704
J707
J709
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-----Continue From Previous Page-----
J715&J717: Modem Daughter Board Connector
J716 : SD&MS Card Socket
J718 : IEEE 1394 Connector
J719 : External Micro Phone Jack
J720 : Line Out HP/OPT Jack
J721 : External Line-in Jack
J719
J721
J720
J715
J717
J718
J716
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4. Definition & Location of Major Components
4.1 Mother Board - A
PU2 : +3VS/+5VS Voltage Generator
PU3 : CPU Core Voltage Generator
PU14: +1.8V/+1.35V Voltage Generator
PU15 : +2.5VS/+1.25V Voltage Generator
U2 : TV Encoder Controller
U15: SYS BIOS Controller
U16: WINBOND KBC Controller
U524: TPA02012 Audio Amplifier
PU2
PU3
U2
PU14
PU15
U16
U524
U15
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4. Definition & Location of Major Components
U706 : Thermal Sensor/Fan Controller
U713 : Intel BANIAS CPU
U714 : Intel 855GM/GME North Bridge
U715 : Intel ICH4-M South Bridge
U719 : LAN-RTL8100CL Controller
U724 : IEEE1394 Controller
U725 : SUBWOOFER AMP Controller
U726 : Audio CODEC(ALC655)
U727 : CB710 Card Bus Reader Controller
U715
U714
U713
U719
U727
U724
U706
U725
U726
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5. Pin Descriptions of Major Components
5.1 Intel Banias Pentium M Processor(1)
Signal Name Type Description
A[31:3]#

I/O A[31:3]# (Address) define a 2 32 -byte physical memory address space.
In sub-phase 1 of the address phase, these pins transmit the address of a
transaction. In sub-phase 2, these pins transmit transaction type
information. These signals must connect the appropriate pins of both
agents on the Intel Pentium M processor system bus. A[31:3]# are source
synchronous signals and are latched into the receiving buffers by
ADSTB[1:0]#. Address signals are used as straps which are sampled
before RESET# is deasserted.
A20M# I If A20M# (Address-20 Mask) is asserted, the processor masks physical
address bit 20 (A20#) before looking up a line in any internal cache and
before driving a read/write transaction on the bus. Asserting A20M#
emulates the 8086 processor's address wrap-around at the 1-Mbyte
boundary. Assertion of A20M# is only supported in real mode.
A20M# is an asynchronous signal. However, to ensure recognition of
this signal following an Input/Output write instruction, it must be valid
along with the TRDY# assertion of the corresponding Input/Output
Write bus transaction.
ADS# I/O ADS# (Address Strobe) is asserted to indicate the validity of the
transaction address on the A[31:3]# and REQ[4:0]# pins. All bus agents
observe the ADS# activation to begin parity checking, protocol
checking, address decode, internal snoop, or deferred reply ID match
operations associated with the new transaction.
ADSTB[1:0]# I/O Address strobes are used to latch A[31:3]# and REQ[4:0]# on their rising
and falling edges. Strobes are associated with signals as shown below.
Signals Associated Strobe
REQ[4:0]#, A[16:3]# ADSTB[0]#
A[31:17]# ADSTB[1]#

BCLK[1:0] I The differential pair BCLK (Bus Clock) determines the system bus
frequency. All processor system bus agents must receive these signals to
drive their outputs and latch their inputs.
BNR# I/O BNR# (Block Next Request) is used to assert a bus stall by any bus agent
that is unable to accept new bus transactions. During a bus stall, the
current bus owner cannot issue any new transactions.
BPM[2:0]#
BPM[3]
O
I/O
BPM[3:0]# (Breakpoint Monitor) are breakpoint and performance
monitor signals. They are outputs from the processor that indicate the
status of breakpoints and programmable counters used for monitoring
processor performance. BPM[3:0]# should connect the appropriate pins
of all Intel Pentium M processor system bus agents. This includes debug
or performance monitoring tools.

BPRI# I BPRI# (Bus Priority Request) is used to arbitrate for ownership of the
processor system bus. It must connect the appropriate pins of both
processor system bus agents. Observing BPRI# active (as asserted by
the priority agent) causes the other agent to stop issuing new requests,
unless such requests are part of an ongoing locked operation. The
priority agent keeps BPRI# asserted until all of its requests are
completed, then releases the bus by deasserting BPRI#.
BR0# I/O BR0# is used by the processor to request the bus. The arbitration is done
between the Intel Pentium M processor (Symmetric Agent) and the
MCH-M (High Priority Agent) of the Intel 855PM or Intel 855GM
chipset.
COMPP3:0] Analog COMP[3:0] must be terminated on the system board using precision
(1% tolerance) resistors. Refer to the platform design guides for more
implementation details.
D[63:0]# I/O D[63:0]# (Data) are the data signals. These signals provide a 64-bit data
path between the processor system bus agents, and must connect the
appropriate pins on both agents. The data driver asserts DRDY# to
indicate a valid data transfer.
D[63:0]# are quad-pumped signals and will thus be driven four times in
a common clock period. D[63:0]# are latched off the falling edge of
both DSTBP[3:0]# and DSTBN[3:0]#. Each group of 16 data signals
correspond to a pair of one DSTBP# and one DSTBN#. The following
table shows the grouping of data signals to data strobes and DINV#.
Quad-Pumped Signal Groups
Data Group DSTBN#/DSTBP# DINV#
D[15:0]# 0 0
D[31:16]# 1 1
D[47:32]# 2 2
D[63:48]# 3 3
Furthermore, the DINV# pins determine the polarity of the data signals.
Each group of 16 data signals corresponds to one DINV# signal. When
the DINV# signal is active, the corresponding data group is inverted and
therefore sampled active high.
DBR# O DBR# (Data Bus Reset) is used only in processor systems where no
debug port is implemented on the system board. DBR# is used by a
debug port interposer so that an in-target probe can drive system reset. If
a debug port is implemented in the system, DBR# is a no connect.
DBR# is not a processor signal.

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DBSY# I/O DBSY# (Data Bus Busy) is asserted by the agent responsible for driving
data on the processor system bus to indicate that the data bus is in use.
The data bus is released after DBSY# is deasserted. This signal must
connect the appropriate pins on both processor system bus agents.
DEFER# I DEFER# is asserted by an agent to indicate that a transaction cannot be
guaranteed in-order completion. Assertion of DEFER# is normally the
responsibility of the addressed memory or Input/Output agent. This
signal must connect the appropriate pins of both processor system bus
agents.
DINV[3:0]#

I/O DINV[3:0]# (Data Bus Inversion) are source synchronous and indicate
the polarity of the D[63:0]# signals. The DINV[3:0]# signals are
activated when the data on the data bus is inverted. The bus agent will
invert the data bus signals if more than half the bits, within the covered
group, would change level in the next cycle.
DINV[3:0]# Assignment To Data Bus
Bus Signal Data Bus Signals
DINV[3]# D[63:48]#
DINV[2]# D[47:32]#
DINV[1]# D[31:16]#
DINV[0]# D[15:0]#

DPSLP# I DPSLP# when asserted on the platform causes the processor to
transition from the Sleep state to the Deep Sleep state. In order to return
to the Sleep state, DPSLP# must be deasserted. DPSLP# is driven by the
ICH4-M component and also connects to the MCH-M component of the
Intel 855PM or Intel 855GM chipset.
DRDY# I/O DRDY# (Data Ready) is asserted by the data driver on each data
transfer, indicating valid data on the data bus. In a multi-common clock
data transfer, DRDY# may be deasserted to insert idle clocks. This
signal must connect the appropriate pins of both processor system bus
agents.
DSTBN[3:0]# I/O Data strobe used to latch in D[63:0]#.
D[15:0]#, DINV[0]# DSTBN[0]#
D[31:16]#, DINV[1]# DSTBN[1]#
D[47:32]#, DINV[2]# DSTBN[2]#
D[63:48]#, DINV[3]# DSTBN[3]#

DSTBP[3:0]# I/O Data strobe used to latch in D[63:0]#.
D[15:0]#, DINV[0]# DSTBP[0]#
D[31:16]#, DINV[1]# DSTBP[1]#
D[47:32]#, DINV[2]# DSTBP[2]#
D[63:48]#, DINV[3]# DSTBP[3]#

DPWR# I DPWR# is a control signal from the Intel 855PM and Intel 855GM
chipsets used to reduce power on the Intel Pentium M data bus input
buffers.
FERR#/PBE# O FERR# (Floating-point Error)/PBE#(Pending Break Event) is a
multiplexed signal and its meaning is qualified by STPCLK#. When
STPCLK# is not asserted, FERR#/PBE# indicates a floating point when
the processor detects an unmasked floating-point error. FERR# is
similar to the ERROR# signal on the Intel 80387 coprocessor, and is
included for compatibility with systems using MS-DOS* type
floating-point error reporting. When STPCLK# is asserted, an assertion
of FERR#/PBE# indicates that the processor has a pending break event
waiting for service. The assertion of FERR#/PBE# indicates that the
processor should be returned to the Normal state. When FERR#/PBE# is
asserted, indicating a break event, it will remain asserted until
STPCLK# is deasserted. Assertion of PREQ# when STPCLK# is active
will also cause an FERR# break event.
GTLREF I GTLREF determines the signal reference level for AGTL+ input pins.
GTLREF should be set at 2/3 VCCP . GTLREF is used by the AGTL+
receivers to determine if a signal is a logical 0 or logical 1.
HIT#
HITM#
I/O
I/O
HIT# (Snoop Hit) and HITM# (Hit Modified) convey transaction snoop
operation results. Either system bus agent may assert both HIT# and
HITM# together to indicate that it requires a snoop stall, which can be
continued by reasserting HIT# and HITM# together.
IERR# O IERR# (Internal Error) is asserted by a processor as the result of an
internal error. Assertion of IERR# is usually accompanied by a
SHUTDOWN transaction on the processor system bus. This transaction
may optionally be converted to an external error signal (e.g., NMI) by
system core logic. The processor will keep IERR# asserted until the
assertion of RESET#, BINIT#, or INIT#.
IGNNE# I IGNNE# (Ignore Numeric Error) is asserted to force the processor to
ignore a numeric error and continue to execute noncontrol floating-point
instructions. If IGNNE# is deasserted, the processor generates an
exception on a noncontrol floating-point instruction if a previous
floating-point instruction caused an error. IGNNE# has no effect when
the NE bit in control register 0 (CR0) is set.
IGNNE# is an asynchronous signal. However, to ensure recognition of
this signal following an Input/Output write instruction, it must be valid
along with the TRDY# assertion of the corresponding Input/Output
Write bus transaction.
REQ[4:0]# I/O REQ[4:0]# (Request Command) must connect the appropriate pins of
both processor system bus agents. They are asserted by the current bus
owner to define the currently active transaction type. These signals are
source synchronous to ADSTB[0]#.

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INIT#

I INIT# (Initialization), when asserted, resets integer registers inside the
processor without affecting its internal caches or floating-point registers.
The processor then begins execution at the power on Reset vector
configured during power on configuration. The processor continues to
handle snoop requests during INIT# assertion. INIT# is an asynchronous
signal. However, to ensure recognition of this signal following an
Input/Output Write instruction, it must be valid along with the TRDY#
assertion of the corresponding Input/Output Write bus transaction.
INIT# must connect the appropriate pins of both processor system bus
agents. If INIT# is sampled active on the active to inactive transition of
RESET#, then the processor executes its Built-in Self-Test (BIST)
LINT[1:0] I LINT[1:0] (Local APIC Interrupt) must connect the appropriate pins of
all APIC Bus agents. When the APIC is disabled, the LINT0 signal
becomes INTR, a maskable interrupt request signal, and LINT1
becomes NMI, a nonmaskable interrupt. INTR and NMI are backward
compatible with the signals of those names on the Pentium processor.
Both signals are asynchronous.
Both of these signals must be software configured using BIOS
programming of the APIC register space and used either as NMI/INTR
or LINT[1:0]. Because the APIC is enabled by default after Reset,
operation of these pins as LINT[1:0] is the default configuration.
LOCK# I/O LOCK# indicates to the system that a transaction must occur atomically.
This signal must connect the appropriate pins of both processor system
bus agents. For a locked sequence of transactions, LOCK# is asserted
from the beginning of the first transaction to the end of the last
transaction.
When the priority agent asserts BPRI# to arbitrate for ownership of the
processor system bus, it will wait until it observes LOCK# deasserted.
This enables symmetric agents to retain ownership of the processor
system bus throughout the bus locked operation and ensure the
atomicity of lock.
PRDY#

O Probe Ready signal used by debug tools to determine processor debug
readiness.
PREQ# I Probe Request signal used by debug tools to request debug operation of
the processor.
PROCHOT# O PROCHOT# (Processor Hot) will go active when the processor
temperature monitoring sensor detects that the processor has reached its
maximum safe operating temperature. This indicates that the processor
Thermal Control Circuit has been activated, if enabled.
This signal may require voltage translation on the motherboard.
PSI# O Processor Power Status Indicator signal. This signal is asserted when the
processor is in a lower state (Deep Sleep and Deeper Sleep).

PWRGOOD I PWRGOOD (Power Good) is a processor input. The processor requires
this signal as a clean indication that the clocks and power supplies are
stable and within their specifications. Clean implies that the signal will
remain low (capable of sinking leakage current), without glitches, from
the time that the power supplies are turned on until they come within
specification. The signal must then transition monotonically to a high
state. PWRGOOD can be driven inactive at any time, but clocks and
power must again be stable before a subsequent rising edge of
PWRGOOD.
The PWRGOOD signal must be supplied to the processor; it is used to
protect internal circuits against voltage sequencing issues. It should be
driven high throughout the boundary scan operation.
ITP_CLK[1:0] I ITP_CLK[1:0] are copies of BCLK that are used only in processor
systems where no debug port is implemented on the system board.
ITP_CLK[1:0] are used as BCLK[1:0] references for a debug port
implemented on an interposer. If a debug port is implemented in the
system, ITP_CLK[1:0] are no connects. These are not processor signals.
RESET# I Asserting the RESET# signal resets the processor to a known state and
invalidates its internal caches without writing back any of their contents.
For a power-on Reset, RESET# must stay active for at least two
milliseconds after VCC and BCLK have reached their proper
specifications. On observing active RESET#, both system bus agents
will deassert their outputs within two clocks. All processor straps must
be valid within the specified setup time before RESET# is deasserted.
RS[2:0]# I RS[2:0]# (Response Status) are driven by the response agent (the agent
responsible for completion of the current transaction), and must connect
the appropriate pins of both processor system bus agents.
RSVD - These pins are RESERVED and must be left unconnected on the board.
However, it is recommended that routing channels to these pins on the
board be kept open for possible future use. Please refer to the platform
design guides for more details.
SLP# I SLP# (Sleep), when asserted in Stop-Grant state, causes the processor to
enter the Sleep state. During Sleep state, the processor stops providing
internal clock signals to all units, leaving only the Phase-Locked Loop
(PLL) still operating. Processors in this state will not recognize snoops
or interrupts. The processor will recognize only assertion of the
RESET# signal, deassertion of SLP#, and removal of the BCLK input
while in Sleep state. If SLP# is deasserted, the processor exits Sleep
state and returns to Stop-Grant state, restarting its internal clock signals
to the bus and processor core units. If DPSLP# is asserted while in the
Sleep state, the processor will exit the Sleep state and transition to the
Deep Sleep state.

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SMI# I SMI# (System Management Interrupt) is asserted asynchronously by
system logic. On accepting a System Management Interrupt, the
processor saves the current state and enter System Management Mode
(SMM). An SMI Acknowledge transaction is issued, and the processor
begins program execution from the SMM handler.
If SMI# is asserted during the deassertion of RESET# the processor will
tristate its outputs.
STPCLK# I STPCLK# (Stop Clock), when asserted, causes the processor to enter a
low power Stop-Grant state. The processor issues a Stop-Grant
Acknowledge transaction, and stops providing internal clock signals to
all processor core units except the system bus and APIC units. The
processor continues to snoop bus transactions and service interrupts
while in Stop-Grant state. When STPCLK# is deasserted, the processor
restarts its internal clock to all units and resumes execution. The
assertion of STPCLK# has no effect on the bus clock; STPCLK# is an
asynchronous input.
TCK I TCK (Test Clock) provides the clock input for the processor Test Bus
(also known as the Test Access Port).
TDI I TDI (Test Data In) transfers serial test data into the processor. TDI
provides the serial input needed for JTAG specification support.
TDO O TDO (Test Data Out) transfers serial test data out of the processor. TDO
provides the serial output needed for JTAG specification support.
TEST1,
TEST2,
TEST3
I TEST1, TEST2, and TEST3 must be left unconnected but should have a
stuffing option connection to V SS separately using 1-k, pull-down
resisitors.
THERMDA Other Thermal Diode Anode.
THERMDC Other Thermal Diode Cathode.
THERMTRIP# O The processor protects itself from catastrophic overheating by use of an
internal thermal sensor. This sensor is set well above the normal
operating temperature to ensure that there are no false trips. The
processor will stop all execution when the junction temperature exceeds
approximately 125C. This is signalled to the system by the
THERMTRIP# (Thermal Trip) pin.
TMS I TMS (Test Mode Select) is a JTAG specification support signal used by
debug tools.
TRDY# I TRDY# (Target Ready) is asserted by the target to indicate that it is
ready to receive a write or implicit writeback data transfer. TRDY#
must connect the appropriate pins of both system bus agents.
TRST# I TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST#
must be driven low during power on Reset.

VCC I Processor core power supply.
VCCA[3:0] I VCCA provides isolated power for the internal processor core PLLs.
VCCP I Processor I/O Power Supply.
VCCQ[1:0] I Quiet power supply for on die COMP circuitry. These pins should be
connected to VCCP on the motherboard. However, these connections
should enable addition of decoupling on the VCCQ lines if necessary.
VCCSENSE O VCCSENSE is an isolated low impedance connection to processor core
power (VCC ). It can be used to sense or measure power near the silicon
with little noise.
VID[5:0] O VID[5:0] (Voltage ID) pins are used to support automatic selection of
power supply voltages (Vcc). Unlike some previous generations of
processors, these are CMOS signals that are driven by the Intel Pentium
M processor. The voltage supply for these pins must be valid before the
VR can supply Vcc to the processor. Conversely, the VR output must be
disabled until the voltage supply for the VID pins becomes valid. The
VID pins are needed to support the processor voltage specification
variations.
VSSSENSE O VSSSENSE is an isolated low impedance connection to processor core
VSS. It can be used to sense or measure ground near the silicon with
little noise.

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Host Interface Signal Descriptions
ADS# I/O
AGTL+
Address Strobe: The system bus owner asserts ADS# to indicate the
first of two cycles of a request phase. The GMCH can assert this
signal for snoop cycles and
interrupt messages.
BNR# I/O
AGTL+
Block Next Request: Used to block the current request bus owner
from issuing a new request. This signal is used to dynamically control
the CPU bus pipeline depth.
BPRI# O
AGTL+
Bus Priority Request: The GMCH is the only Priority Agent on the
system bus. It asserts this signal to obtain the ownership of the
address bus. This signal has priority over symmetric bus requests and
will cause the current symmetric owner to
stop issuing new transactions unless the HLOCK# signal was
asserted.
BREQ0# I/O
AGTL+
Bus Request 0#: The GMCH pulls the processor bus BREQ0# signal
low during CPURST#. The signal is sampled by the processor on the
active-to-inactive transition of CPURST#. The minimum setup time
for this signal is 4 BCLKs. The minimum hold time is 2 clocks and
the maximum hold time is 20 BCLKs. BREQ0# should be tristated
after the hold time requirement has been satisfied.
During regular operation, the GMCH will use BREQ0# as an early
indication for FSB Address and Ctl input buffer and sense amp
activation.
CPURST# O
AGTL+
CPU Reset: The CPURST# pin is an output from the GMCH. The
GMCH asserts CPURST# while RESET# (PCIRST# from ICH4-M)
is asserted and for approximately 1 ms after RESET# is deasserted.
The CPURST# allows the processor to begin execution in a known
state.
Note that the ICH4-M must provide CPU strap set-up and hold-times
around CPURST#.
This requires strict synchronization between GMCH, CPURST#
deassertion and ICH4-M driving the straps.
DBSY# I/O
AGTL+
Data Bus Busy: Used by the data bus owner to hold the data bus for
transfers requiring more than one cycle.
DEFER# O
AGTL+
Defer: GMCH will generate a deferred response as defined by the
rules of the GMCHs Dynamic Defer policy. The GMCH will also
use the DEFER# signal to indicate a CPU retry response.

DINV[3:0]# I/O
AGTL+
Dynamic Bus Inversion: Driven along with the HD[63:0]# signals.
Indicates if the associated signals are inverted or not. DINV[3:0]# are
asserted such that the number of data bits driven electrically low (low
voltage) within the corresponding 16-bit group never exceeds 8.
DINV# Data Bits
DINV[3]# HD[63:48]#
DINV[2]# HD[47:32]#
DINV[1]# HD[31:16]#
DINV[0]# HD[16:0]#
DPSLP# I
CMOS
Deep Sleep #: This signal comes from the ICH4-M device, providing
an indication of C3 and C4 state control to the CPU. Deassertion of
this signal is used as an early indication for C3 and C4 wake up (to
active HPLL). Note that this is a low-voltage
CMOS buffer operating on the FSB VTT power plane.
DRDY# I/O
AGTL+
Data Ready: Asserted for each cycle that data is transferred.
HA[31:3]# I/O
AGTL+
Host Address Bus: HA[31:3]# connects to the CPU address bus.
During processor cycles the HA[31:3]# are inputs. The GMCH drives
HA[31:3]# during snoop cycles on behalf of Hub interface.
HA[31:3]# are transferred at 2x rate. Note that the
address is inverted on the CPU bus.
HADSTB[1:0]# I/O
AGTL+
Host Address Strobe: HA[31:3]# connects to the CPU address bus.
During CPU cycles, the source synchronous strobes are used to
transfer HA[31:3]# and HREQ[4:0]# at the 2x transfer rate.
Strobe Address Bits
HADSTB[0]# HA[16:3]#, HREQ[4:0]#
HADSTB[1]# HA[31:17]#
HD[63:0]# I/O
AGTL+
Host Data: These signals are connected to the CPU data bus.
HD[63:0]# are transferred at 4x rate. Note that the data signals are
inverted on the CPU bus.

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Host Interface Signal Descriptions (Continued)
HDSTBP[3:0]#
HDSTBN[3:0]#
I/O
AGTL+
Differential Host Data Strobes: The differential source synchronous
strobes are used to transfer HD[63:0]# and DINV[3:0]# at the 4x
transfer rate.
Strobe Data Bits
HDSTBP[3]#, HDSTBN[3]# HD[63:48]#, DINV[3]#
HIT# I/O
AGTL+
Hit: Indicates that a caching agent holds an unmodified version of the
requested line. Also, driven in conjunction with HITM# by the target
to extend the snoop window.
HITM# I/O
AGTL+
Hit Modified: Indicates that a caching agent holds a modified version
of the requested line and that this agent assumes responsibility for
providing the line.
Also, driven in conjunction with HIT# to extend the snoop window.
HLOCK# I/O
AGTL+
Host Lock: All CPU bus cycles sampled with the assertion of
HLOCK# and ADS#, until the negation of HLOCK# must be atomic,
i.e. no Hub interface snoopable access to system memory is allowed
when HLOCK# is asserted by the CPU.
HREQ[4:0]# I/O
AGTL+
Host Request Command: Defines the attributes of the request.
HREQ[4:0]# are transferred at 2x rate. Asserted by the requesting
agent during both halves of the Request Phase. In the first half the
signals define the transaction type to a level of
detail that is sufficient to begin a snoop request. In the second half the
signals carry additional information to define the complete transaction
type.
The transactions supported by the GMCH Host Bridge are defined in
the Host Interface section of this document.
HTRDY# O
AGTL+
Host Target Ready: Indicates that the target of the processor
transaction is able to enter the data transfer phase.
RS[2:0]# O
AGTL+
Response Status: Indicates the type of response according to the
following the table:
RS[2:0]# Response type
000 Idle state
001 Retry response
010 Deferred response
011 Reserved (not driven by GMCH)
100 Hard Failure (not driven by GMCH)
101 No data response
110 Implicit Write back
111 Normal data response

DDR SDRAM Interface Descriptions
SCS[3:0]# O
SSTL_2
Chip Select: These pins select the particular DDR SDRAM
components during the active state.
NOTE: There is one SCS# per DDR-SDRAM Physical SO-DIMM
device row.
These signals can be toggled on every rising System Memory Clock
edge (SCMDCLK).
SMA[12:0] O
SSTL_2
Multiplexed Memory Address: These signals are used to provide
the multiplexed row and column address to the DDR SDRAM.
SBA[1:0] O
SSTL_2
Bank Select (Memory Bank Address): These signals define which
banks are selected within each DDR SDRAM row. The SMA and
SBA signals combine to address every possible location within a
DDR SDRAM device.
SRAS# O
SSTL_2
DDR Row Address Strobe: SRAS# may be heavily loaded and
requires tw0 DDR SDRAM clock cycles for setup time to the DDR
SDRAMs. Used with SCAS# and SWE# (along with SCS#) to define
the system memory commands.
SCAS# O
SSTL_2
DDR Column Address Strobe: SCAS# may be heavily loaded and
requires two clock cycles for setup time to the DDR SDRAMs. Used
with SRAS# and SWE# (along with SCS#) to define the system
memory commands.
SWE# O
SSTL_2
Write Enable: Used with SCAS# and SRAS# (along with SCS#) to
define the DDR SDRAM commands. SWE# is asserted during writes
to DDR SDRAM.
SWE# may be heavily loaded and requires two clock cycles for setup
time to the DDR SDRAMs.
SDQ[71:0] I/O
SSTL_2
Data Lines: These signals are used to interface to the DDR SDRAM
data bus.
NOTE: ECC error detection is supported: by the SDQ[71:64] signals.

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DDR SDRAM Interface Descriptions (Continued)
SDQS[8:0] I/O
SSTL_2
Data Strobes: Data strobes are used for capturing data. During
writes, SDQS is centered on data. During reads, SDQS is edge
aligned with data. The following list matches the data strobe with the
data bytes.
There is an associated data strobe (DQS) for each data signal (DQ)
and check bit
(CB) group.
SDQS[7] -> SDQ[63:56]
SDQS[6] -> SDQ[55:48]
SDQS[5] -> SDQ[47:40]
SDQS[4] -> SDQ[39:32]
SDQS[3] -> SDQ[31:24]
SDQS[2] -> SDQ[23:16]
SDQS[1] -> SDQ[15:8]
SDQS[0] -> SDQ[7:0]
NOTE: ECC error detection is supported by the SDQS[8] signal.
SCKE[3:0] O
SSTL_2
Clock Enable: These pins are used to signal a self-refresh or power
down command to the DDR SDRAM array when entering system
suspend. SCKE is also used to dynamically power down inactive
DDR SDRAM rows. There is one
SCKE per DDR SDRAM row. These signals can be toggled on every
rising SCK edge.
SMAB[5,4,2,1] O
SSTL_2
Memory Address Copies: These signals are identical to
SMA[5,4,2,1] and are used to reduce loading for selective
CPC(clock-per-command). These copies are not inverted.
SDM[8:0] O
SSTL_2
Data Mask: When activated during writes, the corresponding data
groups in the DDR SDRAM are masked. There is one SDM for every
eight data lines. SDM can be sampled on both edges of the data
strobes.
NOTE: ECC error detection is supported by the SDM[8] signal.
RCVENOUT# O
SSTL_2
Clock Output: Reserved, NC.
RCVENIN# O
SSTL_2
Clock Input: Reserved, NC.

AGP Addressing Signal Descriptions
GPIPE# I
AGP
Pipelined Read: This signal is asserted by the AGP master to
indicate a full width address is to be enqueued on by the target using
the AD bus. One address is placed
in the AGP request queue on each rising clock edge while PIPE# is
asserted. When PIPE# is deasserted no new requests are queued
across the AD bus.
During SBA Operation: This signal is not used if SBA (Side Band
Addressing) is selected.
During FRAME# Operation: This signal is not used during AGP
FRAME# operation.
PIPE# is a sustained tri-state signal from masters (graphics
controller), and is an input to the GMCH.
GSBA[7:0] I
AGP
Side-band Address: These signals are used by the AGP master
(graphics controller) to pass address and command to the GMCH. The
SBA bus and AD bus operate independently. That is, transactions can
proceed on the SBA bus and the
AD bus simultaneously.
During PIPE# Operation: These signals are not used during PIPE#
operation.
During FRAME# Operation: These signals are not used during
AGP FRAME# operation.
NOTE: When sideband addressing is disabled, these signals are
isolated (no external/internal pull-ups are required).
5 contains two mechanisms to queue requests by the AGP master. Note that the master can only use
one mechanism. The master may not switch methods without a full reset of the system. When PIPE# is
used to queue addresses the master isnot allowed to queue addresses using the SBA bus. For example,
during configuration time, if the master indicates that it can use either mechanism, the configuration
software will indicate which mechanism the master will use. Once this choice has been made, the
master will continue to use the mechanism selected until the master is reset (and reprogrammed) to use
the other mode. This change of modes is not a dynamic mechanism, but rather a static decision when
the device is first being configured after reset
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AGP Flow Control Signals
GRBF# I
AGP
Read Buffer Full: Read buffer full indicates if the master is ready to
accept previously requested low priority read data. When RBF# is
asserted the GMCH is not allowed to initiate the return low priority
read data. That is, the GMCH can finish
returning the data for the request currently being serviced. RBF# is
only sampled at the beginning of a cycle.
If the AGP master is always ready to accept return read data then it is
not required to implement this signal.
FRAME# operation.
GWBF# I
AGP
Write-Buffer Full: indicates if the master is ready to accept Fast
Write data from the GMCH. When WBF# is asserted the GMCH is
not allowed to drive Fast Write data to the AGP master. WBF# is
only sampled at the beginning of a cycle.
If the AGP master is always ready to accept fast write data then it is
not required to implement this signal.
FRAME# operation.

AGP Status Signal Descriptions
ST[2:0 Meaning
000 Previously requested low priority
read data is being returned to the
master arbiter to an AGP
001 Previously requested high priority
read data is being returned to the
master
010 The master is to provide low priority
write data for a previously queued
write command
011 The master is to provide high
priority write data for a previously
queued write command.
100 Reserved
101 Reserved
110 Reserved
GST[2:0] O
AGP
Status: Provides
information from
the arbiter to an
AGP Master on
what it may do.
ST[2:0] only
have meaning
to the master
when its GNT# is
asserted. When
GNT# is
deasserted
these signals have
no meaning and
must be gnored.
111 The master has been given
permission to start a bus transaction.
The master may queue AGP requests
by asserting PIPE# or start a PCI
transaction by asserting FRAME#

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AGP Strobe Descriptions
GADSTB[0] I/O
AGP
Address/Data Bus Strobe-0: provides timing for 2x and 4x data on
AD[15:0] and C/BE[1:0]# signals. The agent that is providing the
data will drive this signal.
GADSTB#[0] I/O
AGP
Address/Data Bus Strobe-0 Complement: With AD STB0, forms a
differential strobe pair that provides timing information for the
GADSTB[1] I/O
AGP
Address/Data Bus Strobe-1: Provides timing for 2x and 4x data on
GADSTB#[1] I/O
AGP
Address/Data Bus Strobe-1 Complement: With AD STB1, forms a
differential strobe pair that provides timing information for the
AD[15:0] and C/BE[1:0]# signals in 4X mode. The agent that is
providing the data will drive this signal.
GSBSTB I
AGP
Sideband Strobe: Provides timing for 2x and 4x data on the
SBA[7:0] bus. It is driven by the AGP master after the system has
been configured for 2x or 4x sideband address mode.
GSBSTB# I
AGP
Sideband Strobe Complement: The differential complement to the
SB_STB signal. It is used to provide timing 4x mode.

AGP/PCI Signals-Semantics Descriptions
GFRAME# I/O
AGP
G_FRAME: Frame.
During PIPE# and SBA Operation: Not used by AGP SBA and
PIPE# operations.
During Fast Write Operation: Used to frame transactions as an
output during Fast Writes.
During FRAME# Operation: G_FRAME# is an output when the
GMCH acts as an initiator on the AGP Interface. G_FRAME# is
asserted by the GMCH to indicate the
beginning and duration of an access. G_FRAME# is an input when
the GMCH acts as a FRAME#-based AGP target. As a
FRAME#-based AGP target, the GMCH latches the C/BE[3:0]# and
the AD[31:0] signals on the first clock edge on which
GMCH samples FRAME# active.
GIRDY# I/O
AGP
G_IRDY#: Initiator Ready.
During PIPE# and SBA Operation: Not used while enqueueing
requests via AGP SBA and PIPE#, but used during the data phase of
PIPE# and SBA transactions.
During FRAME# Operation: G_IRDY# is an output when GMCH
acts as a FRAME#-based AGP initiator and an input when the GMCH
acts as a FRAME#-based AGP target. The assertion of G_IRDY#
indicates the current FRAME#-based AGP bus initiator's ability to
complete the current data phase of the transaction.
During Fast Write Operation: In Fast Write mode, G_IRDY#
indicates that the AGP-compliant master is ready to provide all write
data for the current transaction. Once G_IRDY# is asserted for a write
operation, the master is not allowed to insert wait states. The master is
never allowed to insert a wait state during the initial data transfer (32
bytes) of a write transaction. However, it may insert wait states after
each 32-byte block is transferred.

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AGP/PCI Signals-Semantics Descriptions (Continued)
GTRDY# I/O
AGP
G_TRDY#: Target Ready.
During PIPE# and SBA Operation: Not used while enqueueing
requests via AGP SBA and PIPE#, but used during the data phase of
PIPE# and SBA transactions.
During FRAME# Operation: G_TRDY# is an input when the
GMCH acts as an AGP initiator and is an output when the GMCH
acts as a FRAME#-based AGP target. The assertion of G_TRDY#
indicates the targets ability to complete the current data phase of the
transaction.
During Fast Write Operation: In Fast Write mode, G_TRDY#
indicates the AGP-compliant target is ready to receive write data for
the entire transaction (when the transfer size is less than or equal to 32
bytes) or is ready to transfer the initial or
subsequent block (32 bytes) of data when the transfer size is greater
than 32 bytes. The target is allowed to insert wait states after each
block (32 bytes) is transferred on write transactions.
GSTOP# I/O
AGP
G_STOP#: Stop.
During PIPE# and SBA Operation: This signal is not used during
PIPE# or SBA operation.
During FRAME# Operation: G_STOP# is an input when the
GMCH acts as a FRAME#-based AGP initiator and is an output when
the GMCH acts as a FRAME#-based AGP target. G_STOP# is used
for disconnect, retry, and abort sequences on the AGP interface.
GDEVSEL# I/O
AGP
G_ DEVSEL#: Device Select.
During PIPE# and SBA Operation: This signal is not used during
PIPE# or SBA operation.
During FRAME# Operation: G_DEVSEL#, when asserted,
indicates that a FRAME#-based AGP target device has decoded its
address as the target of the current access. The GMCH asserts
G_DEVSEL# based on the DDR SDRAM
address range being accessed by a PCI initiator. As an input,
G_DEVSEL# indicates whether the AGP master has recognized a
PCI cycle to it.
GREQ# I
AGP
G_REQ#: Request.
During SBA Operation: This signal is not used during SBA
operation.
During PIPE# and FRAME# Operation: G_REQ#, when asserted,
indicates that the AGP master is requesting use of the AGP interface
to run a FRAME#- or PIPE#-based operation.

GGNT# O
AGP
G_GNT#: Grant.
During SBA, PIPE# and FRAME# Operation: G_GNT#, along
with the information on the ST[2:0] signals (status bus), indicates
how the AGP interface will be used next. Refer to the AGP Interface
Specification, Revision 2.0 for further explanation
of the ST[2:0] values and their meanings.
GAD[31:0] I/O
AGP
G_AD[31:0]: Address/Data Bus.
During PIPE# and FRAME# Operation: The G_AD[31:0] signals
are used to transfer both address and data information on the AGP
interface.
During SBA Operation: The G_AD[31:0] signals are used to
transfer data on the AGP interface.
GCBE#[3:0] I/O
AGP
Command/Byte Enable.
During FRAME# Operation: During the address phase of a
transaction, the G_CBE[3:0]# signals define the bus command.
During the data phase, the G_CBE[3:0]# signals are used as byte
enables. The byte enables determine which byte lanes carry
meaningful data. The commands issued on the G_CBE# signals
during FRAME#-based AGP transactions are the same G_CBE#
command described in the PCI 2.2 specification.
During PIPE# Operation: When an address is enqueued using
PIPE#, the C/BE# signals carry command information. The command
encoding used during PIPE#-based AGP is different than the
command encoding used during FRAME#-based AGP cycles (or
standard PCI cycles on a PCI bus).
During SBA Operation: These signals are not used during SBA
operation.
GPAR I/O
AGP
Parity.
During FRAME# Operation: G_PAR is driven by the GMCH when
it acts as a FRAME#-based AGP initiator during address and data
phases for a write cycle, and during the address phase for a read
cycle. G_PAR is driven by the GMCH when it acts as a
FRAME#-based AGP target during each data phase of a
FRAME#-based AGP memory read cycle. Even parity is generated
across G_AD[31:0] and G_CBE[3:0]#.
During SBA and PIPE# Operation: This signal is not used during
SBA and PIPE# operation.
PCIRST# from the ICH4-M is assumed to be connected to RSTIN# and is used to reset AGP interface
logic within the GMCH. The AGP agent will also typically use PCIRST# provided by the ICH4-M as
an input to reset its internal logic.
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Hub Interface Signals
HL[10:0] I/O
Hub
Packet Data: Data signals used for HI read and write operations.
HLSTB I/O
Hub
Packet Strobe: One of two differential strobe signals used to transmit
or receive packet data over HI.
HLSTB# I/O
Hub
Packet Strobe Complement: One of two differential strobe signals
used to transmit or receive packet data over HI.

Dedicated LVDS LCD Flat Panel Interface Signal Descriptions
Name Type Voltage Description
ICLKAP O
LVDS
1.25 V 225 mV Channel A differential clock pair output (true):
245-800 MHz
ICLKAM O
LVDS
1.25 V225 mV Channel A differential clock pair output
(compliment): 245-800 MHz.
IYAP[3:0] O
LVDS
1.25 V225 mV Channel A differential data pair 3:0 output (true):
245-800MHz.
IYAM[3:0] O
LVDS
1.25 V225 mV Channel A differential data pair 3:0 output
ICLKBP O
LVDS
1.25 V225 mV Channel B differential clock pair output (true):
245-800 MHz.
ICLKBM O
LVDS
1.25 V225 mV Channel B differential clock pair output
IYBP[3:0] O
LVDS
1.25 V225 mV Channel B differential data pair 3:0 output (true):
245-800MHz.
IYBM[3:0] O
LVDS
1.25 V 225 mV Channel B differential data pair 3:0 output

Digital Video Output B (DVOB) Port Signal Descriptions
Name Type Description
DVOBD[11:0] O
DVO
DVOB Data: This data bus is used to drive 12-bit RGB data on each
edge of the differential clock signals, DVOBCLK and DVOBCLK#.
This provides 24-bits of data per clock period. In dual channel mode,
this provides the lower 12-bits of pixel data.
DVOBD[11:0] should be left as left as NC (Not Connected) if not
used.
DVOBHSYNC O
DVO
Horizontal Sync: HSYNC signal for the DVOB interface.
DVOBHSYNC should be left as left as NC (Not Connected) if not
used.
DVOBVSYNC O
DVO
Vertical Sync: VSYNC signal for the DVOB interface.
DVOBVSYNC should be left as left as NC (Not Connected) if the
signal is NOT used when using internal graphics device.
DVOBBLANK# O
DVO
Flicker Blank or Border Period Indication: DVOBBLANK# is a
programmable output pin driven by the GMCH.
When programmed as a blank period indication, this pin indicates
active pixels excluding the border. When programmed as a border
period indication, this pin indicates active pixel including the border
pixels.
DVOBBLANK# should be left as left as NC (Not Connected) if not
used.
DVOBFLDSTL I
DVO
TV Field and Flat Panel Stall Signal. This input can be
programmed to be either a TV Field input from the TV encoder or
Stall input from the flat panel.
DVOB TV Field Signal: When used as a Field input, it synchronizes
the overlay field with the TV encoder field when the overlay is
displaying an interleaved source.
DVOB Flat Panel Stall Signal: When used as the Stall input, it
indicates that the pixel pipeline should stall one horizontal line. The
signal changes during horizontal blanking. The panel fitting logic,
when expanding the image vertically, uses this.
DVOBFLDSTL needs to be pulled down if not used.

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Digital Video Output C (DVOC) Port Signal Descriptions
DVOCD[11:0] O
DVO
DVOC Data: This data bus is used to drive 12-bit RGB data on each
edge of the differential clock signals, DVOCCLK and DVOCCLK#.
This provides 24-bits of data per clock period. In dual channel mode,
this provides the upper 12-bits of pixel data.
DVOCD[11:0] should be left as left as NC (Not Connected) if not
used.
DVOCHSYNC O
DVO
Horizontal Sync: HSYNC signal for the DVOC interface.
DVOCHSYNC should be left as left as NC (Not Connected) if not
used.
DVOCVSYNC O
DVO
Vertical Sync: VSYNC signal for the DVOC interface.
DVOCVSYNC should be left as left as NC (Not Connected) if the
signal is NOT used when using internal graphics device.
DVOCBLANK# O
DVO
Flicker Blank or Border Period Indication: DVOCBLANK# is a
programmable output pin driven by the GMCH.
When programmed as a blank period indication, this pin indicates
active pixels excluding the border. When programmed as a border
period indication, this pin indicates active pixel including the border
pixels.
DVOCBLANK# should be left as left as NC (Not Connected) if not
used.
DVOCFLDSTL I
DVO
TV Field and Flat Panel Stall Signal. This input can be
programmed to be either a TV Field input from the TV encoder or
Stall input from the flat panel.
DVOC TV Field Signal: When used as a Field input, it synchronizes
the overlay field with the TV encoder field when the overlay is
displaying an interleaved source.
DVOC Flat Panel Stall Signal: When used as the Stall input, it
indicates that the pixel pipeline should stall one horizontal line. The
signal changes during horizontal blanking. The panel fitting logic,
when expanding the image vertically, uses this.
DVOCFLDSTL needs to be pulled down if not used.

DVOB and DVOC Port Common Signal Descriptions
DVOBCINTR# I
DVO
DVOBC Interrupt: This pin is used to signal an interrupt, typically
used to indicate a hot plug or unplug of a digital display.
ADDID[7:0] I
DVO
ADDID[7:0]: These pins are used to communicate to the Video BIOS
when an external device is interfaced to the DVO port.
Note: Bit[7] needs to be strapped low when an on-board DVO device
is present.
The other pins should be left as NC.
DVODETECT I
DVO
DVODETECT: This strapping signal indicates to the GMCH
whether a DVO device is present or not. When a DVO device is
connected, then DVODETECT = 0.

Analog CRT Display Signal Descriptions
Pin Name Type Description
VSYNC O
CMOS
CRT Vertical Synchronization: This signal is used as the vertical
sync signal.
HSYNC O
CMOS
CRT Horizontal Synchronization: This signal is used as the
horizontal sync signal.
RED O
Analog
Red (Analog Video Output): This signal is a CRT Analog video
output from the internal color palette DAC. The DAC is designed for
a 37.5- equivalent load on each pin (e.g., 75- resistor on the
board, in parallel with the 75- CRT load).
RED# O
Analog
Red# (Analog Output): Tied to ground.
GREEN O
Analog
Green (Analog Video Output): This signal is a CRT analog video
a 37.5- equivalent load on each pin (e.g.,75- resistor on the
board, in parallel with the 75- CRT load).
GREEN# O
Analog
Green# (Analog Output): Tied to ground.
BLUE O
Analog
Blue (Analog Video Output) : This signal is a CRT Analog video
a 37.5- equivalent load on each pin (e.g., 75-
ohm resistor on the board, in parallel with the 75- CRT load).
BLUE# O
Analog
Blue# (Analog Output): Tied to ground.

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GPIO Signal Descriptions

GPIO I/F Total Type Comments
RSTIN# I
CMOS
Reset: Primary Reset, Connected to PCIRST# of ICH4-M.
PWROK I
CMOS
Power OK: Indicates that power to GMCH is stable.
AGPBUSY# O
CMOS
AGPBUSY: Output of the GMCH IGD to the ICH4-M, which
indicates that certain graphics activity is taking place. It will indicate
to the ACPI software not to enter the C3 state. It will
also cause a C3/C4 exit if C3/C4 was being entered, or was already
entered when
AGPBUSY# went active. Not active when the IGD is in any ACPI
state other than D0.
EXTTS_0 I
CMOS
External Thermal Sensor Input: This signal is an active low input
to the GMCH and is used to monitor the thermal condition around the
system memory and is used for triggering a read throttle. The GMCH
can be optionally programmed to send a SERR, SCI, or SMI message
to the ICH4-M upon the triggering
of this signal.
LCLKCTLA O
CMOS
SSC Chip Clock Control: Can be used to control an external clock
chip with SSC control.
LCLKCTLB O
CMOS
SSC Chip Data Control: Can be used to control an external clock
chip for SSC control.
PANELVDDEN O
CMOS
LVDS LCD Flat Panel Power Control: This signal is used enable
power to the panel interface.
PANELBKLTE
N
O
CMOS
LVDS LCD Flat Panel Backlight Enable: This signal is used to
enable the backlight inverter (BLI)
PANELBKLTC
TL
O
CMOS
LVDS LCD Flat Panel Backlight Brightness Control: This signal
is used as the Pulse
Width Modulated (PWM) control signal to control the backlight
inverter.
DDCACLK I/O
CMOS
CRT DDC Clock: This signal is used as the DDC clock signal
between the CRT monitor and the GMCH.
DDCADATA I/O
CMOS
CRT DDC Data: This signal is used as the DDC data signal between
the CRT monitor and the GMCH.
DDCPCLK I/O
CMOS
Panel DDC Clock: This signal is used as the DDC clock signal
between the LFP and the GMCH.
DDCPDATA I/O
CMOS
Panel DDC Data: This signal is used as the DDC data signal
between the LFP and the GMCH.

GPIO I/F Total Type Comments
MI2CCLK I/O
DVO
DVO I2C Clock: This signal is used as the I2C_CLK for a digital
display (i.e. TV-Out Encoder, TMDS transmitter). This signal is
tri-stated during a hard reset.
MI2CDATA I/O
DVO
DVO I2C Data: This signal is used as the I2C_DATA for a digital
display (i.e. TV-Out Encoder, TMDS transmitter). This signal is
MDVICLK I/O
DVO
DVI DDC Clock: This signal is used as the DDC clock for a digital
display connector (i.e. primary digital monitor). This signal is
MDVIDATA I/O
DVO
DVI DDC Data: The signal is used as the DDC data for a digital
display connector (i.e. primary digital monitor). This signal is
MDDCDATA I/O
DVO
DVI DDC Clock: The signal is used as the DDC data for a digital
display connector (i.e. secondary digital monitor). This signal is
MDDCCLK I/O
DVO
DVI DDC Data: The signal is used as the DDC clock for a digital
display connector (i.e. secondary digital monitor). This signal is
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Hub Interface Signals
HI[11:0] I/O Hub Interface Signals
HI_STB/HI_STBS I/O Hub Interface Strobe/ Hub Interface Strobe Second: One of two
differential strobe signals used to transmit and receive data through
the hub interface.
Hub Interface 1.5 mode this signal is not differential and is the
second of the two strobe signals.
HI_STB#/
HI_STBF
I/O Hub Interface Strobe Complement / Hub Interface Strobe First:
One of two differential strobe signals used to transmit and receive
data through the hub interface.
Hub Interface 1.5 mode this signal is not differential and is the first
of the two strobe signals.
HICOMP I/O Hub Interface Compensation: Used for hub interface buffer
compensation.
HI_VSWING I Hub Interface Voltage Swing: Analog input used to control the
voltage swing and impedance strength of hub interface pins.

LAN Connect Interface Signals
LAN_CLK I LAN I/F Clock: Driven by the LAN Connect component.
Frequency range is 5 MHz to 50 MHz.
LAN_RXD[2:0] I Received Data: The LAN Connect component uses these signals to
transfer data and control information to the integrated LAN
Controller. These signals have integrated weak pull-up resistors.
LAN_TXD[2:0] O Transmit Data: The integrated LAN Controller uses these signals
to transfer data and control information to the LAN Connect
component.
LAN_RSTSYNC O LAN Reset/Sync: The LAN Connect components Reset and Sync
signals are multiplexed onto this pin.

EEPROM Interface Signals
EE_SHCLK O EEPROM Shift Clock: Serial shift clock output to the EEPROM.
EE_DIN I EEPROM Data In: Transfers data from the EEPROM to the ICH3.
This signal has an integrated pull-up resistor.
EE_DOUT O EEPROM Data Out: Transfers data from the ICH3 to the
EEPROM.
EE_CS O EEPROM Chip Select: Chip select signal to the EEPROM.

Firmware Hub Interface Signals
FWH[3:0]/
LAD[3:0]
I/O Firmware Hub Signals. Muxed with LPC address signals.
FWH[4]/
LFRAME#
I/O LFRAME# Firmware Hub Signals. Muxed with LPC LFRAME#
signal.

PCI Interface Signals
AD[31:0] I/O PCI Address/Data: AD[31:0] is a multiplexed address and data
bus. During the first clock of a transaction, AD[31:0] contain a
physical address (32 bits). During subsequent clocks, AD[31:0]
contain data. The ICH4 drives all 0s on AD[31:0] during the address
phase of all PCI Special Cycles.
C/BE[3:0]# I/O Bus Command and Byte Enables: The command and byte enable
signals are multiplexed on the same PCI pins. During the address
phase of a transaction, C/BE[3:0]# define the bus command. During
the data phase, C/BE[3:0]# define the Byte Enables.
C/BE[3:0]# Command Type
0 0 0 0 Interrupt Acknowledge
0 0 0 1 Special Cycle
0 0 1 0 I/O Read
0 0 1 1 I/O Write
0 1 1 0 Memory Read
0 1 1 1 Memory Write
1 0 1 0 Configuration Read
1 0 1 1 Configuration Write
1 1 0 0 Memory Read Multiple
1 1 1 0 Memory Read Line
1 1 1 1 Memory Write and Invalidate
All command encodings not shown are reserved. The ICH4 does not
decode reserved values, and therefore will not respond if a PCI
master generates a cycle using one of the reserved values.
DEVSEL# I/O Device Select: The ICH4 asserts DEVSEL# to claim a PCI
transaction. As an output, the ICH4 asserts DEVSEL# when a PCI
master peripheral attempts an access to an internal ICH4 address or
an address destined for the hub interface (main memory or AGP).
As an input, DEVSEL# indicates the response to an ICH4-initiated
transaction on the PCI bus. DEVSEL# is tri-stated from the leading
edge of PCIRST#. DEVSEL# remains tri-stated by the ICH4 until
driven by a Target device.

5.3 Intel 82801DBM I/O Controller Hub 4 Mobile (ICH4-M)(1)
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PCI Interface Signals (Continued)
FRAME# I/O Cycle Frame: The current Initiator drives FRAME# to indicate the
beginning and duration of a PCI transaction. While the Initiator
asserts FRAME#, data transfers continue. When the Initiator
negates FRAME#, the transaction is in the final data phase.
FRAME# is an input to the ICH4 when the ICH4 is the Target, and
FRAME# is an output from the ICH4 when the ICH4 is the Initiator.
FRAME# remains tri- stated by the ICH4 until driven by an
Initiator.
IRDY# I/O Initiator Ready: IRDY# indicates the ICH4's ability, as an
Initiator, to complete the current data phase of the transaction. It is
used in conjunction with TRDY#. A data phase is completed on any
clock that both IRDY# and TRDY# are sampled asserted. During a
write, IRDY# indicates the ICH4 has valid data present on
AD[31:0]. During a read, it indicates the ICH4 is prepared to latch
data. IRDY# is an input to the ICH4 when the ICH4 is the Target
and an output from the ICH4 when the ICH4 is an Initiator. IRDY#
remains tri-stated by the ICH4 until driven by an Initiator.
TRDY# I/O Target Ready: TRDY# indicates the ICH4's ability, as a Target, to
complete the current data phase of the transaction. TRDY# is used
in conjunction with IRDY#. A data phase is completed when both
TRDY# and IRDY# are sampled asserted.
During a read, TRDY# indicates that the ICH4, as a Target, has
placed valid data on AD[31:0]. During a write, TRDY# indicates
that the ICH4, as a Target, is prepared to latch data. TRDY# is an
input to the ICH4 when the ICH4 is the Initiator and an output from
the ICH4 when the ICH4 is a Target. TRDY# is tri-stated from the
leading edge of PCIRST#. TRDY# remains tri-stated by the ICH4
until driven by a target.
PAR I/O Calculated/Checked Parity: PAR uses even parity calculated on
36 bits, AD[31:0] plus C/BE[3:0]#. Even parity means that the
ICH4 counts the number of 1s within the 36 bits plus PAR and the
sum is always even. The ICH4 always calculates PAR on 36 bits
regardless of the valid byte enables. The ICH4 generates PAR for
address and data phases and only guarantees PAR to be valid one
PCI clock after the corresponding address or data phase. The ICH4
drives and tri-states PAR identically to the AD[31:0] lines except
that the ICH4 delays PAR by exactly one PCI clock. PAR is an
output during the address phase (delayed one clock) for all ICH4
initiated transactions. PAR is an output during the data phase
(delayed one clock) when the ICH4 is the Initiator of a PCI write
transaction, and when it is the Target of a read transaction. ICH4
checks parity when it is the Target of a PCI write transaction. If a
parity error is detected, the ICH4 will set the appropriate internal
status bits, and has the option to generate an NMI# or SMI#.

STOP# I/O Stop: STOP# indicates that the ICH4, as a Target, is requesting the
Initiator to stop the current transaction. STOP# causes the ICH4, as
an Initiator, to stop the current transaction. STOP# is an output
when the ICH4 is a Target and an input when the ICH4 is an
Initiator. STOP# is tri-stated from the leading edge of PCIRST#.
STOP# remains tri-stated until driven by the ICH4.
PERR# I/O Parity Error: An external PCI device drives PERR# when it
receives data that has a parity error. The ICH4 drives PERR# when
it detects a parity error. The ICH4 can either generate an NMI# or
SMI# upon detecting a parity error (either detected internally or
reported via the PERR# signal).
REQ[4:0]#
REQ[5]#/
REQ[B]#/
GPIO[1]
I PCI Requests: The ICH4 supports up to 6 masters on the PCI bus.
REQ[5]# is muxed with PC/PCI REQ[B]# (must choose one or the
other, but not both). If not used for PCI or PC/PCI,
REQ[5]#/REQ[B]# can instead be used as GPIO[1].
NOTE: REQ[0]# is programmable to have improved arbitration
latency for for supporting PCI-based 1394 controllers.
GNT[4:0]#
GNT[5]#/
GNT[B]#/
GPIO[17]
O PCI Grants: The ICH4 supports up to 6 masters on the PCI bus.
GNT[5]# is muxed with PC/PCI GNT[B]# (must choose one or the
other, but not both). If not needed for PCI or PC/PCI, GNT[5]# can
instead be used as a GPIO.
Pull-up resistors are not required on these signals. If pull-ups are
used, they should be tied to the Vcc3_3 power rail.
GNT[B]#/GNT[5]#/GPIO[17] has an internal pull-up.
PCICLK I PCI Clock: This is a 33 MHz clock. PCICLK provides timing for
all transactions on the PCI Bus.
NOTE: This clock does not stop based on STP_PCI# signal.
PCICLK only stops based on SLP_S1# or SLP_S3#.
PCIRST# O PCI Reset: ICH4 asserts PCIRST# to reset devices that reside on
the PCI bus. The ICH4 asserts PCIRST# during power-up and when
S/W initiates a hard reset sequence through the RC (CF9h) register.
The ICH4 drives PCIRST# inactive a minimum of 1 ms after
PWROK is driven active. The ICH4 drives PCIRST# active
a minimum of 1 ms when initiated through the RC register.
PLOCK# I/O PCI Lock: This signal indicates an exclusive bus operation and
may require multiple transactions to complete. ICH4 asserts
PLOCK# when it performs non- exclusive transactions on the PCI
bus. Devices on the PCI bus (other than the ICH4) are not permitted
to assert the PLOCK# signal.
SERR# I/OD System Error: SERR# can be pulsed active by any PCI device that
detects a system error condition. Upon sampling SERR# active, the
ICH4 has the ability to generate an NMI, SMI#, or interrupt.

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PME# I/OD PCI Power Management Event: PCI peripherals drive PME# to
wake the system from low-power states S1-MS5. PME# assertion
can also be enabled to generate an SCI from the S0 state. In some
cases the ICH4 may drive PME# active due to an internal wake
event. The ICH4 will not drive PME# high, but it will be pulled up
to VccSus3_3 by an internal pull-up resistor.
CLKRUN# I/O PCI Clock Run: Used to support PCI Clock Run protocol.
Connects to PCI devices that need to request clock re-start, or
prevention of clock stopping.
NOTE: An external pull-up to the core power plane is required.
REQ[A]#/
GPIO[0]
REQ[B]#/
REQ[5]#/
GPIO[1]
I PC/PCI DMA Request [A:B]: This request serializes ISA-like
DMA Requests for the purpose of running ISA-compatible DMA
cycles over the PCI bus. This is used by devices such as PCI based
Super I/O or audio codecs which need to perform legacy 8237 DMA
but have no ISA bus.
When not used for PC/PCI requests, these signals can be used as
General Purpose Inputs. REQ[B]# can instead be used as the 6th
PCI bus request.
GNT[A]#/
GPIO[16]
GNT[B]#/
GNT[5]#/
GPIO[17]
O PC/PCI DMA Acknowledges [A: B]: This grant serializes an
ISA-like DACK# for the purpose of running DMA/ISA Master
cycles over the PCI bus. This is used by devices such as PCI based
Super/IO or audio codecs which need to perform legacy 8237 DMA
but have no ISA bus.
When not used for PC/PCI, these signals can be used as General
Purpose Outputs. GNTB# can also be used as the 6th PCI bus
master grant output. These signal have internal pull-up resistors.

IDE Interface Signals
PDCS1#, SDCS1# O Primary and Secondary IDE Device Chip Selects for 100 Range:
For ATA command register block. This output signal is connected
to the corresponding signal on the primary or secondary IDE
connector.
PDCS3#, SDCS3# O Primary and Secondary IDE Device Chip Select for 300 Range:
For ATA control register block. This output signal is connected to
the corresponding signal on the primary or secondary IDE
connector.
PDA[2:0],
SDA[2:0]
O Primary and Secondary IDE Device Address: These output
signals are connected to the corresponding signals on the primary or
secondary IDE connectors. They are used to indicate which byte in
either the ATA command block or control block is being addressed.

IDE Interface Signals (Continued)
PDD[15:0],
SDD[15:0]
I/O Primary and Secondary IDE Device Data: These signals directly
drive the corresponding signals on the primary or secondary IDE
connector. There is a weak internal pull-down resistor on PDD[7]
and SDD[7].
PDDREQ,
SDDREQ
I Primary and Secondary IDE Device DMA Request: These input
signals are directly driven from the DRQ signals on the primary or
secondary IDE connector. It is asserted by the IDE device to request
a data transfer, and used in conjunction with the PCI bus master IDE
function and are not associated with any AT compatible DMA
channel. There is a weak internal pull-down resistor on these
signals.
PDDACK#,
SDDACK#
O Primary and Secondary IDE Device DMA Acknowledge: These
signals directly drive the DAK# signals on the primary and
secondary IDE connectors. Each is asserted by the ICH4 to indicate
to IDE DMA slave devices that a given data transfer cycle (assertion
of DIOR# or DIOW#) is a DMA data transfer cycle. This signal is
used in conjunction with the PCI bus master IDE function and are
not associated with any AT-compatible DMA channel.
PDIOR#/
(PDWSTB/PRDMA
RDY#)

SDIOR#/
(SDWSTB/SRDMA
RDY#)
O Primary and Secondary Disk I/O Read (PIO and Non-Ultra
DMA): This is the command to the IDE device that it may drive
data onto the PDD or SDD lines. Data is latched by the ICH4 on the
deassertion edge of PDIOR# or SDIOR#. The IDE device is
selected either by the ATA register file chip selects (PDCS1# or
SDCS1#, PDCS3# or SDCS3#) and the PDA or SDA lines, or the
IDE DMA acknowledge (PDDAK# or SDDAK#).
Primary and Secondary Disk Write Strobe (Ultra DMA Writes to
Disk): This is the data write strobe for writes to disk. When writing
to disk, ICH4 drives valid data on rising and falling edges of
PDWSTB or SDWSTB. Primary and Secondary Disk DMA Ready
(Ultra DMA Reads from Disk): This is the DMA ready for reads
from disk. When reading from disk, ICH4 deasserts
PRDMARDY# or SRDMARDY# to pause burst data transfers.
PDIOW#/
(PDSTOP)

SDIOW#/
(SDSTOP)
O Primary and Secondary Disk I/O Write (PIO and Non-Ultra
DMA): This is the command to the IDE device that it may latch
data from the PDD or SDD lines. Data is latched by the IDE device
on the deassertion edge of PDIOW# or SDIOW#. The IDE device is
selected either by the ATA register file chip selects (PDCS1# or
SDCS1#, PDCS3# or SDCS3#) and the PDA or SDA lines, or the
IDE DMA acknowledge (PDDAK# or SDDAK#).
Primary and Secondary Disk Stop (Ultra DMA): ICH4 asserts this
signal to terminate a burst.

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IDE Interface Signals (Continued)
PIORDY#/
(PDRSTB/PWDMA
RDY#)

SIORDY#/
(SDRSTB/SWDMA
RDY#)
I Primary and Secondary I/O Channel Ready (PIO): This signal
will keep the strobe active (PDIOR# or SDIOR# on reads, PDIOW#
or SDIOW# on writes) longer than the minimum width. It adds wait
states to PIO transfers.
Primary and Secondary Disk Read Strobe (Ultra DMA Reads from
Disk): When reading from disk, the ICH4 latches data on rising and
falling edges of this signal from the disk.
Primary and Secondary Disk DMA Ready (Ultra DMA Writes to
Disk): When writing to disk, this is de-asserted by the disk to pause
burst data transfers.

Interrupt Signals
SERIRQ I/O Serial Interrupt Request: This pin implements the serial interrupt
protocol.
PIRQ[D:A]# I/OD PCI Interrupt Requests: In Non-APIC Mode the PIRQx# signals
can be routed to interrupts 3, 4, 5, 6, 7, 9, 10, 11, 12, 14 or 15 as
described in the Interrupt Steering section. Each PIRQx# line has a
separate Route Control Register.
In APIC mode, these signals are connected to the internal I/O APIC
in the following fashion: PIRQ[A]# is connected to IRQ16,
PIRQ[B]# to IRQ17, PIRQ[C]# to IRQ18, and PIRQ[D]# to IRQ19.
This frees the legacy interrupts.
PIRQ[H:E]#/
GPIO[5:2]
I/OD PCI Interrupt Requests: In Non-APIC Mode the PIRQx# signals
can be routed to interrupts 3, 4, 5, 6, 7, 9, 10, 11, 12, 14 or 15 as
described in the Interrupt Steering section. Each PIRQx# line has a
separate Route Control Register.
In APIC mode, these signals are connected to the internal I/O APIC
in the following fashion: PIRQ[E]# is connected to IRQ20,
PIRQ[F]# to IRQ21, PIRQ[G]# to IRQ22, and PIRQ[H]# to IRQ23.
This frees the legacy interrupts. If not needed for interrupts, these
signals can be used as GPIO.
IRQ[14:15] I Interrupt Request 14:15: These interrupt inputs are connected to
the IDE drives. IRQ14 is used by the drives connected to the
Primary controller and IRQ15 is used by the drives connected to the
Secondary controller.
APICCLK I APIC Clock: This clock operates up to 33.33 MHz.
APICD[1:0] I/OD APIC Data: These bi-directional open drain signals are used to
send and receive data over the APIC bus. As inputs the data is valid
on the rising edge of APICCLK. As outputs, new data is driven
from the rising edge of the APICCLK.

LPC Interface Signals
LAD[3:0]/
FWH[3:0]
I/O LPC Multiplexed Command, Address, Data: For the LAD[3:0]
signals, internal pull-ups are provided.
LFRAME#/
FWH[4]
O LPC Frame: LFRAME# indicates the start of an LPC cycle, or an
abort.
LDRQ[1:0]# I LPC Serial DMA/Master Request Inputs: LDRQ[1:0]# are used
to request DMA or bus master access. These signals are typically
connected to an external Super I/O device. An internal pull-up
resistor is provided on these signals.

USB Interface Signals
USBP0P,
USBP0N,
USBP1P,
USBP1N
I/O Universal Serial Bus Port 1:0 Differential: These differential
pairs are used to transmit data/address/command signals for ports 0
and 1. These ports can be routed to USB UHCI Controller #1 or the
USB EHCI Controller.
NOTE: No external resistors are required on these signals. The
ICH4 integrates 15 k . pull-downs and provides an output driver
impedance of 45 . which requires no external series resistor
USBP2P,
USBP2N,
USBP3P,
USBP3N
USB EHCI Controller.
impedance of 45 . which requires no external series resistor.
USBP4P,
USBP4N,
USBP5P,
USBP4N
USB EHCI Controller
impedance of 45 . which requires no external series resistor
OC[5:0]# I/O Overcurrent Indicators: These signals set corresponding bits in
the USB controllers to indicate that an overcurrent condition has
occurred.
USBRBIAS O USB Resistor Bias: Analog connection point for an external
resistor to ground. USBRBIAS should be connected to
USBRBIAS# as close to the resistor as possible.
USBRBIAS# I USB Resistor Bias Complement: Analog connection point for an
external resistor to ground. USBRBIAS# should be connected to
USBRBIAS as close to the resistor as possible.

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Power Management Interface Signals
THRM# I Thermal Alarm: This is an active low signal generated by external
hardware to start the hardware clock throttling mode. The signal can
also generate an SMI# or an SCI.
THRMTRIP# I Thermal Trip: When low, THRMTRIP# indicates that a thermal
trip from the processor occurred; the ICH4 will immediately
transition to a S5 state. The ICH4 will not wait for the processor
stop grant cycle since the processor has overheated.
SLP_S1# O S1 Sleep Control: SLP_S1# provides Clock Synthesizer or Power
plane control. Optional use is to shut off power to non-critical
systems when in the S1- M (Powered On Suspend), S3 (Suspend To
RAM), S4 (Suspend to Disk) or S5 (Soft Off) states.
SLP_S3# O S3 Sleep Control: SLP_S3# is for power plane control. It shuts off
power to all non-critical systems when in S3 (Suspend To RAM),
S4 (Suspend to Disk), or S5 (Soft Off) states.
SLP_S4# O S4 Sleep Control: SLP_S4# is for power plane control. It shuts
power to all non-critical systems when in the S4 (Suspend to Disk)
or S5 (Soft Off) state.
SLP_S5# O S5 Sleep Control: SLP_S5# is for power plane control. The signal
is used to shut power off to all non-critical systems when in the S5
(Soft Off) states.
PWROK I Power OK: When asserted, PWROK is an indication to the ICH4
that core power and PCICLK have been stable for at least 1 ms.
PWROK can be driven asynchronously. When PWROK is negated,
the ICH4 asserts PCIRST#.
NOTE: PWROK must deassert for a minimum of 3 RTC clock
periods for the ICH4 to fully reset the power and properly generate
the PCIRST# output
PWRBTN# I Power Button: The Power Button causes SMI# or SCI to indicate a
system request to go to a sleep state. If the system is already in a
sleep state, this signal causes a wake event. If PWRBTN# is pressed
for more than 4 seconds, this causes an unconditional transition
(power button override) to the S5 state with only the PWRBTN#
available as a wake event. Override occurs even if the system is in
the S1-MS4 states. This signal has an internal pull-up resistor.
RI# I Ring Indicate: This signal is an input from the modem interface. It
can be enabled as a wake event, and this is preserved across power
failures.
SYS_RESET# I System Reset: This pin forces an internal reset after being
debounced. The ICH4 will reset immediately if the SMBus is idle;
otherwise, it will wait up to 25 ms 2 ms for the SMBus to idle
before forcing a reset on the system.
RSMRST# I Resume Well Reset: This signal is used for resetting the resume
power plane logic.

Power Management Interface Signals (Continued)
LAN_RST# I LAN Reset: This signal must be asserted at least 10 ms after the
resume well power (VccLAN3_3 and VccLAN1_5 is valid. When
deasserted, this signal is an indication that the resume well power is
stable.
SUS_STAT#/
LPCPD#
O Suspend Status: This signal is asserted by the ICH4 to indicate that
the system will be entering a low power state soon. This can be
monitored by devices with memory that need to switch from normal
refresh to suspend refresh mode. It can also be used by other
peripherals as an indication that they should isolate their outputs
that may be going to powered-off planes. This signal is called
LPCPD# on the LPC I/F.
C3_STAT# O C3_STAT#: This signal will typically be configured as C3_STAT#.
It is used for indicating to an AGP device that a C3 state transition
is beginning or ending. If C3_STAT# functionality is not required,
this signal may be used as a GPO.
NOTE: This signal will be asserted in S1-M on the ICH4-M.
SUSCLK O Suspend Clock: Output of the RTC generator circuit to use by other
chips for refresh clock.
AGPBUSY# I AGP Bus Busy: To support the C3 state. This signal is an
indication that the AGP device is busy. When this signal is asserted,
the BM_STS bit will be set. If this functionality is not needed, this
signal may be configured as a GPI.
STP_PCI# O Stop PCI Clock: This signal is an output to the external clock
generator for it to turn off the PCI clock. Used to support PCI
CLKRUN# protocol. If this functionality is not needed, This signal
can be configured as a GPO.
STP_CPU# O Stop CPU Clock: Output to the external clock generator for it to
turn off the processor clock. Used to support the C3 state. If this
functionality is not needed, this signal can be configured as a GPO.
BATLOW# I Battery Low: This signal is an input from the battery to indicate
that there is insufficient power to boot the system. Assertion will
prevent wake from S1-MS5 state. Can also be enabled to cause an
SMI# when asserted.
CPUPERF# OD CPU Performance: CPUPERF# is used for Intel SpeedStep
technology support. The signal selects which power state to put the
processor in.
SSMUXSEL O SpeedStep Mux Select: SSMUXSEL is used for Intel SpeedStep
technology support. The signal selects the voltage level for the
processor.
VGATE/
VRMPWRGD
I VGATE/VRM Power Good: VGATE/VRMPWRGD is used for
Intel SpeedStep technology support. This is an output from the
processors voltage regulator to indicate that the voltage is stable.
This signal may go inactive during an Intel SpeedStep transition.

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Power Management Interface Signals (Continued)
DPRSLPVR O Deeper Sleep - Voltage Regulator: This signal is used to lower the
voltage of VRM during C4 and S1-M states. When the signal is
high, the voltage regulator outputs the lower Deeper Sleep
voltage. When the signal is low (default), the voltage regulator
outputs the higher Normal voltage. During PCIRST#, the output
driver is disabled and an internal pull-down is enabled. This is
needed for implementing a strap on the pin. When PCIRST#
deasserts, the output driver is enabled. To guarantee no glitches on
the DPRSLPVR pin, the pull-down is disabled after the output
driver is fully enabled.
NOTE: DPRSLPVR is sampled at the rising edge of PWROK as a
functional strap.

Processor Interface Signals
A20M# O Mask A20: A20M# will go active based on either setting the
appropriate bit in the Port 92h register, or based on the A20GATE
input being active.
Speed Strap: During the reset sequence, ICH4 drives A20M# high
if the corresponding bit is set in the FREQ_STRP register.
CPUSLP# O CPU Sleep: This signal puts the processor into a state that saves
substantial power compared to Stop-Grant state. However, during
that time, no snoops occur. The ICH4 can optionally assert the
CPUSLP# signal when going to the S1-M state.
FERR# I Numeric Coprocessor Error: This signal is tied to the coprocessor
error signal on the processor. FERR# is only used if the ICH4
coprocessor error reporting function is enabled in the General
Control Register (Device 31:Function 0, Offset D0, bit 13). If
FERR# is asserted, the ICH4 generates an internal IRQ13 to its
interrupt controller unit. It is also used to gate the IGNNE# signal to
ensure that IGNNE# is not asserted to the processor unless FERR#
is active. FERR# requires an external weak pull-up to ensure a high
level when the coprocessor error function is disabled.
NOTE: FERR# can be used in some states for notification by the
processor of pending interrupt events. This functionality is
independent of the General Control Register bit setting.
INTR O CPU Interrupt: INTR is asserted by the ICH4 to signal the
processor that an interrupt request is pending and needs to be
serviced. It is an asynchronous output and normally driven low.
Speed Strap: During the reset sequence, ICH4 drives INTR high if
the corresponding bit is set in the FREQ_STRP register.

Processor Interface Signals (Continued)
IGNNE# O Ignore Numeric Error: This signal is connected to the ignore error
pin on the processor. IGNNE# is only used if the ICH4 coprocessor
error reporting function is enabled in the General Control Register
(Device 31:Function 0, Offset D0, bit 13). If FERR# is active,
indicating a coprocessor error, a write to the Coprocessor Error
Register (F0h) causes the IGNNE# to be asserted. IGNNE# remains
asserted until FERR# is negated. If FERR# is not asserted when the
Coprocessor Error Register is written, the IGNNE# signal is not
asserted.
Speed Strap: During the reset sequence, ICH4 drives IGNNE# high
if the corresponding bit is set in the FREQ_STRP register.
INIT# O Initialization: INIT# is asserted by the ICH4 for 16 PCI clocks to
reset the processor. ICH4 can be configured to support CPU BIST.
In that case, INIT# will be active when PCIRST# is active.
NMI O Non-Maskable Interrupt: NMI is used to force a non-Maskable
interrupt to the processor. The ICH4 can generate an NMI when
either SERR# or IOCHK# is asserted. The processor detects an NMI
when it detects a rising edge on NMI.
NMI is reset by setting the corresponding NMI source
enable/disable bit in the NMI Status and Control Register.
Speed Strap: During the reset sequence, ICH4 drives NMI high if
the corresponding bit is set in the FREQ_STRP register.
SMI# O System Management Interrupt: SMI# is an active low output
synchronous to PCICLK. It is asserted by the ICH4 in response to
one of many enabled hardware or software events.
STPCLK# O Stop Clock Request: STPCLK# is an active low output
synchronous to PCICLK. It is asserted by the ICH4 in response to
one of many hardware or software events. When the processor
samples STPCLK# asserted, it responds by stopping its internal
clock.
RCIN# I Keyboard Controller Reset CPU: The keyboard controller can
generate INIT# to the processor. This saves the external OR gate
with the ICH4s other sources of INIT#. When the ICH4 detects the
assertion of this signal, INIT# is generated for 16 PCI clocks.
NOTE: The ICH4 ignores RCIN# assertion during transitions to the
S1-M, S3, S4 and S5 states.
A20GATE I A20 Gate: A20GATE is from the keyboard controller. The signal
acts as an alternative method to force the A20M# signal active. It
saves the external OR gate needed with various other PCIsets.

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Processor Interface Signals (Continued)
CPUPWRGD OD CPU Power Good: This signal should be connected to the
processors PWRGOOD input. To allow for Intel SpeedStep
technology support, this signal is kept high during an Intel
SpeedStep technology state transition to prevent loss of processor
context. This is an open-drain output signal (external pull-up
resistor required) that represents a logical AND of the ICH4s
PWROK and VGATE / VRMPWRGD signals.
DPSLP# O Deeper Sleep: This signal is asserted by the ICH4 to the processor.
When the signal is low, the processor enters the Deeper Sleep state
by gating off the processor Core clock inside the processor. When
the signal is high (default), the processor is not in the Deeper Sleep
state. This signal behaves identically to the STP_CPU# signal, but
at the processor voltage level.

SMBus Interface Signals
SMBDATA I/OD SMBus Data: External pull-up is required.
SMBCLK I/OD SMBus Clock: External pull-up is required.
SMBALERT#/
GPIO[11]
I SMBus Alert: This signal is used to wake the system or generate
SMI#. If not used for SMBALERT#, it can be used as a GPI.

System Management Interface Signals
INTRUDER# I Intruder Detect: Can be set to disable system if box detected open.
This signals status is readable, so it can be used like a GPI if the
Intruder Detection is not needed.
SMLINK[1:0] I/OD System Management Link: SMBus link to optional external
system management ASIC or LAN controller. External pull-ups are
required.
Note that SMLINK[0] corresponds to an SMBus Clock signal, and
SMLINK[1] corresponds to an SMBus Data signal.

Real Time Clock Interface Signals
RTCX1 Special Crystal Input 1: This signal is connected to the 32.768 kHz crystal.
RTCX2 Special Crystal Input 2: This signal is connected to the 32.768 kHz crystal.

Other Clock Signals
CLK14 I Oscillator Clock: Used for 8254 timers. It runs at 14.31818 MHz.
This clock is permitted to stop during S1-M (or lower) states.
CLK48 I 48 MHz Clock: This clock is used to run the USB controller. It runs
at 48 MHz. This clock is permitted to stop during S1-M (or lower)
states.
CLK66 I 66 MHz Clock: This is used to run the hub interface. It runs at 66
MHz. This clock is permitted to stop during S1-M (or lower) states.

Miscellaneous Signals
SPKR O Speaker: The SPKR signal is the output of counter 2 and is
internally ANDed with Port 61h bit 1 to provide Speaker Data
Enable. This signal drives an external speaker driver device, which
in turn drives the system speaker. Upon PCIRST#, its output state is
0.
NOTE: SPKR is sampled at the rising edge of PWROK as a
functional strap.
RTCRST# I RTC Reset: When asserted, this signal resets register bits in the
RTC well and sets the RTC_PWR_STS bit (bit 2 in
GEN_PMCON3 register).
NOTES:
1. Clearing CMOS in an ICH4-based platform can be done by using
a jumper on RTCRST# or GPI, or using SAFEMODE strap.
Implementations should not attempt to clear CMOS by using a
jumper to pull VccRTC low.
2. Unless entering the XOR Chain Test Mode, the RTCRST# input
must always be high when all other RTC power planes are on.

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AC97 Link Signals
AC_RST# O AC 97 Reset: This signal is a master hardware reset to external
Codec(s).
AC_SYNC O AC 97 Sync: This signal is a 48 kHz fixed rate sample sync to the
Codec(s).
AC_BIT_CLK I AC97 Bit Clock: This signal is a 12.288 MHz serial data clock
generated by the external Codec(s). This signal has an integrated
pull-down resistor.
AC_SDOUT O AC97 Serial Data Out: Serial TDM data output to the Codec(s).
NOTE: AC_SDOUT is sampled at the rising edge of PWROK as a
functional strap.
AC_SDIN[1:0] I AC97 Serial Data In 2:0: These signals are Serial TDM data inputs
from the three Codecs.
NOTE: An integrated pull-down resistor on AC_BIT_CLK is enabled when either: The ACLINK
Shutoff bit in the AC97 Global Control Register is set to 1, or Both Function 5 and Function 6 of
Device 31 are disabled. Otherwise, the integrated pull-down resistor is disabled.

General Purpose I/O Signals
GPIO[43:32] I/O Can be input or output. Main power well.
GPIO[31:29] O Not implemented.
GPIO[28:27] I/O Can be input or output. Resume power well. Unmuxed.
GPIO[26] I/O Not implemented.
GPIO[25] I/O Can be input or output. Resume power well. Unmuxed.
GPIO[24:18] I/O Not Implemented in Mobile (Assign to native Functionality).
GPIO[17:16] O Fixed as Output only. Main power well. Can be used instead as
PC/PCI GNT[A:B]#. GPIO[17] can also alternatively be used for
PCI GNT[5]#. Integrated pull-up resistor.
GPIO[15:14] I Not implemented.
GPIO[13:12] I Fixed as Input only. Resume power well. Unmuxed.
GPIO[11] I Fixed as Input only. Resume power well. Can be used instead as
SMBALERT#.
GPIO[10:9] I Not implemented.
GPIO[8] I Fixed as Input only. Resume power well. Unmuxed.
GPIO[7] I Fixed as Input only. Main power well. Unmuxed.
GPIO[6] I Not Implemented in Mobile (Assign to Native Functionality)
GPIO[5:2] I Fixed as Input only. Main power well. Can be used instead as
PIRQ[E:H]#.
GPIO[1:0] I Fixed as Input only. Main power well. Can be used instead as
PC/PCI REQ[A:B]#. GPIO[1] can also alternatively be used for PCI
REQ[5]#.
NOTE: Main power well GPIO are 5V tolerant, except for GPIO[43:32]. Resume power well GPIO
are not 5V tolerant.
Power and Ground Signals
Signal Name Description
VCC3_3 3.3 V supply for core well I/O buffers. This power may be shut off in S3, S4, S5
or G3 states.
VCC1_5 1.5 V supply for core well logic. This power may be shut off in S3, S4, S5 or G3
states.
VCCHI 1.5 V supply for Hub Interface 1.5 logic.
1.8 V supply for Hub Interface 1.0 logic.
This power may be shut off in S3, S4, S5 or G3 states.
V5REF Reference for 5 V tolerance on core well inputs. This power may be shut off in
S3, S4, S5 or G3 states.
HIREF Analog Input. Expected voltages are:
0.9 V for HI 1.0 (Normal Hub Interface) Series Termination
350 mV for HI 1.5 (Enhanced Hub Interface) Parallel Termination
This power is shut off in S3, S4, S5, and G3 states.
VCCSUS3_3 3.3 V supply for resume well I/O buffers. This power is not expected to be shut
off unless the main battery is removed or completely drained and AC power is
not available.
VCCSUS1_5 1.5 V supply for resume well logic. This power is not expected to be shut off
unless the main battery is removed or completely drained and AC power is not
available.
V5REF_SUS Reference for 5 V tolerance on resume well inputs. This power is not expected
to be shut off unless the main battery is removed or completely drained and AC
power is not available.
VCCLAN3_3 3.3 V supply for LAN Connect interface buffers. This is a separate power plane
that may or may not be powered in S3S5 states depending upon the presence or
absence of AC power and network connectivity. This plane must be on in S0 and
S1-M.
VCCLAN1_5 1.5 V supply for LAN Controller logic. This is a separate power plane that may
or may not be powered in S3S5 states depending upon the presence or absence
of AC power and network connectivity. This plane must be on in S0 and S1-M.
VCCRTC 3.3 V (can drop to 2.0 V min. in G3 state) supply for the RTC well. This power
is not expected to be shut off unless the RTC battery is removed or completely
drained.
NOTE: Implementations should not attempt to clear CMOS by using a jumper
to pull VccRTC low. Clearing CMOS in an ICH4-based platform can be done
by using a jumper on RTCRST# or GPI, or using SAFEMODE strap.
VCCPLL 1.5 V supply for core well logic. This signal is used for the USB PLL. This
power may be shut off in S3, S4, S5 or G3 states.
VBIAS RTC well bias voltage. The DC reference voltage applied to this pin sets a
current that is mirrored throughout the oscillator and buffer circuitry.
V_CPU_IO Powered by the same supply as the processor I/O voltage. This supply is used to
drive the processor interface outputs.
VSS Grounds.

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U713
INTEL
BANIAS/DOTHAN
U714
North Bridge
855GME
Internal KB
Touch Pad
U16
WINBOND
W83L950D
U726
AUDIO
CODEC
ALC655
MIC
Line In
Card Reader
Socket
PCI BUS
LPC BUS
J711
DDR 266
AC 97
U524
Amplifier
TPA0212
U15
FWH
BIOS
HDD
USB2.0
CD-ROM
U715
ICH4-M
MDC RJ11
FAN
U727
PCMCIA
CARD READER
CB710
L
C
D
L
C
D
CRT
RGB
LVDS
66MHZ
Speaker
J6
Mini PCI
Card Socket
TV
HP/OPT Jack
Subwoofer
IEEE 1394
U719
RTL8100CL
Host
400MHZ
6. System Block Diagram
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7.1 Introduction
Each time the computer is turned on, the system BIOS runs a series of internal checks on the hardware. This
power-on self test (post) allows the computer to detect problems as early as the power-on stage. Error messages of
post can alert you to the problems of your computer.If an error is detected during these tests, you will see an error
message displayed on the screen. If the error occurs before the display is initialized, then the screen cannot display
the error message. Error codes or system beeps are used to identify a post error that occurs when the screen is not
available.
The value for the diagnostic port is written at the beginning of the test. Therefore, if the test failed, the user can
determine where the problem occurred by reading the last value written to the port by the debug card plug at MINI
PCI slot.
7. Maintenance Diagnostics
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The Mini PCI DOG killer card is a single-step debug tool which utilizes Mini PCI interface (Type III A) and is
able to hold a PCI bus cycle so that address, data and control bus states on PCI bus can be inspected. Especially,
the tool can help an engineer trace address/data bus for BIOS read cycles as soon as power on and debug open
or short circuit problems easily. Usually, this sort of problem will make a PC motherboard fail to boot.
P/N:411906900001
Description: PWA-MPDOG;MINI PCI DOGKELLER CARD
Note: Order it from MIC/TSSC
7.2 Diagnostic Tool for Mini PCI Slot :
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Following is a list of error codes in sequent display on the debug board.
POST (HEX) DESCRIPTION
17H Size Memory
18H Dispatch To RAM Test
19H checksum the ROM
1AH Reset PIC's
1BH Initialize Video Adapter(s)
1CH Initialize Video (6845 Regs)
1DH Initialize Color Adapter
1EH Initialize Monochrome Adapter
1FH Test 8237A Page Registers
20H Test Keyboard
21H Test Keyboard Controller
22H Check If CMOS Ram Valid
23H Test Battery Fail & CMOS X-SUM
24H Test the DMA controllers
25H Initialize 8237A Controller
26H Initialize Int Vectors
27H RAM Quick Sizing
28H Protected mode entered safely
29H RAM test completed
2AH Protected mode exit successful
2BH Setup Shadow
2CH Going To Initialize Video
00h Boot started
01h Disable A20 through A20
02h Initialize CS
03h Test RAM
04h Move BL into the RAM
05h Execution in RAM
06h Check OVERRIDE option
07h Shadow System BIOS
08h Checksum System BIOS ROM
09h Proceed with Normal Boot
0Ah Proceed with Crisis Boot
0Fh Fatal Error
F0h .... - No RAM
F1h ..._ - RAM test failed
99h Resume SMRAM not Found
10H Some Type Of Long Reset
11H Turn off FASTA20 for POST
12H Signal Power On Reset
13H Initialize the Chipset
14H Search For ISA Bus VGA Adapter
15H Reset Counter/Timer 1
16H user register config through CMOS
7.3 Error Codes - 1
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2DH Search For Monochrome Adapter
2EH Search For Color Adapter
2FH Signon messages displayed
30H special init of keyboard ctlr
31H Test If Keyboard Present
32H Test Keyboard Interrupt
33H Test Keyboard Command Byte
34H TEST, Blank and count all RAM
35H Protected mode entered safely (2).
36H RAM test complete
37H Protected mode exit successful
38H Update OUTPUT port
39H Setup Cache Controller
3AH Test If 18.2Hz Periodic Working
3BH test for RTC ticking
3CH initialize the hardware vectors
3DH Search and Init the Mouse
3EH Update NUMLOCK status
3FH special init of COMM and LPT ports
40H Configure the COMM and LPT ports
41H Initialize the floppies
42H Initialize the hard disk
43H Initialize option ROMs
44H OEM's init of power management
45H Update NUMLOCK status
46H Test For Coprocessor Installed
47H OEM functions before boot
48H Dispatch To Op. Sys. Boot
49H Jump Into Bootstrap Code
50H ACPI INIT
51H PM INIT & GEYSERVILLE CPU INIT
52H USB HC INIT
F8H PXE BIOS decomp error
F9H PCI BIOS decomp error
FAH PNP BIOS decomp error
FBH LOGO BIOS decomp error
FCH LOGO Image decomp error
FDH Energy Image decomp error
FEH ROMDEBUG Image decomp error
88H PM code decomp error
CAH CPU SMM remap code
CBH CPU SMM BASE remap Done
7.3 Error Codes - 2
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D0H check rom signature, 1.x video
D1H enable RAM area in regs
D2H copy ROM to RAM in regs
D3H update segment range attr
D4H configure memory registers
D5H configure I/O registers
D6H configure IRQ assignments
D7H turn on PCI device
D8H 2.x video r/w segment
D9H OEM defined, rom init
DAH disable add-in rom card decode
DBH PCI return(config and no video)
DCH enable RAM area in regs
DDH copy ROM to RAM in regs
DEH update segment range attr
DFH configure memory registers
E0H configure I/O registers
E1H configure IRQ assignments
E2H turn on PCI device
E3H 2.x video r/w segment
E4H OEM defined, rom init
E5H disable add-in rom card decode
E6H PCI return(config and no video)
E7H look for PCI bridge device
E8H search IDE controllers on the PCI bus
E9H start of cardbus config
A1H Enable/Verify R/W Status Runtime Data
A2H Get/Verrify R/W Stattus NVRAM data area
A3H Resolve System Nodes with the CMOS settings
A4H Init. var. in the PNP BIOS Runtime Data area
A5H Hook INT 15
A6H copy/setup $PnP Install Check in F0000 seg.
A7H Allow the OEM any Last Minute Hooks
A8H Write protect RTData Area & NVRAM Copy Buffer
A9H return from pnp_init proc
7.3 Error Codes - 3
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8.1 No Power
8.3 No Display
8.2 Battery Can not Be Charged
8.4 External Monitor No Display
8.5 Memory Test Error
8.6 Keyboard/Touch pad Test Error
8.7 USB Port Test Error
8.9 CD-ROM Driver Test Error
8.10 Audio Failure
8.11 LAN Test Error
8.12 Modem Test Error
8.13 MINI-PCI Test Error
8.14 Card Bus&Reader Test Error
8.16 IEEE 1394 Failure
8.15 TV Encoder Test Failure
8.8 Hard Disk Drive Test Error
8. Trouble Shooting
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When the power button is pressed, nothing happens, no fan activity is heard and power indicator is not light up.
Power In
PJ 701
PWR_VDDIN
VDD5 VDD5S
PD702 PF1
PL1 PL2
PR701
U11
Q13
PQ701
ADINP
DVMAIN
Battery
Charge
+3VS-P +3VS
+5VS_P
PD703 JS704
PU702
PL701
PU2
PU701
P32
P32
P25
P24
P25
P27
P32
P32
P27
PD713
PF703
PU7
PL710
+5VS
P24
U701
P15
+VCC_USB_0
U704,L70 3
L704,Q10
P25
+5V
U728
+CARD_VCC
P17
To Next Page
Page on M/B board circuit diagram. P27
NOTE:.
PD704
VDD3
VDD3S VDD1.5
U6 F3,U13
+3V
U707,Q701
L706,L707
P25 P25 P25
P25
Q51,L71
PR711
PR707
JS711,JS713,JS715
JS718,JS719,JS721
P33
PL708
PD709
PL703
PL702
PQ707
P32
PQ704
PD704
Discharge
VDD3_AVREF
8.1 No Power
P25
Q48
L702
L701
+VCC_USB_1
+VCC_USB_2
U705,L708
1394_AVCC
+PHYVDD
P25
P18
L743
L746
U18
VA
P20
+VCC_CORE
P31
PU3,PU9,PU10,PU11
PU12,PU13,PL711,
PD718,PR740
Q43
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P27
+1.25V_DDR
+1.8V
+1.35V
+1.25V_DDR_P
+1.8V_P
+1.35V_P
PU707,PL714,PR741
PU709,PL717,PR744
P29
P29 P24
P5
P26 P24
PU705,PL713,PR739
Continue To Previous Page
DVMAIN
JS71,JS717
JS1,JS12
JS72,JS722
JS706,PL712
8.1 No Power
JS708,JS709,JS710
+2.5VS_DDR_P
PU708,PL715,PR742
P24 P26
JS703,PL716
+2.5VS_DDR
PU14
PU15
DVDD
P16
L732
PU6,PL707,PR732
+1.05V_P
P28
+VCCP
P24
JS728,JS729,JS730
PU703
+1.5V_P
PU4,PL706,PR719
P28 P24
JS72,JS725
JS10,PL3
+1.5V
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No power
Connect
AC adaptor
or battery
Please replace
the faulty
AC adaptor or
Battery.
Power
OK?
Yes
No
Please try another known good battery
or AC adapter.
Yes
Is the
Notebook connected
to power (Either AC adaptor
or battery)?
NO
Board-level
Troubleshooting
Where
From Power Source
Problem(First use
AC to power it)
Check following parts and signals:
Parts: Signals:
ALWAYS
DVMAIN
ADEN#
BATT_DEAD
PF1
PL1
PL2
PD702
PQ701
Parts: Signals:
J703
PF702
PQ6
PQ704
PL704
PL705
BATT
AC
POWER
BATTERY
8.1 No Power
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G
S
D
2 3 1
6 7 8 5
PJ701
PF1 PL2 PR701
PD703
PD702
PD704
G
S
D
2
3
1
6
7
8
5
PQ701
PD701
DVMAIN
PQ704
PR720
PR45
PQ6
PQ24
LEARNING
ADINP
PWR_VDDIN
BATT
ADEN#
I_LIMIT PR1 R428 H8_I_LIMIT
U16
7A/24VDC
120Z/100M
120Z/100M
RLZ24D
.01
RS+
RS-
OUT
VCC
GND1
GND0
PU1
4
5
6
AO4407
PR702
470K
PR703
BAV70LT1
BAV70LT1
SBM1040
100K
AO4407
33K
2N7002
PR71
226K
DTC144WK
10 0 76
23
PQ702
D21
100K
2N7002
1M
RLS4148
PL1
WINBOND
KBC
PR705
14
3
2
1
P22
P32
3
2
1
To chapter 8.2
8.1 No Power(1)
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PR23
PR24
PR20
PWR_VDDIN
VDD3
VDD3S
J703
6
5
4
3
2
1
7
PF702
PL705
U16
WINBOND
KBC
0
0
PD2
BAV99
PD3
BAV99
78
77
2
3
BAT_V
BAT_C
BAT_D
BAT_T
120Z/100M
PR716
499K
PL704
120Z/100M
4.99K
7A/24VDC
1
2
3
4 5
6
7
8
22*4
RP45
4
6
7
8
2
3
1
5
14 ADEN#
PQ6
2N7002
D21
RLS4148
PR45
33K
PR720
100K
DVMAIN
PD704
BAV70LT1
P32
B
A
T
T
C
O
N
N
E
C
T
O
R
P22
BATT
PQ704
AO4407
PC722
0.01U
PR714
100K
8.1 No Power(2)
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Battery can not Charge
Connect
AC adaptor.
No
Yes
No
Yes
Is the
notebook connected
to power (AC adaptor)?
1. Make sure that the battery is good.
2. Make sure that the battery is installed properly.
Please replace the
faulty Battery.
Battery charge
OK?
Parts Signal
PF703
PL708
PQ707
PL710
PD713
PD714
PD709
PQ13
PQ14
PU7
PQ15
PD5
PR65
ADINP
CHANGING
BATT
BAT_V
BAT_T
BAT_C
BAT_D
BATT_DEAD
I_CTRL
Board-level
Troubleshooting
Replace
Motherboard
PR70
PQ11
PC33
PR63
PU5
PR74
PR75
PR76
PQ12
There are problems in charging the battery.
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G
S
D
2
3
1
6
7
8
5
C1
ADINP
PR86
PC39
BATT
PR74
PR76
CHARGING
21N+
CHARGING
PF703
TR/3216FF-3A
PL708
BEAD_120Z/100M
0
PQ13
DTA144WK
PQ14
2N7002
U16
WINBOND
KBC
8
C2
VCC 21IN+
PU7
11
12 16
PD713
EC31QS04
PL709
3.0UH
PQ707
AO4407
PR79 124K
PR78
0
PR87
4.7K
PR88
4.7K
PR89
100K
PQ15
MMBT2222A
PD5
BAS32L
PD714
EC31QS04
33UH
PL710
R483 0
26
10 I_CTRL
78
77
BAT_V
BAT_T
BAT_C
BAT_D
2
3
15
2
13.7K
249K
PD709
BZV55C15V
PQ12
2N7002
1000P
PR75
20K
P33
P22
TL594C
From U16
From chapter 8.1(1)
PC48 0.01U
13
BATT_DEAD#
-
DVMAIN VDD5
PR70 PR65
+
PU5
5
6
8
7
4
BATT_DEAD =8.56V
PR69
100K
590K 3.3K
LMV393M
DTC144TKA
Q39
1.25V
PQ11
SCK431LCSK-.5
PC33
0.1U
PR63
80.6K
PC36
0.01U
Reference chapter 8.1(1)
Reference chapter 8.1(2)
There are problems in charging the battery.
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Replace monitor
or LCD.
Board-level
Troubleshooting
Yes
No
Monitor
or LCD module
OK?
Make sure that CPU module,
DIMM memory are installed
Properly.
Display
OK?
Yes
No
Correct it.
Using debug card,depending
on the error codes to make
sure which parts maybe faulty
Replace
Motherboard
1.Try another known good CPU
module, DIMM module and BIOS.
2.Remove all of I/O device (FDD,
HDD, CD-ROM.) from
motherboard except LCD or monitor.
Display
OK?
1. Replace faulty part.
2. Connect the I/O device to the
M/B one at a time to find out
which part is causing the problem.
Yes
No
No Display
8.3 No Display
Using circuit diagram ,check
the faulty parts
There is no display on both LCD and VGA monitor after power on although the LCD and monitor is known-good.
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****** System Clock Check ******
U726
U713
R874
R875 44,45
U714
35,38
48,49
R865 R872
R873 R878
J713
U715
R895 R1137 MINIPCI_SIO48M 39
R877
R816 11
USBCLK_ICH
R824 PCICLK_ICH
R858
R859 R472 14M_CODEC
7
56
12 R826
U727
U719
R827 13 PCICLK_LAN
PCICLK_CARD
48M_DREFCLK
66M_DEFSSCLK
HCLK_MCH
HCLK_MCH#
PCICLK_MINIPCI
14M_ICH
U712
Clock
Generator
ICS950810
29,30 SMBDATA
SMBCLK
R821
+3V
R831
28
VTT_PWRGD#
R828
U724
PCICLK_1394 16
U15
10 R825 PCICLK_FWH
U16
17 R817 PCICK_KBC
2
3
X703
14.318MHZ
CPU
NB
MINI
ICH4_M
R860
+3V
54
55
40
4.7K
FS2
R863
L722 CLKANA
L726
L43
L718
+3V
CLK66
CLKCPU
CLKPCI 8,14
43
19,32
46,50
1,26,37
8.2K
120Z/100M
120Z/100M
120Z/100M
120Z/100M
10K
0
CORE_CLKEN#
PR56
0
PR731
2K
+3V
PR57 0
PR59
1M
2N7002
PQ8
VCCP_PWRGD
PR715
100K
PR717 0 27
PU703
+3VS_P
33*2 HCLK_CPU HCLK_CPU#
33*4
33
0
J711
33
33
33
33
33 0
33
33
33
33
33
FS1
FS0
P11
P28
P19
P13
P20
P17
P16
P18
P23
P22
P2 P3
P4 P5
P14
AUDIO
P6
LTC3728L
CARDBUS
LAN
DDR
KBC
SYS
IEEE
READER
CODEC
SODIMM
1394
BIOS
WINBOND
-PCI
C804 C794
27P 27P
8.3 No Display(1)
R863 4.7K
R894 4.7K
001
FS2 FS1 FS0 CPU
0 1 x 100.00
0:00
1:3.3V
UNIT:MHZ
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****** System Reset Check ******
IMP811
PCIRST#
RSTDRV1#
U714
855GM
/GME
U715
ICH4_M
RESET# VCC
G
N
D
PWROK
1
2
H8_PWRON
Power
Module
H8_RSMRST
Q42
FDV301N
RSMRST#
+3VS
3
+5V
R492
R476
Q37
Q41
DTC144TKA
DTC144TKA
10K
10K
J
7
1
4
H
D
D
44
1394_PCIRST#
PCIRST#0
92
U724
VT6307L
MCH_PCIRST#
KBC_PCIRST# 64
U16
WINBOND
KBC
U719
LAN_PCIRST# 27
RTL8100CL
CARD_PCIRST#
U727
CARDBUS
READER
+3V
+3V
MINIPCI_PCIRST# 26
J713
FWH_PCIRST#
U15
2
SST49LFOO4A
TV_PCIRST# U2 13
CH7011A
U21
R531
VDD3
25
SW2
R7
PWRBTN# 1
1K
H8_RESET#
W83L950D
U16
10K
MN
VCC
18
8
2
3
4
RESET
HCPURST#
BANIAS
U713
PWROK
C
O
N
N
E
C
T
O
R
M
I
N
I
P
C
I
C
O
N
N
E
C
T
O
R
74AHC08_V
U9A
U9B
74AHC08_V
U9C
74AHC08_V
1
2
3
4
5
6
7
8
9
TC010-PSS11CET
P14 P13
P22
P25
P15
P17
P19
P11
P18
P16
P22
P2 P3
P5 P4
P27
LTC3728L
P25
U10
MAX809
NORTH
BRIDGE
W
I
N
B
O
N
D
K
B
C
P23
1394
BIOS
TV_CARD
LAN
Controller
+VCCP
R301
330
HPWRGD
HPWRGD
VRMPWRGD
U9D
ICH_VGATE
+3V
+3V
Convert
P26 P31
ICH_PWRBTN
ICH_PWRBTN#
H8_SUSB
SUSB#
JL3
JL1
R909
0
J
7
0
8
8.3 No Display(2)
7
Convert to
Q31
+3V
Convert to
Q49
P15
C
D
R
O
M
C
O
N
N
E
C
T
O
R
RSTDRV2# 5
JL7
JL8
JL9
JL4
JL5
JL6
JL10
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****** VGA Controller Checking ******
J2
U714
855GM/GME
FPVDEN R801 0 R22 0
R19 10K G
S
D
2 3 1
6 7 8 5
R16 1M
C14
0.22U
F1 2A
+3V
L15 120Z/100M 1,2,3
TXCLK+
U715
ICH4_M
TXCLK- ICLKAM
ICLKAP
R361
0 R363
0
IYAM0
R350 0
R349 0
IYAP0
TXOUT0-
TXOUT0+
IYAM1
R357 0
R353 0
IYAP1
TXOUT1-
TXOUT1+
IYAM2
R1177 0
R1176 0
IYAP2
TXOUT2-
TXOUT2+
IYAM3
R1179 0
0
IYAP3
TXOUT3-
TXOUT3+
R1178
19
21
25
27
20
22
26
28
13
15
PANEL_ID[0..3] 6,7,10,14
+3V
R11~R14
10K*4
RP26 0*4
L
C
D

C
O
N
N
E
C
T
O
R
P14
P5
P12
Q9
SI4835DY
8.3 No Display(3)
8050
8050
N/B Maintenance
N/B Maintenance
101
****** Back Light & Cover Switch Checking ******
J1
DVMAIN
I
n
v
e
r
t
e
r
P12
8.3 No Display(4)
L17 1,2
L18 3
VDD3S
L10 4 ENABKL_VGA_C R323 ENABKL_VGA
L9 R5 0 BLADJ 11
P22
U16
WINBOND
KBC
BATT_R# 35
36 BATT_G#
8
7
6
5
1
2
3
4
8
9
10
11
79 AC_POWER#
BATT_POWER#
Q719
SW1
SUSB#
P13
U715
ICH4-M
13 BATT_LED#
+3VS
Q720
DTC114TKA DTC114TKA
+3VS +3VS
U703B U703C U703D
R1140 180K
C947
4.7U
74AHC14_V
R1152 1M
30V/0.1A
R3 1K
R373
470K
+3VS
16 H8_LIDSW#
+3V
R380
10K R383
0 D2 BAT54 ENABKL_NB
0 D16 BAT54 H8_ENABKL
R384
D15 BAT54
+3V
R372
10K
PWROK
120Z/100M
120Z/100M
120Z/100M
120Z/100M
0
27
U714
P4
855GM
PWROK
74AHC14_V 74AHC14_V
To U713 in this page
6
8050
8050
N/B Maintenance
N/B Maintenance
102
P31
PU3
LTC3734
G
D
S
2 3 1
6 7 8 5
D
S
2 3 1
6 7 8 5
G
+VCC_CORE
24
23
G
D
S
2 3 1
6 7 8 5
G
D
S
2 3 1
6 7 8 5
G
D
S
2 3 1
6 7 8 5
21
22
DVMAIN
+5VS_P
STOP_CPU#
P13
U715
ICH4_M
PR32 0 4
PR104 0
VOS-
PF2
7A/24VDC
PL5
120Z/100M
PL4
120Z/100M
PC12 0.1U
PC13 10U
PU9 PU10
FDS6694 FDS6694
PR740
0.001
PL711
0.68UH
PD718
EC31QS04-TE12L
2N7002
CPU
BANIAS
P3
VID0 PR52 0 13
14
15
17
18
19
PR44
PR40
VID1
VID2
VID3
VID4
VID5
0
0
PR34
PR33
PR31
0
0
0
U713
+5VS_P
PR5 10 29
PR4 10K 31
S1+
S1-
PU12 PU13 PU11
DD_CPU
FDS6694 FDS6694 FDS6694
RUN/SS 10
PR61 0
Q19
PWRON_SUSB#
VDD5
PQ5
2N7002
PQ7
2N7002
PR50
1M
PC28
3300P
PU15
P26
LTC3728L
DVMAIN
R251
220K
+2.5VS_DDR
30
2
PR30
100K
PC18
1000P
PR28 576K
PR29
13.3K
3
28 100P PC15 PR19 13.3K
1
8 PR15 56.2k
7
6
PR37
10
10
PR38
PC21
1000P
S1+
S1-
PR43 11
PR17
VOS-
PC11
220P
PR16 1.3M 9
499K
12.7K
To Pin12
+3VS
PR731
2K
PQ8
2N7002
+3V
PR729
249K
PR57
P28
PU703
LTC3728L
0 PR59 1M
PQ9
MMBT3904L
12
CLK-
GEN
P11
ICS950810
+3VS
PD4
BAT54C
PR49
100K
PQ10
MMBT3904L
U712
+VCC_PWRGD
G
28 D S
2
1
3
R831
10K
+3V
PR58
4.12K
PR60
43.2K
R821
0 0
PR56
TO
From Left
8.3 No Display(5)
CPU Core does not exist .
8050
8050
N/B Maintenance
N/B Maintenance
103
Display
OK?
External Monitor No Display
1. Confirm monitor is good and check
the cable are connected properly.
2. Try another known good monitor.
Replace faulty monitor.
Yes
No
Yes
Re-soldering.
No
Parts:
U715
R6
R10
R785
R138
R136
R137
R783
R135
Signals:
Check if J702
are cold solder?
CRT_IN#
DDCK
DDDA
HSYNC
VCYNC
RED
GREEN
BLUE
Board-level
Troubleshooting
Replace
Motherboard
R139
Q5
Q6
Q7
Q8
L12
L13
L11
L7
There is no display or picture abnormal on CRT monitor, but LCD can normally display.
8050
8050
N/B Maintenance
N/B Maintenance
104
R10
R6
+5V_H +5V_H
+5V_H
5
15
14
13
12
J702
CHAGND
R1 0
CHAGND GND
L12
120Z/100M
Q6
2N7002
Q5
2N7002
L7
120Z/100M
Q7
2N7002
Q8
2N7002
L13
U715
CRT_IN#
BEAD_600Z/100M
R9 1K
R804
802K
+3V
855_CRT_DDCK
855_CRT_DDDA
855_CRT_VSYNC
855_CRT_HSYNC
855_CRT_RED
855_CRT_GREEN
855_CRT_BLUE
U714
855GM/
GME
4.7K
4.7K
L11
120Z/100M
ICH
3
2
1
6,7,8,16,17
P4
NB
P13
P12
C
R
T

C
O
N
N
E
C
T
O
R
R1166
R331
R1167
R343
R344 L60
L59
L58
There is no display or picture abnormal on CRT monitor, but LCD can normally display.
0
0
R703 0
0
0
0
220Z/100M
220Z/100M
220Z/100M
8050
8050
N/B Maintenance
N/B Maintenance
105
Memory Test Error
Test
OK?
Replace the faulty
SDRAM module.
Yes
No
Parts: Signals:
1.If your system installed with expansion
SO-DIMM module then check them for
proper installation.
2.Make sure that your SO-DIMM sockets
are OK.
3.Then try another known good SO-DIMM
modules.
If your system host bus clock
running at 100MHZ then make
sure that SO-DIMM module
meet require of DDR 333.
Replace the faulty
SDRAM module.
No
Yes
MD[0..63]
SMBCLK
SMBDATA
DQS[0..7]
DM[0..7]
MCB[0..7]
MA0
MA3
MA[6..12]
WE#
CAS#
RAS#
BA[0,1]
NB_DM8
NB_DQS8
CLK_DDR[0..5]
CLK_DDR[0..5]#
Board-level
Troubleshooting
Replace
Motherboard
U714
J711
J712
U712
R979
R1040
R1030
R1031
R1011
R1016
R948
R949
R950
R955
R340
C337
C346
Check following parts and signals
Either on board or extend SDRAM is failure or system hangs up.
8050
8050
N/B Maintenance
N/B Maintenance
106
+1.25V_DDR
MD[0..63]
DQS[0..7]
DM[0..7]
MCB[0..7]
MA0 MA3
MA[6..12]
WE# CAS#
RAS# BA[0,1]
NB_DM8
NB_DQS8
NB_CLK_DDR[0..5]
NB_CLK_DDR[0..5]#
J711
&
J712
+3V
+2.5VS_DDR
R340 C337 C346
75 0.01U 0.1U
197
NB_MD[0..63]
NB_DQS[0..7]
NB_DM[0..7]
NB_CB[0..7]
NB_MA0 NB_MA3
NB_MA[6..12]
NB_WE# NB_CAS#
NB_RAS# NB_BA[0,1]
R948,R949
R972~R975
R1031
R969~R971
U714
SMA [1,2]
SMA[4,5]
SMAB[1,2]
SMAB [4,5]
CKE [0~3]
CS# [0,1]
R1011,R1016..
R950,R955..
R977,R978..
R1032~R1036
10
10
10
10
10
R1030
NB_DM8
NB_DQS8
NB_CLK_DDR[0..5]
NB_CLK_DDR[0..5]#
R979
R1040
R319
R320
R335~R338 R359
R360 R1103~R1106
10
10
10
10*12
RP29~RP43
56*8
U712
CLOCK
GENERATOR
29 SMBDATA
30 SMBCLK
193
195
855GM
/GME
0.6MM/200P
/H5.2
P11
P6
D
D
R
-
S
O
D
I
M
M
P4 P5
NB
U715
ICH4-M
P13
+3V VDD3S
R315
2.2K
R318
2.2K
Q21
R316
10K
R317
10K
Q22
2N7002
2N7002
SMB_DATA
SMB_CLK
Either on board or extend SDRAM is failure or system hangs up.
8050
8050
N/B Maintenance
N/B Maintenance
107
Keyboard or Touch-Pad
Test Error
Try another known good Keyboard
or Touch-pad.
Test
Ok?
Replace the faulty
Keyboard or
Touch-Pad
Yes
No
Check
U16, J4,J5
for cold solder?
Yes
No
Re-soldering
Parts
U16
U715
F701
L716
L36
L37
R132
R151
J4
J5
Signals
VDD3
VDD_AVREF
KBC X+
KBC X-
H8/T_CLK
H8/T_DATA
KI[0:7]
KO[0:15]
PWRBTN#
KBD_US/JP#
Yes
No
Correct it.
Is K/B or
T/P cable connected to
notebook
properly?
Board-level
Troubleshooting
Replace
Motherboard
8.6 Keyboard (K/B) /Touch-Pad (T/P) Test Error
Error message of keyboard or touch-pad failure is shown or any key does not work.
8050
8050
N/B Maintenance
N/B Maintenance
108
L716 F701
+5V
J4
U16
KI 0~7
KO 0~15
J5
KBD_US/JP#
R165
U715
R132
L36
L37
GND
R151
VDD3
C445 C448 C449
WINBOND
KBC
120Z/100M
120Z/100M
0.5A/POLYSW 120Z/100M
T_CLK
0
0
T_DATA 9
6
SW_LEFT
SW_RIGHT
SW5
SW4
1~16
17~24
39~54
55~62
10K
25
C450
2 1
X1
8MHz
R404
1M
C447
KBC_X+
KBC_X- 29
28
22P 22P
ICH4_M
R392
8.2K
69
LAD[0..3] 65~68
64
SERIRQ
KBC_PCIRST#
LFRAME#
SUSB#
H8_SUSB
Q49
DTC144TKA
0.1U 0.1U 10U
71
30
VDD3_AVREF
R414 0 72
+3V
63
22
+3V
4
2
1
3
5
6
P23
U9
P22
P13
P22
VDD3
8.6 Keyboard (K/B) /Touch-Pad (T/P) Test Error
P11
U712
CLKGEN
17 PCICK_KBC R817 33 PCICLK_KBC 70
RP44
4.7K*8
Error message of keyboard or touch-pad failure is shown or any key does not work.
8050
8050
N/B Maintenance
N/B Maintenance
109
USB Test Error
Check if the USB device is installed
properly. (Including charge board.)
Re-test
OK?
No
Yes
No
Yes
Correct it
Replace another known good USB
device.
Replace
Motherboard
Replace
the faulty part
Test
OK?
Parts: Signals:
U715
U705
U701
U712
J701
J706
L701
L702
L2
L5
+5VS
USBP0+
USBP0-
USBP1+
USBP1-
USBP2+
USBP2-
Board-level
Troubleshooting
USBOC0#
+VCC_USB_0
+VCC_USB_1
+VCC_USB_2
L22
L708
R701
C701
R706
C713
C703
C709
An error occurs when a USB I/O device is installed.
8050
8050
N/B Maintenance
N/B Maintenance
110
U715
ICH4_M
C701 R701
L701
L702
C713
L708
USB_OC1#
USB_OC0#
+VCC_USB_0
J701
+VCC_USB_1
1
A1
USBCLK_ICH
A4
4
1
+
+
R706
33K 150U
120Z/100M
+5VS
VOUT1
VIN0
G
N
D
VOUT0
3
4
1
5
2
U705
VIN1
C709
1U
150U 33K
+5VS
VIN0
G
N
D
VOUT0
3
4
1
5
2
U701
VIN1
C703
1U
120Z/100M
120Z/100M
U
S
B

P
o
r
t

C
o
n
n
e
c
t
o
r
U712
CLK-GEN
39
+VCC_USB_2
USB/4PX2/DIP
J706
4
GND1
GND2
U
S
B

P
o
r
t

C
o
n
n
e
c
t
o
r
USB/4PX1
3 4
1 2
L2
3 4
1 2
L5
3 4
1 2
L22
A2
A3
2
3
2
3
USBP0+
USBP0-
USBP1+
USBP1-
USBP2+
USBP2-
P15
P14
P15
P11
P15
P15
VOUT1
R877
90Z/100M
90Z/100M
90Z/100M
33
An error occurs when a USB I/O device is installed.
8050
8050
N/B Maintenance
N/B Maintenance
111
Hard Driver Test
Error
Yes
No
Parts: Signals: Re-boot
OK?
Replace the faulty parts.
1.Check the BIOS setup
2.Replace another good hard driver or
cable try again
Check the system driver for proper
installation.
No
Re - Test
OK?
End
U715
J714
Q37
Q41
L733
R476
R492
R1081
R1074
PCIRST#0
PIORDY
PDD[0..15]
PDA[0..2]
PDIOR#
PDIOW#
PDDACK#
PDCS1#
PDCS3#
Yes
Board-level
Troubleshooting
Replace
Motherboard
PDDREQ
IRQ14
+5V
+5V_HDD
Either an error message is shown, or the drive motor spins non-stop, while reading data from or writing
data to hard disk.
8050
8050
N/B Maintenance
N/B Maintenance
112
ICH4_M
U715
PD_D[0..15]
PDIOW#
PDIOR#
PIORDY
PDDACK#
IRQ14
PDA[0.. 2]
PDCS1#
PDCS3#
R1081 R1074
+3V
+5V
R492
R476
Q41
Q37
PCIRST#0 RSTDRV1#
J714
L733
+5V
120Z/100M
4.7K 8.2K
10K
10K
DTC144TKA
DTC144TKA
27~42
22
20
18
16
14
9,10,12
8
7
H
D
D

C
O
N
N
E
C
T
3
+5V_HDD
P15
P11
44
Either an error message is shown, or the drive motor spins non-stop, while reading data from or writing
data to hard disk.
8050
8050
N/B Maintenance
N/B Maintenance
113
CD-ROM Driver
Test Error
Yes
No
Parts: Signals:
Test
OK?
Correct it
Try another known good compact disk.
Check the CD-ROM driver for proper
installation.
No
Re - Test
OK?
Replace
the faulty parts.
U715
J708
Q37
Q41
R492
R476
R909
R833
R834
L723
Yes
Board-level
Troubleshooting
Replace
Motherboard
PCIRST#0
RSTDRV2#
SIORDY
SDD[0..15]
SDA[0..2]
SDIOR#
SDIOW#
SDDACK#
SDCS1#
SDCS3#
SDDREQ
IRQ15
+5V
+5V_CDROM
CDROM_LEFT
CDROM_RIGHT
CDROM_COMM
CD-ROM driver cant run normally,maybe an error message is shown when reading data from CD-ROM.
8050
8050
N/B Maintenance
N/B Maintenance
114
R909
J708
C
D
R
O
M

C
O
N
N
E
C
T
ICH4_M
U715
SD_D[0..15]
SDIOW#
SDIOR#
SIORDY
SDDACK#
IRQ15
SDA[0.. 2]
SDCS1#
SDCS3#
R833 R834
+3V
+5V
R492
R476
Q41
Q37
PCIRST#0 RSTDRV2#
L723
+5V 120Z/100M
4.7K 8.2K
10K
10K
DTC144TKA
DTC144TKA
6~21
25
24
27
28
29
31,33,34
35
36
38~42
0 5
+5V_CDROM
U726
AUDIO
CODEC
18
19
20
C507
C513
C515
1U
1U
0.22
R538
R547
R550
6.8K
0
6.8K
1
2
3
CDROM_LEFT
CDROM_COMM
CDROM_RIGHT
P15
P11
P20
R537 R549 R546
6.8K 6.8K 6.8K
CD-ROM driver cant run normally,maybe an error message is shown when reading data from CD-ROM.
8050
8050
N/B Maintenance
N/B Maintenance
115
Test
OK?
Audio Failure
1. Check if speaker cables are connected
properly.
2. Make sure all the drivers are installed
properly.
Try another known good speaker,
CD-ROM.
Re-test
OK?
Board-level
Troubleshooting
Replace
Motherboard
Yes
Correct it.
Yes
No
No
Parts:
U18
U17
U524
U726
U715
U712
U19
U725
J3
J7
J705
J719
L741
Signals:
ROUT+
ROUT-
SBSPKR
CARDSPK#
PC_BEEP
AVDD
ACRST#
ACSDOUT
ACSDIN0
ACBITCLK
14M_CODEC
MIC_VREF
2464_VREF
Replace the
faulty parts.
D715
Q711
Q713
Q23
D17
D19
D22
U18
AMP_LEFT
AMP_RIGHT
SUB_LEFT
SUB_RIGHT
AMP_SHUTDOWN
ROUT+
ROUT-
LOUT+
LOUT-
8.10 Audio Failure
There is trouble with the sound from speaker or completely no sound
8050
8050
N/B Maintenance
N/B Maintenance
116
L70
L734
U17
R1157
U715
+3V
ACSDOUT
ACRST#
ACSYNC R812
R530 ACSDIN0
ACBITCLK L69 R498
U712
14M_CODEC R859 R472
AOUT_L
AOUT_R
R1130 AMP_LEFT
AMP_RIGHT
R1135
R1128
VA
7,18,19 L67
+5V
U524
R532
MIC
2464_VREF
J719
L744
0
+
-
OUT
ADJ
GND
IN
EN
C467
U18
+5V
0.01U
L66
R438
10K
C456
1U
BEAD_600Z/100M
BEAD_600Z/100M
BEAD_600Z/100M
SUB_RIGHT
SUB_LEFT
TPA0212_GND
0
120Z/100M
0
0
0
0 R1127
MIC5205BM5
120Z/100M
5
4
U727
SBSPKR A
B Y
VCC
C457
C458 CARDSPK#
0.1U
0.1U
NC7S32
1
2
CB710
ICS950810
CLKGEN
ICH4_M
1,9
ALC655
11
5
8 22
10
6 0 22
0 35
36
2 56 33 0
12
25,38
PC_BEEP
AVDD
C492
C497
1U
1U
C484
C480
1U
5
6
20
23
1U
SBSPKR
To Next Page U19
TO NEXT PAGE U19
TO NEXT PAGE U19
EAPD
TO NEXT PAGE D22
P14
P11
P21
P20
P20 P20
P17
AMP
EXTERNAL MIC JACK
U726
AUDIO
CODEC
To U715
TO NEXT PAGE J720
SPDIFOUT
CARD
READER
24
24
C969
C974
1U
1U
R519
R324
0
0
L76
L53
J721
Line/In Jack
P20
BEAD_600Z/100M
BEAD_600Z/100M
21
48
47
C975 1U
28
R1155
R1150
0
0
INTERNAL
MIC1
R1154 0 R535 R1153 4.7K 0
8.10 Audio Failure(Audio Codec)
L751
120Z/100M
8050
8050
N/B Maintenance
N/B Maintenance
117
U715
ROUT+
ROUT-
LOUT+
LOUT-
L52
L50
L14
L16
21
16
4
9
C474
C489
R329 L80
+
J7
J3
U524
C474
L78
+5V
R1158
D715
OPTIN#
DEVICE_DECT
SPDIFOUT
R1185
VA
+3V
Q711
Q713
Q23
R367
DECT_HP#OPT
L754
L55
Drive
LED
IC
AGND
J720
L757
DEVICE_DECT
+3V
D22
+5V
Q38 R477
AMP_SHUTDOWN
VDD3S
R906
R905
0
SUB_OUTR
SUB_OUTL
C496 R502
C483 R496
U725
+5V
R27
5
8
6 L63
R26
R1125
2464_VREF
SUB_RIGHT
SUB_LEFT
R479 C482
R509 C490
U19
3
1
2
7
5
6
VA
R511 R463
R510
100 22.1K
22.1K
0.15U 22.1K
0.15U 22.1K
EAPD
+
600Z/100M
600Z/100M
600Z/100M
600Z/100M
100U 100U
R528
600Z/100M
22
22
600Z/100M
600Z/100M L755
600Z/100M
600Z/100M
600Z/100M
L758
600Z/100M
DTC144TKA
10K
DTA144WK
D19
RLS4148
0
0
120Z/100M
LM4871
0
D17
RLS4148
8.2K
0.22U 8.2K
0.22U
BAT54C
LMV822
8.2K
10K
BAW56
HDR/MA-2
TPA0212_GND
ICH4_M
GP1FD310TP
HDR/MA-2
From Previous Page U726
R322
4.7K
R1183
10K
VA 15,17
DEVICE_DECT#
10K
DEVICE_DECT#
DECT_HP#/
OPT REMARK
0
1
0
1
0
1
0
1
HP in
OPT in
No this condition
No device
P21
P13
P21
P21
P21
H
P
/
O
P
T

C
O
N
N
E
C
T
O
R
To U524
AUDIO AMP
Internal
Speaker
Connector
Subwoofer
Speaker
Connector
J
7
0
5
KBC_MUTE
8.10 Audio Failure(Audio Amplifier & Subwoofer)
1
4
R1122 2.1K
C471 1000P
D27
RLS4148
R445 0
80
P2
U16
WINBOND
KBC
8050
8050
N/B Maintenance
N/B Maintenance
118
LAN Test Error
Yes
No
Test
OK?
Correct it.
Correct it.
No
Check if BIOS setup is ok.
Re-test
OK?
Board-level
Troubleshooting
Replace
Motherboard
Parts: Signals:
1.Check if the driver is installed properly.
2.Check if the notebook connect with the
LAN properly.
Yes
U719
U717
U723
J709
L732
L735
L737
L51
L49
Q709
X706
R1101
R1111
R1115
R907
R211
R212
EECK
EEDI
EEDO
EECS
PJRX+
PJRX-
PJTX1-
PJTX+
LAN_XTANL1
LAN_XTANL2
PCICLK_LAN
LAN_WAKE
PCI_AD[0..31]
PCI_C/BR#[0..3]
PCI_PAR
LAN_PCIRST#
PCI_STOP#
AVDDL
DVDD
SB_PME#
PCLKRUN#
PCI_DEVSEL#
PCI_FRAME#
PCI_INTE#
PCI_REQ3
PCI_IRDY#
PCI_SERR
8.11 LAN Test Error
An error occurs when a LAN device is installed.
8050
8050
N/B Maintenance
N/B Maintenance
119
C911
+3VS
1
2
3
CS
SK
DI
DO
GND
VCC
5
8
U723
U719
+3VS
R1111
LAN_WAKE
Q709
U712
PCICLK_LAN
R907
VDD3S
U715
ICH4_M
PCI_AD[0..31] PCI_C/BE#[0..3]
PCI_DEVSEL# PCI_FRAME#
PCI_GNT3#
PCI_REQ3#
PCI_INTE#
PCI_IRDY#
PCI_TRDY#
PCI_PAR
PCI_PERR#
PCI_SERR# PCI_STOP#
LAN_PCIRST#
+2.5VS_DDR L732
DVDD
+3VS
SB_PME#
PCLKRUN#
+3VS
LAN_XTAL1
LAN_XTAL2
R1101
X706
1 2
C914 C915
25MHZ
RTL8100CL
PMDI0+
PMDI0-
3 4
1 2
L51
MDI0+
MDI0-
EECK
EEDI
EEDO
EECS
93C46
1U
10K
U717
LF-H80P
4
L735 120Z/100M
L737
MDI1+ PMDI1+
MDI1- PMDI1-
3
4
1 2
L49
J709
PJTX1-
PJTX+
PJRX-
PJRX+
8
7
2
1
9
10
15
16
1
2
3
6
1
2
5
6
26,41,56,71
84,94,107
3,7,16,20 120Z/100M
AVDDL
120Z/100M
12
24,32,45,54,64
78,99,110,116,126
111
109
108
106
121
122
27P 27P
105
DTC144TKA 0
R1115
10K
28 13
ICS950810
31
65,68,61,29,25
63,67,70,75,69
76 33,34 44,60..
R211,R212,R241
8.2K*11
L
A
N

C
O
N
N
E
C
T
O
R
1M
P16
P13
P16
P11
P16
P16
LAN Controller
MDO3+
MDO3-
MDO2+
MD23-
MCT4
MCT3
11
14
4
5
7
8
R152
R930
75
75
RP27
0*4
27
30
PCI_AD18 R947 100
8.11 LAN Test Error
An error occurs when a LAN device is installed.
R1110 3.6K
8050
8050
N/B Maintenance
N/B Maintenance
120
MODEM Test Error
No
Test
OK?
No
Replace a known good modem
Re-test
OK?
Board-level
Troubleshooting
1.Check if the driver is installed properly.
2.Check if the notebook connect with the
phone LAN properly.
Correct it.
Replace
Motherboard
Signals:
Yes
+5V
+3VS
+3V
MONO_OUT
ACSDOUT
ACRST#
ACSYNC
ACBITCLK
ACSDIN1
MODEMP
MODEMN
J717
J715
U726
R1132
C937
R498
L69
R1120
R1131
L724
F2
Yes
Correct it.
Parts:
An error occurs when run the modem
8050
8050
N/B Maintenance
N/B Maintenance
121
JP, use 4pcs of 2kV 1000P cap
US, use 2pcs of 2kV 1000P cap
UK, use 4pcs of 3kV 1000P cap
U726
MONO_OUT
J717
ACSDOUT
ACRST#
C937
+3V
+3VS
ACSYNC
R498 L69 R1120
U715
R1131
+5V
R1132
1 4
3 2
L724
J
7
1
5
F2
J
7
0
9
MODEMP
MODEMN
ACBITCLK
50UH
M
O
D
E
M
C
O
N
N
E
C
T
O
R
0.1U
HDR/MA-2
2
1
MINISMDC014-2
37
5
11
10
6 22 0 22 30
22
25
23
1
16
21
17
10,18
22 24
4.7K
ACSDIN1
A2
A1
ALC555
ICH4_M
RJ11-2P
/RJ45-8P
P20
P14
P20
P16
Phone Lan
Connector
P20 Lan Connector
An error occurs when run the modem
C148
C806
1000P
1000P
8050
8050
N/B Maintenance
N/B Maintenance
122
Please change the
faulty part then end.
Correct it
Please try another known good Mini PCI device.
1.Please check if the Mini PCI device is
installed properly.
2.Confirm Mini PCI device driver is
installed ok.
Mini PCI Test Error
Test
OK?
Re-test
OK?
Yes
No
Yes
No
Parts:
U715
J509
U712
U9
Q704
R1137
R1079
R1007
R1077
R1075
R1091
Board-level
Troubleshooting
Please replace
Motherboard
Signals
PCI_AD[0:31]
PCI_C/BE# [0:3]
PCI_REQ2#
PCI_FRAME#
PCI_IRDY#
PCI_TRDY#
PCI_DEVSEL#
PCI_STOP#
PCI_INTD#
PCI_RESET#
PCI_GNT2#
PCI_SERR#
CLKRUN#
PCI_PERR#
LAD [0:3]
LFRAME#
LRDQ0#
WIRELESS_PD#
MINIPCI_PME#
SIO_48M
PCICLK_MINIPCI
8.13 Mini PCI Test Error
An error message is shown after Mini PCI device is installed or the Mini PCI device doest work.
8050
8050
N/B Maintenance
N/B Maintenance
123
R1007
+3V
J713
U715
MINIPCI_LPCDRQ#
R1075
R1079 PCICLK_MINIPCI
R1083
R179
R211..
+3V
R1091
PCI_PERR#
PCLKRUN#
LAD[0..3]
LFRAME#
+5V
SIO_48M R1137
U712
R895
R1068
PCI_INTD#
PCI_GNT2#
PCI_REQ2#
+3V
U9C
PCIRST#
R1077
9
10
8
R1080
+3V
R915
Q704
SB_PME#
PCI_AD[0..31]
121
PCI_STOP#
PCI_DEVSE# WIRELESS_PD# 14,24
1897
10K
13
PCI_FRAM#
PCI_TRDY#
PCI_IRDY#
PCI_SERR#
PCI_C/BE#[0..3]
LRDQ0#
33
R816 33
39
11
25
26
0
0
MINIPCI_PME# 34
ICH4_M
M
I
N
I
P
C
I

C
O
N
N
E
C
T
O
R
ICS950810
P13
P19
P11
P14
0
0
PCI_AD17
8.13 Mini PCI Test Error
An error message is shown after Mini PCI device is installed or the Mini PCI device doest work.
48 R1092 100
JL8
8050
8050
N/B Maintenance
N/B Maintenance
124
PC Card Slot Failure
1. Check if the PCMCIA CARD device is
installed properly.
2. Confirm PCMCIA card driver is installed ok.
Test
OK?
Re-test
OK?
Yes
No
Yes
No
Change the faulty
part then end.
Parts:
U727
J716
U728
J6
U9
R186
R180
R211
R212
R1121
R1129
R826
R1203
Try another known good PCMCIA card device.
Correct it
Board-level
Troubleshooting
Replace
Motherboard
Signals
AD[0..31]
C/BE# [0..3]
DEVSEL#
FRAME#
IRDY#
TRDY#
STOP#
PAR
PERR#
SERR#
P_REQ0#
SERIRQ
PCIRST#
P_GNT0#
PIRQA#
SUSB#
RI#
PCLK_CARD
VCC5_EN#
VCC3_EN#
VPPD0
VPPD1
+VPPOUT
+3V
+5V
8.14 CardBus & Reader Test Error
An error occurs when a PC card device is installed.
8050
8050
N/B Maintenance
N/B Maintenance
125
CB710
U727
U715
ICH4_M
PCI_AD[0..31]
PCLKRUN#
8.2K*7
+3V
TPS2211A
U728
+3V
3,4
+5V
5,6
R1121
R1129
16
8
10K
10K
+CARD_VCC
J6
17,51
FM/34
PX2/1.
27MM
VCC5_EN#
VCC3_EN#
VPPD0
VPPD1
+VPPOUT 18,52
J716
PCICLK_CARD
ICS950810
12 R826 33
PCI_GNT0#
SUSB# R1200 4.7K
CARD_PCIRST#
9
10
8
PCI_REQ0#
R186
8.2k
PCI_FRAME#
R231
8.2k*2
PCI_IRDY#
PCI_TRDY#
PCI_DEVSEL# PCI_STOP#
PCI_PERR#
PCI_SERR#
PCI_PAR PCI_C/BE#[0..3]
SERIRQ
VCCD0#
VCCD1#
VPPD0
VPPD1
R211,
R212
R180
R1199
R1201
10K*2
+3V
MA/15PX2/ST
SDCD#
+SD_MSVDD
20,27,29
MS_INS# MS_BS MS_SDIO 2,12,14
SD_WP# SD_CMD 1,4,6
R1198 10 SD_CLK 7
8~11
CAD[0..31]
CCD2# CCD1# 36,67
CVS[1,2] 43,57
CCBE[0..3]#
R2_ A18 R2_ D2 4732,40 R2_ D14
CBLOCK# 48~50 CSTOP# CDEVSEL#
CTRDY# 13,15,53 CPAR CGNT#
CSTSCHG CAUDIO CSERR# 59,62,63
CINT# CIRDY# CPERR# 14,16,20
CREQ# CRST# CFRAME# 54,58,60
CCLK 19 R1213 33
7,12,21,61
2~6,8~11
1
2
15
14
U712
U9
P17
P17
P17
P13
P11
P17
CLKGEN
S
D

C
a
r
d
CardBus
Reader
R1202
8.14 CardBus & Reader Test Error
An error occurs when a PC card device is installed.
PCI_AD20 100
JL7
M
S

C
a
r
d
5 R1203 10 MS_SCLK
SD[0..3]
8050
8050
N/B Maintenance
N/B Maintenance
126
TV Fail
1. Check if the TV device is installed
properly.
2. Confirm TV driver is installed ok.
Yes
No
Test
OK?
Correct it.
Correct it.
Yes
No
Re-test
OK?
Board-level
Troubleshooting
Replace
Motherboard
Parts:
Signals
DOVCD[0..11]
POUT/DET#
TV_DDDA
TV_DDCK
DVOVREF
TV_PCIRST#
855_TV_COMP
855_TV_LUMA
855_TV_CRMA
DVOCCLK
DVOCCLK#
DVOCVSYNC
U2
J704
U714
U715
U9
Q702
Q712
L56
L19
L20
C17
C19
C344
R59
R807
R395
R162
R113
R114
R157
R111
R112
R115
R128
R147
R1240
R763
R766
X701
DVOCHSYNC
XIN
XOUT
8.15 TV ENCODER Test Failure
An error occurs when using the computer as TV.
8050
8050
N/B Maintenance
N/B Maintenance
127
U714
U2
CH7011A
XIN
XOUT
42
43
U715
ICH4_M
TV_PCIRST#
9
10
8 13
3
+1.5V
R59
1K
R114,R157
855GM/
GME
DVOCCLK
DVOCCLK# POUT/DET# 0*5 DVOCHSYNC R125,,R128,R147
DVOCVSYNC
4,5,46,56,57
DVOCD[0..11] R111,R112,,R115.. 50~55,58~63
J704
7
4
6
C344 33P
L56
L19
L20
120Z/100M
39
37
38
R1240
R763
R766 0
0
0
C17
C19
33P
33P
120Z/100M
120Z/100M
R162 15
14
Q702
R113
Q712
TV_DDCK
TV_DDDA
0*12
2N7002
2N7002
+3V
X701
14.318MHZ
1
2
DVOVREF
0
0
R807 R935
10K 10K
855_TV_CRMA
855_TV_LUMA
855_TV_COMP
P11
U9
P4
P13
T
V
_
C
A
R
D
C
O
N
N
E
C
T
O
R
P26
8.15 TV ENCODER Test Failure
An error occurs when using the computer as TV.
C52 C56
20P 20P
JL10
8050
8050
N/B Maintenance
N/B Maintenance
128
IEEE 1394 Fail
1. Check if the 1394 device is installed
properly.
2. Confirm 1394 driver is installed ok.
Yes
No
Test
OK?
Correct it.
Correct it.
Yes
No
Re-test
OK?
Board-level
Troubleshooting
Replace
Motherboard
Parts:
Signals
PCI_AD[0..31]
PCI_C/BE# [0..3]
PC_DEVSEL#
PCI_FRAME#
PCI_IRDY#
PCI_TRDY#
PCI_STOP#
PCI_PAR
PCI_PERR#
PCI_REQ1#
PCI_PME#
+3V,+3VS
+PHYVDD
1394_PCIRST#
PCI_GNT1#EE
CS_1394
EECK_1394
EEDI_1394
EEDO_1394
TPBIAS
TPA+_6307
TPA-_6307
TPB+_6307
TPB-_6307
1394_AVCC
XI
XO
U724
U722
J718
U9
U712
U715
L743
L746
L740
L83
R1117
R828
R1116
R1142
R1141
X707
8.16 IEEE 1394 Test Failure
An error occurs when a IEEE 1394 device is installed..
8050
8050
N/B Maintenance
N/B Maintenance
129
U724
VT6307L
U715
ICH4_M
PCI_AD[0..31] 5~28,97~120
PCI_C/BE#[0..3] 4,15,107,122
PCI_FRAME# PCI_DEVSEL# PCI_TRDY# PCI_IRDY#
PCI_GNT1# PCI_REQ1# PCI_INTG# PCI_PERR# PCI_STOP#
PCICLK_1394
U712
ICS950810
R828 33
1394_PCIRST#
93
2
1
3
U9
PCI_PAR 3
92
PCI_PME# 37
U722
93C46
P18
EECS_1394
EECK_1394
EEDI_1394
EEDO_1394
1
2
3
4
CS
SK
DI
DO
8
VCC
+3V
X707
24.576MHZ
C932 C939
10P 10P
R1116 1M
XI
XO
60
61
2 1
4 3
L740
120Z/100M
2 1
4 3
L83
120Z/100M
TPB-_6307
TPB+_6307
TPA-_6307
TPA+_6307
J718
1
2
3
4
R1142 R1141
54.9 54.9
TPBIAS 74
70
71
72
73
29
30
31
32
R1117 100 PCI_AD21 108
VCC0~7
+3V
VCCRAM
+PHYVDD
120Z/100M
L743
39,49
+3VS
120Z/100M
L746
1394_AVCC
62,65,75
76,89,90
+3V
R211,
R212,
R218
8.2K
24,8,20
123,126
16
1
3
9
4
C
O
N
N
E
C
T
O
R
P11
P13
P18
P18
8.16 IEEE 1394 Test Failure
An error occurs when a IEEE 1394 device is installed..
JL2
R1143 R1144
R1148 C965
270P
54.9
4.99K
54.9
8050
8050
N/B Maintenance
N/B Maintenance
130
Part Number Description Price(US)
442672600031 AC ADPT ASSY;19V,3.16A,DELTA,706
361400003030 ADHESIVE;ABS+PC PACK,G485,CEMIDA
361400003005 ADHESIVE;HEAT,TRANSFER,HTA-48(W)
441681730001 BATT ASS'Y;11.1V,4.0Ah,LI,BL3244
441681730002 BATT ASSY;11.1V,4.0Ah,LI,CASE CL
441681730003 BATT ASSY;11.1V,4.0Ah,LI,CORE PA
338536010006 BATTERY;LI,3.6V/2.0AH,18650,PANA
340680900025 BEZEL ASSY;DVDRW,MKE,UJ815,8050
242670800113 BFM-WORLD MARK;WINXP,7521N
340680900006 BRACKET ASSY;SYSTEM,8050
340680900009 BRACKET ASSY;TP,8050
342672200010 BRACKET;CD-ROM,8500
322680900001 CABLE FFC;TP,8050
272075103408 CAP ;0.1U CR 50V 10% 0603 X7R S C10,C11,C12,C15,C3,C5,C6,C7,C8
272005104705 CAP ;1U CR 50V +80-20% 0805 Y5V C14A,C14B,C4A,C4B
272075101404 CAP; 0.001U CR 50V 10% 0603 X7R C13
272075471409 CAP; 0.0047U CR 50V 10% 0603 X7 C4
272075223702 CAP; 0.22U CR 50V +80-20% 0603 C1,C2,C20A,C24,C25
272105103702 CAP;.01U ,50V,+80-20%,0402,SMT C171,C176,C337,C339,C343,C386
272075103401 CAP;.01U ,CR,50V ,10%,0603,X7R,S C13,C8
272075103401 CAP;.01U ,CR,50V ,10%,0603,X7R,S C11,C3
272073223401 CAP;.022U,CR,25V ,10%,0603,X7R,S C9
272075473401 CAP;.047U,50V,10%,0603,X7R,SMT C313
272102473402 CAP;.047uF ,16V ,+-10%,0402,X7R, C841
272072824401 CAP;.082U ,16V ,10%,0603,X7R,SMT C16
272071154401 CAP;.15U ,CR,10V,10%,0603,X7R,SM C482,C490
272105104701 CAP;.1U ,16V,+80-20%,0402,SMT C1000,C104,C12,C13,C133,C16,C
272102104401 CAP;.1U ,CR,10V,10%,0402,X5R,SM PC44
272072104402 CAP;.1U ,CR,16V,10%,0603,X7R,SM C17
272072104402 CAP;.1U ,CR,16V,10%,0603,X7R,SM C12,C6
272073104401 CAP;.1U ,CR,25V,10%,0603,X7R,PR C22,C7
272005104402 CAP;.1U ,50V,+/-10%,0805,X7R,SMT PC9
272005104404 CAP;.1U,CR,50V,10%,0805,SMT PC4,PC51,PC52,PC65,PC66,PC7,P
272102224701 CAP;.22U ,10V ,+80-20%,0402,Y5V, C14,C483,C496,C515
272071332401 CAP;.33U ,10V ,10%,0603,X7R,SMT C2
272102334701 CAP;.33U ,CR,10V ,+80-20%,0402,Y C964
272030102401 CAP;1000P,2KV,10%,1808,X7R,SMT C148,C327,C806
272105102501 CAP;1000P,50V ,+/-20%,0402,X7R,S C1006,C1007,C1008,C340,C357,C
272105102408 CAP;1000P,CR,50V,10%,0402,X7R,SM C960,C962,PC14,PC17,PC18,PC19
272075102403 CAP;1000P,CR,50V,10%,0603,X7R,SM C471
272105101402 CAP;100P ,50V ,+ -10%,0402,NPO,S C10,C330,C455,C498,C520,C521,C
272075101401 CAP;100P ,50V ,10%,0603,COG,SMT C20,C21
272105101401 CAP;100P ,50V ,5%,0402,COG,SMT C150,C18,C20,C503
272010101301 CAP;100P,2KV,5%,1206,NPO,SMT,onl C18
272010101302 CAP;100P,2KV,5%,1206,NPO,SMT,onl
272105100303 CAP;10P ,CR,50V ,5%,0402,NPO,SM C789,C790,C791,C795,C796,C797
272021106501 CAP;10U ,10V ,20%,1210,X7R,SMT C475
272011106701 CAP;10U ,10V,+80-20%,1206,Y5V,S C166,C174,C238,C271,C355,C772
272023106502 CAP;10U,25V,M,1210,T2.5MM,X5R,SM PC703,PC704,PC705,PC721,PC73
272001106702 CAP;10U,6.3V,+- 20%,0805,X5R,SMT C155,C156,C157,C158,C168,C173
9. Spare Part List(1)
8050
8050
N/B Maintenance
N/B Maintenance
131
272431157507 CAP;150U ,TPC,6.3V,20%,H1.9,7343 C701,C713,C768,PC712,PC719,PC
272431157512 CAP;150U,6.3V,+/-20%,H2.8,PT,NCC
272105181403 CAP;180P,50V,10%,0402,SMT PC24,PC25,PC61,PC63,PC738
272001105403 CAP;1U ,10%,10V ,0805,X7R,SMT PC3,PC46
272012105401 CAP;1U ,CR,16V ,10%,1206,X7R,S C14A,C14B
272003105701 CAP;1U ,CR,25V ,+80%-20%,0805, PC701
272102105701 CAP;1U ,CR,6.3V ,80-20%,0402,Y C1002,C11,C160,C206,C210,C219
272071105403 CAP;1U ,10V ,10%,0603,X5R,SMT C10,C4
272002225701 CAP;2.2U ,CR,16V ,+80-20%,0805,Y C921,C961
272071225401 CAP;2.2U ,CR,6.3V ,10%,0603,X5R, C1001,C151,C161,C239,C24,C283
272105200401 CAP;20P ,50V,+-10%,0402,SMT C52,C56
272105222501 CAP;2200P,50V ,+/-20%,0402,X7R,S C470,C494,C509,C728,C869
272075222401 CAP;2200P,50V ,10%,0603,X7R,SMT C15A
272075222401 CAP;2200P,50V ,10%,0603,X7R,SMT C5
272105221403 CAP;220P ,CR,50V ,10%,0402,X7R,S C165,PC11,PC73,PC734,PC75
272431227504 CAP;220U ,4V ,20%,7343,POSCAP,SM PC729,PC749
272431227528 CAP;220U,2.5V,TPE-MC,20%,POSCAP, PC775,PC778,PC781,PC784,PC78
272105220402 CAP;22P ,50V ,+ -10%,0402,NPO,S C447,C450,C855,C861
272105271403 CAP;270P ,50V,+-10%,0402,X7R,SMT C15,C21,C782,C965
272105270303 CAP;27P ,50V ,5%,0402,COG,SMT C794,C804,C914,C915
272105332402 CAP;3300P,50V,10%,0402,SMT PC28,PC56
272431337506 CAP;330U,4V,20%,7343,SMT PC787,PC788
272103331401 CAP;33P ,25V ,+/-10%,0402,NPO,S C17,C19,C344
272023475401 CAP;4.7U ,25V ,10%,1210,X5R,SMT C1
272001475701 CAP;4.7U ,CR,10V ,+80-20%,0805,Y C311,C517,C871,C941,C947
272070475701 CAP;4.7U,CR,6.3V,+80-20%,0603,Y5 C860,C908
272075471401 CAP;470P ,50V,10%,0603,X7R,SMT C15B
272105470402 CAP;47P ,50V ,+ -10%,0402,NPO,S C1,C143,C144,C154,C172,C2,C4,C
272030050302 CAP;5P,3KV,5%,1808,NPO,SMT,only C19
221673150002 CARD BOARD;FRAME,PALLET,8060
221673150003 CARD BOARD;TOP/BTM,PALLET,8060
221600020252 CARTON;BATTERY,CAIMAN,PWR
221673120003 CARTON;N-B,8060
431680900003 CASE KIT;8050,INTERGRATE
335152000026 CFM-BAT;FUSE,THERMAL,NEC,SF91E
242678500005 CFM-INTEL;CENTRINO,NOTEBOOK,8081
273000500115 CHOKE COIL;400uH MIN,120m MAX; L724
273000150313 CHOKE COIL;90OHM/100MHZ,20%,2012 L2,L22,L5
361200001018 CLEANNER;YC-336,LIQUID,STENCIL/P
331000000302 CON HOLDER;PCMCIA,UP,STANDOFF 0. J6
291000000023 CON;4-IN-1 MEMORY CARD,MS,SD,XD, J2
291000000706 CON;BATTERY,7P,MA,2.5MM,R/A,C103 J703
331710015016 CON;D,FM,15P,3ROW,SUYIN,070912FR J702
291000622007 CON;DIMM,R/A,200P,.6,H9.2,REVERS J711
291000152603 CON;FPC/FFC,26P,1MM,R/A,KBD,SMT J5
331040050018 CON;HDR,BTB R/A,0.8MM,S-TECH1507 J708
291000023008 CON;HDR,FM,15P*2,0.8MM.H5,R/A,SM J717
331030044019 CON;HDR,FM.22P*2,R/A,ST,ACE-1A2, J714
291000021105 CON;HDR,MA,11P*1,ACES,87213-1100 CN1
291000021105 CON;HDR,MA,11P*1,ACES,87213-1100 J1
8050
8050
N/B Maintenance
N/B Maintenance
132
291000013027 CON;HDR,MA,15P*2,ACES,88026-3000 J716
291000013026 CON;HDR,MA,15P*2,ACES,88029-3000 J1
291000013025 CON;HDR,MA,15P*2,ACES,88107-3000 J2
291000020206 CON;HDR,MA,2P*1,1.25MM,H2.57,R/A J3,J7,J705,J715
291000010209 CON;HDR,MA,2P*1,1.25MM,H4.2,ST,S J710
291000000203 CON;HDR,MA,2P*1,3.5MM,R/A,SMT,SM J2
291000020204 CON;HDR,MA,2P*1,3.5MM,R/A,SMT,SM
291000010303 CON;HDR,MA,3P*1,1.25MM,H4.2,ST,S J707
331040004024 CON;HDR,MA,4P*1,H=5.9,R/A,USB,DI J706
291000010619 CON;HDR,MA,6P,ACES,87151-0607,SM J4
291000256843 CON;IC CARD,68P,UP,STANDOFF 0.0 J6
331000004009 CON;IEEE1394,MA,4P*1,0.8MM,R/A J718
331870007007 CON;MINI DIN,7P,R/A,W/GROUND,330 J704
291000811008 CON;PHONE JACK,2 IN 1,7.0MM,ALLT J709
331910002006 CON;POWER JACK,2P,20VDC,5A,DIP PJ701
331840010008 CON;STEREO JACK,10P,W/SPDIF,R/A, J720
291000920605 CON;STEREO JACK,6P,W9.5,33184000 J719,J721
331000008033 CON;USB,FM,H15.64,R/A,4P*2,2522A J701
345677000018 CONDUCTIVE TAPE;LCD,LYNX
331000007025 CONNECTOR;7 PIN,DIP,ALLTOP,C1034 CON1
441681730031 CONTACT PLATE ASSY;W4L27T0.15,FU
441674800032 CONTACT PLATE ASSY;W4L27T0.15,S-
342503100004 CONTACT PLATE;W4L27,1/2R,1/2T,75
342502900001 CONTACT PLATE;W4L27T0.15,7068
342503100002 CONTACT PLATE;W4L63,1/2R,1/4T,75
340680900004 COVER ASSY;8050
340680900010 COVER ASSY;HDD,8050
340680900012 COVER ASSY;LCD,8050
340680900029 COVER ASSY;MINIPCI,8050
344680900002 cover;bat t ery,8050
344680900015 COVER;CPU,8050
344680900016 COVER;DDR,8050
344680900049 COVER;HINGE,L,8050
344680900011 COVER;HINGE,R,8050
344680900010 COVER;REAR,L,8050
344680900009 COVER;REAR,R,8050
272625470401 CP;47P*4 ,8P,50V ,10%,1206,NPO,S CP2
323767340001 DDR SODIMM MODULE;DDR333,256MB,M
331660020005 DIMM SOCKET;DDR SODIMM 200P, CA0 J712
288111544001 DIODE; 1SR-154-400 400V 1.0A D1
288110355001 DIODE;1SS355,80V,100mA,SOD-23,SM D2
288100140007 DIODE;B140,40V,1A,SMA,DIODES,SMT PD706
288100340008 DIODE;B340LA,40V,3A,SMA,DIODES,S PD713,PD714,PD718
288100032013 DIODE;BAS32L,VRRM75V,MELF,SOD-80 D24,D7,PD5
288100054001 DIODE;BAT54,30V,200mA,SOT-23 D10,D11,D15,D16,D2
288100054002 DIODE;BAT54C,SCHOTTKY DIODE,SOT2 D22,PD4
288100070006 DIODE;BAV70LT1,70V,225MW,SOT-23, D12,D18,PD702,PD704
288100099012 DIODE;BAV99LT1,70V,450MA,SOT-23, PD2,PD3
288100056017 DIODE;BAW56LT1,70V,215MA,SOT-23, D704,D715,PD1,PD6,PD7,PD705
288105515001 DIODE;BZV55-C15,ZENER,5%,SOD-80, PD709
8050
8050
N/B Maintenance
N/B Maintenance
133
288104148001 DIODE;RLS4148,200MA,500MW,MELF,S D17,D19,D21,D27,D703
288100024002 DIODE;RLZ24D,ZENER,23.63V,5%,SMT PD701
288101040006 DIODE;SBM1040,10A,SCHOTTKY,POWER PD703
288100056005 DIODE;UDZ5.6B,ZENER,5.6V,UMD2,SM D13
288100056005 DIODE;UDZ5.6B,ZENER,5.6V,UMD2,SM ZD3,ZD4
344680900048 DUMMY CARD;PCMCIA,8050
523468090014 DVD MULTI ASSY;KME,UJDA-815,8050
272601107506 EC;100U ,6.3V,M,9.3*3.6,-55~105' C466,C474,C489,C951
227680900003 END CAP;NORMAL,L/R,8050
481680900002 F/W ASSY;KBD CTRL,8050 U16
481680900005 F/W ASSY;SYS/VGA BIOS,8050,INTEG U15
273000150002 FERRIET CHIP;120OHM/100MHZ,2012, L41,L732,L735,L737
273000610025 FERRITE ARRAY;120OHM/100MHZ,ONLY FA2
273000620001 FERRITE ARRAY;600OHM/100MHZ,2520 L49,L51,L740,L83
273000130001 FERRITE CHIP;120OHM/100MHZ,1608, L19,L20,L38,L42,L43,L45,L56,L7
273000150013 FERRITE CHIP;120OHM/100MHZ,2012, L15,L17,L18,L25,L46,L47,L54,L6
273000130039 FERRITE CHIP;130OHM/100MHZ,1608, L10,L11,L12,L36,L37,L7,L9
273000130015 FERRITE CHIP;220OHM/100MHZ,1608, L58,L59,L60
273000130006 FERRITE CHIP;600OHM/100MHZ,.2A,1 L13,L14,L16,L50,L52,L53,L55,L5
342672400007 FINGER;EMI GROUNDING SMD FINGER TP45,TP48,TP50
335152000085 FUSE; 128 DC-7A/50V 139only UC F1
295000010028 FUSE;0.14A/60V,POLY SWITCH,PTC,S F2
295000010048 FUSE;0.5A/15V,POLY SWITCH,SMD F701
295000010114 FUSE;FAST,1.75A,63VDC,1206,SMT,P F1
295000100004 FUSE;FAST,1A,63V,1206,THIN FILM F3
295000010140 FUSE;FAST,2A,63VDC,1206,SMT,0433 F1
295000010141 FUSE;FAST,3A,32VDC,1206,SMT,0433 PF703
335152000097 FUSE;LR4-73X,POLY SWITCH,PWR
295000010163 FUSE;NORMAL,7A/24VDC,0433007,120 PF1,PF2,PF702
347105015007 GASKET;1,05,015,007
347105030025 GASKET;1,05,030,025
347105035020 GASKET;1,05,035,020
347105040015 GASKET;1,05,040,015
347108030008 GASKET;1,08,030,008
347110003010 GASKET;1,10,003,010
347110010010 GASKET;1,10,010,010
523402379038 HD DRIVE,40GB,2.5",MHT2040AT,FUJ
523468090002 HDD ASSY;40GB,MHT2040AT,FUJITSU,
451680900031 HDD ME KIT;8050
340680900013 HEATSINK ASSY;8050
451680900092 HEATSINK ASSY;MPT,8050
451680900091 HEATSINK ASSY;UNP,8050
451999900002 HEATSINK OPTION;8050
343677100001 HEATSINK;NORTHBRIDGE,BANIAS,LYNX
342680900006 HINGE;L,8050
342680900005 HINGE;R,8050
340680900011 HOUSEING ASSY;LCD,8050
340680900005 HOUSING ASSY;8050
451680900071 HOUSING KIT;8050
344680900003 housing;bat t ery,8050
8050
8050
N/B Maintenance
N/B Maintenance
134
291000614793 IC SOCKET;UPGA479M,479P,MOLEX U713
324180786389 IC,CPU,BANIAS,1.6GHZ,MICRO-FCPGA
282574008005 IC;74AHC08,QUAD 2-I/P AND,TSSOP, U9
282574014004 IC;74AHC14,HEX INVERTER,TSSOP,14 U703
282574132001 IC;74AHCT1G32,SINGLE OR GAT,SOT2 U17
284500522001 IC;855GME GMCH,NORTH BRIDGE,BGA, U714
284507460002 IC;ADT7460,TEMPERATURE MTR,QSOP, U706
284500655003 IC;ALC655,AUDIO CODEC,LQFP,48P,S U726
286301117021 IC;AMS1117,VOL REGULATOR,1A,SOT- U6
286303107001 IC;AMS3107C,3.3V,1%,VOL REGULATO U13
286002040001 IC;BQ2040,GAS GAUGE,SO,16P,SMT IC1
286300710002 IC;CB710,CARDBUS/CARD READER,LFG U727
284507011001 IC;CH7011A,TV ENCODER,LQFP,64P U2
286302211006 IC;CP2211,POWER DISTRI SW,REV.C1 U728
283467540001 IC;EEPROM,M24C02-WMN6T,2K,SO8,SM IC2
283467540002 IC;EEPROM,M93C46-WMN6T,64*16 BIT U722,U723
283467530001 IC;EEPROM,S24CC02A,2K,SO8,SMT,ON
283450040001 IC;FLASH,512*8,FWH,M50FW040K1,PL
283449004001 IC;FLASH,512*8,FWH/LPC,PM49FL004
283467490001 IC;FLASH,512K*8,FWH,SST49LF004A,
283467490002 IC;FLASH,512K*8,FWH,W39V040FAP,P
284582801044 IC;FW82801DBM,ICH4-M,BGA,421P U715
286369229301 IC;G692L293T,RESET CIRCUIT,2.93V U21
286300690001 IC;GMT690B,RESET CIRCUIT,2.93V,S U10
284595081201 IC;ICS950812,CK408 CLOCK GEN,TSS U712
286104871002 IC;LM4871LD,AUDIO AMP,4Ohm,2.5W, U725
286100393004 IC;LMV393,DUAL COMPARTOR,SSOP,8P PU5
286100822002 IC;LMV822,OP AMP,DUAL,CMOS,MSOP, U19
286302951015 IC;LP2951ACM,VOLTAGE REGULATOR,S U11
286303728002 IC;LTC3728LX,PWM CTRL,LTC,5X5 QF PU14,PU15,PU2,PU703
286303734001 IC;LTC3734,PWM CONTROLLER,32-QFN PU3
286104173001 IC;MAX4173F,I-SENSE AMP,SOT23,6P PU1
286301414001 IC;MM1414,PROTECTION,TSOP-20A,PR IC4
281101015001 IC;MP1015EM-Z,CCFL CTRL,TSSOP20, U1
286309167001 IC;RT9167-47CB,200MA LDO REGULAT U18
286309701001 IC;RT9701,POWER DISTRI SW,SOT23- U701,U705
284508100009 IC;RTL8100CL,LAN CONTROLLER,LQFP U719
286300812002 IC;S-812C,DECECTOR,SOT-89,PRC IC3
286300431014 IC;SC431LCSK-.5,.5%,ADJ REG,SOT2 PQ11
286300594001 IC;TL594C,PWM CONTROL,SO,16P PU7
286100212001 IC;TPA0212,AMPLIFIER,TSSOP,24P,S U524
284506307001 IC;VT6307L,PCI-1394,2PORT,LQFP,1 U724
284583950002 IC;W83L950D-Ver.C,LPC_KBC,LQFP,8
273000990054 INDUCTOR;10UH,D124C,+/-20%,TOKO, PL702,PL703
273000990184 INDUCTOR;3.0UH,30%,CDRH5D28,H3.0 PL717
273000990186 INDUCTOR;3.0UH,30%,CDRH6D28,H2.8 PL709,PL713,PL714
273000990185 INDUCTOR;3.9UH,30%,CDRH8D43,H4.5 PL706,PL707,PL715
273000990021 INDUCTOR;33uH,CDRH124,SUMIDA,SMT PL710
273000990127 INDUCTOR;IHLP5050CE-01-0.68uH,VI PL711
346503100005 INSULATOR;5,BATTERY ASSY,7521Li
8050
8050
N/B Maintenance
N/B Maintenance
135
346503200202 INSULATOR;BATT ASSY,ONE ROUND,BL
346681800004 INSULATOR;BATT,ASSY,L129W15T0.25
346680900002 INSULATOR;CARD READER,8050
346680900010 INSULATOR;DDR,MINIPCI,8050
346677300001 INSULATOR;FIBER,UL94V-0,D=17.5mm
346680900005 INSULATOR;INVERTER,LCD,8050
346680900017 INSULATOR;L16W8.5T0.05MM,DIALAMY
346680900001 INSULATOR;MB,8050
346680900007 INSULATOR;PCB,ASSY,L105,W12T1.0
346680900009 INSULATOR;PCMCIA,8050
361400003003 JET-MELT ADHESIVES;3478-Q,5/8in*
531020237777 KBD;88,UI,K011818A1,8050,BK
451680900001 LABEL KIT;N-B,8050
242600000145 LABEL;10*10,BLANK,COMMON
242600000439 LABEL;25*6,HI-TEMP,COMMON
242600000439 LABEL;25*6,HI-TEMP,COMMON
242600000378 LABEL;27*7MM,HI-TEMP 260'C
242668300028 LABEL;32*7MM,POLYESTER FILM,HOPE
242600000232 LABEL;6*6MM,GAL,BLANK,COMMON
242680900001 LABEL;AGENCY-GLOBAL,8050
242679900005 LABEL;BAR CODE,(25*10MM)*12pcs,8
242600000157 LABEL;BAR CODE,125*65,COMMON
242680900005 LABEL;BATT,11.1V/4.0AH,LI,PANSON
242600000433 LABEL;BLANK,11*5MM,COMMON
242669900009 LABEL;BLANK,60*80MM,7170
242600000452 LABEL;BLANK,7MM*7MM,PRC
242600000452 LABEL;BLANK,7MM*7MM,PRC
242669600005 LABEL;LOT NUMBER,RACE
242600000001 LABEL;PAL,20*5MM,COMMON
242600000315 LABEL;RED ARROW HEAD,PRC
441680900031 LCD ASSY;SAMSUNG,XGA,15.4",LTN15
451680900051 LCD ME KIT;SAMSUNG,15.4",8050
413000020388 LCD;LTN154X1-L02,TFT15.4",XGA,SA
294011200069 LED;GREEN,19-21VGC/TR8,LED_CL190
294011200069 LED;GREEN,19-21VGC/TR8,LED_CL190
294011200034 LED;GREEN,H.8,0603,19-21VGC/TR,S LED4,LED5
294011200034 LED;GREEN,H.8,0603,19-21VGC/TR,S LED3,LED6
294011200016 LED;GREEN,H0.8,0603,CL-190G,SMT D32,D33,D34,D35,D36,D37,D38
294011200043 LED;RE/GR,H0.8,L1.9,W1.6,19-22SR LED1
294011200043 LED;RE/GR,H0.8,L1.9,W1.6,19-22SR LED2
416268090001 LT PF;SAMSUNG,15.4",LTN154WX,805
526268090006 LTX;8050/5ADB/40K/9UI9/B5D3A/XL
339115000046 MICROPHONE;-60dB+-2dB,D6.0*H2.7, MIC1
291000251246 MINIPCI SOCKET;124P,R/A,0.8MM,H= J713
346680900011 MYLAR;COVER,LCD,8050
461680900006 PACKING KIT;N-B BOX,8050
227680900002 PAD;LCD/KB,8050
8050
8050
N/B Maintenance
N/B Maintenance
136
224670830002 PALLET;1250*1080*130,7521N
221673150001 PARTITION;AK BOX,8060
221600050218 PARTITION;BATTERY,MARLIN,CAIMAN,
221673150004 PARTITION;PALLET,8060
221600050219 PARTITION;TOP/BTM,BATTERY,MARLIN
412681300001 PCB ASSY;D/A BD,DA-1A08-A,PWR
412678800001 PCB ASSY;FAX MODEM 56K,1456VQL4A
412673400008 PCB ASSY;MINI-PCI,TYPE IIIB,INTE
316680900003 PCB;PWA-8050 Card Reader_Transit R0B
316680900001 PCB;PWA-8050 M BD R01
316680900006 PCB;PWA-8050/BATT ,PR AND GA BD
316681300001 PCB;PWA-INVERTER BD (DA-1A08-A); R0E
222670820003 PE BAG;L560*W345,7521N
222503220001 PE BUBBLE BAG;BATTERY,GRAMPUS
273000150033 PHASEOUT;FERRITE CHIP,120OHM/100 L743,L746
411680900011 PWA;PWA-8050,MOTHER BD,INTERGRAT
411680900013 PWA;PWA-8050,MOTHER BD,SMT,INTER
411680900012 PWA;PWA-8050,MOTHER BD,T/U,INTER
411680900008 PWA;PWA-8050-CARD READER TRANSIT
411681300001 PWA;PWA-INVERTER BD,DA-1A08-A,PW
411681300004 PWA;PWA-INVERTER BD,SMT BOT,DA-1
411681300003 PWA;PWA-INVERTER BD,SMT TOP,DA-1
411681300002 PWA;PWA-INVERTER BD,SMT,DA-1A08-
411681710001 PWA-PWA-BATT BD;LI,4.4Ah,2P3S,BL
411681710002 PWA-PWA-BATT BD;SMT,BL3244G095/8
332810000034 PWR CORD;250V/2.5A,2P,BLK,EU,175
271046017301 RES;.001,2W,5%,2512,CYNTEC,SMT PR740
271045087101 RES;.008 ,1W ,1% ,2512,SMT PR742
271045107101 RES;.01 ,1W ,1% ,2512,SMT PR701
271034127101 RES;.012,1/2W,1%,2010,WSL2010,VI PR707,PR711,PR719,PR732,PR73
271586026101 RES;.02 ,2W,1%,2512,SMT PR22
271002000301 RES;0 ,1/10W,5% ,0805,SMT L62,L65,L73,L88,R1,R123,R26,R2
271061000002 RES;0 ,1/16W,0402,SMT PR103,PR104,PR11,PR111,PR120
271071000002 RES;0 ,1/16W,5% ,0603,SMT L69,L719,L728,L744,L747,L751,L
271012000301 RES;0 ,1/8W,5% ,1206,SMT PR86
271044100101 RES;0.010,1.5W, 1%,2512,SMT;PWR R6
271045507103 RES;0.050,1W, 1%,2512,SMT, only R24A,R24B,R24C
271061010101 RES;1,1/16W,1%,0402,SMT PR18
271061135101 RES;1.3M,1/16W,1%,0402,SMT PR16,R1158
271061152501 RES;1.5K ,1/16W,5% ,0402,SMT R1084,R798
271071152302 RES;1.5K ,1/16W,5% ,0603,SMT R17
271071152302 RES;1.5K ,1/16W,5% ,0603,SMT R19
271061196212 RES;1.96K,1/16W,1%,0402,SMT PR710
271061100501 RES;10 ,1/16W,5% ,0402,SMT PR1,R1000,R1001,R1009,R1010,R
271061100102 RES;10,1/16W,1%,0402,SMT PR37,PR38,PR5
271061102312 RES;10.2K,1/16W,1% ,0402,SMT R496,R502
271061101103 RES;100 ,1/16W,1% ,0402,SMT R1092,R1117,R1202,R208,R257,R
271071101301 RES;100 ,1/16W,5% ,0603,SMT R11,R12,R14,R15,R16,R20,R21
271061104102 RES;100K ,1/16W,1% ,0402,SMT PR10,PR112,PR114,PR12,PR30,P
271071104101 RES;100K ,1/16W,1% ,0603,SMT R18,R22,R23,R9
8050
8050
N/B Maintenance
N/B Maintenance
137
271061104501 RES;100K ,1/16W,5% ,0402,SMT PR69,PR703,PR720,PR83,PR89,R
271071104302 RES;100K ,1/16W,5% ,0603,SMT R7
271061107411 RES;107K,1/16W,1%,0402,SMT PR35
271061103102 RES;10K ,1/16W,1% ,0402,SMT PR102,PR119,PR4,PR47,PR724,P
271061103501 RES;10K ,1/16W,5% ,0402,SMT R1007,R1098,R11,R1103,R1115,R
271071103302 RES;10K ,1/16W,5% ,0603,SMT R2
271071103302 RES;10K ,1/16W,5% ,0603,SMT R5,R7,R8
271061106501 RES;10M ,1/16W,5% ,0402,SMT R296,R938
271061118211 RES;11.8K,1/16W,1%,0402,SMT PR116
271061127212 RES;12.7K,1/16W,1%,0402,SMT PR17
271061124312 RES;124K,1/16W,1%,0402,SMT PR79
271071127011 RES;127 ,1/16W,1% ,0603,SMT R14A
271071127011 RES;127 ,1/16W,1% ,0603,SMT R163
271061133311 RES;13.3K,1/16W,1%,0402,SMT PR19,PR29
271061137371 RES;13.7K,1/16W,.1%,0402,SMT PR74
271061133101 RES;13.7K,1/16W,1%,0402,SMT PR96
271071131101 RES;130 ,1/16W,1% ,0603,SMT R911
271071141102 RES;140 ,1/16W,1% ,0603,SMT R37
271061151102 RES;150 ,1/16W, 1%,0402,SMT R220,R446,R791,R850,R884,R912
271061153102 RES;15K ,1/16W,1% ,0402,SMT PR105,PR107,PR122,PR727,PR72
271061152302 RES;15K ,1/16W,5% ,0402,SMT R1008
271061180101 RES;18.2 ,1/16W,1% ,0402,SMT R838
271061184302 RES;180K ,1/16W, 5%,0402,SMT R1140,R288
271061183102 RES;18K,1/16W,1%,0402,SMT PR718,R462,R507
271061196213 RES;19.6K,1/16W,1%,0402,SMT PR36,PR97,PR99
271061102105 RES;1K ,1/16W,1% ,0402,SMT PR121,PR53,R1006,R141,R328,R5
271061102303 RES;1K ,1/16W,5% ,0402,SMT R1136,R1147,R155,R181,R21,R25
271071102302 RES;1K ,1/16W,5% ,0603,SMT R11
271061105501 RES;1M ,1/16W,5% ,0402,SMT PR106,PR115,PR123,PR26,PR27,P
271071105301 RES;1M ,1/16W,5% ,0603,SMT R10,R3
271061222501 RES;2.2K ,1/16W,5% ,0402,SMT R315,R318
271061222101 RES;2.2K,1/16W,1%,0402,SMT PR6
271061232111 RES;2.32K,1/16W,1%,0402,SMT PR39
271061249211 RES;2.49K,1/16W,1% ,0402,SMT PR77
271061272102 RES;2.7K ,1/16W,1% ,0402,SMT R448,R449
271061205212 RES;20.5K,1/16W,1%,0402,SMT PR113
271071201301 RES;200 ,1/16W,5% ,0603,SMT R1A,R1B
271061201101 RES;200 ,1/16W, 1%,0402,SMT R280
271061204102 RES;200K ,1/16W,1% ,0402,SMT PR54,PR55
271061203701 RES;20K ,1/16W,.1%,0402,SMT PR75
271061203102 RES;20K ,1/16W,1% ,0402,SMT PR117,PR21,PR41,PR722,PR726,R
271061220501 RES;22 ,1/16W,5% ,0402,SMT R1120,R1131,R306,R329,R424,R4
271061220102 RES;22,1/16W,1% ,0402,SMT R253
271061221312 RES;22.1K,1/16W,1% ,0402,SMT R463,R479,R509,R510
271071221211 RES;22.1K,1/16W,1% ,0603,SMT R1122
271061221313 RES;220 ,1/16W, 5%,0402,SMT R552,R555,R556,R557
271061224501 RES;220K ,1/16W,5% ,0402,SMT R251
271071224301 RES;220K ,1/16W,5% ,0603,SMT R1
271061226311 RES;226K,1/16W,1%,0402,SMT PR71
271061223102 RES;22K,1/16W,1% ,0402,SMT R325,R520
8050
8050
N/B Maintenance
N/B Maintenance
138
271061249212 RES;24.9K,1/16W,1%,0402,SMT PR98
271061249312 RES;249K,1/16W,1%,0402,SMT PR729,PR76
271061270102 RES;27.4 ,1/16W, 1%,0402,SMT R133,R213,R291
271071274811 RES;27.4 ,1/16W,1% ,0603,SMT R792,R839
271072287011 RES;287 ,1/10W,1% ,0603,SMT R914
271061202102 RES;2K ,1/16W,1% ,0402,SMT PR101,PR124,PR46,PR725,PR731
271071202301 RES;2K ,1/16W,5% ,0603,SMT R12
271061332312 RES;3.3K,1/16W,5% ,0402,SMT PR70
271071362101 RES;3.6K ,1/16W,1% ,0603,SMT R1110
271061301112 RES;301 ,1/16W,1% ,0402,SMT R793,R855
271071301311 RES;301K ,1/16W,1% ,0603,SMT R13,R3
271061330501 RES;33 ,1/16W,5% ,0402,SMT R1213,R816,R817,R818,R824,R82
271061331304 RES;330 ,1/16W,5% ,0402,SMT R1073,R1089,R301,R49,R54
271071331301 RES;330 ,1/16W,5% ,0603,SMT R16,R21,R22
271071331301 RES;330 ,1/16W,5% ,0603,SMT R18,R20,R23
271071331301 RES;330 ,1/16W,5% ,0603,SMT C14
271061333501 RES;33K ,1/16W,5% ,0402,SMT PR45,R701,R706
271071374812 RES;37.4 ,1/16W,1% ,0603,SMT R898
271061390501 RES;39, 1/16W, 5%,0402,SMT R225
271061391103 RES;390,1/16W,1% ,0402,SMT R876
271061412111 RES;4.12K,1/16W,1%,0402,SMT PR58
271071432111 RES;4.32K,1/16W,1% ,0603,SMT R10
271061442212 RES;4.42K,1/16W,1% ,0402,SMT R1127,R1130
271071478101 RES;4.7 ,1/16W,1% ,0603,SMT PR109,PR110,PR2,PR3,PR708,PR
271002472301 RES;4.7K ,1/10W,5% ,0805,SMT PR704,PR706
271061472501 RES;4.7K ,1/16W,5% ,0402,SMT R10,R1081,R1132,R1154,R1200,R
271071472302 RES;4.7K ,1/16W,5% ,0603,SMT PR87,PR88
271061499212 RES;4.99K,1/16W,1% ,0402,SMT PR20,R1148
271061402011 RES;40.2 ,1/16W,1% ,0402,SMT R832
271071432211 RES;43.2K,1/16W,1% ,0603,SMT R1
271061432212 RES;43.2K,1/16W,1%,0402,SMT PR118,PR60,R1187,R1189,R1205,
271061471501 RES;470 ,1/16W,5% ,0402,SMT R1085,R553,R554,R558
271072474101 RES;470K ,1/10W,1% ,0603,SMT R4
271061474501 RES;470K ,1/16W,5% ,0402,SMT PR702,R373
271061473501 RES;47K ,1/16W,5% ,0402,SMT R442,R443,R702,R708,R929,R940
271071487811 RES;48.7 ,1/16W,1% ,0603,SMT R900
271071487011 RES;487 ,1/16W,1% ,0603,SMT,MUS R883
271061499012 RES;49.9 ,1/16W,1% ,0402,SMT R1082,R1086,R1087,R1090,R209,
271061499411 RES;499K ,1/16W,1% ,0402,SMT PR43,PR716
271071499311 RES;499K ,1/16W,1% ,0603,SMT R17
271061562102 RES;5.6K ,1/16W, 1%,0402,SMT R1099,R542
271061510303 RES;51, 1/16W, 5%,0402,SMT R224,R228,R238,R243,R289
271061549011 RES;54.9 ,1/16W,1% ,0402,SMT R1141,R1142,R1143,R1144,R142,
271061560501 RES;56 ,1/16W,5% ,0402,SMT R198,R264,R269,R273,R856,R936
271061562212 RES;56.2K,1/16W,1%,0402,SMT PR15
271071563101 RES;56K ,1/16W,1% ,0603,SMT R6
271061576411 RES;576K ,1/16W,1% ,0402,SMT PR28
271061590411 RES;590K,1/16W,1%,0402,SMT PR65
271061619211 RES;6.19K,1/16W,1% ,0402,SMT PR81
271061634211 RES;6.34K,1/16W,1% ,0402,SMT R1145
8050
8050
N/B Maintenance
N/B Maintenance
139
271061649212 RES;6.49K,1/16W,1% ,0402,SMT PR721
271061682501 RES;6.8K ,1/16W,5% ,0402,SMT R537,R538,R546,R547
271061604011 RES;60.4 ,1/16W,1% ,0402,SMT R923,R924
271002604011 RES;604 ,1/10W,1% ,0805,SMT R945,R946
271061634214 RES;63.4K,1/16W,1%,0402,SMT PR42
271071681813 RES;68.1,1/16W,1%,0603,SMT R903
271061681501 RES;680 ,1/16W,5% ,0402,SMT R214
271071684101 RES;680K ,1/16W,1% ,0603,SMT R5
271061752102 RES;7.5K,1/16W,1%,0402,SMT PR84
271061750501 RES;75 ,1/16W,5% ,0402,SMT R152,R271,R277,R46,R930
271061753101 RES;75,1/16W,1%,0402,SMT R144,R145,R334,R340,R784
271071753301 RES;75K ,1/16W,5% ,0603,SMT R8
271071822102 RES;8.2K ,1/16W,1% ,0603,SMT R14B
271061822501 RES;8.2K ,1/16W,5% ,0402,SMT R1004,R1005,R1074,R1119,R1228
271061806311 RES;80.6K,1/16W,1% ,0402,SMT PR63,PR66
451680900151 ROM ME KIT;8050
271611000301 RP;0*4 ,8P ,1/16W,5% ,0612,SMT RP26,RP27
271611103301 RP;10K*4 ,8P ,1/16W,5% ,0612,SMT RP719
271621103302 RP;10K*8 ,10P,1/32W,5% ,1206,SMT RP46
271611220301 RP;22*4 ,8P ,1/16W,5% ,0612,SMT RP45
271621472302 RP;4.7K*8,10P,1/32W,5% ,1206,SMT RP44
271571560302 RP;56*8 ,16P,1/16W,5% ,1606,SMT RP29,RP30,RP31,RP32,RP33,RP3
271611750301 RP;75*4 ,8P ,1/16W,5% ,0612,SMT RP2
345677300001 RUBBER;SILICONE RUBBER,T=1.5mm,D
371102010252 SCREW;M2L2.5,K-HEAD(+),NIB/NLK
371102010252 SCREW;M2L2.5,K-HEAD(+),NIB/NLK
340680900008 SHIELDING ASSY;COVER,8050
340680900026 SHIELDING ASSY;HDD,8050
333050000117 SHRINK TUBE;UL,600V,105'C,ID2.5*
342677000014 SMT NUT;A40M20-50,EMI STOP,LYNX MTG701,MTG702
342680900001 SMT NUT;A40M20-62,EMI STOP,8050 MTG703,MTG704
361400003021 SOLDER CREAM;NOCLEAN,P4020870980
361200003047 SOLDER PASTE;NO CLEAN,RMA,CK3000
365350000003 SOLDER WIRE;0.8MM,SN43/PB43/BI14
600100010009 SOLDER WIRE;63/37,0.8,CM,N/C,PRC
341680900001 SPC SCREW;#4-1/4,8050
370102010502 SPC-SCREW;M2 L5,NIB,K-HD,t 0.8,NL
370102611601 SPC-SCREW;M2.6*L16,NIB,K-HD
370102610401 SPC-SCREW;M2.6L4,K-HD,t 0.8,NIB/N
370102610401 SPC-SCREW;M2.6L4,K-HD,t 0.8,NIB/N
370102610603 SPC-SCREW;M2.6L6,K-HD,NIB/NLK
370102610603 SPC-SCREW;M2.6L6,K-HD,NIB/NLK
370102010201 SPC-SCREW;M2L2,NIW,K-HD,t =0.8,NL
370102030301 SPC-SCREW;M2L3,K-HD,1,NIB/NLK
370102030301 SPC-SCREW;M2L3,K-HD,1,NIB/NLK
370102010303 SPC-SCREW;M2L3,NIW,K-HD(+),NYLOK
370102010409 SPC-SCREW;M2L4,K-HD(t 0.3),NIB/NL
370102010409 SPC-SCREW;M2L4,K-HD(t 0.3),NIB/NL
8050
8050
N/B Maintenance
N/B Maintenance
140
370103010405 SPC-SCREW;M3L4,NIW,K-HD,T0.3
340680900002 SPEAKER ASSY;L,8050
340680900003 SPEAKER ASSY;R,8050
340680900001 SPEAKER ASSY;WOOFER,8050
226600030332 SPONGE;320*290*10,CAIMAN,PWR
346677000016 SPONGE;RTC,LYNX
341677000002 SPRING;SCREW,HEATSINK,LYNX
523408610018 SUPER COMBO DRIVE;UJ-815B,PANASO
297140200003 SW;COVER SWITCH,0.1A,30V,4P,T-ME SW1
297004010001 SW;PUSH BUTTOM,5P,SPST,12VDC,50m SW2,SW4,SW5
225600000061 TAPE;ADHENSIVE,DOUBLE-FACE,W20,U
225600000054 TAPE;INSULATING,POLYESTER FILM,1
310111103029 THERMISTOR;10K,1%,BN35-3H103F,18 RT1
442680900051 TOUCHPAD MODULE;SYNAPTICS,TM42PU
288227002006 TRANS;2N7002LT1,N-CHANNEL FET,ES PQ1,PQ12,PQ14,PQ16,PQ17,PQ1
288204406001 TRANS;AO4406,N-MOS,.0165OHM,SO8 PU10,PU9
288204407001 TRANS;AO4407,P-MOS,.01OHM,SO8,SM PQ701,PQ704,PQ707
288204409001 TRANS;AO4409,P-MOSFET,SO-8P,MSL, Q3,Q5
288204410010 TRANS;AO4410,N-MOSFET,ID=18A,0.0 PU11,PU12,PU13
288204900001 TRANS;AO4900,DUAL N-MOSFET WITH PU4,PU6,PU702,PU705,PU707,PU
288204914001 TRANS;AO4914,DUAL N-MOSFET,WITH PU701
288200144008 TRANS;DTA144EKA,PNP,SMT Q1
288204435003 TRANS;FDS4435,P-MOSFET,35mOHM,SO Q9,U704,U707
288200301001 TRANS;FDV301N,N-CHANNEL,SOT23 Q42
288202222019 TRANS;MMBT2222ALT1,NPN,TO236AB,O PQ15
288203904022 TRANS;MMBT3904L,NPN,Tr35NS,TO236 PQ10,PQ9,Q20,Q708,Q718
288221371002 TRANS;MUN2137T1,PNP,SMT,ON PQ13,Q711
288202215001 TRANS;MUN2215T1,N-MOSFET,SC59,SM Q719,Q720
288202237002 TRANS;MUN2237T1,NPN,SOT-23,SMT,O PQ24,Q47
288202240001 TRANS;MUN2240T1,NPN,SOT-23,ON Q12,Q23,Q26,Q27,Q29,Q31,Q32,Q
288202301001 TRANS;SI2301DS,P-MOSFET,SOT-23 Q13,Q14,Q24,Q43,Q48,Q51
288204800001 TRANS;SI4800DY,N-MOS,.0185OHM,SO U7
273001050069 TRANSFORMER;10/100 BASE,NS0013,S
332110020165 WIRE ;#20AWG,UL1007,L=160mm,RED, CN1
332110020173 WIRE ;#20AWG,UL1007,L=256mm,BLAC CN4
332110026151 WIRE ;#26AWG,UL1007,L=142mm,YELL CN3
332110026150 WIRE ;#26AWG,UL1007,L=208mm,BLUE CN2
422677000008 WIRE ASSY;BATT TO MB,FOR LYNX,MO J710
340680900028 WIRE ASSY;INVERTER,8050
422674300071 WIRE ASSY;MDC,E-NOTE
422680900003 WIRE CABLE;SAM LTN154X1,8050
340680900027 WLEN ASSY;CABLE,8050
273001050160 XFMR;CI8.5,25T/2150T,300mH,ONLY T1
273001050039 XSFORMER;10/100 BASE,LF-H80P,SMT U717
274011431414 XTAL;14.318MHZ,32PF,50PPM,8*4.5, X701,X703
274012457406 XTAL;24.576MHZ,16PF,50PPM,8*4.5, X707
274012500415 XTAL;25MHZ,20PF,30PPM,8.0*4.5,SM X706
274013276103 XTAL;32.768KHZ,20PPM,12.5PF,CM20 X704
274010800405 XTAL;8Mhz,30PPM,16PF,8*4.5,2P,SM X1
P/N: 526268090006
PDF created with FinePrint pdfFactory trial version http://www.fineprint.com
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PAGE 8 VGA-M10(2/4)
PAGE26 +2.5VS_DDR_P/+1.25V_DDR_P
PRODUCT CODE- 6809
PAGE24 PULL HIGH
PAGE 9 VGA-M10 (3/4)
PAGE18 IEEE1394
PAGE 7 VGA-M10(1/4)
PAGE17 R5C811/841
PROJECT CODE- G095
PAGE 2 CPU- BANIAS(1/2)
PCB P/N 316680900001
PAGE22 KBC(W83L950D)
PAGE11 CLOCK SYNTHERIZER/TV ENCODER
PAGE23 TOUCHP_PAD/FWH/LED
PAGE12 CRT/LCD
PAGE19 MINI-PCI
PAGE20 AUDIO CODEC(ALC655)
PAGE10 VGA-M10(4/4)
PAGE 6 DDR-DIMM
PAGE15 CDROM/HDD/USB CONNECTOR
PAGE21 AUDIO AMPLIFIER/SUBWOOFER
PAGE25 PERPHERIAL
PAGE14 SOUTHBRIDGE-ICH4-M(2/2)
8050 R01
PAGE 1 TITLE
PAGE 5 NB-MONTARA-GME(2/2)
PAGE13 SOUTHBRIDGE-ICH4-M(1/2)
PAGE 3 CPU-BANIAS(2/2)
PAGE16 LAN RTL8100CL
ASSY P/N 411680900011
PAGE 4 NB-MONTARA-GME(1/2)
LAN PCI_INTE#
TAPEOUT DAY
CARDBUS /
CARDREADER
AD18
2003/8/26
HISTORY
PCI_REQ3# /
PCI_GNT3#
INTERRUPT
REVISION
R00 PCI DEVICE
PCI_INTB# /
PCI_INTC#
REQ/GNT
AD20
IDSEL
ISSUES CHECK DESIGN DRAWN

AD21 PCI_INTG# IEEE1394
AD17 MINIPCI
PCI_REQ0# /
PCI_GNT0#
PCI_REQ1# /
PCI_GNT1#
PCI_INTD# PCI_REQ2# /
PCI_GNT2#
MDC
CARDREADER
CPU
PAGE27 +3VS_P/+5VS_P
PAGE30 +1.2V/1.0V_M10
PAGE28 +1.5V_P/+1.05V_P
PAGE33 CHARGER/DISCHARGER
PAGE31 CPUCORE
PAGE29 +1.8V_P/1.35V_P
PAGE32 ADAPTER/VMAIN
R0A 2003/10/09
CHANGE MDC AND MINIPCI CONNECTORS PLACEMENT FROM
SOLDER SIDE TO COMPONENT SIDE
4. CHANGE CARDBUS CONNENTOR PLACEMENT FORM
COMPONENT SIDE TO SOLDER SIDE
CHANGE LVDS ROUTING FAR AWAY POWER SWITCHING
SIGNALS
6.
3.
2. USE IEEE1394 CONTROLLER VT6307 INSTEAD OF
R5C592
ADD SPDIF FUNCTION
5.
CHANGE CARDBUS/CARD READER CONTROLLER FROM
R5C592 TO CB710
EMI
2003/11/07 R0B
1.
1. CHANGE TV CONNECTOR
EC
R01 2003/12/16
2. CHANGE BATTERY CONNECTOR
1. EXCHANGE TV CONNECTOR PIN 6 AND PIN 7
2. ADD SPREAD SPECTRUM CIRCUIT BUT RESERVE
3. ADD POWER CONSUMPTION SAVING CIRCUIT BUT RESERVE
ESD
8050N
PCB 316680900001/ASSY 411680900011 R01
8050 MOTHERB/D
C
1 34 Monday, December 29, 2003
Title
Size
Document
Number
Rev
Date: Sheet of
GND GND_45 GND
GND_45 GND GND
1394_GND
GND GND GND
GND GND
GND GND
GND GND
GND
CHAGND
CAGND
AGND
GND
GND
GND
GND
GND
GND GND GND GND
GND GND GND GND
GND
GND
+5V +3V
+5V +3V
+1.35V
GND
GND
GND
GND
+2.5V_M10
GND_USB 1394_GND
GND GND
TP46
TOUCHPAD_METAL10
1
MTG2
ID3.0/OD11
MTG118-RD433-N-30X16
4
5
6
7
9 1
0
1 2 3
8
1
1
12
13
14
15
16
TP4
TOUCHPAD_METAL5
1
FD703
FIDUCIAL-MARK
1
FD2
FIDUCIAL-MARK
1
TP44
TOUCHPAD_METAL10
1
MTG13
ID3.0/OD11
MTG118-RD433-N-30X16
4
5
6
7
9 1
0
1 2 3
8
1
1
12
13
14
15
16
MTG1
ID3.0/OD11
MTG118NRD433_3016B
4
5
6
7
9 1
0
1 2 3
8
1
1
12
13
14
15
16
TP52
TOUCHPAD_METAL10
1
MTG32
ID5.3/OD7.5
1
TP48
TOUCHPAD_METAL10
1
TP45
TOUCHPAD_METAL10
1
MTG3
ID3.0/OD9.0
MTG118-RD354-N-30X12
4
5
6
7 9
10
1 2 3
8
11
12
FD701
FIDUCIAL-MARK
1
MTG28
ID5.3/OD7.5
1
C1007
1000P
0402 50V
+/-20%
1 2
FD1
FIDUCIAL-MARK
1
MTG14
ID3.0/OD11
MTG118NRD433_3016B
4
5
6
7
9 1
0
1 2 3
8
1
1
12
13
14
15
16
MTG701
MTG/ID1.2/OD4.6
342677000014
1
MTG12
ID5.3/OD7.5
1
MTG22
ID2.8/OD11
1
MTG24
ID5.3/OD7.5
1
MTG9
ID3.0/OD11
MTG118-RD433-N-30X16
4
5
6
7
9 1
0
1 2 3
8
1
1
12
13
14
15
16
MTG7
ID3.0/OD11
MTG118NRD433_3016A
4
5
6
7
9 1
0
1 2 3
8
1
1
12
13
14
15
16
MTG703
MTG/ID1.2/OD4.6
1
MTG10
ID2.8/OD11
1
MTG4
ID3.0/OD11
MTG118-RD433-N-30X16
4
5
6
7
9 1
0
1 2 3
8
1
1
12
13
14
15
16
FD4
FIDUCIAL-MARK
1
C357
1000P
0402 50V
+/-20%
1 2
C1006
1000P
0402 50V
+/-20%
1 2
MTG31
ID3.0/OD8.0/CP7.5X9.5
1
MTG704
MTG/ID1.2/OD4.6
1
MTG702
MTG/ID1.2/OD4.6
342677000014
1
MTG15
ID3.0/OD9.0
MTG118-RD354-N-30X12
4
5
6
7 9
10
1 2 3
8
11
12
MTG8
ID3.0/OD11
MTG118NRD433_3016A
4
5
6
7
9 1
0
1 2 3
8
1
1
12
13
14
15
16
FD3
FIDUCIAL-MARK
1
TP723
TOUCHPAD_METAL10
1
C1008
1000P
0402 50V
+/-20%
1 2
MTG6
ID3.0/OD9.0
MTG118-RD354-N-30X12
4
5
6
7 9
10
1 2 3
8
11
12
TP51
TOUCHPAD_METAL10
1
TP722
TOUCHPAD_METAL10
1
TP59
RD080_051/NA
1
TP42
TOUCHPAD_METAL10
1
TP47
TOUCHPAD_METAL10
1
MTG27
ID5.3/OD7.5
1
TP58
RD080_051/NA
1
MTG11
ID3.0/OD11
MTG118NRD433_3016A
4
5
6
7
9 1
0
1 2 3
8
1
1
12
13
14
15
16
TP3
TOUCHPAD_METAL5
1
FD702
FIDUCIAL-MARK
1
MTG5
ID3.0/OD9.0
1
JS702
SHORT-SMT4
1 2
TP50
TOUCHPAD_METAL10
1
FD704
FIDUCIAL-MARK
1
TP43
TOUCHPAD_METAL10
1
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
VCCP : PROCESSOR I/O POWER SUPPLY.
Close to CPU as possible. < 0.5"
VCC : PROCESSOR CORE POWER SUPPLY.
VCCA : ISOLATE POWER FOR INTERNAL PLL.
VCCQ : QUIET POWER SUPPLY FOR ON DIE COMP CKT.
HCOMP1 & HCOMP3 should be
route with 5 mil width
1.8V, 0.6A, 10uF and 10nF each VCCA pin.
1.5V for future support.
PLACEMENT MAX. 3" FROM CPU.
Don't overlay by CHOKE or vibrating signals.
HCOMP0 & HCOMP2 should be
Close to CPU as possible.
CPU-BANIAS (1/2)
Place close to CPU socket within 2".
PCB 316680900001/ASSY 411680900011 R01
8050 MOTHERB/D
C
Title
Size
Document
Number
Rev
Date: Sheet of
HDINV#[0..3]
HDSTBN#[0..3]
HRS#[0..2]
HD#[0..63]
HDSTBP#[0..3]
HREQ#[0..4]
HA#[3..31]
HD#5
HA#10
HA#20
HDSTBN#0
HSMI#
HD#12
HTRST#
HD#46
HD#16
HD#13
HA#14
HREQ#0
HD#18
HD#2
HA#16
HD#60
HA#28
HCOMP0
HDBR# HD#59
HD#42
HD#33
HD#62
HDSTBP#2
HD#38
CPU_TEST2
HD#4 HA#7
HD#11
HA#22
HDSTBN#1
HPWRGD
HD#14
HD#55
CPU_THERMDA
HBR0#
HPREQ#
HD#34
HA#19
HREQ#4
HD#29
HD#27
HPWRGD
HD#9
HDINV#2
HSLP#
HRS#1 HD#53
HD#22
HD#50
HA#30
CPU_TEST3
HTCLK
HA#18
HA#4
HA#27
HDSTBN#2
HA#26
HD#21
HD#25
HD#51
HD#40
HRS#0
HD#39
HD#45
HREQ#3
HCOMP1
HDSTBP#3
HDPSLP#
HD#6
HD#20
HPROCHOT#
HTDI
CPU_THERMDC
HPRDY#
HD#8
HDINV#3
HD#58
HRS#2
HD#61
HD#3
HA#9
HA#25
HDSTBN#3
HA#31
HA#15
HD#26
HD#35
HBPM#0
HREQ#2
HCOMP3
HA#23
HINTR
HA#5
HD#28
HSTPCLK#
HD#17
HTDO
HDINV#0
HD#63
HD#57
HINIT#
HD#36
HD#19
HD#10 HA#13
HD#56
HBPM#1
HPSI#
HA20M#
HDSTBP#0
HD#52
HD#1
HA#24
HD#43
HD#24
HBR0#
HD#47
HREQ#1
HD#7
HA#8
HCOMP2
HA#21
HNMI
HIGNNE#
HD#23
HA#29
CPU_TEST1
HTMS
HDINV#1
HD#31
HD#15
HA#12
HA#3
HD#30
HA#6
HD#0
HA#11
HD#48
HD#54
HD#37
HD#44
HD#41
HD#49
HDSTBP#1
HD#32
HA#17
HA20M#
HINIT#
HSTPCLK#
HIGNNE#
HSLP#
HINTR
HDPSLP#
HDBR#
HSMI#
HNMI
HCOMP3
CPU_TEST2
CPU_TEST3
HCOMP2
CPU_TEST1
HCOMP1
HCOMP0
HPROCHOT#
HTDO
HPRDY#
HBPM#1
HTDI
HPREQ#
HTMS
HBPM#0
HTRST#
HTCLK
HA#[3..31] 4 HD#[0..63] 4
HREQ#[0..4] 4
HADS# 4
HADSTB#0 4
HADSTB#1 4
HBR0# 4
HBPRI# 4
HBNR# 4
HLOCK# 4
HHIT# 4
HHITM# 4
HDEFER# 4
HTRDY# 4
HRS#[0..2] 4
HA20M# 13
HFERR# 14
HDPWR# 4
HSLP# 13
HIGNNE# 13
HSMI# 13
HPWRGD 13
HSTPCLK# 13
HDPSLP# 4,13
HINTR 13
HNMI 13
HINIT# 13,23
HCPURST# 4
CLK_ITP_CPU 11
CLK_ITP_CPU# 11
HDSTBN#[0..3] 4
HDSTBP#[0..3] 4
HDBSY# 4
HDRDY# 4
CPU_THRMTRIP_OUT# 14
HCLK_CPU 11
HCLK_CPU# 11
HDINV#[0..3] 4
HCPURST# 4
CPU_THERMDA 22
CPU_THERMDC 22
HPROCHOT# 22
PM_PS 31
+VCC_CORE
+VCCP
+VCC_CORE
+VCC_CORE
GND
+VCCP
+VCCP
+1.5V +VCCA
GND
+1.8V
+3V
+VCCP
GND
GND
+VCCP
GND
+VCCP
GND
+VCC_CORE
R124 0/NA 0805
1 2
R214
680
0402
5%
1
2
U713A
BANIAS
BGA479_SKT3
P4
U4
V3
R3
V2
W1
T4
W2
Y4
Y1
U1
AA3
Y3
AA2
AF4
AC4
AC7
AC3
AD3
AE4
AD2
AB4
AC6
AD5
AE2
AD6
AF3
AE1
AF1
R2
P3
T2
P1
T1
U3
N2
AE5
A4
A19
A25
A22
B21
A24
B26
A21
B20
C20
B24
D24
E24
C26
B23
E23
C25
H23
G25
L23
M26
H24
F25
G24
J23
M23
J25
L26
N24
M25
H26
N25
K25
Y26
AA24
T25
U23
V23
R24
R26
R23
AA23
U26
V24
U25
V26
Y23
AA26
Y25
AB25
AC23
AB24
AC20
AC22
AC25
AD23
AE22
AF23
AD24
AF20
AE21
AD21
AF25
AF22
AF26
C23
K24
W25
AE24
C22
L24
W24
AE25
M2
H2
B18
A18
A7
B5
B11
D1
D4
C6
B7
C2
D3
A3
B4
E4
H1
K1
L2
M3
K3
K4
L4
N4
J3
L1
J2
C19
B17
E1
A6
C17
A16
A15
A3#
A4#
A5#
A6#
A7#
A8#
A9#
A10#
A11#
A12#
A13#
A14#
A15#
A16#
A17#
A18#
A19#
A20#
A21#
A22#
A23#
A24#
A25#
A26#
A27#
A28#
A29#
A30#
A31#
REQ0#
REQ1#
REQ2#
REQ3#
REQ4#
ADSTB0#
ADS#
ADSTB1#
IERR#
D0#
D1#
D2#
D3#
D4#
D5#
D6#
D7#
D8#
D9#
D10#
D11#
D12#
D13#
D14#
D15#
D16#
D17#
D18#
D19#
D20#
D21#
D22#
D23#
D24#
D25#
D26#
D27#
D28#
D29#
D30#
D31#
D32#
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D40#
D41#
D42#
D43#
D44#
D45#
D46#
D47#
D48#
D49#
D50#
D51#
D52#
D53#
D54#
D55#
D56#
D57#
D58#
D59#
D60#
D61#
D62#
D63#
DSTBN0#
DSTBN1#
DSTBN2#
DSTBN3#
DSTBP0#
DSTBP1#
DSTBP2#
DSTBP3#
DBSY#
DRDY#
THERMDA
THERMDC
DBR#
INIT#
RESET#
LINT0
LINT1
STPCLK#
DPSLP#
A20M#
FERR#
IGNNE#
SMI#
PWRGOOD
RS0#
RS1#
RS2#
TRDY#
HIT#
HITM#
DEFER#
BR0#
BPRI#
BNR#
LOCK#
DPWR#
PROCHOT#
PSI#
SLP#
THERMTRIP#
ITP_CLK0
ITP_CLK1
C161
2.2U
0603
+/-10%
1
2
R142 54.9 0402 1%
1 2
C165
220P
0402
50V
10%
1
2
R225
39
0402
1%
1
2
R133 27.4 0402 1%
1 2
C163
0.1U
0402
10%
1
2
R246 10K/NA 0402 5%
1 2
R123 0 0805
1 2
R293 200/NA 0402 5%
1 2
R242 0 0402 1 2
R141
1K
0402
1%
1
2
R204 1K/NA 0402 5%
1 2
R289
51
0402
5%
1
2
R134
2K
0402
1%
1
2
R294 200/NA 0402 5%
1 2
R256 200/NA 0402 5%
1 2
R265 200/NA 0402 5%
1 2
R247 200/NA 0402 5%
1 2
R224
51
0402
5%
1
2
C317
0.1U
0402
10%
1
2
C322
2.2U
0603
+/-10%
1
2
C162
0.1U
0402
10%
1
2
R143 1K/NA 0402 5%
1 2
R237 0 0402 1 2
R229
51/NA
0402
5%
1
2
R249 200/NA 0402 5%
1 2
R301
330
0402
5%
1
2
R243
51
0402
5%
1
2
R198
56
0402
5%
1
2
R248 200/NA 0402 5%
1 2
R291 27.4 0402 1%
1 2
U713B
BANIAS
BGA479_SKT3
D6
D8
D18
D20
D22
E5
E7
E9
E17
E19
E21
F6
F8
F18
F20
F22
G5
G21
H6
H22
J5
J21
K22
U5
V6
V22
W5
W21
Y6
Y22
AA5
AA7
AA9
AA11
AA13
AA15
AA17
AA19
AA21
AB6
AB8
AB10
AB12
AB14
AB16
AB18
AB20
AB22
AC9
AC11
AC13
AC15
AC17
AC19
AD8
AD10
AD12
AD14
AD16
AD18
AE9
B15
B14
AC1
A9
C9
B8
C8
A13
C12
A12
C11
B13
B10
A10
AD26
E26
G1
AF7
C14
C3
C5
F23
C16
P25
P26
AB2
AB1
D25
J26
T24
AD20
AE11
AE13
AE15
AE17
AE19
AF8
AF10
AF12
AF14
AF16
AF18
VCC_0
VCC_1
VCC_2
VCC_3
VCC_4
VCC_5
VCC_6
VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12
VCC_13
VCC_14
VCC_15
VCC_16
VCC_17
VCC_18
VCC_19
VCC_20
VCC_21
VCC_22
VCC_23
VCC_24
VCC_25
VCC_26
VCC_27
VCC_28
VCC_29
VCC_30
VCC_31
VCC_32
VCC_33
VCC_34
VCC_35
VCC_36
VCC_37
VCC_38
VCC_39
VCC_40
VCC_41
VCC_42
VCC_43
VCC_44
VCC_45
VCC_46
VCC_47
VCC_48
VCC_49
VCC_50
VCC_51
VCC_52
VCC_53
VCC_54
VCC_55
VCC_56
VCC_57
VCC_58
VCC_59
VCC_60
BCLK0
BCLK1
GTLREF3
BPM2#
BPM3#
BPM1#
BPM0#
TCK
TDI
TDO
TMS
TRST#
PREQ#
PRDY#
GTLREF0
GTLREF1
GTLREF2
RSVD_0
RSVD_2
RSVD_3
TEST1
TEST2
TEST3
COMP0
COMP1
COMP2
COMP3
DINV0#
DINV1#
DINV2#
DINV3#
VCC_61
VCC_62
VCC_63
VCC_64
VCC_65
VCC_66
VCC_67
VCC_68
VCC_69
VCC_70
VCC_71
R228
51
0402
5%
1
2
R302 200/NA 0402 5%
1 2
C323
2.2U
0603
+/-10%
1
2
C316
0.1U
0402
10%
1
2
R292 0/NA5%
1 2
R268 200/NA 0402 5%
1 2
R300 54.9 0402 1%
1 2
R220
150
0402
1%
1
2
R264 56 0402
5%
1 2
R213
27.4
0402
1%
1
2
C151
2.2U
0603
+/-10%
1
2
R219
51/NA
0402
5%
1
2
R238
51
0402
5%
1
2
R255 1K/NA 0402 5%
1 2
C160
1U
0402
10V
+80-20%
1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
1.05V, 2.4A
0.844V ~ 1.356V, 32A
CPU-BANIAS (2/2)
(1.05V)
1
0
1.004
1
1
0
1
0
1
1
0
1
0
0
1.548
1
0
0
1
0
1.660
1
0
0.924
0
1
0
1
0
1
0
1
1.164
0
0
0
1
1.612
1
0
1
0
1
0
0
0
0
1
0
0.716
1
0
0
0.780
0
0 0.876
0
1
0
1
0
0
1.580
0
1.484
1
1
0
3
0
1
0
0
1
1
0
1.532
1
1
0
1
1
0
5
0
1
1
1
1
1
1
1
1.212
0
0
0
1
0
0
1
1
0
1
1
0
0
1
0
5
0
1
0
1
0
4
0
0
1
0
0
1
1
0
0
1
1
0.940
1
0.764
0
1
0
1
0
1
1
0
1.516
1
0
1
0
0
0
0
1.596
1
1.564
1
0
0
0
1
1
1
1
0
1 1
0
0
1
0
0
0
1
0
0.908
1
1
0
1
0
0.972
0
0
1.260
1
1
1
0
0
0
1.020
1
1
0
1.356
0
1
0
0
0
2
0
0
1
1
1
0
1
0
0
0.812
0
1.388
1 1
1.116
0
0
1
1
1
0
0
1
1
1
0
1
1
0.860
1
1
1.436
1
0
1
0
1
1
1.420
1.100
1
1
1
0
1
1
0
0
0
0
0
0
1
VID VID
1
0
0
1
1.500
0
0
0
1
0
1
0
0
0
0
1.452
0
1
1.180
1
1
1
1
1
1
1
0
0
0
1
1.292
0
0
0
0
1
1.132
1.468
0
1
1
1
0
1
1
0
0
1.196
1.036
1.244
1.628
0
1
1
1
4
0
0.796
1
0
0
1
0
1
1.372
0.956
1
0
1
1.324
1
0
1
1
1
1
1
1
0
1
1
1
1
0
0
1
0.988
0
0
1
1
0.828
1.148
VCC-Core
0
0
1
1
1
0
1
1
0
1
0
0
0.732
0
0
0
0
0.700
1.676
1.228
1
1
1.068
0
0
1
1
1
0
0.844
0
1
1
0
1
1
1
1
0
0.892
1
1
0
1
0.748
1
0
0
0
1
1
1.340
1
1
0
0
1
0
0
0
1
1
0
0
0
0
0
0
0
1.276
1
1.084
1
0
0
1
0
0
1.692
1 0
0
1
1
1
1.052
0
0
1
1.644
1
0
1.308
1
0
3
1
1
1
1
0
0
1
1
1.404
0
1
VCC-Core
1
0
1
2
0
1.708
0
0
0
1
1
1
B/CB#
GPIO16
Banias
CPU
Celeron
Banias CPU
power on default = 1
1 0
POWER CONSUMPTION SAVING CIRCUIT
PCB 316680900001/ASSY 411680900011 R01
8050 MOTHERB/D
C
Title
Size
Document
Number
Rev
Date: Sheet of
VID0
VID2
VID3
VID1
VID5
VID3
VID4
VID[0..4]
VID0
VID1
VID4
VID2
CPUVID5 VID5
CPUVID5
VID[0..4] 31
STOP_CPU# 11,13,31
B/CB# 13,24
VID5 31
GND
GND
+VCCP
+VCC_CORE
GND
GND
+VCC_CORE
GND
+VCC_CORE
GND
GND
+VCC_CORE
+VCC_CORE
+VCCP
GND
+VCCA
+VCCP
+VCCQ
GND
+VCCP
GND
GND
+VCCQ +VCCP
GND
+5V
GND
+VCC_CORE
GND
GND
+1.5V
C209
10U
6.3V
0805
1
2
R193 0 1 2
R298 4.7K/NA 0402 1 2
C222
0.1U
0402
16V
10%
1
2
C248
0.1U
0402
16V
10%
1
2
C279
10U
6.3V
0805
1
2
C249
10U
6.3V
0805
1
2
C831
10U
6.3V
0805
1
2
C187
10U
6.3V
0805
1
2
C191
0.1U
0402
16V
10%
1
2
U713C
BANIAS
BGA479_SKT3
A2
A5
A8
A11
A14
A17
A20
A23
A26
B3
B6
B9
B12
B16
B19
B22
B25
C1
C4
C7
C10
C13
C15
C18
C21
C24
D2
D5
D7
D9
D11
D13
D15
D17
D19
D21
D23
D26
E3
E6
E8
E10
E12
E14
E16
E18
E20
E22
E25
F1
F4
F5
F7
F9
F11
F13
F15
F17
F19
F21
F24
G2
G6
G22
G23
G26
H3
H5
H21
H25
J1
J4
J6
J22
J24
K2
K5
K21
K23
K26
L3
L6
L22
L25
M1
M4
M5
M21
M24
N3
N6
N22
N23
N26
P2
P5
P21
P24
R1
R4
R6
R22
R25
T3
T5
T21
T23
T26
U2
U6
U22
U24
V1
V4
V5
V21
V25
W3
W6
W22
W23
W26
Y2
Y5
Y21
Y24
AA1
AA4
AA6
AA8
AA10
AA12
AA14
AA16
AA18
AA20
AA22
AA25
AB3
AB5
AB7
AB9
AB11
AB13
AB15
AB17
VSS_0
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
C175
10U
6.3V
0805
1
2
C250
10U
6.3V
0805
1
2
C183
10U
6.3V
0805
1
2
C266
0.1U
0402
16V
10%
1
2
D14
BAT54/NA
1 3
C201
0.1U
0402
16V
10%
1
2
C251
0.1U
0402
16V
10%
1
2
C296
10U
6.3V
0805
1
2
C236
0.1U
0402
16V
10%
1
2
+
C1004
220U/NA
7343
4V
1
2
RP28
4.7K*4/NA
1206
1
2
3
4
8
7
6
5
L41
120Z/100M
2012
1 2
C240
10U
6.3V
0805
1
2
C193
10U
6.3V
0805
1
2
C179
10U
6.3V
0805
1
2
C155
10U
6.3V
0805
1
2
C807
10U
6.3V
0805
1
2
C190
10U
6.3V
0805
1
2
C177
10U
6.3V
0805
1
2
C181
0.1U
0402
16V
10%
1
2
C242
0.1U
0402
16V
10%
1
2
C320
10U
6.3V
0805
1
2
C230
10U
6.3V
0805
1
2
C235
0.1U
0402
16V
10%
1
2
C199
10U
6.3V
0805
1
2
+
C1005
220U/NA
7343
4V
1
2
C188
10U
6.3V
0805
1
2
C192
10U
6.3V
0805
1
2
C195
0.1U
0402
16V
10%
1
2
U713D
BANIAS
BGA479_SKT3
AD1
AC8
AC10
AC12
AC14
AC16
AC18
AC21
AC24
E2
F2
F3
G3
G4
H4
D10
D12
D14
D16
E11
E13
E15
F10
F12
F14
F16
K6
L5
L21
M6
M22
N5
N21
P6
P22
R5
R21
T6
T22
P23
W4
AE7
F26
B1
N1
AC5
AC2
AB26
AB23
AB21
AB19
AD4
AD7
AD9
AD11
AD13
U21
AE8
AE6
AE3
AD25
AD22
AD19
AD17
AD15
AE10
AE12
AE14
AE16
AE18
AE20
AE23
AE26
AF2
AF5
AF9
AF11
AF13
AF15
AF17
AF19
AF21
AF6 AF24
AC26
VSS_160
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VID0
VID1
VID2
VID3
VID4
VID5
VCCP_0
VCCP_1
VCCP_2
VCCP_3
VCCP_4
VCCP_5
VCCP_6
VCCP_7
VCCP_8
VCCP_9
VCCP_10
VCCP_11
VCCP_12
VCCP_13
VCCP_14
VCCP_15
VCCP_16
VCCP_17
VCCP_18
VCCP_19
VCCP_20
VCCP_21
VCCP_22
VCCP_23
VCCQ0
VCCQ1
VCCSENSE
VCCA0
VCCA1
VCCA2
VSS_151
VSS_150
VSS_149
VSS_148
VSS_147
VSS_146
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VCCP_24
VSS_173
VSS_172
VSS_171
VSS_170
VSS_169
VSS_168
VSS_167
VSS_166
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSSENSE VSS_191
VCCA3
C194
0.1U
0402
16V
10%
1
2
R899 54.9 0402 1%
1 2
C254
10U
6.3V
0805
1
2
C156
10U
6.3V
0805
1
2
C256
10U
6.3V
0805
1
2
C312
10U
6.3V
0805
1
2
R885 54.9 0402 1%
1 2
C231
10U
6.3V
0805
1
2
C270
10U
6.3V
0805
1
2
+
C768
150U
7343
6.3V
1
2
C241
10U
6.3V
0805
1
2
C321
10U
6.3V
0805
1
2
C214
10U
6.3V
0805
1
2
C268
0.1U
0402
16V
10%
1
2
R299 4.7K/NA 0402 1 2
C280
0.1U
0402
16V
10%
1
2
C189
10U
6.3V
0805
1
2
D S
G
Q28
SI2301DS/NA
G
D S
C237
10U
6.3V
0805
1
2
C196
0.1U
0402
16V
10%
1
2
D
S
Q45
2N7002/NA
G
D
S
C198
10U
6.3V
0805
1
2
C157
10U
6.3V
0805
1
2
C178
0.1U
0402
16V
10%
1
2
C257
10U
6.3V
0805
1
2
C319
0.1U
0402
16V
10%
1
2
C168
10U
6.3V
0805
1
2
D S
Q16
2N7002/NA
G
D S
C258
10U
6.3V
0805
1
2
C180
10U
6.3V
0805
1
2
C203
10U
6.3V
0805
1
2
C259
0.1U
0402
16V
10%
1
2
C200
0.1U
0402
16V
10%
1
2
C185
0.1U
0402
16V
10%
1
2
R400
10K/NA
0402
5% 1
2
C204
0.1U
0402
16V
10%
1
2
C265
0.1U
0402
16V
10%
1
2
C264
10U
6.3V
0805
1
2
C158
10U
6.3V
0805
1
2
C220
10U
6.3V
0805
1
2
C182
0.1U
0402
16V
10%
1
2
C173
10U
6.3V
0805
1
2
C318
0.1U
0402
16V
10%
1
2
C267
10U
6.3V
0805
1
2
R401
1K/NA
0402
5% 1
2
C226
10U
6.3V
0805
1
2
C186
0.1U
0402
16V
10%
1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Maximum length less than
0.5" from pin to voltage
divider.
Maximum length less than 0.5" from pin to
voltage divider.
Less than 0.5"
Less than 0.5"
(1.05V)
Place near to GMCH.
Non SSC
W/ SSC HXRCOMP & HYRCOMP should be
NB-MONTARA-GME(1/2)
CHANGE TO 0402
CHANGE TO 0402
CHANGE TO 0402 CHANGE TO 0402
ADD ID : 0x7Fh
CHECK
AGPBUS
NB CONNECT TO TV ENCORDER
WHENUSEINTEGRATEVGA
ADDALLRESISTOR
M10-P CONNECT TO NB
WHENUSEINTEGRATEVGA
DELALLRESISTOR
WHENUSEINTEGRATEVGA
ADDR181
WHENUSEINTEGRATEVGA
ADD R798 DEL R857 R1104
RDDP recommend
1K ohm
resistor
WHENUSEINTEGRATEVGA
DELR206
PCB 316680900001/ASSY 411680900011 R01
8050 MOTHERB/D
C
Title
Size
Document
Number
Rev
Date: Sheet of
HA#[3..31] HD#[0..63]
HREQ#[0..4]
HDINV#[0..3]
HDSTBN#[0..3]
HDSTBP#[0..3]
HRS#[0..2]
HA#3
HA#4
HA#5
HA#6
HA#9
HA#7
HA#10
HA#8
HA#13
HA#11
HA#14
HA#12
HA#17
HA#15
HA#18
HA#16
HA#21
HA#19
HA#22
HA#20
HA#25
HA#23
HA#26
HA#24
HA#29
HA#27
HA#30
HA#28
HA#31
HD#0
HD#1
HD#3
HD#2
HD#5
HD#6
HD#4
HD#7
HD#12
HD#15
HD#14
HD#13
HD#9
HD#10
HD#8
HD#11
HD#20
HD#31
HD#23
HD#22
HD#24
HD#29
HD#21
HD#17
HD#18
HD#27
HD#28
HD#16
HD#19
HD#25
HD#30
HD#26
HD#36
HD#47
HD#39
HD#38
HD#40
HD#45
HD#37
HD#33
HD#34
HD#43
HD#44
HD#32
HD#35
HD#41
HD#46
HD#42
HD#52
HD#63
HD#55
HD#54
HD#56
HD#61
HD#53
HD#49
HD#50
HD#59
HD#60
HD#48
HD#51
HD#57
HD#62
HD#58
HREQ#0
HREQ#1
HREQ#2
HREQ#3
HREQ#4
HDINV#0
HDINV#1
HDINV#2
HDINV#3
HDSTBP#0
HDSTBP#1
HDSTBP#2
HDSTBP#3
HDSTBN#0
HDSTBN#1
HDSTBN#3
HDSTBN#2
HRS#0
HRS#1
HRS#2
HDVREF
HAVREF
HCCVREF
HAVREF HCCVREF
HXRCOMP
HXSWING
HYRCOMP
HYSWING
HXRCOMP
HYRCOMP
HXSWING HYSWING
HUB_RCOMP
REFSET
HUB_RCOMP
HUB_HI8
HUB_MCH_VREF
MCH_PSWING
HUB_HI[0..10]
HUB_HI1
HUB_HI4
HUB_HI10
HUB_HI9
855_DPMS
HUB_HI5
855_DVOCBLANK#
HUB_MCH_VREF
855_DVODETECT
HUB_HI0
HUB_HI6
MCH_PSWING
HUB_HI2
HUB_HI7
855_DVOBFLDSTL
REFSET
HUB_HI3
RCVENOUT#
RCVENIN#
855_MDVIDATA
855_DVODETECT
855_MDDCCLK
855_DVOCD5
855_DVOBCLK
855_DVOBD7
855_MI2CDATA
855_DVOCCLK
855_MDVICLK
855_ADDID5
855_ADDID6
855_ADDID0
855_ADDID3
855_ADDID2
855_DVOBCLK
855_DVOBCLK#
855_DVOBD0
855_DVOBD1
855_DVOBD2
855_DVOBD3
855_DVOBD4
855_DVOBD5
855_DVOBD6
855_DVOBD7
855_DVOBD8
855_DVODETECT
855_ADDID0
855_ADDID1
855_ADDID2
855_ADDID3
855_ADDID4
855_ADDID5
855_ADDID7
855_ADDID6
855_DVOCCLK
855_DVOCCLK#
855_DVOBCCLKINT
855_MDDCCLK
855_MDDCCDATA
855_MDVICLK
855_MDVIDATA
855_MI2CCLK
855_MI2CDATA
855_DVOCHSYNC
855_DVOCVSYNC
855_DVOBBLANK#
855_DVOBHSYNC
855_DVOBVSYNC
855_DVOCD4
855_DVOCD2
855_DVOCD8
855_DVOCD1
855_DVOCD9
855_DVOCD3
855_DVOCD6
855_DVOCD0
855_DVOCD10
855_DVOCD7
855_DVOCD5
855_DVOCD11
855_DPMS
IYAM0
IYAM1
IYAM2
IYAM3
IYAP0
IYAP1
IYAP2
IYAP3
IYBM0
IYBM1
IYBM2
IYBM3
IYBP0
IYBP1
IYBP2
IYBP3
ICLKAM
ICLKAP
ICLKBM
ICLKBP
855_CRT_BLUE
855_CRT_GREEN
855_DVOBD10
855_DVOBD11
855_MI2CCLK
855_DVOBBLANK#
855_ADDID1
855_ADDID4
855_ADDID7
855_DVOCCLK#
855_DVOBCLK#
855_DDDA
855_BLUE
855_DVOBCINTR#
855_DVOBD9
855_ADDID4
855_ADDID3
855_ADDID0
855_ADDID2
855_ADDID5
855_ADDID7
855_ADDID1
855_ADDID6
855_MDDCCDATA
855_MDVICLK
855_MDVIDATA
855_MDDCCLK
855_MI2CDATA
855_DVOCD5
855_DVOBCCLKINT
855_DVOBCINTR#
855_DVOCD10
855_DVOCD2
855_DVOCD8
855_DVOCCLK#
855_DVOCD0
855_DVOCD1
855_DVOCFLDSTL
855_DVOCD11
855_DVOCD4
855_DVOCCLK
855_DVOCD7
855_DVOCVSYNC
855_DVOCHSYNC
855_DVOCD3
855_DVOCD6
855_MI2CCLK
855_DVOCD9
855_DVOCVSYNC AGP_AD16
AGP_AD11 855_DVOBD11
AGP_AD7 855_DVOBD4
AGP_AD4 855_DVOBD3
AGP_AD26 855_DVOCD9
AGP_AD24 855_DVOCD7
DVOCD4
855_DVOCD1 AGP_AD20
855_DVOBFLDSTL AGP_AD14
855_DVOBD1 AGP_AD2
AGP_AD19 855_DVOCD0
AGP_AD10 855_DVOBD8
855_DVOBD6 AGP_AD8
855_DVOCD10 AGP_AD29
DVOCD5
DVOCD7
DVOCD0
AGP_AD23 855_DVOCD4
AGP_AD22 855_DVOCD3
AGP_AD3 855_DVOBD0
AGP_AD30 855_DVOBCINTR#
AGP_AD1 855_DVOBVSYNC
855_DVOCHSYNC AGP_AD17
AGP_AD5 855_DVOBD2
DVOCD11
AGP_AD28 855_DVOCD11
855_DVOCD6 AGP_AD25
DVOCD6
DVOCD9
AGP_AD[0..31]
855_MDDCCDATA AGP_AD15
AGP_AD13 855_DVOBCCLKINT
855_DVOBD5 AGP_AD6
AGP_AD21 855_DVOCD2
855_DVOCFLDSTL
DVOCD[0..11]
AGP_AD0 855_DVOBHSYNC
855_DVOCD8 AGP_AD27
DVOCD1
DVOCD2
DVOCD10
AGP_AD12 855_DVOBD10
DVOCD8
AGP_AD31 855_DVOCFLDSTL
AGP_AD9 855_DVOBD9
AGP_AD18 855_DVOCBLANK#
DVOCD3
DVOVREF
DVOVREF
DVOVREF
855_MI2CCLK
855_MI2CDATA
IYAM3
IYAM1
IYAP1
IYAP0
IYAP3
IYAM2
IYAP2
IYAM0
ICLKAM
ICLKAP
855_RED
855_GREEN
855_HSYNC
855_VSYNC
855_CRT_RED
855_CRT_DDCK
855_CRT_DDDA
855_DDCK
855_DDDA
855_DDCK
855_BLUE
855_RED
855_GREEN
855_CRT_VSYNC
855_CRT_HSYNC 855_HSYNC
855_VSYNC
HA#[3..31] 2
HREQ#[0..4] 2
HADSTB#0 2
HADSTB#1 2
HDSTBP#[0..3] 2
HDSTBN#[0..3] 2
HDINV#[0..3] 2
HADS# 2
HTRDY# 2
HDRDY# 2
HDEFER# 2
HHITM# 2
HLOCK# 2
HHIT# 2
HBR0# 2
HBNR# 2
HDBSY# 2
HBPRI# 2
HRS#[0..2] 2
HCPURST# 2
PWROK 12,13,17,25,31
HD#[0..63] 2
DVOVREF 11
HDPWR# 2
HDPSLP# 2,13
HUB_STB 14
AGPBUSY# 7,13,24
48M_DREFCLK 11
HUB_HI[0..10] 14
HUB_STB# 14
HCLK_MCH 11
66M_MCH 11
MCH_PCIRST# 13
HCLK_MCH# 11
BLADJ 12,22
FPVDEN 12
ENABKL_NB 12
AGP_CBE#1 7
AGP_TRDY# 7
AGP_ADSTB0 7
AGP_STOP# 7
AGP_FRAME# 7
AGP_DEVSEL# 7
AGP_CBE#0 7
AGP_ADSTB1 7
AGP_PAR 7
AGP_CBE#3 7
AGP_CBE#2 5,7
AGP_IRDY# 7
AGP_SBA0 7
AGP_SBA6 7
AGP_SBA4 7
AGP_SBA1 7
AGP_SBA2 7
AGP_SBA5 7
AGP_SBA3 7
SUSCLK 13
TXCLK+ 12
TXCLK- 12
GCBE2# 5,7
GSBSTB# 5,7
GSBSTB 5,7
GWBF# 5,7
GRBF# 5,7
GST0 5,7
GST1 5,7
GST2 5,7
AGP_SBA7 7
AGP_SBSTBS 5,7
AGP_SBSTBF 5,7
AGP_WBF# 5,7
AGP_RBF# 5,7
AGP_ST0 5,7
AGP_ST1 5,7
AGP_ST2 5,7
GGNT# 5,7
GREQ# 5,7
AGP_GNT# 5,7
AGP_REQ# 5,7
TXOUT3-_ATI 7
TXOUT2+_ATI 7
TXOUT0+_ATI 7
TXOUT1+_ATI 7
TXOUT3+_ATI 7
TXOUT0-_ATI 7
TXOUT2-_ATI 7
TXOUT1-_ATI 7
AGP_ADSTB0# 7
AGP_ADSTB1# 7
AGP_AD[0..31] 7,24
AGP_VREF 7
POUT/DET# 11
DVOCCLK 11
MI2CCLK 11
DVOCVSYNC 11
DVOBCINTR# 11
DVOCCLK# 11
DVOCFLDSTL 11
MI2CDATA 11
DVOCHSYNC 11
DVOCD[0..11] 11
TXOUT3- 12
TXOUT0- 12
TXOUT1+ 12
TXOUT2- 12
TXOUT2+ 12
TXOUT3+ 12
TXOUT0+ 12
TXOUT1- 12
TXCLK-_ATI 7
TXCLK+_ATI 7
855_CRT_RED 12
855_CRT_BLUE 12
855_CRT_GREEN 12
855_CRT_DDCK 12
855_CRT_DDDA 12
855_CRT_HSYNC 12
855_CRT_VSYNC 12
66M_DEFSSCLK 11
+VCCP
GND
GND
+VCCP
GND
+VCCP
GND
GND
+VCCP +VCCP
GND
+1.35V
GND
+1.35V
+1.35V
GND
GND
GND
+3V
GND
+3V
GND
GND
+3V
GND
GND
+1.5V
GND
GND GND
+1.5V
+1.5V
+1.5V
+1.5V
GND
+1.5V
+1.5V
+1.5V
GND
R203 0 0402 1 2
TP21 1
R188 330/NA 0402 1 2
R156
0
0402
1 2
C837
1U/NA
0402
10V
+80-20%
1
2
R209
49.9
0402
1%
1
2
R1103 10K 0402 1 2
R202 0/NA 0402 1 2
R144
75
0402
1%
1
2
C286
1U/NA
0402
10V
+80-20%
1
2
R800 10K 0402 1 2
R148 0 0402 1 2
R113 0 0402 1 2
R353 0 0402 1 2
R903
68.1
0603
1%
1
2
R157 0 0402 1 2
R795 0/NA 0402 1 2
R130 0 0402 1 2
R361 0 0402 1 2
C844
0.1U
0402
50V
+80-20%
1
2
TP32 1
R168 8.2K/NA 0402 1 2
R1178 0 0402 1 2
C287
0.1U
0402
50V
+80-20%
1
2
R801 0 0402 1 2
R789 0 0402 1 2
R344 0 0402 1 2
C843
0.01U/NA
0402
50V
+80-20%
1
2
C840
0.1U
0402
50V
+80-20%
1
2
R832
40.2 0402 1 2
C842
1U
0402
10V
+80-20%
1
2
R792 27.4
1 2
R189 8.2K/NA 0402 1 2
R181 1K 0402 1 2
R155
1K
0402
5%
1
2
TP31 1
R235 10K 04021 2
R147 0 0402 1 2
U714B
855GM/GME
BGA707_25
N27
N28
P27
M25
B20
B18
H28
K28
J11
K22
H27
K25
L24
J27
G28
L27
L23
L25
J24
H25
K23
G27
K26
J23
H26
F25
F26
B27
H23
E27
G25
F28
D27
G24
C28
B26
G22
C26
E26
G23
B28
B21
G21
C24
C23
D22
C25
E24
D24
G20
E23
B22
B23
F23
F21
C20
C21
G18
E19
E20
G17
D20
F19
C19
C17
F17
B19
G16
E16
C16
E17
D16
C18
P23
T25
T28
R27
U23
U24
R24
U28
V28
U27
T27
V27
U25
V26
Y24
V25
V23
W25
Y25
AA27
W24
W23
W27
Y27
AA28
W28
AB27
Y26
AB28
R28
P25
R23
R25
T23
T26
AA26
J28
C27
E22
D18
K27
D26
E21
E18
K21
J21
J17
Y22
Y28
J25
E25
B25
G19
N23
P26
M27
L28
N25
P28
M23
F15
M26
M28
N24
HIT#
HITM#
HLOCK#
HTRDY#
HXRCOMP
HXSWING
HYRCOMP
HYSWING
PWROK
HD[0]#
HD[1]#
HD[2]#
HD[3]#
HD[4]#
HD[5]#
HD[6]#
HD[7]#
HD[8]#
HD[9]#
HD[10]#
HD[11]#
HD[12]#
HD[13]#
HD[14]#
HD[15]#
HD[16]#
HD[17]#
HD[18]#
HD[19]#
HD[20]#
HD[21]#
HD[22]#
HD[23]#
HD24]#
HD[25]#
HD[26]#
HD[27]#
HD[28]#
HD[29]#
HD[30]#
HD[31]#
HD[32]#
HD[33]#
HD[34]#
HD[35]#
HD[36]#
HD[37]#
HD[38]#
HD[39]#
HD[40]#
HD[41]#
HD[42]#
HD[43]#
HD[44]#
HD[45]#
HD[46]#
HD[47]#
HD[48]#
HD[49]#
HD[50]#
HD[51]#
HD[52]#
HD[53]#
HD[54]#
HD[55]#
HD[56]#
HD[57]#
HD[58]#
HD[59]#
HD[60]#
HD[61]#
HD[62]#
HD[63]#
HA[3]#
HA[4]#
HA[5]#
HA[6]#
HA[7]#
HA[8]#
HA[9]#
HA[10]#
HA[11]#
HA[12]#
HA[13]#
HA[14]#
HA[15]#
HA[16]#
HA[17]#
HA[18]#
HA[19]#
HA[20]#
HA[21]#
HA[22]#
HA[23]#
HA[24]#
HA[25]#
HA[26]#
HA[27]#
HA[28]#
HA[29]#
HA[30]#
HA[31]#
HREQ[0]#
HREQ[1]#
HREQ[2]#
HREQ[3]#
HREQ[4]#
HADSTB[0]#
HADSTB[1]#
HDSTBN[0]#
HDSTBN[1]#
HDSTBN[2]#
HDSTBN[3]#
HDSTBP[0]#
HDSTBP[1]#
HDSTBP[2]#
HDSTBP[3]#
HDVREF[0]
HDVREF[1]
HDVREF[2]
HAVREF
HCCVREF
DINV[0]#
DINV[1]#
DINV[2]#
DINV[3]#
RS[0]#
RS[1]#
RS[2]#
ADS#
BNR#
BPRI#
BREQ0#
CPURST#
DBSY#
DEFER#
DRDY#
R114 0 0402 1 2
R112 0 0402 1 2
R210 10K/NA 04021 2
R784
75
0402
1%
1
2
R145
75
0402
1%
1
2
R797 0/NA 0402 1 2
R161 0/NA 0402 1 2
R914
287
0603
1%
1/10W
1
2
R131 0 0402 1 2
R169 330/NA 0402 1 2
C810
0.1U
0402
50V
+80-20%
1
2
R1176 0 0402 1 2
R166
10K
0402
5%
1 2
C836
0.1U
0402
50V
+80-20%
1
2
TP22 1
R348 0
0402
1 2
R177 8.2K/NA 0402 1 2
R182 8.2K/NA 0402 1 2
R918
100
0402
1%
1
2
R125 0 0402 1 2
R126 0 0402 1 2
R150 0 0402 1 2
R791
150
0402
1%
1
2
C215
0.1U
0402
50V
+80-20%
1
2
R206
1K/NA
0402
5%
1 2
TP20 1
R796 0/NA 0402 1 2
R116 0 0402 1 2
R357 0 0402 1 2
R184 8.2K/NA 0402 1 2
R236 10K 04021 2
R154 0/NA 0402 1 2
R111 0 0402 1 2
R59
1K
0402
5%
1
2
R793
301
0402
1%
1
2
R1166 0 0402 1 2
C217
0.1U
0402
50V
+80-20%
1
2
TP38 1
TP36 1
R345 0
0402
1 2
R174 330/NA 0402 1 2
C170
33P/NA
0402
25V
+/-10%
1
2
R910
100
0402
1%
1
2
R128 0 0402 1 2
R172 8.2K/NA 0402 1 2
R176 330/NA 0402 1 2
R850
150
0402
1%
1
2
R898
37.4
0603
1%
1 2
R1104
100K/NA
0402
5%
1
2
R349 0 0402 1 2
R794 0/NA 0402 1 2
R1177 0 0402 1 2
R175 8.2K/NA 0402 1 2
C784
0.1U
0402
50V
+80-20%
1
2
R149 0 0402 1 2
C216
0.1U
0402
50V
+80-20%
1
2
R227 10K 04021 2
R257
100
0402
1%
1
2
D
S
Q15
2N7002 G
D
S
R217
0 0402 1 2
R855
301
0402
1%
1
2
C815
0.1U
0402
50V
+80-20%
1
2
R835 0/NA
0402 5%
1 2
R127 0 0402 1 2
R159 0/NA 0402 1 2
R857
100K/NA 0402
1 2
TP27 1
R153 0/NA 0402 1 2
R258
49.9
0402
1%
1
2
R1167 0 0402 1 2
R798 1.5K
0402 5%
1 2
R117 0 0402 1 2
R183 330/NA 0402 1 2
R160 0/NA 0402 1 2
R170 8.2K/NA 0402 1 2
C775
33P/NA
0402
25V
+/-10%
1
2
R799 10K/NA 04021 2
TP30 1
R226 10K 04021 2
C169
33P/NA
0402
25V
+/-10%
1
2
R913
100
0402
1%
1
2
R171 330/NA 0402 1 2
R350 0 0402 1 2 R331 0 0402 1 2
R129 0 0402 1 2
R158 0/NA 0402 1 2
R146 0 0402 1 2
R902
49.9
0402
1%
1
2
TP26 1
R162 0 0402 1 2
R64
1K
0402
5%
1
2
U714A
855GM/GME
BGA707_25
E5
F5
E3
E2
G5
F4
G6
F6
F7
AE29
AD29
C9
D9
B6
G9
B4
C5
D5
Y23
AA22
B7
L2
M3
G2
B17
K5
K1
K3
K2
J6
J5
H2
H1
H3
H4
H6
G3
H5
K6
L5
L7
D1
C8
D8
H10
A7
A8
U7
U4
U3
V3
W2
W6
V6
W7
T3
V5
V4
R3
R5
R6
R4
P6
P5
N5
P2
N2
N3
M1
M5
M2
T6
T5
L3
J3
J2
G14
E15
C15
C13
F14
E14
C14
B13
H12
E12
C12
G11
G12
E11
C11
G10
H9
C6
A10
G8
F8
A5
U2
AC16
AC15
AD28
D6
Y3
F1
T2
W3
V2
W1
D14
E13
E10
F10
P7
T7
N7
M6
K7
N6
E8
AJ29
AH29
B29
A29
AJ28
A28
AA9
AJ4
AJ2
A2
AH1
B1
P4
P3
J9
ADDID[0]
ADDID[1]
ADDID[2]
ADDID[3]
ADDID[4]
ADDID[5]
ADDID[6]
ADDID[7]
AGPBUSY#
BCLK
BCLK#
BLUE
BLUE#
DDCACLK
DDCADATA
DDCPCLK
DDCPDATA
DPMS
DPSLP#
DPWR#
DREFCLK
DVOBBLANK#
DVOBCCLKINT
DVOBCINTR#
DREFSSCLK
DVOCD[0]
DVOCD[1]
DVOCD[2]
DVOCD[3]
DVOCD[4]
DVOCD[5]
DVOCD[6]
DVOCD[7]
DVOCD[8]
DVOCD[9]
DVOCD[10]
DVOCD[11]
DVOCFLDSTL
DVOCHSYNC
DVOCVSYNC
DVODETECT
DVORCOMP
GEEN
GREEN#
HSYNC
RED
RED#
HL[0]
HL[1]
HL[2]
HL[3]
HL[4]
HL[5]
HL[6]
HL[7]
HL[8]
HL[9]
HL[10]
DVOBD[0]
DVOBD[1]
DVOBD[2]
DVOBD[3]
DVOBD[4]
DVOBD[5]
DVOBD[6]
DVOBD[7]
DVOBD[8]
DVOBD[9]
DVOBD[10]
DVOBD[11]
DVOBFLDSTL
DVOBHSYNC
DVOBVSYNC
DVOCBLANK#
DVOCCLK
DVOCCLK#
IYAM[0]
IYAM[1]
IYAM[2]
IYAM[3]
IYAP[0]
IYAP[1]
IYAP[2]
IYAP[3]
IYBM[0]
IYBM[1]
IYBM[2]
IYBM[3]
IYBP[0]
IYBP[1]
IYBP[2]
IYBP[3]
LCLKCTLA
LCLKCTLB
LIBG
PANELBKLTCTL
PANELBKLTEN
PANELVDDEN
PSWING
RCVENIN#
RCVENOUT#
RSTIN#
EXTTS_0
GCLKIN
GVREF
HLRCOMP
HLSTB
HLSTB#
HLVREF
ICLKAM
ICLKAP
ICLKBM
ICLKBP
MDDCCLK
MDDCDATA
MDVICLK
MDVIDATA
MI2CCLK
MI2CDATA
REFSET
NC_0
NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
NC_7
NC_8
NC_9
NC_10
NC_11
DVOBCLK#
DVOBCLK
VSYNC
R839 27.4
1 2
R115 0 0402 1 2
R363 0 0402 1 2
R167 330/NA 0402 1 2
R279
0/NA 0402 1 2
R163 127 1% 1 2
R343 0 0402 1 2
R790 10K 0402 1 2
R208
100
0402
1%
1
2
R216 10K 0402 1 2
R1179 0 0402 1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Place within 0.5" with 15-mil wide.
Clock config bit GST[1,0]
PSB/Sys Mem Core/GFX Core(CL/CH)
00(def): 400/266/200(133/200)
01 : 400/200/200(100/200)
10 : 400/200/133(100/133)
NB_MONTARA-GME(2/2)
CHANGE TO 0402
CHANGE TO 0402
CHANGE TO 0402
CHANGE TO 0402
PCB 316680900001/ASSY 411680900011 R01
8050 MOTHERB/D
C
Title
Size
Document
Number
Rev
Date: Sheet of
SMAB[4..5]
NB_MA8
SMAB4
SMAB5
MCH_SMRCOMP
MCH_SMRCOMP
VTTHF_0
VTTHF_1
VTTHF_2
VTTHF_3
VTTHF_4
VCCGPIO
VCCQSM
VCCADPLLA
GST0
NB_MA0
NB_MA3
VSSADAC
VCCGPIO
VCCAHPLL
VTTHF_2
VCCADAC
VTTHF_4
VCCTXLVDS
VCCASM
VTTHF_0
VCCADAC
VCCAGPLL
VCCADPLLB
VTTHF_3
VCCASM
VCCTXLVDS
VCCQSM
VTTHF_1
VCCAGPLL
VCCADPLLA
VCCADPLLB
VCCAHPLL
VCCALVDS
NB_MD15
NB_MD40
NB_DQS5
NB_CB2
NB_MD8
NB_MD36
NB_MD30
SMA4
NB_MD20
NB_DM5
NB_DQS7
NB_MA3
NB_CB[0..7]
NB_MD62
NB_MD54
NB_MD2
NB_MD56
NB_MD9
SMA[1..2]
NB_DM0
NB_DQS6
NB_DQS4
NB_CB1
NB_MD26
NB_MD22
NB_MA11
NB_MA6
NB_MD53
NB_MD3
NB_MD46
NB_MD43
NB_MD35
SMAB2
NB_MA12
NB_CB7
NB_DM7
NB_MD1
NB_DM3
NB_CB0
NB_MD51
NB_MD21
NB_MD10
NB_MD29
NB_MA10
NB_MD52
GST1
NB_DM1
MCH_SMVSWINGH
NB_MD42
NB_MD63
NB_MD57
NB_MD11
NB_MD4
NB_MD41
NB_MD34
NB_MD28
SMAB1
SMAB[1..2]
NB_DM8
NB_DQS0
MCH_SMVSWINGL
NB_DM2
NB_MD50
NB_MD18
NB_MD16
NB_MA9
NB_MD49
NB_MD45
NB_MD5
MCH_SMVSWINGL
NB_MD38
NB_MD27
NB_DQS1
NB_MD24
NB_MD61
NB_CB5
NB_MD12
NB_MD39
NB_MA0
NB_MD[0..63]
NB_MD23
NB_MD37
NB_DM[0..8]
NB_DQS[0..8]
NB_MD0
NB_CB4
NB_MD44
NB_MD13
NB_MD6
NB_MD47
NB_MD17
NB_DM4
MCH_SMVSWINGH
NB_DQS2
NB_CB6
NB_MD25
NB_MA7
SMA1
NB_MD55
NB_MD48
NB_MD60
NB_MD59
NB_MD7
NB_MD33
SMA[4..5]
NB_CB3
NB_DM6
NB_DQS3
NB_MD14
NB_MD31
NB_MD19
SMA5
SMA2
NB_DQS8
NB_MD58
NB_MD32
VSSADAC
NB_MA0 6
NB_MA3 6
SMA[1..2] 6
SMA[4..5] 6
SMAB[1..2] 6
SMAB[4..5] 6
NB_WE# 6
NB_CAS# 6
NB_RAS# 6
NB_BA0 6
NB_BA1 6
CS#0 6
CS#1 6
CS#2 6
CS#3 6
CKE0 6
CKE1 6
CKE2 6
CKE3 6
NB_MD[0..63] 6
NB_CB[0..7] 6
NB_DQS[0..8] 6
NB_DM[0..8] 6
NB_MA6 6
NB_MA7 6
NB_MA8 6
NB_MA9 6
NB_MA10 6
NB_MA12 6
NB_MA11 6
GCBE2# 7
GST0 7
GST1 7
GST2 7
GSBSTB 7
GSBSTB# 7
GRBF# 7
GWBF# 7
GGNT# 7
GREQ# 7
NB_CLK_DDR5 6
NB_CLK_DDR2# 6
NB_CLK_DDR3# 6
NB_CLK_DDR2 6
NB_CLK_DDR3 6
NB_CLK_DDR1# 6
NB_CLK_DDR1 6
NB_CLK_DDR0 6
NB_CLK_DDR4# 6
NB_CLK_DDR5# 6
NB_CLK_DDR4 6
NB_CLK_DDR0# 6
GND GND
+2.5VS_DDR +2.5VS_DDR
GND GND
GND
+1.25V_DDR
+2.5VS_DDR
GND
GND
+1.35V
GND
GND
GND GND
+1.35V
+1.35V
GND
+1.5V
GND
GND
GND
+1.35V
GND
+3V
GND
+2.5VS_DDR
GND
+1.35V +1.35V
GND
+2.5VS_DDR
GND
GND
GND
GND
GND
GND
+VCCP
+1.35V
+1.5V
+1.5V
+2.5VS_DDR
+1.5V +1.5V
GND
+1.5V
+2.5V_M10
C781 0.1U 0402
50V +80-20%
1 2
C232
0.1U
0402
50V
+80-20%
1
2
U714E
855GM/GME
BGA707_25
AA29
W29
U29
N29
L29
J29
G29
E29
C29
AE28
AC28
E28
D28
AJ27
AG27
AC27
F27
A27
AJ26
AB26
W26
R26
N26
L26
J26
G26
AE25
AA25
D25
A25
AG24
AA24
V24
T24
P24
M24
K24
H24
F24
B24
AJ23
AC23
AA23
D23
A23
AE22
W22
U22
R22
N22
L22
J22
F22
C22
AG21
AB21
AA21
Y21
V21
T21
P21
M21
H21
D21
A21
AJ20
AC20
AA20
J20
F20
AE19
AB19
H19
D19
A19
AJ18
AG18
AA18
J18
F18
AC17
AB17
U17
R17
N17
H17
D17
A17
AE16
AA16
T16
P16
J16
F16
AG15
AB15
U15
R15
N15
H15
D15
AC14
AA14
T14
P14
J14
AE13
AB13
U13
R13
N13
H13
F13
D13
A13
AJ12
AG12
AA12
J12
AJ11
AC11
AB11
H11
F11
D11
AE10
AJ10
AA10
C10
AG9
AB9
W9
U9
T9
R9
N9
L9
E9
AC8
Y8
V8
T8
P8
K8
H8
AJ7
AE7
AA7
R7
M7
J7
G7
E7
C7
AG6
Y6
L6
Y5
U5
B5
AE4
AC4
AA4
W4
T4
N4
K4
G4
D4
AJ3
AG3
R2
AJ1
AE1
AA1
U1
L1
G1
C1
J10
U26
VSS_0
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
L38
120Z/100M
1 2
TP25 1
R924
60.4
0402
1%
1
2
C255
0.1U
0402
50V
+80-20%
1
2
C783
10U
6.3V
0805
10%
1
2
C857
0.1U
0402
50V
+80-20%
1
2 C174
10U
16V
1206
1
2
L714
120Z/100M
1 2
C324
10U
6.3V
0805
10%
1
2
C852
10U
16V
1206
1
2
C273
0.1U
0402
50V
+80-20%
1
2
C832 0.1U 0402
50V +80-20%
1 2
C297
0.1U
0402
50V
+80-20%
1
2
C290
0.1U
0402
50V
+80-20%
1
2
C785
0.01U
0402
50V
+80-20%
1
2
L717
120Z/100M
1 2
C293
0.1U
0402
50V
+80-20%
1
2
C303
0.1U
0402
50V
+80-20%
1
2
R942
150
0402
1%
1
2
L45
120Z/100M
1 2
L42
120Z/100M
1 2
L729
120Z/100M
1 2
L727
120Z/100M
1 2
C858
0.1U
0402
50V
+80-20%
1
2
R941
150
0402
1%
1
2
C281
10U
6.3V
0805
10%
1
2
U714D
855GM/GME
BGA707_25
W21
AA19
AA17
T17
P17
U16
R16
N16
AA15
T15
P15
J15
U14
R14
N14
H14
T13
P13
B15
B14
J13
G13
P9
M9
K9
R8
N8
M8
L8
J8
H7
E6
M4
J4
E4
N1
J1
E1
V9
W8
U8
V7
U6
W5
Y1
V1
AJ8
AJ6
A4
A3
AG29
AF29
AC29
AF27
AJ25
AF24
AB22
AJ21
AF21
AB20
AF18
AB18
AJ17
AB16
AF15
AB14
AJ13
AA13
AF12
AB12
AA11
AB10
AJ9
AF9
Y9
AB8
AA8
Y7
AF6
AB6
AA6
AJ5
Y4
AF3
AB3
AG1
AC1
A12
D10
B10
F9
B8
B11
AB29
Y29
K29
F29
A26
V22
T22
P22
M22
H22
U21
R21
N21
L21
H20
A20
J19
H18
A18
H16
G15
V29
M29
H29
A24
A22
B9
A9
A6
B16
Y2
D29
A11
AF1
AD1
VCC_0
VCC_1
VCC_2
VCC_3
VCC_4
VCC_5
VCC_6
VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12
VCC_13
VCC_14
VCC_15
VCC_16
VCC_17
VCCDLVDS_0
VCCDLVDS_1
VCCDLVDS_2
VCCDLVDS_3
VCCDVO_0
VCCDVO_1
VCCDVO_2
VCCDVO_3
VCCDVO_4
VCCDVO_5
VCCDVO_6
VCCDVO_7
VCCDVO_8
VCCDVO_9
VCCDVO_10
VCCDVO_11
VCCDVO_12
VCCDVO_13
VCCDVO_14
VCCDVO_15
VCCHL_0
VCCHL_1
VCCHL_2
VCCHL_3
VCCHL_4
VCCHL_5
VCCHL_6
VCCHL_7
VCCQSM_0
VCCQSM_1
VCCGPIO_0
VCCGPIO_1
VCCSM_0
VCCSM_1
VCCSM_2
VCCSM_3
VCCSM_4
VCCSM_5
VCCSM_6
VCCSM_7
VCCSM_8
VCCSM_9
VCCSM_10
VCCSM_11
VCCSM_12
VCCSM_13
VCCSM_14
VCCSM_15
VCCSM_16
VCCSM_17
VCCSM_18
VCCSM_19
VCCSM_20
VCCSM_21
VCCSM_22
VCCSM_23
VCCSM_24
VCCSM_25
VCCSM_26
VCCSM_27
VCCSM_28
VCCSM_29
VCCSM_30
VCCSM_31
VCCSM_32
VCCSM_33
VCCSM_34
VCCSM_35
VCCSM_36
VCCTXLVDS_0
VCCTXLVDS_1
VCCTXLVDS_2
VCCTXLVDS_3
VSSADAC
VSSALVDS
VTTLF_0
VTTLF_1
VTTLF_2
VTTLF_3
VTTLF_4
VTTLF_5
VTTLF_6
VTTLF_7
VTTLF_8
VTTLF_9
VTTLF_10
VTTLF_11
VTTLF_12
VTTLF_13
VTTLF_14
VTTLF_15
VTTLF_16
VTTLF_17
VTTLF_18
VTTLF_19
VTTLF_20
VTTHF_0
VTTHF_1
VTTHF_2
VTTHF_3
VTTHF_4
VCCADAC_0
VCCADAC_1
VCCADPLLA
VCCADPLLB
VCCAGPLL
VCCAHPLL
VCCALVDS
VCCASM_0
VCCASM_1
C252
0.1U
0402
50V
+80-20%
1
2
C328
0.1U
0402
50V
+80-20%
1
2
C282
0.1U
0402
50V
+80-20%
1
2
C859
0.01U
0402
50V
+80-20%
1
2
C227
10U
6.3V
0805
10%
1
2
C848
0.01U
0402
50V
+80-20%
1
2
C197
0.1U
0402
50V
+80-20%
1
2
C234
10U
6.3V
0805
10%
1
2
C772
10U
16V
1206
1
2
C302
0.1U
0402
50V
+80-20%
1
2
C818 0.1U 0402
50V +80-20%
1 2
C846
0.1U/NA
0402
50V
+80-20%
1
2
L730
120Z/100M/NA
1 2
C171
0.01U
0402
50V
+80-20%
1
2
C779
0.1U
0402
50V
+80-20%
1
2
C314
10U
6.3V
0805
10%
1
2
C299
0.1U
0402
50V
+80-20%
1
2
U714C
855GM/GME
BGA707_25
F12
D12
B12
AA5
L4
C4
F3
D3
C3
B3
F2
D2
C2
B2
D7
AD22
AD20
AC24
AB2
AA2
AC26
AB25
AC3
AD4
AC2
AD2
AB23
AB24
AA3
AB4
AC7
AB7
AC9
AC10
AD23
AD26
AC22
AC25
AF2
AE3
AF4
AH2
AD3
AE2
AG4
AH3
AD6
AG5
AG7
AF5
AE8
AH4
AF7
AH6
AF8
AG8
AH9
AG10
AH7
AD9
AF10
AE11
AH10
AH11
AG13
AF14
AG11
AD12
AF13
AH13
AH16
AG17
AF19
AE20
AD18
AE18
AH18
AG19
AH20
AG20
AF22
AH22
AF20
AH19
AH21
AG22
AE23
AH23
AE24
AH25
AG23
AF23
AF25
AG25
AH26
AE26
AF28
AG28
AG26
AF26
AE27
AD27
AG14
AE14
AE17
AG16
AH14
AE15
AF16
AF17
AG2
AH5
AH8
AE12
AH17
AE21
AH24
AH27
AD15
AC18
AD14
AD13
AD17
AD11
AC13
AD8
AD7
AC6
AC5
AC19
AD5
AB5
AD16
AC12
AF11
AD10
AB1
AJ24
AJ19
AJ22
AC21
AD25
AE5
AE6
AE9
AH12
AD19
AD21
AD24
AH28
AH15
RSVD_0
RSVD_1
RSVD_2
RSVD_3
RSVD_5
GST[0]
RSVD_7
RSVD_8
GST[1]
RSVD_11
RSVD_6
RSVD_9
GST[2]
RSVD_10
RSVD_4
SBA[0]
SBA[1]
SCAS#
SCK[0]
SCK[0]#
SCK[1]
SCK[1]#
SCK[2]
SCK[2]#
SCK[3]
SCK[3]#
SCK[4]
SCK[4]#
SCK[5]
SCK[5]#
SCKE[0]
SCKE[1]
SCKE[2]
SCKE[3]
SCS[0]#
SCS[1]#
SCS[2]#
SCS[3]#
SDQ[0]
SDQ[1]
SDQ[2]
SDQ[3]
SDQ[4]
SDQ[5]
SDQ[6]
SDQ[7]
SDQ[8]
SDQ[9]
SDQ[10]
SDQ[12]
SDQ[11]
SDQ[13]
SDQ[14]
SDQ[15]
SDQ[16]
SDQ[17]
SDQ[18]
SDQ[19]
SDQ[20]
SDQ[21]
SDQ[22]
SDQ[23]
SDQ[24]
SDQ[25]
SDQ[26]
SDQ[27]
SDQ[28]
SDQ[29]
SDQ[30]
SDQ[31]
SDQ[32]
SDQ[33]
SDQ[34]
SDQ[35]
SDQ[36]
SDQ[37]
SDQ[38]
SDQ[39]
SDQ[40]
SDQ[41]
SDQ[42]
SDQ[43]
SDQ[44]
SDQ[45]
SDQ[46]
SDQ[47]
SDQ[48]
SDQ[49]
SDQ[50]
SDQ[51]
SDQ[52]
SDQ[53]
SDQ[54]
SDQ[55]
SDQ[56]
SDQ[57]
SDQ[59]
SDQ[58]
SDQ[60]
SDQ[61]
SDQ[62]
SDQ[63]
SDQ[64]
SDQ[65]
SDQ[66]
SDQ[67]
SDQ[68]
SDQ[69]
SDQ[70]
SDQ[71]
SDQS[0]
SDQS[1]
SDQS[2]
SDQS[3]
SDQS[4]
SDQS[5]
SDQS[6]
SDQS[7]
SDQS[8]
SMA[0]
SMA[1]
SMA[2]
SMA[3]
SMA[4]
SMA[5]
SMA[6]
SMA[7]
SMA[8]
SMA[9]
SMA[10]
SMA[11]
SMA[12]
SMAB[1]
SMAB[2]
SMAB[4]
SMAB[5]
SMRCOMP
SMVREF_0
SMVSWINGH
SMVSWINGL
SRAS#
SWE#
SDM[0]
SDM[1]
SDM[2]
SDM[3]
SDM[4]
SDM[5]
SDM[6]
SDM[7]
SDM[8]
L715
120Z/100M
1 2
L713
120Z/100M
1 2
C814 0.1U 0402
50V +80-20%
1 2
R945
604
0603
1%
1
2
C243
10U
6.3V
0805
10%
1
2
C325
10U
6.3V
0805
10%
1
2
R822
1K
0402
5%
1
2
C847
0.1U
0402
50V
+80-20%
1
2
C202
0.1U
0402
50V
+80-20%
1
2
C291
0.1U
0402
50V
+80-20%
1
2
C184
0.1U
0402
50V
+80-20%
1
2
C309
0.1U
0402
50V
+80-20%
1
2
C851
10U
6.3V
0805
10%
1
2
C205
0.1U
0402
50V
+80-20%
1
2
C263
10U
6.3V
0805
10%
1
2
C238
10U
16V
1206
1
2
C343
0.01U
0402
50V
+80-20%
1
2
C166
10U
16V
1206
1
2
C780 0.1U 0402
50V +80-20%
1 2
R806
1K/NA
0402
5%
1
2
TP40 1
L720
120Z/100M
1 2
C272
10U
6.3V
0805
10%
1
2
C777
0.1U
0402
50V
+80-20%
1
2
C860
4.7U
6.3V
0603
+80-20%
1
2
C276
0.1U
0402
50V
+80-20%
1
2
C786
0.01U
0402
50V
+80-20%
1
2
C776
0.01U
0402
50V
+80-20%
1
2
R923
60.4
0402
1%
1
2
C288
0.1U
0402
50V
+80-20%
1
2
TP35 1
C176
0.01U
0402
50V
+80-20%
1
2
C850
10U
16V
1206
1
2
C271
10U
16V
1206
1
2
TP703 1
C247
0.1U
0402
50V
+80-20%
1
2
C300
0.1U
0402
50V
+80-20%
1
2
TP41 1
C808
0.1U
0402
50V
+80-20%
1
2
C218
0.1U
0402
50V
+80-20%
1
2
R946
604
0603
1%
1
2
C301
0.1U
0402
50V
+80-20%
1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DDR -SODIMM
PCB 316680900001/ASSY 411680900011 R01
8050 MOTHERB/D
C
Title
Size
Document
Number
Rev
Date: Sheet of
MD45
MD25
MA8
MD30
SMBDATA
MD20
CAS#
MD57 MD61
DQS7
BA1
MD4
MD52
DQS8
DQS1
DM3
MD18
CLK_DDR3#
NB_BA1
MD36
NB_MA12
NB_WE#
MD45
MD52
MD35
DM8
CKE0
DM4
CKE2
MD20
NB_MA10
MCB0
MD38
DM8
NB_MA9
DM7
MD4
MA11
MD7
DQS3
CKE3
CLK_DDR1
RAS#
MD26
CLK_DDR3
MD39
MD6
DQS2
DM6
NB_CAS#
NB_MA3
DQS4
MD38
DM7
MCB7
DM1
MD54
MD29
CLK_DDR1#
MCB7
SMA4
MD0
SMBCLK
MA6
SMAB5
MD30
MD10
DM2
MD13
MD14
MD36
MD13
MD19
MD46
MD50
CLK_DDR5
MD3
MD23
DQS0
MD58
CS#2
MD23
MD9
MD32
DM0
MD62
SMAB4
DM6
NB_BA0
DM5
NB_RAS#
MD16
SMA2
DM2
MD2
MD42
DM1
CS#3
DM4
MD22
CS#1
NB_MA7 NB_MA6
MD22
DQS5
MD41
MD51
MD61
DM0
MD48
DM3
CLK_DDR4
MD55
SMAB2
MCB3
MD46
MD29
MD54
DM5
MD55
CLK_DDR4#
MD14
MD62
MD39
MD7
MD6
MCB1
MD34
NB_MA11
NB_MA8
MCB0
CKE1
CS#0
BA0
DQS5
DQS1
MD50
MD34
MD42
SMBDATA
MD26
SMA5
MD16
CLK_DDR0
MCB3
MD58
MD48
MD32
MD3
CLK_DDR0#
MD2
MD51
MA12
WE#
MD25
MA3
CLK_DDR2
MD35
MD18
MCB1
MA10
SMBCLK
DQS3
DQS7
MA9
MA7
DQS4
MD10
DQS8
MD41
DQS2
MD9
DQS0
MD19
MD57
MD0
MD0
MD3
MD6
MD7
MD8
MD9
MD10
MD11
MD13
MD14
MD15
MD17
MD19
MD24
MD39
MD27
MD40
MD41
MD30
MD31
MD32
MD21
MD34
MD36
MD37
MD46
MD61
MD49
MD50
MD51
MD52
MD53
MD54
MD55
MD56
MD58
MD44
MD63
NB_MD1
NB_MD12
NB_MD34
NB_MD47
NB_MD50
NB_MD0
NB_MD10
NB_MD21
NB_MD27
NB_MD53
NB_MD9
NB_MD14
NB_MD29
NB_MD22
NB_MD48
NB_MD61
NB_MD25
NB_MD32
NB_MD55
NB_MD2
NB_MD43
NB_MD5
NB_MD20
NB_MD36
NB_MD39
NB_MD49
NB_MD62
NB_MD57
NB_MD4
NB_MD23
NB_MD28
NB_MD26
NB_MD24
NB_MD38
NB_MD45
NB_MD56
NB_MD3
NB_MD13
NB_MD33
NB_MD40
NB_MD8
NB_MD17
NB_MD19
NB_MD44
NB_MD35
NB_MD59
NB_MD52
NB_MD6
NB_MD7
NB_MD37
NB_MD41
NB_MD54
NB_MD15
NB_MD31
NB_MD51
NB_MD58
NB_MD60
NB_MD30
NB_MD11
NB_MD16
NB_MD18
NB_MD42
NB_MD46
NB_MD63
NB_MD[0..63]
DQS0
DQS5
DQS4
DM1
NB_DM7
DM6
NB_DM3
NB_DM4
NB_DM2
NB_DM5
NB_DM6
DM0 NB_DM0
NB_DM1
DM7
DM4
NB_MA7
MA6
NB_MA3
NB_MA6
NB_MA0
MA7
MA10 NB_MA10
NB_MA8
MA9 NB_MA9
MA11 NB_MA11
NB_MA12 MA12
NB_CB2
NB_CB0
NB_CB7
MCB0
MCB6 NB_CB6
NB_CB4
NB_CB5
MCB1 NB_CB1
MCB3 NB_CB3
NB_CB[0..7]
NB_DM[0..7]
NB_WE#
NB_CAS#
NB_RAS#
NB_BA0
NB_BA1
CAS#
RAS#
BA0
BA1
MD2
MD4
MD5
MD16
MD12
MD23
MD20
MD18
MD28
MD22
MD25
MD26
MD29
MD35
MD38
MD33
MD47
MD43
MD48
MD45
MD42
MD62
MD57
MD59
DQS2
MD60
DQS3
DQS7
DM5
DM3
DM2
MCB7
MCB2
MA3
MA8
WE#
CKE3
CKE2
CS#3
CS#2
DM8
MD24
MD37
MD5
MD24
MD37
MD47
MD56
CLK_DDR5#
MD31
MD15 MD11
MD44
MD21
MCB6
NB_MA0
MD12
MD11
MCB2
MD1
MD40
MD33
MD17
MD33
MD60
SMA1
MD40
MD53
MD44
MD53 MD49
MD5
MD49
MD56
MD31
MD17
MD63
CLK_DDR2#
MCB6
MD43
MD15
MD59
MCB2
MD27
MD59
MD28
MA0
MD63
MD8
MD28
MD47
MD60
MD8
MD27
MD12
SMAB1
MD21
MD1
MD43
MA0
MCB4
MCB4 MCB4
MCB5
MCB5
MCB5
CLK_DDR1
CLK_DDR2
CLK_DDR0#
CLK_DDR0
CLK_DDR3
CLK_DDR3#
CLK_DDR1#
CLK_DDR2#
CLK_DDR4
CLK_DDR4#
CLK_DDR5
CLK_DDR5#
NB_DQS1 DQS1
NB_DQS6
NB_DQS3
NB_DQS[0..7]
NB_DQS2
NB_DQS7
NB_DQS5
NB_DQS4
NB_DQS0
DQS8
CKE0
CKE1
CKE0_S1
CKE1_S1
CS#0_S1
CKE1_S1
CS#0_S1
CKE0_S1
MD51
MD55
DM6
MD54
MD50
DQS6
MD60
MD63
MD59
MD61
MD58
DQS7
DM7
MD57
MD62
MD56
DQS6
DQS6
DQS6
MD46
MD48
MD49
MD43
MD47
MD52
MD53
MD42
MD40
MD35
DM5
DQS5
MD44
MD39
MD41
MD45
MD32
MD33
MD38
MD37
DM4
MD36
MD34
DQS4
MD25
DQS3
MD30
MD29
DM3
MD26
MD27
MD31
MD18
MD22
MD28
MD19
MD24
DQS2
DM2
MD23
MD21
MD14
MD11
MD16
MD10
MD17
MD15
MD20
MD7
MD3
MD13
DQS1
MD9
DM1
MD8
MD12
MD5
MD2
DM0
DQS0
MD4
MD6
MD0
MCB5
MCB1
MCB0
DQS8
MCB6
MCB4
DM8
MCB2
SMA2
SMA4
SMA5
SMA1
SMAB2
SMAB5
SMAB4
SMAB1
MCB3
MCB7
CKE0
CKE1
CKE2
CS#3
CS#1
NB_RAS#
NB_WE#
NB_BA0
NB_CAS#
CS#2
CS#0
CS#0
SMA4
SMAB5
CKE3
MD1
MD1
CS#1
CS#1_S1
CS#1_S1
SMAB4
NB_MA9
SMAB2
NB_MA12
SMA2
SMA5
NB_MA11
NB_MA8
SMAB1
NB_MA0
SMA1
NB_BA1
NB_MA7
NB_MA3
NB_MA10
NB_MA6
SMBDATA 11,14
SMBCLK 11,14
NB_MD[0..63] 5
NB_CB[0..7]
NB_DM[0..7]
NB_WE# 5
NB_CAS# 5
NB_RAS# 5
NB_BA0 5
NB_BA1 5
CKE0 5
CKE1 5
CKE3 5
CKE2 5
CS#2 5
CS#1 5
CS#3 5
CS#0 5
NB_CLK_DDR0 5
NB_CLK_DDR1 5
NB_CLK_DDR3# 5
NB_CLK_DDR5# 5
NB_CLK_DDR1# 5
NB_CLK_DDR5 5
NB_CLK_DDR4 5
NB_CLK_DDR2# 5
NB_CLK_DDR0# 5
NB_CLK_DDR4# 5
NB_CLK_DDR3 5
NB_MA0 5
NB_MA3 5
NB_MA6 5
NB_MA7 5
NB_MA8 5
NB_MA9 5
NB_MA10 5
NB_MA11 5
NB_MA12 5
NB_DM8 5
NB_DQS[0..7]
NB_DQS8 5
NB_CLK_DDR2 5
SMAB1 5
SMA1 5
SMAB5 5
SMAB2 5
SMA4 5
SMA2 5
SMAB4 5
SMA5 5
+DDR_VREF
+3V
GND
+1.25V_DDR
+DDR_VREF
GND
GND
GND
+1.25V_DDR
GND
GND
+DDR_VREF
GND
+1.25V_DDR
GND
+3V
+2.5VS_DDR
+2.5VS_DDR
+2.5VS_DDR
+2.5VS_DDR
+2.5VS_DDR
+1.25V_DDR
GND
+1.25V_DDR
+3V
R967 10 0402 1 2
C353
0.1U
0402
50V
+80-20%
1
2
R1060 10 0402 1 2
R1052 10 0402 1 2
R351 0 0402 5% 1 2
R999 10 0402 1 2
RP41
56*8
RPX8
1
2
3
4
5
6
7
8 9
10
11
12
13
14
15
16
C409
0.01U
0402
50V
+80-20%
1
2
R962 10 0402 1 2
C431
0.01U
0402
50V
+80-20%
1
2
C402
0.01U
0402
50V
+80-20%
1
2
R996 10 0402 1 2
R987 10 0402 1 2
C366
0.1U
0402
50V
+80-20%
1
2
R984 10 0402 1 2
R1026 10 0402 1 2
R1029 0 0402 5% 1 2
R1057 10 0402 1 2
R335 0 0402 5% 1 2
C404
0.01U
0402
50V
+80-20%
1
2
R959 10 0402 1 2
RP43
56*8
RPX8
1
2
3
4
5
6
7
8 9
10
11
12
13
14
15
16
R1038 10 0402 1 2
R1046 10 0402 1 2
C426
0.01U
0402
50V
+80-20%
1
2
J712
0.6MM/200P/H5.2
QUASAR
CA0115-200N01
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
RP42
56*8
RPX8
1
2
3
4
5
6
7
8 9
10
11
12
13
14
15
16
R1001 10 0402 1 2
C415
0.01U
0402
50V
+80-20%
1
2
C335
0.1U
0402
50V
+80-20%
1
2
C333
0.1U
0402
50V
+80-20%
1
2
C395
0.01U
0402
50V
+80-20%
1
2
C331
0.1U
0402
50V
+80-20%
1
2
R1010 10 0402 1 2
R966 10 0402 1 2
R994 10 0402 1 2
R949 10 0402 1 2
R1031 10 0402 1 2
R1034 10 0402 1 2
R1022 10 0402 1 2
R1051 10 0402 1 2
C400
0.01U
0402
50V
+80-20%
1
2
R975 10 0402 1 2
R1021 10 0402 1 2
C371
1U
0402
10V
+80-20%
1
2
C424
0.1U
0402
50V
+80-20%
1
2
C421
0.01U
0402
50V
+80-20%
1
2
C437
10U
6.3V
0805
10%
1
2
R995 10 0402 1 2
R1018 10 0402 1 2
R354 0 0402 5% 1 2
R1043 10 0402 1 2
R977 10 0402 1 2
C428
0.01U
0402
50V
+80-20%
1
2
C412
0.01U
0402
50V
+80-20%
1
2
R951 10 0402 1 2
R1055 10 0402 1 2
R1056 10 0402 1 2
R950 10 0402 1 2
R1023 10 0402 1 2
RP36
56*8
RPX8
1
2
3
4
5
6
7
8 9
10
11
12
13
14
15
16
R1015 10 0402 1 2
R976 0 0402 5% 1 2 C346
0.1U
0402
50V
+80-20%
1
2
C413
0.01U
0402
50V
+80-20%
1
2
R985 10 0402 1 2
C351
0.1U
0402
50V
+80-20%
1
2
C401
0.01U
0402
50V
+80-20%
1
2
C338
0.1U
0402
50V
+80-20%
1
2
R1000 10 0402 1 2
R948 10 0402 1 2
C350
0.1U
0402
50V
+80-20%
1
2
C347
0.1U
0402
50V
+80-20%
1
2
R960 10 0402 1 2
R970 10 0402 1 2
R973 10 0402 1 2
C433
0.01U
0402
50V
+80-20%
1
2
C397
0.01U
0402
50V
+80-20%
1
2
C392
0.01U
0402
50V
+80-20%
1
2
C388
0.01U
0402
50V
+80-20%
1
2
R1061 10 0402 1 2
R957 10 0402 1 2
R1016 10 0402 1 2
RP31
56*8
RPX8
1
2
3
4
5
6
7
8 9
10
11
12
13
14
15
16
R334
75
0402
1%
1
2
R982 10 0402 1 2
C432
0.01U
0402
50V
+80-20%
1
2
C408
0.01U
0402
50V
+80-20%
1
2
RP30
56*8
RPX8
1
2
3
4
5
6
7
8 9
10
11
12
13
14
15
16
R974 10 0402 1 2
RP35
56*8
RPX8
1
2
3
4
5
6
7
8 9
10
11
12
13
14
15
16
C422
0.1U
0402
50V
+80-20%
1
2
C420
0.01U
0402
50V
+80-20%
1
2
R1013 10 0402 1 2
R352 0 0402 5% 1 2
R1049 10 0402 1 2
R980 10 0402 1 2
R953 10 0402 1 2
R1024 10 0402 1 2
C405
0.01U
0402
50V
+80-20%
1
2
R954 10 0402 1 2
R1025 10 0402 1 2
C434
0.01U
0402
50V
+80-20%
1
2
R1062 10 0402 1 2
R955 10 0402 1 2
R1027 10 0402 1 2
R993 10 0402 1 2
R961 10 0402 1 2
C411
0.01U
0402
50V
+80-20%
1
2
C407
0.01U
0402
50V
+80-20%
1
2
R1042 10 0402 1 2
R1047 10 0402 1 2
R1040 10 0402 1 2
C393
0.01U
0402
50V
+80-20%
1
2
RP32
56*8
RPX8
1
2
3
4
5
6
7
8 9
10
11
12
13
14
15
16
R1030 10 0402 1 2
C348
1U
0402
10V
+80-20%
1
2
C417
0.01U
0402
50V
+80-20%
1
2
R1054 10 0402 1 2
R1050 10 0402 1 2
C370
0.1U
0402
50V
+80-20%
1
2
C352
0.1U
0402
50V
+80-20%
1
2
C398
0.01U
0402
50V
+80-20%
1
2
R965 10 0402 1 2
C429
0.01U
0402
50V
+80-20%
1
2
C332
0.1U
0402
50V
+80-20%
1
2
C369
0.1U
0402
50V
+80-20%
1
2
R1014 10 0402 1 2
RP34
56*8
RPX8
1
2
3
4
5
6
7
8 9
10
11
12
13
14
15
16
R336 0 0402 5% 1 2
C403
0.01U
0402
50V
+80-20%
1
2
C391
0.01U
0402
50V
+80-20%
1
2
R1032 10 0402 1 2
R998 10 0402 1 2
R983 10 0402 1 2
RP38
56*8
RPX8
1
2
3
4
5
6
7
8 9
10
11
12
13
14
15
16
C337
0.01U
0402
50V
+80-20%
1
2
R1019 10 0402 1 2
R359 0 0402 5% 1 2
C387
0.01U
0402
50V
+80-20%
1
2
R988 10 0402 1 2
R979 10 0402 1 2
R347 0 0402 5% 1 2
C419
0.01U
0402
50V
+80-20%
1
2
RP33
56*8
RPX8
1
2
3
4
5
6
7
8 9
10
11
12
13
14
15
16
R1059 10 0402 1 2
R1011 10 0402 1 2
RP37
56*8
RPX8
1
2
3
4
5
6
7
8 9
10
11
12
13
14
15
16
R952 10 0402 1 2
C436
10U
6.3V
0805
10%
1
2
C406
0.01U
0402
50V
+80-20%
1
2
R1041 10 0402 1 2
R963 10 0402 1 2
R338 0 0402 5% 1 2
C384
0.1U
0402
50V
+80-20%
1
2
R1048 10 0402 1 2
R1039 10 0402 1 2
R1020 10 0402 1 2
R990 10 0402 1 2
R971 10 0402 1 2
R340
75
0402
1%
1
2
C386
0.01U
0402
50V
+80-20%
1
2
C418
0.01U
0402
50V
+80-20%
1
2
C399
0.01U
0402
50V
+80-20%
1
2
C389
0.01U
0402
50V
+80-20%
1
2
R992 10 0402 1 2
J711
0.6MM/200P/H9.2
QUASAR
CA0145-200N01
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
R989 10 0402 1 2
C425
0.01U
0402
50V
+80-20%
1
2
R956 10 0402 1 2
C372
0.1U
0402
50V
+80-20%
1
2
RP39
56*8
RPX8
1
2
3
4
5
6
7
8 9
10
11
12
13
14
15
16 R1028 10 0402 1 2
R320 0 0402 5% 1 2
R1036 10 0402 1 2
C349
0.1U
0402
50V
+80-20%
1
2
R1053 10 0402 1 2
R1045 10 0402 1 2
R968 0 0402 5% 1 2
R360 0 0402 5% 1 2
C394
0.01U
0402
50V
+80-20%
1
2
RP29
56*8
RPX8
1
2
3
4
5
6
7
8 9
10
11
12
13
14
15
16
R997 10 0402 1 2
C430
0.01U
0402
50V
+80-20%
1
2
R958 10 0402 1 2
C423
0.1U
0402
50V
+80-20%
1
2
C410
0.01U
0402
50V
+80-20%
1
2
R1044 10 0402 1 2
R969 10 0402 1 2
C336
1U
0402
10V
+80-20%
1
2
C414
0.01U
0402
50V
+80-20%
1
2
RP40
56*8
RPX8
1
2
3
4
5
6
7
8 9
10
11
12
13
14
15
16
R981 10 0402 1 2
R1058 10 0402 1 2
R978 10 0402 1 2
R1037 0 0402 5% 1 2
R972 10 0402 1 2
R337 0 0402 5% 1 2
C416
0.01U
0402
50V
+80-20%
1
2
R1017 10 0402 1 2
R991 10 0402 1 2
C427
0.01U
0402
50V
+80-20%
1
2
C334
0.1U
0402
50V
+80-20%
1
2
C396
0.01U
0402
50V
+80-20%
1
2
R1033 10 0402 1 2
R986 10 0402 1 2
C390
0.01U
0402
50V
+80-20%
1
2
R1009 10 0402 1 2
R319 0 0402 5% 1 2
C868
0.1U
0402
50V
+80-20%
1
2
R1035 10 0402 1 2
R1012 10 0402 1 2
R964 10 0402 1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
R777
100
1.02K
Bus configuration straps
1.5V, AGP4X, ID=16
AGP MODE
R779
1.02K
AGP MODE
324
49.9R
FOR M10
AGP3.0(8X).35V
R794
715 ohm is recommanded for R2SET.
40R M10
AGP2.0(4X).75V
M9+
ATI M10-P(1/4)
For MEM_ID
LVDS CH2
LVDS CH1
USE 22P 5%
64M EtroTech EM6A9320B1-3.6M
0 64M Samsung K4D263238E-GL36
Reserve
0
1
ZV13
1 1
ZV11 ZV12
0
128M EtroTech H230904RAT309A
0
64M Infineon HYB25D128323CL3.6
1
64M Hynix
Reserve
Reserve
Reserve
PCB 316680900001/ASSY 411680900011 R01
8050 MOTHERB/D
C
Title
Size
Document
Number
Rev
Date: Sheet of
AGP_SBA[0..7]
AGP_CBE#[0..3]
AGP_AD[0..31]
AGP_AD16
AGP_AD12
M10_GPIO5
AGP_CBE#0
M10_GPIO0
M10_GPIO1
ATI_CRT_RED
AGP_AD26
M10_GPIO6
AGP_AD24
I2C_DAT
M10_GPIO9
AGP_ST2
AGP_AD25
AGP_SBA5
AGP_AD10
ATI_CRT_BLUE
AGP_VREF
M10_GPIO4
AGP_SBA0
M10_GPIO12
AGP_CBE#3
AGP_SBA1
AGP_AD22
AGP_AD3
AGP_AD1
AGP_ST1
AGP_AD31
M10_GPIO3
I2C_CLK
AGP_AD6
AGP_SBA3
AGP_AD11
AGP_AD27
AGP_AD14
AGP_AD20
AGP_AD8
ATI_CRT_GREEN
AGP_AD29
M10_GPIO3
AGPTEST
AGP_AD7
AGP_SBA7
AGP_AD17
M10_GPIO6
AGP_AD21
AGP_SBA4
AGP_AD28
AGP_ST0
M10_GPIO5
AGP_AD15
M10_GPIO1
AGP_CBE#2
AGP_AD5
M10_GPIO2
AGP_SBA6
AGP_AD2
AGP_AD18
AGP_AD19
AGP_AD13
AGP_AD30
M10_GPIO2
AGP_SBA2
M10_GPIO13
AGP_AD4
AGP_AD23
AGP_AD9
AGPTEST
M10_GPIO11
M10_GPIO4
M10_GPIO10
AGP_CBE#1
AGP_VREF
M10_GPIO8
AGP_AD0
M10_GPIO13
M10_GPIO10 M10_GPIO11
M10_GPIO9
M10_GPIO8
M10_GPIO12
DIGON
M10_GPIO7
M10_GPIO0
M10_GPIO14
AGPBUSY#
M10_GPIO7
ZV13
ZV12
STP_AGP#
X2
X1
REF_OUT
X2
X1
OSC_SPREAD
REF_OUT
OSC_SPREAD
ENABKL
ATI_CRT_BLUE
ATI_CRT_GREEN
ATI_CRT_RED
ATI_TV_CRMA
ATI_TV_LUMA
BLON
M10_GPIO14
ATI_TV_COMP
ZV11
ZV12
ZV13
ZV11
PANEL_ID2 12,14,24
ENABKL 12
AGP_ADSTB0 4
AGP_GNT# 5
AGP_FRAME# 4
AGP_WBF# 5
ATI_CRT_RED 12
AGP_VREF 4
ATI_CRT_BLUE 12
ATI_TV_LUMA 11
AGP_ADSTB0# 4
AGP_SBSTBS 5
AGP_TRDY# 4
AGP_ST0 5
ATI_CRT_HSYNC 12
ATI_CRT_VSYNC 12
ATI_CRT_DDDA 12
AGP_ADSTB1# 4
AGP_SBSTBF 5
AGP_PAR 4
AGP_STOP# 4
AGP_AD[0..31] 4,24
ATI_CRT_GREEN 12
AGP_ST1 5
PANEL_ID3 12,14,24
ATI_CRT_DDCK 12
AGP_ST2 5
ATI_PCIRST# 13
AGP_RBF# 5
66M_AGP 11
AGP_REQ# 5
AGP_IRDY# 4
AGP_DEVSEL# 4
PCI_INTA# 13,24
ATI_TV_CRMA 11
AGP_SBA[0..7] 4
AGP_ADSTB1 4
AGP_CBE#[0..3] 4,5
ENAVDD 12
SW_1.5V/1.25V 30
PANEL_ID0 12,14,24
PANEL_ID1 12,14,24
AGPBUSY# 4,13,24
SB_SUSST# 13
STP_AGP# 13,24
TXOUT0-_ATI 4
TXOUT3+_ATI 4
TXOUT0+_ATI 4
TXOUT2+_ATI 4
TXOUT3-_ATI 4
TXOUT2-_ATI 4
TXOUT1+_ATI 4
TXCLK+_ATI 4
TXCLK-_ATI 4
TXOUT1-_ATI 4
ATI_TV_COMP 11
+3V
+3V
GND
+3V
AGP_VDDQ
AGP_VDDQ
GND
GND
GND
GND
+3V
+3V
AGP_VDDQ
GND
GND
GND
GND
GND
GND
GND
GND
GND
+3V
+3V
GND
GND
+3VS
GND
+3V +3V
GND GND
+3V
+3V +3V
GND GND
GND
GND
GND GND
GND GND
+3V
GND
GND
R66 10K/NA 0402 1 2
R786
620/NA
0603
5%
1 2
R744 10K/NA 0402 1 2
C766
22P/NA
0402
50V
+/-10%
1
2
R764
499/NA 0603 1%
1 2
X702
27MHZ/NA
TXC8X4.5
1 2
C145 0.1U/NA
0402 50V +80-20%
1 2
C131
0.1U/NA
0402
50V
+80-20%
1
2
R78 33/NA 0402 5% 1 2
RP715
10K*8/NA1206
1
2
3
4
5 6
7
8
9
10
R776
1M/NA
0402 5%
1 2
C774
0.1U/NA
0402
16V
10%
1
2
R104
10K/NA 0402 5%
1 2
C770
270P/NA
0402
50V
+/-10%
1
2
R769
75/NA
0402
5%
1
2
U710A
MOBILITY-M10-P/NA
BGA644_64_1MM
H29
H28
J29
J28
K29
K28
L29
L28
N28
P29
P28
R29
R28
T29
T28
U29
N25
R26
P25
R27
R25
T25
T26
U25
V27
W26
W25
Y26
Y25
AA26
AA25
AA27
N29
U28
P26
U26
AG30
AG28
AF28
AD26
M25
N26
V29
V28
W29
W28
AE26
AC26
AH30
AH29
AE29
M28
V25
AB29
AD28
AD29
AC28
AC29
AA28
AA29
Y28
Y29
AF29
AD27
AE28
AB28
M29
V26
M26
M27
AK21
AJ23
AJ22
AK22
AJ24
AK24
AG23
AG24
AK25
AJ25
AH28
AJ29
AH27
AG26
AJ5
AH5
AJ4
AK4
AH4
AF4
AJ3
AK3
AH3
AJ2
AH2
AH1
AG3
AG1
AG2
AF3
AF2
AF5
AH6
AJ6
AK6
AH7
AK7
AJ7
AH8
AJ8
AH9
AJ9
AK9
AH10
AE6
AG6
AF6
AE7
AF7
AE8
AG8
AF8
AE9
AF9
AG10
AF10
AJ10
AK10
AJ11
AH11
AK16
AH16
AH17
AJ16
AH18
AJ17
AK19
AH19
AK18
AJ18
AG16
AF16
AG17
AF17
AF18
AE18
AH20
AG20
AF19
AG19
AE12
AG12
AJ13
AH14
AJ14
AH15
AJ15
AK15
AH13
AK13
AE13
AE14
AF12
AK27
AJ27
AG25
AH25
AH26
AF25
AF24
AF26
B6
E8
AC25
AJ26
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
C/BE#0
C/BE#1
C/BE#2
C/BE#3
PCICLK
RST#
REQ#
GNT#
PAR
STOP#
DEVSEL#
TRDY#
IRDY#
FRAME#
INTA#
WBF#
STP_AGP#
AGP_BUSY#
RBF#
AD_STBF0
AD_STBF1
SB_STBF
SBA0
SBA1
SBA2
SBA3
SBA4
SBA5
SBA6
SBA7
ST0
ST1
ST2
SB_STBS
AD_STBS0
AD_STBS1
AGPREF
AGPTEST
R2SET
C_R
Y_G
COMP_B
H2SYNC
V2SYNC
DDC3CLK
DDC3DATA
SSIN
SSOUT
XTALIN
XTALOUT
TESTEN
SUS_STAT#
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
ROMCS#
ZV_LCDDATA0
ZV_LCDDATA1
ZV_LCDDATA2
ZV_LCDDATA3
ZV_LCDDATA4
ZV_LCDDATA5
ZV_LCDDATA6
ZV_LCDDATA7
ZV_LCDDATA8
ZV_LCDDATA9
ZV_LCDDATA10
ZV_LCDDATA11
ZV_LCDDATA12
ZV_LCDDATA13
ZV_LCDDATA14
ZV_LCDDATA15
ZV_LCDDATA16
ZV_LCDDATA17
ZV_LCDDATA18
ZV_LCDDATA19
ZV_LCDDATA20
ZV_LCDDATA21
ZV_LCDDATA22
ZV_LCDDATA23
ZV_LCDCNTL0
ZV_LCDCNTL1
ZV_LCDCNTL2
ZV_LCDCNTL3
TXOUT_L0N
TXOUT_L0P
TXOUT_L1N
TXOUT_L1P
TXOUT_L2N
TXOUT_L2P
TXOUT_L3N
TXOUT_L3P
TXCLK_LN
TXCLK_LP
TXOUT_U0N
TXOUT_U0P
TXOUT_U1N
TXOUT_U1P
TXOUT_U2N
TXOUT_U2P
TXOUT_U3N
TXOUT_U3P
TXCLK_UN
TXCLK_UP
DIGON
BLON
TX0M
TX0P
TX1M
TX1P
TX2M
TX2P
TXCM
TXCP
DDC2CLK
DDC2DATA
HPD1
R
G
HSYNC
VSYNC
RSET
DDC1DATA
DDC1CLK
AUXWIN
TEST_MCLK
TEST_YCLK
AGP8X_DET#
B
R748 1K/NA 0402 1 2
TP6 1
R773 0/NA 0402 1 2
C123
1000P/NA
0402
50V
+/-20%
1
2
R110
1.02K/NA
0402
1%
1
2
R62 1K/NA 0402 1 2
C110
10U/NA
6.3V
0805
10%
1
2
R772 150/NA 0402
1%
1 2
R737 10K/NA 0402 1 2
C734
0.01U/NA
0402
50V
+80-20%
1
2
TP53
1
C755
0.1U/NA
0402
16V
10%
1
2
C128
0.01U/NA
0402
50V
+80-20%
1
2
R734 10K/NA 0402 1 2
R768
75/NA
0402
5%
1
2
R84 100K/NA
0402 5%
1 2
SW701
HDS402/NA
SW_HDS402
1
2
4
3
TP8 1
TP2 1
TP14 1
R82 10K/NA
0402
1 2
TP11 1
C146
10U/NA
6.3V
0805
10%
1
2
R743 10K/NA 0402 1 2
TP7 1
R58 10K/NA
0402
1 2
R775 0/NA 0402 1 2
C149
0.01U/NA
0402
50V
10%
1
2
R83 1K/NA 0402 1 2
C126
1000P/NA
0402
50V
+/-20%
1
2
R85
0/NA
0402 5%
1 2
R101
20K/NA
0402
1% 1
2
R774 0/NA 0402 1 2
R67 10K/NA 0402 1 2
R733 10K/NA 0402 1 2
R76 10K/NA 0402 1 2
RP718
0*4/NA
1206
1
2
3
4
8
7
6
5
R61 10K/NA 0402 1 2
C760
47P/NA
0402
25V
+/-10%
1
2
R762
715/NA 0603 5%
1 2
TP12 1
R405 0/NA
0402 5%
1 2
R121 10K/NA
0402 5%
1 2
R749 1K/NA 0402 1 2
R77 33/NA 0402 5% 1 2
R742 10K/NA 0402 1 2
R122 0/NA 0402 5% 1 2
R752
0/NA 0402 5% 1 2
U711
P2779A/NA
SO8
1
2
3
4 5
6
7
8
XIN/CLKIN
XOUT
PD#
LF VSS
MODOUT
REF
VDD
C757
1U/NA
0402
10V
+80-20%
1
2
C773 22P/NA
0402 50V +/-10%
1 2
TP9 1
TP1 1
C120
0.01U/NA
0402
50V
+80-20%
1
2
R86
10K/NA
0402
5%
1
2
R779 0/NA 0402 5% 1 2
R771
0/NA
0402
5%
1
2
C72
0.1U/NA
0402
50V
+80-20%
1
2
R406 0/NA
0402 5%
1 2
U703A
74AHC14_V
TSSOP14
1 2
1
4
7
C759
47P/NA
0402
25V
+/-10%
1
2
R105 22/NA
0402 5%
1 2
R765
8.2K/NA
0402
5%
1
2
L711
120Z/100M/NA
2012
1
2
TP15 1
TP702 1
C761
47P/NA
0402
25V
+/-10%
1
2
C733
0.01U/NA
0402
50V
+80-20%
1
2
R118 0/NA 0402 5% 1 2
R57 10K/NA 0402 1 2
TP10 1
R79
2.21K/NA
0402
1%
1
2
C122
10U/NA
6.3V
0805
10%
1
2
R120
1.02K/NA
0402
1%
1
2
TP54
1
TP55
1
R778
33/NA
0402 5% 1 2
R407 0/NA
0402 5%
1 2
R767
75/NA
0402
5%
1
2
C765
22P/NA
0402
50V
+/-10%
1
2
R102 1K/NA
0402 5%
1 2
R738 10K/NA 0402 1 2
R119
40.2/NA 0402 1%
1 2
R770 0/NA 0402 1 2
R735 10K/NA 0402 1 2
R100 0/NA 0402 1 2
C69
0.01U/NA
0402
50V
+80-20%
1
2
R72
2.21K/NA
0402
1%
1
2
C68
0.01U/NA
0402
50V
+80-20%
1
2
R140 47K/NA 0402 5% 1 2
R739 10K/NA 0402 1 2
TP13 1
R777
180/NA
0603
1%
1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
CONNECT LVDDR_25 TO 1.8V FOR M9
, TO 2.5V FOR M10
1.8V for M9 , 1.5V for M10
ATI M10-P(2/4)
PCB 316680900001/ASSY 411680900011 R01
8050 MOTHERB/D
C
Title
Size
Document
Number
Rev
Date: Sheet of
GND
VDD_CORE
GND
+3V
GND
AVDD_1.8
GND
GND
VGA_1.2/1.0
VGA_1.2/1.0
VDD_DAC2.5
VDD_MEM_IO
A2VDDQ_1.8
AVDD_1.8
VDD_CORE
VDD_PLL1.8
GND
VDD_MEM_IO
AGP_VDDQ
+1.8V
VDD_PLL1.8
VDD_MEMPLL1.8
VDD_MEM_IO
VDD_PNLIO1.8
GND
VDD_MCLK2.5
AGP_VDDQ
VDD_PNLPLL1.8
GND
VDD_MEM_IO
GND
+1.5V
VDD_DAC2.5
GND
VDD_PNLIO1.8
VDD_CORE1.5
VDD_PNLPLL1.8
+1.8V
GND
VDD_MEMPLL1.8
VDDDI_1.8
VDD_PNLIO2.5
VDD_PNLIO2.5
GND
A2VDDQ_1.8
VDD_CORE1.5
GND
GND
VDD_MEM_IO
VDD_CORE1.8
VDDDI_1.8
+2.5V_M10
+2.5V_M10
VDD_MCLK2.5
GND
VDD_MEM_IO
L35 120Z/100M/NA
2012
1 2
C135
0.1U/NA
0402
50V
+80-20%
1
2
L705 120Z/100M/NA
2012
1 2
C132
0.01U/NA
0402
50V
+80-20%
1
2
C136
0.1U/NA
0402
50V
+80-20%
1
2
C125
0.1U/NA
0402
50V
+80-20%
1
2
C91
0.01U/NA
0402
50V
+80-20%
1
2
C54
0.1U/NA
0402
50V
+80-20%
1
2
C762
10U/NA
6.3V
0805
10%
1
2
C80
0.1U/NA
0402
50V
+80-20%
1
2
C111
0.1U/NA
0402
50V
+80-20%
1
2
C769
0.1U/NA
0402
50V
+80-20%
1
2
C152
0.1U/NA
0402
50V
+80-20%
1
2
C107
0.1U/NA
0402
50V
+80-20%
1
2
C737
0.1U/NA
0402
50V
+80-20%
1
2
C127
10U/NA
6.3V
0805
10%
1
2
C81
0.1U/NA
0402
50V
+80-20%
1
2
C108
1000P/NA
0402
50V
+/-20%
1
2
C77
0.01U/NA
0402
50V
+80-20%
1
2
C96
0.01U/NA
0402
50V
+80-20%
1
2
R55
0/NA
0805
1
2
C88
0.1U/NA
0402
50V
+80-20%
1
2
C74
1000P/NA
0402
50V
+/-20%
1
2
U710D
MOBILITY-M10-P/NA
BGA644_64_1MM
AC13
AC15
AC17
AD13
AD15
M12
M13
M14
M17
M18
M19
N12
N13
N14
N17
N18
N19
P12
P13
P14
P17
P18
P19
U12
U13
U14
U17
U18
U19
V12
V13
V14
V17
V18
V19
W12
W13
W14
W17
W18
W19
W30
Y27
AA23
AA24
AB30
AC23
AC27
AE30
AF27
J30
M23
M24
N30
P23
P27
T23
T24
T30
U27
V23
V24
A15
A21
A28
A3
A9
AA1
AA4
AA7
AA8
AD4
B1
B30
D11
D14
D17
D20
D23
D26
D5
D8
E27
F4
G10
G13
G15
G19
G22
G27
G7
H10
H13
H15
H17
H19
H22
J1
J23
J24
J4
J7
J8
L27
L8
M4
N7
N8
R1
R4
T7
T8
V4
V7
V8
AC11
AC20
H11
H20
L23
P8
Y23
Y8
M15
R19
T12
W16
F18
N6
AE24
AE22
AF13
AF14
AE15
AF21
AE17
AE20
AJ20
A7
AK28
AK12
AG21
AH21
AF22
AH24
AC19
AC21
AC22
AC8
AD19
AD21
AD22
AD7
AC9
AD10
AD9
AG7
AC10
D13
D19
N4
T4
AB4
D10
D25
E4
VDDC_0
VDDC_1
VDDC_2
VDDC_3
VDDC_4
VDDC_5
VDDC_6
VDDC_7
VDDC_8
VDDC_9
VDDC_10
VDDC_11
VDDC_12
VDDC_13
VDDC_14
VDDC_15
VDDC_16
VDDC_17
VDDC_18
VDDC_19
VDDC_20
VDDC_21
VDDC_22
VDDC_23
VDDC_24
VDDC_25
VDDC_26
VDDC_27
VDDC_28
VDDC_29
VDDC_30
VDDC_31
VDDC_32
VDDC_33
VDDC_34
VDDC_35
VDDC_36
VDDC_37
VDDC_38
VDDC_39
VDDC_40
VDDP_19
VDDP_20
VDDP_0
VDDP_1
VDDP_2
VDDP_3
VDDP_4
VDDP_5
VDDP_6
VDDP_7
VDDP_8
VDDP_9
VDDP_10
VDDP_11
VDDP_12
VDDP_13
VDDP_14
VDDP_15
VDDP_16
VDDP_17
VDDP_18
VDDR1_0
VDDR1_1
VDDR1_2
VDDR1_3
VDDR1_4
VDDR1_5
VDDR1_6
VDDR1_7
VDDR1_8
VDDR1_9
VDDR1_10
VDDR1_11
VDDR1_12
VDDR1_13
VDDR1_14
VDDR1_15
VDDR1_16
VDDR1_17
VDDR1_18
VDDR1_19
VDDR1_20
VDDR1_21
VDDR1_22
VDDR1_23
VDDR1_24
VDDR1_25
VDDR1_26
VDDR1_27
VDDR1_28
VDDR1_29
VDDR1_30
VDDR1_31
VDDR1_32
VDDR1_33
VDDR1_34
VDDR1_35
VDDR1_36
VDDR1_37
VDDR1_38
VDDR1_39
VDDR1_40
VDDR1_41
VDDR1_42
VDDR1_43
VDDR1_44
VDDR1_45
VDDR1_46
VDDR1_47
VDDR1_48
VDDR1_49
VDDR1_50
VDDR1_51
VDDR1_52
VDDC15_0
VDDC15_1
VDDC15_2
VDDC15_3
VDDC15_4
VDDC15_5
VDDC15_6
VDDC15_7
VDDCI_0
VDDCI_1
VDDCI_2
VDDCI_3
VDDRH0
VDDRH1
VDD1DI
VDD2DI
TXVDDR_0
TXVDDR_1
LVDDR_18_0
LVDDR_18_1
LVDDR_25_0
LVDDR_25_1
LPVDD
MPVDD
PVDD
TPVDD
A2VDD_0
A2VDD_1
A2VDDQ
AVDD
VDDR3_0
VDDR3_1
VDDR3_2
VDDR3_3
VDDR3_4
VDDR3_5
VDDR3_6
VDDR3_7
VDDR4_1
VDDR4_2
VDDR4_3
VDDR4_4
VDDR4_0
VDDR1_53
VDDR1_54
VDDR1_55
VDDR1_56
VSS_119
VSS_120
VSS_121
VSS_122
C95
0.01U/NA
0402
50V
+80-20%
1
2
L710 120Z/100M/NA
2012
1 2
C767
0.1U/NA
0402
50V
+80-20%
1
2
C758
10U/NA
6.3V
0805
10%
1
2
C90
0.1U/NA
0402
50V
+80-20%
1
2
U710E
MOBILITY-M10-P/NA
BGA644_64_1MM
A10
A16
A2
A22
A29
AA30
AB1
AB23
AB24
AB27
AB7
AB8
AC12
AC14
AC16
AC18
AC4
AD12
AD16
AD18
AD25
AD30
AE27
AG11
AG15
AG18
AG22
AG27
AG5
AG9
AJ1
AJ30
AK2
AK29
C1
C28
C3
C30
D12
D15
D18
D21
D24
D27
D4
D6
D9
F27
G12
G16
G18
G21
G24
G9
H12
H14
H16
H18
H21
H23
H27
H4
H8
H9
K1
K23
K24
K27
K30
K7
AE23
AE21
F19
M6
AG13
AG14
AH12
AH23
AD24
AF23
AH22
AJ21
AJ19
AE16
AE19
AF15
AF20
A6
AJ28
AJ12
P15
P16
P4
R12
R13
R14
R15
R16
R17
R18
R23
K8
U23
L4
M16
M30
M7
M8
R24
R30
R7
R8
T1
T13
T14
T15
T16
T17
T18
T19
T27
U15
U16
U4
U8
V15
V16
V30
W15
W23
W24
W27
W7
W8
Y4
N15
N16
N23
N24
N27
VSS_0
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS1DI
VSS2DI
VSSRH0
VSSRH1
TXVSSR_0
TXVSSR_1
TXVSSR_2
AVSSN
AVSSQ
A2VSSQ
A2VSSN_0
A2VSSN_1
LPVSS
LVSSR_0
LVSSR_1
LVSSR_2
LVSSR_3
MPVSS
PVSS
TPVSS
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_70
VSS_123
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
C106
0.01U/NA
0402
50V
+80-20%
1
2
C139
0.1U/NA
0402
50V
+80-20%
1
2
C84
10U/NA
6.3V
0805
10%
1
2
L26 120Z/100M/NA
2012
1 2
C105
0.1U/NA
0402
50V
+80-20%
1
2
L31 120Z/100M/NA
2012
1 2
C98
10U/NA
6.3V
0805
10%
1
2
C153
0.1U/NA
0402
50V
+80-20%
1
2
C764
0.1U/NA
0402
50V
+80-20%
1
2
C86
0.1U/NA
0402
50V
+80-20%
1
2
L29 120Z/100M/NA
2012
1 2
C124
0.1U/NA
0402
50V
+80-20%
1
2
C138
10U/NA
6.3V
0805
10%
1
2
C89
10U/NA
6.3V
0805
10%
1
2
C76
1000P/NA
0402
50V
+/-20%
1
2
C113
0.1U/NA
0402
50V
+80-20%
1
2
C85
0.01U/NA
0402
50V
+80-20%
1
2
C109
0.1U/NA
0402
50V
+80-20%
1
2
C117
0.01U/NA
0402
50V
+80-20%
1
2
C79
10U/NA
6.3V
0805
10%
1
2
C119
0.1U/NA
0402
50V
+80-20%
1
2
C66
0.01U/NA
0402
50V
+80-20%
1
2
C44
1000P/NA
0402
50V
+/-20%
1
2
C114
10U/NA
6.3V
0805
10%
1
2
R94 0/NA
0805
1 2
L28
120Z/100M/NA
2012
1
2
C75
0.1U/NA
0402
50V
+80-20%
1
2
C78
10U/NA
6.3V
0805
10%
1
2
C763
0.1U/NA
0402
50V
+80-20%
1
2
C99
1000P/NA
0402
50V
+/-20%
1
2
C58
0.01U/NA
0402
50V
+80-20%
1
2
C137
0.01U/NA
0402
50V
+80-20%
1
2
C116
0.1U/NA
0402
50V
+80-20%
1
2
C739
10U/NA
6.3V
0805
10%
1
2
C101
1000P/NA
0402
50V
+/-20%
1
2
C112
10U/NA
6.3V
0805
10%
1
2
+
C743
150U/NA
7343
2.5V
1
2
C130
0.1U/NA
0402
50V
+80-20%
1
2
C118
0.1U/NA
0402
50V
+80-20%
1
2
C141
10U/NA
6.3V
0805
10%
1
2
C100
1000P/NA
0402
50V
+/-20%
1
2
L712 120Z/100M/NA
2012
1 2
C747
0.1U/NA
0402
50V
+80-20%
1
2
L32 120Z/100M/NA
2012
1 2
C746
0.1U/NA
0402
50V
+80-20%
1
2
C60
0.01U/NA
0402
50V
+80-20%
1
2
C134
0.1U/NA
0402
50V
+80-20%
1
2
L709 120Z/100M/NA
2012
1 2
C103
0.1U/NA
0402
50V
+80-20%
1
2
L27 120Z/100M/NA
2012
1 2
C55
10U/NA
6.3V
0805
10%
1
2
C121
10U/NA
6.3V
0805
10%
1
2
C115
0.1U/NA
0402
50V
+80-20%
1
2
L24 120Z/100M/NA
2012
1 2
C97
1000P/NA
0402
50V
+/-20%
1
2
C92
10U/NA
6.3V
0805
10%
1
2
C736
10U/NA
6.3V
0805
10%
1
2
C82
10U/NA
6.3V
0805
10%
1
2
L34 120Z/100M/NA
2012
1 2
L39 120Z/100M/NA
2012
1 2
C738
0.1U/NA
0402
50V
+80-20%
1
2
L30 120Z/100M/NA
2012
1 2
C147
1000P/NA
0402
50V
+/-20%
1
2
C129
0.1U/NA
0402
50V
+80-20%
1
2
C164
10U/NA
6.3V
0805
10%
1
2
C87
1000P/NA
0402
50V
+/-20%
1
2
L33 120Z/100M/NA
2012
1 2
C102
0.1U/NA
0402
50V
+80-20%
1
2
C167
10U/NA
6.3V
0805
10%
1
2
C83
0.1U/NA
0402
50V
+80-20%
1
2
C140
0.1U/NA
0402
50V
+80-20%
1
2
C50
10U/NA
6.3V
0805
10%
1
2
L40 120Z/100M/NA
2012
1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
MEMVMODE=1.8V
MEMVMODE1=GND
MEMVMODE1=1.8V
FOR 2.5V VDDR1
MEMVMODE=GND
FOR 1.8V VDDR1(ELPIDA)
ATI M10-P(3/4)
PCB 316680900001/ASSY 411680900011 R01
8050 MOTHERB/D
C
Title
Size
Document
Number
Rev
Date: Sheet of
VMDB[0..63]
VDQMA#[0..7]
VQSA[0..7]
VQSB[0..7]
VDQMB#[0..7]
VMDA[0..63]
MEMA_MD2
MEMA_MD3
MEMA_MD4
MEMA_MD5
MEMA_MD8
MEMA_MD10
MEMA_MD6
MEMA_MD9
MEMA_MD7
MEMA_MD11
MEMA_MD14
MEMA_MD16
MEMA_MD12
MEMA_MD15
MEMA_MD13
MEMA_MD17
MEMA_MD20
MEMA_MD22
MEMA_MD18
MEMA_MD21
MEMA_MD19
MEMA_MD23
MEMA_MD26
MEMA_MD28
MEMA_MD24
MEMA_MD27
MEMA_MD25
MEMA_MD29
MEMA_MD32
MEMA_MD34
MEMA_MD30
MEMA_MD33
MEMA_MD31
MEMA_MD35
MEMA_MD38
MEMA_MD40
MEMA_MD36
MEMA_MD39
MEMA_MD37
MEMA_MD41
MEMA_MD44
MEMA_MD46
MEMA_MD42
MEMA_MD45
MEMA_MD43
MEMA_MD47
MEMA_MD54
MEMA_MD49
MEMA_MD52
MEMA_MD55
MEMA_MD59
MEMA_MD53
MEMA_MD58
MEMA_MD50
MEMA_MD57
MEMA_MD48
MEMA_MD56
MEMA_MD51
MEMA_MD61
MEMA_MD63
MEMA_MD62
MEMA_MD60
MEMA_MA0
MEMA_MA1
MEMA_MA2
MEMA_MA3
MEMA_MA4
MEMA_MA9
MEMA_MA5
MEMA_MA6
MEMA_MA7
MEMA_MA8
MEMA_MA10
MEMA_MA11
MEMA_MA12
MEMA_MA13
MEMA_DQM#4
MEMA_DQM#0
MEMA_DQM#1
MEMA_DQM#2
MEMA_DQM#3
MEMA_DQM#5
MEMA_DQM#7
MEMA_DQM#6
MEMA_QSA2
MEMA_QSA5
MEMA_QSA4
MEMA_QSA3
MEMA_QSA7
MEMA_QSA6
MEMA_QSA1
MEMA_QSA0
MEMA_RAS#
MEMA_CAS#
MEMA_WE#
MEMA_CS0#
MEMA_CS1#
MEMA_CKE
MEMA_MD22
MEMA_MD12
MEMA_MD7
MEMA_MD35
MEMA_MD15
MEMA_MD10
MEMA_MD42
MEMA_MD29
MEMA_MD48
MEMA_MD4
MEMA_MD21
MEMA_MD31
MEMA_MD8
MEMA_MD34
MEMA_MD13
MEMA_MD25
MEMA_MD19
MEMA_MD61
MEMA_MD30
MEMA_MD57
MEMA_MD51
MEMA_MD59
MEMA_MD6
MEMA_MD37
MEMA_MD52
MEMA_MD32
MEMA_MD53
MEMA_MD16
MEMA_MD11
MEMA_MD58
MEMA_MD27
MEMA_MD50
MEMA_MD40
MEMA_MD9
MEMA_MD54
MEMA_MD63
MEMA_MD0
MEMA_MD55
MEMA_MD33
MEMA_MD43
MEMA_MD20
MEMA_MD47
MEMA_MD41
MEMA_MD26
MEMA_MD46
MEMA_MD38
MEMA_MD49
MEMA_MD23
MEMA_MD17
MEMA_MD24
MEMA_MD45
MEMA_MD18
MEMA_MD60
MEMA_MD1
MEMA_MD36
MEMA_MD62
MEMA_MD14
MEMA_MD5
MEMA_MD28
MEMA_MD44
MEMA_MD56
MEMA_MD39
MEMA_CLK0
MEMA_CLK0#
MEMA_CLK1
MEMA_CLK1#
VCLKA0
VCLKA#0
VCLKA1
VCLKA#1
VCLKB0
VCLKB1
VCLKB#1
VCLKB#0
DIMA_0
DIMA_1
MEMA_MD0
MEMA_MD1
MEMA_QSA4
MEMA_DQM#7
MEMA_DQM#0
MEMA_DQM#6
MEMA_DQM#2
MEMA_QSA7
MEMA_DQM#4
MEMA_DQM#1
MEMA_QSA2
MEMA_QSA0
MEMA_DQM#5
MEMA_QSA5
MEMA_DQM#3
MEMA_QSA1
MEMA_QSA3
MEMA_RAS#
MEMA_CAS#
MEMA_WE#
VDQMA#6
VDQMA#3
VDQMA#2
VDQMA#5
VDQMA#4
VDQMA#1
VDQMA#7
VQSA3
VQSA7
VQSA5
VQSA0
VQSA4
VQSA1
VMDB49
VMDB31
VMDB39
VMDB50
VMDB63
VMDB52
VMDB20
VMDB22
VMDB29
VMDB8
VMDB5
VMDB28
VMDB32
VMDB37
VMDB44
VMDB30
VMDB55
VMDB1
VMDB25
VMDB54
VMDB60
VMDB45
VMDB53
VMDB7
VMDB42
VMDB56
VMDB24
VMDB6
VMDB18
VMDB17
VDQMB#6
VDQMB#7
VDQMB#4
VDQMB#3
VDQMB#5
VDQMB#1
VQSB3
VQSB7
VQSB1
VQSB6
VQSB0
VQSB2
VDQMA#0
VQSA2
VQSA6 MEMA_QSA6
MEMB_QSA0
MEMB_DQM#5
MEMB_QSA1
MEMB_QSA5
MEMB_DQM#7
MEMB_QSA6
MEMB_QSA4
MEMB_QSA7
MEMB_QSA2
MEMB_DQM#4
MEMB_DQM#1
MEMB_DQM#0
MEMB_DQM#6
MEMB_QSA3
MEMB_DQM#3
VDQMB#0
VDQMB#2
VQSB4
VQSB5
MEMB_DQM#2
VGA_THERMDC
VGA_THERMDA
VMDA60
VMDA34
VMDA27
VMDA20
VMDA49
VMDA16
VMDA4
VMDA28
VMDA10
VMDA14
VMDA44
VMDA47
VMDA58
VMDA21
VMDA7
VMDA12
VMDA18
VMDA50
VMDA13
VMDA39
VMDA53
VMDA3
VMDA32
VMDA63
VMDA23
VMDA31
VMDA1
VMDA9
VMDA19
VMDA15
VMDA6
VMDA11
VMDA17
VMDA8
VMDA5
VMDA26
VMDA25
VMDA29
VMDA35
VMDA22
VMDA33
VMDA30
VMDA24
VMDA42
VMDA41
VMDA36
VMDA45
VMDA48
VMDA51
VMDA38
VMDA43
VMDA46
VMDA40
VMDA37
VMDA57
VMDA52
VMDA61
VMDA55
VMDA54
VMDA59
VMDA62
VMDA56
MEMB_MD14
MEMB_MD43
MEMB_MD63
MEMB_MD16
MEMB_MD40
MEMB_MD12
MEMB_MD59
MEMB_MD19
MEMB_MD24
MEMB_MD18
MEMB_MD50
MEMB_MD22
MEMB_MD48
MEMB_MD7
MEMB_MD26
MEMB_MD20
MEMB_MD34
MEMB_MD38
MEMB_MD55
MEMB_MD31
MEMB_MD10
MEMB_MD2
MEMB_MD51
MEMB_MD11
MEMB_MD29
MEMB_MD37
MEMB_MD5
MEMB_MD52
MEMB_MD53
MEMB_MD61
MEMB_MD15
MEMB_MD42
MEMB_MD39
MEMB_MD46
MEMB_MD13
MEMB_MD6
MEMB_MD35
MEMB_MD49
MEMB_MD27
MEMB_MD41
MEMB_MD8
MEMB_MD28
MEMB_MD54
MEMB_MD57
MEMB_MD36
MEMB_MD0
MEMB_MD32
MEMB_MD56
MEMB_MD9
MEMB_MD60
MEMB_MD25
MEMB_MD23
MEMB_MD47
MEMB_MD4
MEMB_MD1
MEMB_MD33
MEMB_MD62
MEMB_MD17
MEMB_MD45
MEMB_MD21
MEMB_MD30
MEMB_MD44
MEMB_MD3
MEMB_MD58
VMDB0
VMDB9
VMDB12
VMDB15
VMDB3
VMDB11
VMDB2
VMDB14
VMDB13
VMDB10
VMDB4
VMDB21
VMDB16
VMDB19
VMDB27
VMDB23
VMDB26
VMDB40
VMDB38
VMDB41
VMDB47
VMDB35
VMDB43
VMDB34
VMDB46
VMDB36
VMDB33
VMDB48
VMDB57
VMDB51
VMDB59
VMDB62
VMDB61
VMDB58
DIMA_1
DIMA_0 VDIMA_0
VDIMA_1
DIMB_0
DIMB_1 VDIMB_1
VDIMB_0
MEMA_MD2
MEMA_MD3
VMDA0
VMDA2
MEMA_CS1#
VCSB#1 MEMB_CS1#
MEMB_MA13
MEMB_MA3
MEMB_MD48
MEMB_MD9
MEMB_MD51
MEMB_MD30
MEMB_MD0
MEMB_DQM#0
MEMB_MA11
MEMB_MD50
MEMB_MD39
MEMB_MD12
MEMB_MD4
MEMB_CS1#
MEMB_WE#
MEMB_DQM#3
MEMB_DQM#2
MEMB_MD47
MEMB_MD44
MEMB_MD24
MEMB_MD23
MEMB_QSA3
MEMB_MD14
MEMB_MD5
MEMB_MD2
DIMB_1
MEMB_CKE
MEMB_MD49
MEMB_MD45
MEMB_MD28
MEMB_MD26
MEMB_MD18
DIMB_0
MEMB_QSA5
MEMB_MD63
MEMB_MD22
MEMB_MD10
MEMB_QSA4
MEMB_MD56
MEMB_MD43
MEMB_MD34
MEMB_MD11
MEMB_MD8
MEMB_MD7
MEMB_MD3
MEMB_MA5
MEMB_MD62
MEMB_MD40
MEMB_MD15
MEMB_QSA6
MEMB_QSA2
MEMB_MD57
MEMB_MD52
MEMB_MD25
MEMB_MD6
MEMB_CS0#
MEMB_DQM#5
MEMB_MD29
MEMB_QSA7
MEMB_DQM#7
MEMB_MA12
MEMB_MA9
MEMB_MA8
MEMB_MD55
MEMB_MD53
MEMB_MD42
MEMB_MD41
MEMB_MD32
MEMB_CAS#
MEMB_QSA0
MEMB_MD21
MEMB_MD13
MEMB_QSA1
MEMB_DQM#6
MEMB_MA7
MEMB_MA6
MEMB_MD61
MEMB_MD59
MEMB_MD37
MEMB_MD36
MEMB_MD33
MEMB_MD17
MEMB_RAS#
MEMB_MA10
MEMB_MD20
MEMB_MD19
MEMB_DQM#4
MEMB_DQM#1
MEMB_MA0
MEMB_MD60
MEMB_MD54
MEMB_MD46
MEMB_MD38
MEMB_MD31
MEMB_MD27
MEMB_MD1
MEMB_MA4
MEMB_MA2
MEMB_MD58
MEMB_MD35
MEMB_MD16
MEMB_MA1
VCSA#1
MEMB_MA5
MEMB_MA7
MEMB_MA4
MEMB_MA6
MEMB_MA9
MEMB_MA11
MEMB_MA8
VCKEB MEMB_CKE
MEMA_MA3
MEMA_MA0
MEMA_CS0#
MEMA_MA10
MEMA_MA1
MEMA_MA2
MEMA_MA13
MEMA_MA12
VRASA#
VWEA#
VCSA#0
VCASA#
VCASB#
VCSB#0
MEMB_RAS# VRASB#
VWEB#
MEMB_CAS#
MEMB_CS0#
MEMB_WE#
MEMB_MA10
MEMB_MA13
VMB[0..13]
VMB13
MEMB_MA1
VMB12
VMB4
VMB11
MEMB_MA0
VMB9
VMB0
VMB10
VMB3
VMB8
MEMB_MA12
VMB5
VMB7
VMB6
MEMB_MA3
MEMB_MA2 VMB2
VMB1
VCKEA
VMA0
MEMA_MA11
VMA13
VMA5
MEMA_CKE
MEMA_MA8
VMA2
MEMA_MA5
VMA[0..13]
VMA9
VMA1
VMA10
MEMA_MA9
VMA12
MEMA_MA6
VMA3
VMA6
VMA7 MEMA_MA7
MEMA_MA4
VMA8
VMA4
VMA11
VCLKA0 10
VCLKA#0 10
VCLKA1 10
VCLKA#1 10
VCLKB1 10
VCLKB#0 10
VCLKB#1 10
VCLKB0 10
VMDB[0..63] 10
VMDA[0..63] 10
VDQMA#[0..7] 10
VQSA[0..7] 10
VDQMB#[0..7] 10
VQSB[0..7] 10
VDIMA_0 10
VDIMA_1 10
VDIMB_1 10
VDIMB_0 10
VCSB#1 10
VGA_THERMDA 22
VGA_THERMDC 22
VCSA#1 10
VMB[0..13] 10
VCSB#0 10
VCKEB 10
VRASB# 10
VWEB# 10
VCASB# 10
VCSA#0 10
VCKEA 10
VMA[0..13] 10
VRASA# 10
VWEA# 10
VCASA# 10
AGP_VDDQ
GND
GND
GND
+3V
GND GND
GND
GND
VDD_CORE1.8
VDD_MEM_IO
GND
GND
GND
VDD_MEM_IO
GND
R741
1K/NA 0402 1%
1 2
U710C
MOBILITY-M10-P/NA
BGA644_64_1MM
D7
F7
E7
G6
G5
F5
E5
C4
B5
C5
A4
B4
C2
D3
D1
D2
G4
H6
H5
J6
K5
K4
L6
L5
G2
F3
H2
E2
F2
J3
F1
H3
U6
U5
U3
V6
W5
W4
Y6
Y5
U2
V2
V1
V3
W3
Y2
Y3
AA2
AA6
AA5
AB6
AB5
AD6
AD5
AE5
AE4
AB2
AB3
AC2
AC3
AD3
AE1
AE2
AE3
N5
M1
M3
L3
L2
M2
M5
P6
N3
K2
K3
J2
P5
P3
E6
B2
J5
G3
W6
W2
AC6
AD2
F6
B3
K6
G1
V5
W1
AC5
AD1
R2
T5
T6
R5
R6
R3
N1
N2
T2
T3
C6
C7
C8
B7
P2
B8
E3
AA3
DQB0
DQB1
DQB2
DQB3
DQB4
DQB5
DQB6
DQB7
DQB8
DQB9
DQB10
DQB11
DQB12
DQB13
DQB14
DQB15
DQB16
DQB17
DQB18
DQB19
DQB20
DQB21
DQB22
DQB23
DQB24
DQB25
DQB26
DQB27
DQB28
DQB29
DQB30
DQB31
DQB32
DQB33
DQB34
DQB35
DQB36
DQB37
DQB38
DQB39
DQB40
DQB41
DQB42
DQB43
DQB44
DQB45
DQB46
DQB47
DQB48
DQB49
DQB50
DQB51
DQB52
DQB53
DQB54
DQB55
DQB56
DQB57
DQB58
DQB59
DQB60
DQB61
DQB62
DQB63
MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
MAB13
DQMB#0
DQMB#1
DQMB#2
DQMB#3
DQMB#4
DQMB#5
DQMB#6
DQMB#7
QSB0
QSB1
QSB2
QSB3
QSB4
QSB5
QSB6
QSB7
RASB#
CASB#
WEB#
CSB0#
CSB1#
CKEB
CLKB0
CLKB0#
CLKB1
CLKB1#
MEMVMODE0
MEMVMODE1
MEMTEST
MVREFD
MAB14
MVREFS
DIMB_0
DIMB_1
RP711
24*4/NA
1206
1
2
3
4
8
7
6
5
RP705
24*4/NA
1206
1
2
3
4
8
7
6
5
R42
56/NA
0402 5%
1 2
C729 470P/NA
0402 50V 10%
1 2
R51 10/NA 0402 5% 1 2
R74 4.7K/NA
0402 5%
1 2
R750
47/NA
0402
5%
1
2
R109 24/NA 0402 5% 1 2
RP18
24*4/NA
1206
1
2
3
4
8
7
6
5
R758 56/NA
0402 5%
1 2
RP12
24*4/NA
1206
1
2
3
4
8
7
6
5
RP3
24*4/NA
1206
1
2
3
4
8
7
6
5
RP9
24*4/NA
1206
1
2
3
4
8
7
6
5
RP708
24*4/NA
1206
1
2
3
4
8
7
6
5
RP23
24*4/NA
1206
1
2
3
4
8
7
6
5
RP710
24*4/NA
1206
1
2
3
4
8
7
6
5
R35 24/NA 0402 5% 1 2
C751 470P/NA
0402 50V 10%
1 2
R98 0/NA 5%
0402G_DFS
1 2
R756 56/NA
0402 5%
1 2
RP4
24*4/NA
1206
1
2
3
4
8
7
6
5
R757 10/NA 0402 5% 1 2
R29 24/NA 0402 5% 1 2
RP17
24*4/NA
1206
1
2
3
4
8
7
6
5
RP11
24*4/NA
1206
1
2
3
4
8
7
6
5
R727 10/NA 0402 5% 1 2
R731 24/NA 0402 5% 1 2
R716 24/NA 0402 5% 1 2
R41 24/NA 0402 5% 1 2
R761 10/NA 0402 5% 1 2
R69 4.7K/NA
0402 5%
1 2
R723 24/NA 0402 5% 1 2
RP21
24*4/NA
1206
1
2
3
4
8
7
6
5
R725 56/NA
0402 5%
1 2
RP712
24*4/NA
1206
1
2
3
4
8
7
6
5
R787 0/NA 5%
0402G_DFS
1 2
RP704
24*4/NA
1206
1
2
3
4
8
7
6
5
R97 0/NA 5%
0402G_DFS
1 2
R759 10/NA 0402 5% 1 2
R718 24/NA 0402 5% 1 2
RP701
24*4/NA
1206
1
2
3
4
8
7
6
5
RP20
24*4/NA
1206
1
2
3
4
8
7
6
5
R746 0/NA 0402 1 2
R755
10/NA
0402 5% 1 2
R722 24/NA 0402 5% 1 2
RP10
0*4/NA
1206
1
2
3
4
8
7
6
5
RP707
24*4/NA
1206
1
2
3
4
8
7
6
5
C730
10U/NA
6.3V
0805 10%
1 2
R50 10/NA 0402 5% 1 2
R726 56/NA
0402 5%
1 2
R721 24/NA 0402 5% 1 2
R106 24/NA 0402 5% 1 2
R736
1K/NA 0402 1%
1 2
R724 24/NA 0402 5% 1 2
R39 24/NA 0402 5% 1 2
RP6
0*8/NA
RPX8
1
2
3
4
5
6
7
8 9
10
11
12
13
14
15
16
R44
1K/NA
0402 1% 1 2
RP713
24*4/NA
1206
1
2
3
4
8
7
6
5
C742 470P/NA
0402 50V 10%
1 2
R747 0/NA 5%
0402G_DFS
1 2
R711 0/NA 0402 1 2
TP17 1
RP717
24*4/NA
1206
1
2
3
4
8
7
6
5
RP7
24*4/NA
1206
1
2
3
4
8
7
6
5
RP13
24*4/NA
1206
1
2
3
4
8
7
6
5
RP5
24*4/NA
1206
1
2
3
4
8
7
6
5
R36 0/NA 0402 1 2
R81 0/NA 0402 1 2
R709 24/NA 0402 5% 1 2
R729 24/NA 0402 5% 1 2
R719 24/NA 0402 5% 1 2
C41 470P/NA
0402 50V 10%
1 2
RP8
0*8/NA
RPX8
1
2
3
4
5
6
7
8 9
10
11
12
13
14
15
16
R93 24/NA 0402 5% 1 2
R75
4.7K/NA
0402
5%
1
2
RP703
24*4/NA
1206
1
2
3
4
8
7
6
5
R45
1K/NA
0402 1% 1 2
RP14
0*8/NA
RPX8
1
2
3
4
5
6
7
8 9
10
11
12
13
14
15
16
R30 24/NA 0402 5% 1 2
R717 24/NA 0402 5% 1 2
R33 24/NA 0402 5% 1 2
C735 0.1U/NA
0402 50V +80-20%
1 2
R43
56/NA
0402 5%
1 2
R92 24/NA 0402 5% 1 2
R31 0/NA 0402 1 2
RP24
24*4/NA
1206
1
2
3
4
8
7
6
5
R80 0/NA 0402 1 2
RP702
24*4/NA
1206
1
2
3
4
8
7
6
5
R91 24/NA 0402 5% 1 2
C732 0.1U/NA
0402 50V +80-20%
1 2
R89 0/NA 0402 1 2
R40 24/NA 0402 5% 1 2
RP22
24*4/NA
1206
1
2
3
4
8
7
6
5
RP706
24*4/NA
1206
1
2
3
4
8
7
6
5
RP716
24*4/NA
1206
1
2
3
4
8
7
6
5
U710B
MOBILITY-M10-P/NA
BGA644_64_1MM
L25
L26
K25
K26
J26
H25
H26
G26
G30
D29
D28
E28
E29
G29
G28
F28
G25
F26
E26
F25
E24
F23
E23
D22
B29
C29
C25
C27
B28
B25
C26
B26
F17
E17
D16
F16
E15
F14
E14
F13
C17
B18
B17
B15
C13
B14
C14
C16
A13
A12
C12
B12
C10
C9
B9
B10
E13
E12
E10
F12
F11
E9
F9
F8
E22
B22
B23
B24
C23
C22
F22
F21
C21
A24
C24
A25
E21
B20
J25
F29
E25
A27
F15
C15
C11
E11
J27
F30
F24
B27
E16
B16
B11
F10
A19
E18
E19
E20
F20
B19
B21
C20
C18
A18
AG4
AE10
AE11
AF11
AB26
AB25
AG29
AE25
C19
D30
B13
DQA0
DQA1
DQA2
DQA3
DQA4
DQA5
DQA6
DQA7
DQA8
DQA9
DQA10
DQA11
DQA12
DQA13
DQA14
DQA15
DQA16
DQA17
DQA18
DQA19
DQA20
DQA21
DQA22
DQA23
DQA24
DQA25
DQA26
DQA27
DQA28
DQA29
DQA30
DQA31
DQA32
DQA33
DQA34
DQA35
DQA36
DQA37
DQA38
DQA39
DQA40
DQA41
DQA42
DQA43
DQA44
DQA45
DQA46
DQA47
DQA48
DQA49
DQA50
DQA51
DQA52
DQA53
DQA54
DQA55
DQA56
DQA57
DQA58
DQA59
DQA60
DQA61
DQA62
DQA63
MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
MAA13
DQMA#0
DQMA#1
DQMA#2
DQMA#3
DQMA#4
DQMA#5
DQMA#6
DQMA#7
QSA0
QSA1
QSA2
QSA3
QSA4
QSA5
QSA6
QSA7
RASA#
CASA#
WEA#
CSA0#
CSA1#
CKEA
CLKA0
CLKA0#
CLKA1
CLKA1#
VREFG
DVOVMODE
DMINUS
DPLUS
DBI_LO
DBI_HI
RSTB_MSK
PLLTEST
MAA14
DIMA_0
DIMA_1
R107 24/NA 0402 5% 1 2
R730 24/NA 0402 5% 1 2
R732 24/NA 0402 5% 1 2
R745
1K/NA 0402 1%
1 2
R710 24/NA 0402 5% 1 2
R38 24/NA 0402 5% 1 2
RP16
0*4/NA
1206
1
2
3
4
8
7
6
5
R754 56/NA
0402 5%
1 2
RP15
0*8/NA
RPX8
1
2
3
4
5
6
7
8 9
10
11
12
13
14
15
16
R108 24/NA 0402 5% 1 2
R728 10/NA 0402 5% 1 2
R715 24/NA 0402 5% 1 2
R760 56/NA
0402 5%
1 2
R70
4.7K/NA
0402
5%
1
2
C731
10U/NA
6.3V
0805 10%
1 2
R740
1K/NA 0402 1%
1 2
R90 24/NA 0402 5% 1 2
RP709
24*4/NA
1206
1
2
3
4
8
7
6
5
R720 24/NA 0402 5% 1 2
RP19
24*4/NA
1206
1
2
3
4
8
7
6
5
RP714
24*4/NA
1206
1
2
3
4
8
7
6
5
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
VRAM
PCB 316680900001/ASSY 411680900011 R01
8050 MOTHERB/D
C
Title
Size
Document
Number
Rev
Date: Sheet of
VQSB[0..7]
VMA[0..13]
VMB[0..13]
VQSA[0..7]
VDQMA#[0..7]
VMDA[0..63]
VDQMB#[0..7]
VMDB[0..63]
VDQMA#0
VMDA30
VMA1
VQSA1
VMDA19
VMDA31
VMA3
VMDA7
VWEA#
VCSA#1
VMA13
VMA4
VMA6
VCASA#
VMA2
VMDA15
VMDA11
VDQMA#3
VMDA28
VMDA5
VMDA16
VMDA21
VMDA26
VMA10
VCLKA#0
VMA0
VQSA3
VMDA18
VMDA2
VMDA13
VMDA23
VMDA22
VMA8
VMDA0
VCKEA
VMDA14
VCSA#0
VMA9
VMDA27
VQSA2
VRASA#
VMDA29
VMA11
VMDA25
VMDA12
VMDA24
VCLKA0
VMA12
VMDA17
VMA7
VMDA8
VMDA4
VMDA1
VDQMA#2
VMDA9
VMDA3
VMDA6
VDQMA#1
VMDA20
VMA5
VMDA10
VQSA0
VDD_MEM_IOREF
VDD_MEM_IOREF
VMDA47
VWEA#
VMDA52
VMDA36
VMDA46
VMDA51
VMDA38
VMDA56
VMA3
VMDA33
VMDA54
VMDA44
VMA1
VMDA35
VMA11
VMDA41
VMDA49
VMA0
VMDA45
VMDA62
VDQMA#5
VMDA59
VMA6
VMDA34
VMDA53
VMDA37
VMDA48
VMA9
VMDA61
VMDA32
VMDA40
VCLKA1
VMA10 VMDA42
VCKEA
VMDA58
VQSA6
VCSA#0
VDQMA#4
VCSA#1
VQSA7
VMA7
VMA2
VDQMA#6
VRASA#
VMA8
VMA13
VMDA55
VMDA60
VDQMA#7
VMDA50
VCASA#
VMA4
VMDA39
VQSA4
VCLKA#1
VMDA63
VMDA43
VMA12
VMDA57
VQSA5
VMA5
VDD_MEM_IOREF
VDD_MEM_IOREF
VQSB2
VMB13
VMDB27
VMDB31
VMDB12
VMDB9
VDQMB#2
VMDB21
VCSB#0
VQSB3
VMB0
VQSB1
VMDB16
VMB10
VMB2
VDQMB#1
VMDB14
VMB6
VQSB0
VMB7
VCASB#
VMDB13
VMDB10
VMB4
VMB5
VMDB23
VMDB25
VMDB15
VMDB11
VMB3
VCLKB0
VMB1
VDQMB#3
VMDB5
VCLKB#0
VMDB8
VMDB3
VMDB4
VMDB30
VMB12
VMB8
VMDB19
VMDB18
VMDB1
VDQMB#0
VMB11
VMDB17
VMDB0
VCKEB
VRASB#
VMDB29
VMB9
VMDB7
VWEB#
VMDB24
VCSB#1
VMDB26
VMDB22
VMDB28
VMDB20
VMDB2
VMDB6
VDD_MEM_IOREF
VDD_MEM_IOREF
VMDB49
VRASB#
VMDB51
VCLKB1
VMB11
VMDB35
VMDB59
VMB7
VQSB7
VMB5
VMDB53
VMDB62
VMDB34
VMDB47
VMDB41
VMDB45
VMB1
VCASB#
VMB2
VWEB#
VDQMB#4
VMDB60
VMB6
VMDB46
VCKEB
VQSB6
VMDB40
VQSB5
VMDB39
VMDB42
VMB12
VMDB38
VMB8 VQSB4
VMDB52
VMDB61
VDQMB#7
VMB10
VMB0
VMB9
VCSB#1
VMDB55
VMDB33
VMDB50
VCLKB#1
VMDB56
VMDB43
VMB3
VMDB44
VMDB36
VMDB54
VMDB63
VMB13
VMDB48
VDQMB#6
VMDB57
VMDB37
VCSB#0
VMDB58
VMDB32
VMB4
VDQMB#5
VDD_MEM_IOREF
VDD_MEM_IOREF
VDQMA#[0..7] 9
VWEA# 9
VQSB[0..7] 9
VCLKA#0 9
VCLKA0 9
VCSA#1 9
VMA[0..13] 9
VRASA# 9
VQSA[0..7] 9
VCASA# 9
VMDB[0..63] 9
VCKEA 9
VMB[0..13] 9
VMDA[0..63] 9
VCSA#0 9
VDQMB#[0..7] 9
VDIMA_0 9
VCSA#1 9
VDIMA_1 9
VCASB# 9
VCSB#1 9
VRASB# 9
VWEB# 9
VCKEB 9
VCSB#0 9
VCLKB#0 9
VCLKB0 9
VDIMB_0 9
VRASB# 9
VCLKB1 9
VCKEB 9
VCLKB#1 9
VCASB# 9
VCSB#1 9
VWEB# 9
VCSB#0 9
VDIMB_1 9
VRASA# 9
VCASA# 9
VWEA# 9
VCSA#0 9
VCLKA1 9
VCLKA#1 9
VCKEA1 9
GND
VDD_MEM_IO
GND
+2.5V_M10
VDD_MEM_IO
GND
+2.5V_M10
GND
VDD_MEM_IO
GND
GND
VDD_MEM_IO
GND
+2.5V_M10
GND
VDD_MEM_IO
GND
+2.5V_M10
GND
VDD_MEM_IO
GND
GND
VDD_MEM_IO
+2.5V_M10
VDD_MEM_IO
GND
GND
GND
VDD_MEM_IO
+2.5V_M10
GND
GND
VDD_MEM_IO
+2.5V_M10
VDD_MEM_IO
VDD_MEM_IO
+2.5V_M10
GND
GND
GND
C741
0.1U/NA
0402
16V
10%
1
2
C754
0.1U/NA
0402
16V
10%
1
2
R713
1K/NA
0402
1%
1
2
C37
10U/NA
6.3V
0805
10%
1
2
C721
1U/NA
0402
10V
+80-20%
1
2
C27
0.1U/NA
0402
16V
10%
1
2
R32
1K/NA
0402
1%
1
2
R712
1K/NA
0402
1%
1
2
C28
1U/NA
0402
10V
+80-20%
1
2
C753
1U/NA
0402
10V
+80-20%
1
2
C744
0.1U/NA
0402
16V
10%
1
2
C62
1U/NA
0402
10V
+80-20%
1
2
C749
0.01U/NA
0402
50V
+80-20%
1
2
R751
1K/NA
0402
1%
1
2
C722
10U/NA
6.3V
0805
10%
1
2
U3
HY5DU2832222F/NA
BGA144F_08MM_1
M12
M4
M5
L5
M6
M7
L8
M8
M9
M10
M3
L4
L7
A2
G11
G2
A11
L1
K1
K2
M1
L10
M11
L6
M2
B3
B10
G3
G10
K11
K12
K3
L2
L3
G7
G8
H5
J3
H6
A1
B11
A6
B5
A5
A4
B1
C2
C1
D1
J12
J11
H12
H11
F12
F11
E12
E11
E2
E1
F2
F1
H2
H1
J1
J2
D12
C12
C11
B12
A9
A8
B8
A7
C6
C7
D3
D10
K6
K7
K10
B2
B4
B6
B7
B9
D2
D11
E3
E10
F3
F10
H3
H10
J5
D9
D7
D6
K5
L11
H7
H8
G5
G6
E5
E6
E7
E8
F5
F6
F7
F8
J6
J7
J8
K4
K9
D4
C8
C9
C10
D5
D8
E4
E9
F4
F9
G4
G9
H4
H9
J4
J9
J10
G12
G1
A12
A3
C3
C4
C5
A10
L12
K8
L9
VREF
A0
A1
A2
A3
A4
A5
A6
A7
A8/AP
BA0
BA1
A9
DQM0
DQM1
DQM2
DQM3
RAS
CAS
WE
CS
CK
CKE
A11
NC1
NC2
NC3
NC4
NC5
NC6
NC7
VDD_4
NC8
NC9
VSS/TH1
VSS/TH2
VSS/TH3
VDDQ_14
VSS/TH4
DQS0
VDDQ_5
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
VDD_0
VDD_1
VDD_2
VDD_3
VDD_5
VDD_6
VDD_7
VDDQ_0
VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9
VDDQ_10
VDDQ_11
VDDQ_12
VDDQ_13
VSS_3
VSS_2
VSS_1
VSS_0
A10
CK#
VSS/TH5
VSS/TH6
VSS/TH7
VSS/TH8
VSS/TH9
VSS/TH10
VSS/TH11
VSS/TH12
VSS/TH13
VSS/TH14
VSS/TH15
VSS/TH16
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSSQ_0
VSSQ_1
VSSQ_2
VSSQ_3
VSSQ_4
VSSQ_5
VSSQ_6
VSSQ_7
VSSQ_8
VSSQ_9
VSSQ_10
VSSQ_11
VSSQ_12
VSSQ_13
VSSQ_14
VDDQ_15
DQS1
DQS2
DQS3
VSSQ_15
VSSQ_16
VSSQ_17
VSSQ_18
VSSQ_19
MCL
A12/RFU1
BA2/RFU2
U709
HY5DU2832222F/NA
BGA144F_08MM_1
M12
M4
M5
L5
M6
M7
L8
M8
M9
M10
M3
L4
L7
A2
G11
G2
A11
L1
K1
K2
M1
L10
M11
L6
M2
B3
B10
G3
G10
K11
K12
K3
L2
L3
G7
G8
H5
J3
H6
A1
B11
A6
B5
A5
A4
B1
C2
C1
D1
J12
J11
H12
H11
F12
F11
E12
E11
E2
E1
F2
F1
H2
H1
J1
J2
D12
C12
C11
B12
A9
A8
B8
A7
C6
C7
D3
D10
K6
K7
K10
B2
B4
B6
B7
B9
D2
D11
E3
E10
F3
F10
H3
H10
J5
D9
D7
D6
K5
L11
H7
H8
G5
G6
E5
E6
E7
E8
F5
F6
F7
F8
J6
J7
J8
K4
K9
D4
C8
C9
C10
D5
D8
E4
E9
F4
F9
G4
G9
H4
H9
J4
J9
J10
G12
G1
A12
A3
C3
C4
C5
A10
L12
K8
L9
VREF
A0
A1
A2
A3
A4
A5
A6
A7
A8/AP
BA0
BA1
A9
DQM0
DQM1
DQM2
DQM3
RAS
CAS
WE
CS
CK
CKE
A11
NC1
NC2
NC3
NC4
NC5
NC6
NC7
VDD_4
NC8
NC9
VSS/TH1
VSS/TH2
VSS/TH3
VDDQ_14
VSS/TH4
DQS0
VDDQ_5
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
VDD_0
VDD_1
VDD_2
VDD_3
VDD_5
VDD_6
VDD_7
VDDQ_0
VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9
VDDQ_10
VDDQ_11
VDDQ_12
VDDQ_13
VSS_3
VSS_2
VSS_1
VSS_0
A10
CK#
VSS/TH5
VSS/TH6
VSS/TH7
VSS/TH8
VSS/TH9
VSS/TH10
VSS/TH11
VSS/TH12
VSS/TH13
VSS/TH14
VSS/TH15
VSS/TH16
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSSQ_0
VSSQ_1
VSSQ_2
VSSQ_3
VSSQ_4
VSSQ_5
VSSQ_6
VSSQ_7
VSSQ_8
VSSQ_9
VSSQ_10
VSSQ_11
VSSQ_12
VSSQ_13
VSSQ_14
VDDQ_15
DQS1
DQS2
DQS3
VSSQ_15
VSSQ_16
VSSQ_17
VSSQ_18
VSSQ_19
MCL
A12/RFU1
BA2/RFU2
C29
0.1U/NA
0402
16V
10%
1
2
C30
1U/NA
0402
10V
+80-20%
1
2
R753
1K/NA
0402
1%
1
2
C65
0.1U/NA
0402
16V
10%
1
2
C63
0.1U/NA
0402
16V
10%
1
2
C727
0.01U/NA
0402
50V
+80-20%
1
2
C59
10U/NA
6.3V
0805
10%
1
2
C724
10U/NA
6.3V
0805
10%
1
2
C57
10U/NA
6.3V
0805
10%
1
2
C46
0.1U/NA
0402
16V
10%
1
2
C25
10U/NA
6.3V
0805
10%
1
2
U708
HY5DU2832222F/NA
BGA144F_08MM_1
M12
M4
M5
L5
M6
M7
L8
M8
M9
M10
M3
L4
L7
A2
G11
G2
A11
L1
K1
K2
M1
L10
M11
L6
M2
B3
B10
G3
G10
K11
K12
K3
L2
L3
G7
G8
H5
J3
H6
A1
B11
A6
B5
A5
A4
B1
C2
C1
D1
J12
J11
H12
H11
F12
F11
E12
E11
E2
E1
F2
F1
H2
H1
J1
J2
D12
C12
C11
B12
A9
A8
B8
A7
C6
C7
D3
D10
K6
K7
K10
B2
B4
B6
B7
B9
D2
D11
E3
E10
F3
F10
H3
H10
J5
D9
D7
D6
K5
L11
H7
H8
G5
G6
E5
E6
E7
E8
F5
F6
F7
F8
J6
J7
J8
K4
K9
D4
C8
C9
C10
D5
D8
E4
E9
F4
F9
G4
G9
H4
H9
J4
J9
J10
G12
G1
A12
A3
C3
C4
C5
A10
L12
K8
L9
VREF
A0
A1
A2
A3
A4
A5
A6
A7
A8/AP
BA0
BA1
A9
DQM0
DQM1
DQM2
DQM3
RAS
CAS
WE
CS
CK
CKE
A11
NC1
NC2
NC3
NC4
NC5
NC6
NC7
VDD_4
NC8
NC9
VSS/TH1
VSS/TH2
VSS/TH3
VDDQ_14
VSS/TH4
DQS0
VDDQ_5
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
VDD_0
VDD_1
VDD_2
VDD_3
VDD_5
VDD_6
VDD_7
VDDQ_0
VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9
VDDQ_10
VDDQ_11
VDDQ_12
VDDQ_13
VSS_3
VSS_2
VSS_1
VSS_0
A10
CK#
VSS/TH5
VSS/TH6
VSS/TH7
VSS/TH8
VSS/TH9
VSS/TH10
VSS/TH11
VSS/TH12
VSS/TH13
VSS/TH14
VSS/TH15
VSS/TH16
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSSQ_0
VSSQ_1
VSSQ_2
VSSQ_3
VSSQ_4
VSSQ_5
VSSQ_6
VSSQ_7
VSSQ_8
VSSQ_9
VSSQ_10
VSSQ_11
VSSQ_12
VSSQ_13
VSSQ_14
VDDQ_15
DQS1
DQS2
DQS3
VSSQ_15
VSSQ_16
VSSQ_17
VSSQ_18
VSSQ_19
MCL
A12/RFU1
BA2/RFU2
C748
1U/NA
0402
10V
+80-20%
1
2
C48
1U/NA
0402
10V
+80-20%
1
2
C47
0.01U/NA
0402
50V
+80-20%
1
2
C720
0.1U/NA
0402
16V
10%
1
2
C740
10U/NA
6.3V
0805
10%
1
2
C33
0.01U/NA
0402
50V
+80-20%
1
2
C34
0.01U/NA
0402
50V
+80-20%
1
2
C718
0.1U/NA
0402
16V
10%
1
2
C723
1U/NA
0402
10V
+80-20%
1
2
R60
1K/NA
0402
1%
1
2
R65
1K/NA
0402
1%
1
2
C719
0.1U/NA
0402
16V
10%
1
2
C32
10U/NA
6.3V
0805
10%
1
2
C756
10U/NA
6.3V
0805
10%
1
2
C35
0.1U/NA
0402
16V
10%
1
2
C49
10U/NA
6.3V
0805
10%
1
2
C752
0.1U/NA
0402
16V
10%
1
2
C725
0.1U/NA
0402
16V
10%
1
2
C45
0.1U/NA
0402
16V
10%
1
2
C716
10U/NA
6.3V
0805
10%
1
2
R34
1K/NA
0402
1%
1
2
C726
0.01U/NA
0402
50V
+80-20%
1
2
C745
0.01U/NA
0402
50V
+80-20%
1
2
C750
10U/NA
6.3V
0805
10%
1
2
C51
0.01U/NA
0402
50V
+80-20%
1
2
U1
HY5DU2832222F/NA
BGA144F_08MM_1
M12
M4
M5
L5
M6
M7
L8
M8
M9
M10
M3
L4
L7
A2
G11
G2
A11
L1
K1
K2
M1
L10
M11
L6
M2
B3
B10
G3
G10
K11
K12
K3
L2
L3
G7
G8
H5
J3
H6
A1
B11
A6
B5
A5
A4
B1
C2
C1
D1
J12
J11
H12
H11
F12
F11
E12
E11
E2
E1
F2
F1
H2
H1
J1
J2
D12
C12
C11
B12
A9
A8
B8
A7
C6
C7
D3
D10
K6
K7
K10
B2
B4
B6
B7
B9
D2
D11
E3
E10
F3
F10
H3
H10
J5
D9
D7
D6
K5
L11
H7
H8
G5
G6
E5
E6
E7
E8
F5
F6
F7
F8
J6
J7
J8
K4
K9
D4
C8
C9
C10
D5
D8
E4
E9
F4
F9
G4
G9
H4
H9
J4
J9
J10
G12
G1
A12
A3
C3
C4
C5
A10
L12
K8
L9
VREF
A0
A1
A2
A3
A4
A5
A6
A7
A8/AP
BA0
BA1
A9
DQM0
DQM1
DQM2
DQM3
RAS
CAS
WE
CS
CK
CKE
A11
NC1
NC2
NC3
NC4
NC5
NC6
NC7
VDD_4
NC8
NC9
VSS/TH1
VSS/TH2
VSS/TH3
VDDQ_14
VSS/TH4
DQS0
VDDQ_5
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
VDD_0
VDD_1
VDD_2
VDD_3
VDD_5
VDD_6
VDD_7
VDDQ_0
VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9
VDDQ_10
VDDQ_11
VDDQ_12
VDDQ_13
VSS_3
VSS_2
VSS_1
VSS_0
A10
CK#
VSS/TH5
VSS/TH6
VSS/TH7
VSS/TH8
VSS/TH9
VSS/TH10
VSS/TH11
VSS/TH12
VSS/TH13
VSS/TH14
VSS/TH15
VSS/TH16
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSSQ_0
VSSQ_1
VSSQ_2
VSSQ_3
VSSQ_4
VSSQ_5
VSSQ_6
VSSQ_7
VSSQ_8
VSSQ_9
VSSQ_10
VSSQ_11
VSSQ_12
VSSQ_13
VSSQ_14
VDDQ_15
DQS1
DQS2
DQS3
VSSQ_15
VSSQ_16
VSSQ_17
VSSQ_18
VSSQ_19
MCL
A12/RFU1
BA2/RFU2
C36
0.1U/NA
0402
16V
10%
1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
CLOCK SYNTHERIZER
33.33
1
Tristate
1 66.66
100.00
X
133.33
Mid
X
66.66
1
TCLK/2
Reserved
X
0
1
X
PCI*
Mid
33.33
FS0
TCLK/2
UNIT: MHz
1
Reserved
FS1
Reserved
0
1 0
Reserved
33.33
0
0
0:0V
TCLK/2
Mid Tristate
1:3.3V
Tristate
FS2
0
166.66 33.33
0
Reserved
1
CPU 3V66[5:0]
1
66.66
Mid
66.66 200.00
0
Reserved
001
Layout note: Place crystal within
500 mils of CLK Gen.
TV ENCODER
Place near
to 7011.
Default NTSC
USE 20P 5%
WHEN USE INTEGRATE VGA R887/NA
WHENUSEINTEGRATEVGA
ADD R763 R766 U2 R1240
PCB 316680900001/ASSY 411680900011 R01
8050 MOTHERB/D
C
Title
Size
Document
Number
Rev
Date: Sheet of
FS1
FS2
FS0
CLK_PCI_STOP#
VTT_PWRGD#
CLK_CPU_STOP#
CLK_PD#
HCLK_MCH
HCLK_CPU
ITP_CPU
HCLK_MCH#
ITP_CPU#
HCLK_CPU#
VTT_PWRGD#
FS1
FS2
FS0
HCLK_CPU
ITP_CPU#
HCLK_CPU#
CLK_PCI_STOP#
CLK_CPU_STOP#
CLK_PD#
HCLK_MCH#
ITP_CPU
HCLK_MCH
TV_DDDA
TV_DDCK
DVOCD[0..11]
DVOCD7
855_TV_LUMA
DVOCD3
DVOCD6
DVOCD1
XOUT
DVOCD9
DVOCD8
DVOCD10
DVOCD2
DVOCD4
DVOCD5
DVOCD11
TV_DDCK
855_TV_CRMA
TV_DDDA
DVOCD0
XIN
PCICK_KBC
XIN
XOUT
PCICK_1394
PCICK_KBC
PCICK_1394
DEFSSCLK
DEFSSCLK
855_TV_COMP
CVBS1
855_TV_COMP
CVBS1
DVOVREF
855_TV_CRMA
855_TV_LUMA
855_TV_COMP
CORE_CLKEN# 31
SUSA# 13
STOP_CPU# 3,13,31
STOP_PCI# 13
14M_CODEC 20
14M_ICH 13
HCLK_CPU# 2
HCLK_CPU 2
HCLK_MCH 4
CLK_ITP_CPU# 2
CLK_ITP_CPU 2
PCICLK_FWH 23
PCICLK_MINIPCI 19
PCICLK_CARD 17
PCICLK_LAN 16
PCICLK_ICH 13
66M_MCH 4
66M_ICH 14
SMBDATA 6,14
SMBCLK 6,14
HCLK_MCH# 4
USBCLK_ICH 14
MI2CCLK 4
MI2CDATA 4
DVOVREF 4
DVOCCLK 4
DVOCCLK# 4
DVOCHSYNC 4
DVOCVSYNC 4
POUT/DET# 4
DVOCFLDSTL 4
TV_PCIRST# 13
DVOBCINTR# 4
DVOCD[0..11] 4
66M_AGP 7
48M_DREFCLK 4
66M_DEFSSCLK 4
PCICLK_KBC 22
PCICLK_1394 18
SIO_48M 19
ATI_TV_LUMA 7
ATI_TV_CRMA 7
ATI_TV_COMP 7
+3V
GND +3V
GND
GND
GND
+3VCLK66
+3VCLKCPU
GND
+3V
+3V
+3VCLKANA
+3VCLKPCI
GND GND
GND
+3VCLKPCI
GND GND
+3V
+3V +3VCLK66
GND GND
+3V +3VCLKANA
GND GND
GND GND
+3V +3VCLKCPU
TV_GND
GND
TV_GND
GND TV_GND
+3V
+3V
+3V
GND
+3V +3V
GND
GND
+3VA_TV
+3V
GND
+3V
GND
GND
GND
+3V
+3V
GND
GND
+1.5V
+3V
+3V
+3VA_TV
GND
GND
GND
GND
GND GND GND
GND GND
+3V
+3V
GND
TV_GND
R892 49.9 0402 1% 1 2
R47
8.2K/NA
0402
5%
1
2
L726 120Z/100M 1608 1 2
C71
0.1U
0402
50V
+80-20%
1
2
C830
10P/NA
0402
50V +/-10%
1 2
R869
4.7K/NA
0402
5%
1
2
C791
10P
0402
50V
+/-10%
1
2
C42
0.1U
0402
50V
+80-20%
1
2
R763 0 0402 1 2
R882 8.2K/NA
0402
1 2
R704
0
1 2
R848
4.7K
0402
5%
1
2
C796
10P
0402
50V
+/-10%
1
2
C17 33P
0402 25V +/-10%
1 2
R895 33 0402 5% 1 2
R818 33 0402 1 2
R864
4.7K/NA
0402
5%
1
2
C802
0.1U
0402
16V
10%
1
2
R873 33 0402 1 2
D3
BAV99/NA
1 2
3
R877 33 0402 5% 1 2
C21
270P
0402
50V
+/-10%
1
2
C61
0.1U
0402
50V
+80-20%
1
2
C798
10P
0402
50V
+/-10%
1
2
C19 33P
0402 25V +/-10%
1 2
C803
0.1U
0402
16V
10%
1
2
C40
0.1U
0402
50V
+80-20%
1
2
D4
BAV99/NA
1 2
3
R49
330
0402
5%
1
2
C820
0.1U
0402
16V
10%
1
2
L722 120Z/100M 1608 1 2
R46
75
0402
5%
1
2
R861 33/NA 0402 1 2
RP2
75*4
1206
1 2 3 4
8 7 6 5
R37 140 1 2
R889
0/NA
0402 5% 1 2
R68
8.2K
0402
5%
1
2
R828 33 0402 1 2
L19
120Z/100M
1 2
C64
0.1U
0402
50V
+80-20%
1
2
R52 1M/NA
0402 5%
1 2
R807
10K
0402
5% 1
2
R56 0/NA
0402 5%
1 2
R870 49.9/NA 0402 1 2
R830 8.2K/NA
0402
1 2
C822
0.1U
0402
16V
10%
1
2
C39
10U
6.3V
0805
10%
1
2
R886
8.2K/NA
0402
1 2
R878 33 0402 5% 1 2
C809
0.1U
0402
16V
10%
1
2
R891 49.9 0402 1% 1 2
R827 33 0402 1 2
R858 33 0402 5%
1 2
C801
0.1U
0402
16V
10%
1
2
R874 33 0402 1 2
R48
75/NA
0402
5%
1
2
U712
ICS950810
TSSOP56
284595081201
2
3
25
34
43
53
56
29
30
54
55
40
39
38
35
33
21
22
23
24
26
28
14
1
19
32
37
42
46
50
8
4
9
15
20
27
31
36
41
47
5
6
7
10
11
12
13
16
17
18
51
48
44
52
49
45
X1
X2
*PD#
PCI_STOP#
MULTSEL0*
CPU_STOP#*
REF
SDATA
SCLK
FS0
FS1
FS2
48MHZ_USB
48MHZ_DOT
3V66_1/VCH_CLK
3V66_0
66MHZ_OUT0/3V66_2
66MHZ_OUT1/3V66_3
66MHZ_OUT2/3V66_4
66MHZ_IN/3V66_5
VDDA
VTT_PWRGD#
VDDPCI1
VDDREF
VDD3V66_0
VDD3V66_1
VDD48
IREF
VDDCPU0
VDDCPU1
VDDPCI0
GND0
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
PCICLK_F0
PCICLK_F1
PCICLK_F2
PCICLK0
PCICLK1
PCICLK2
PCICLK3
PCICLK4
PCICLK5
PCICLK6
CPUCLKC0
CPUCLKC1
CPUCLKC2
CPUCLKT0
CPUCLKT1
CPUCLKT2
C797
10P
0402
50V
+/-10%
1
2
C827
0.1U
0402
16V
10%
1
2
R876
390
0402
1%
1 2
C793
10P/NA
0402
50V
+/-10%
1
2
C788
2.2U
0603
+/-10%
1
2
C795
10P
0402
50V
+/-10%
1
2
C826
10P/NA
0402
50V
+/-10%
1
2
R865 33 0402 1 2
R872 33 0402 1 2
C789
10P
0402
50V
+/-10%
1
2
J704
7P/RA
SUYIN
33007S-07T1-C
331870007007
1
2
3
4
5
6
GND1
GND2
7
1
2
3
4
5
6
GND1
GND2
7
C52
20P
0402
50V
+/-10%
1
2
R935
10K
0402
5% 1
2
C778
0.1U
0402
16V
10%
1
2
L20
120Z/100M
1 2
R893 49.9 0402 1% 1 2
R862 33/NA 0402 1 2
C799
10P/NA
0402
50V
+/-10%
1
2
U2
CH7011A
PQFP64_0.5MM
2
9
19
20
21
22
23
24
25
26
27
28
29
30
31
32
63
62
61
60
59
58
55
54
53
52
51
50
7
8
3
4
5
10
13
14
15
35
36
37
38
39
42
43
46
47
48
56
57
6 1
1
6
4
1
6
1
7
3
4
4
0
4
1
1
8
3
3
4
4
1 1
2
4
5
4
9
NC0
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
NC10
NC11
NC12
NC13
NC14
NC15
D[0]
D[1]
D[2]
D[3]
D[4]
D[5]
D[6]
D[7]
D[8]
D[9]
D[10]
D[11]
GPIO[1]
GPIO[0]
VREF
H
V
AS
RESET*
SPD
SPC
ISET
CVBS
Y/G
C/R
CVBS/B
XI/FIN
XO
P-OUT
BCO
C/HSYNC
XCLK*
XCLK
D
G
N
D
_
0
D
G
N
D
_
1
D
G
N
D
_
2
A
G
N
D
_
0
A
G
N
D
_
1
G
N
D
_
0
G
N
D
_
1
A
G
N
D
_
2
A
V
D
D
_
0
V
D
D
A
V
D
D
_
1
D
V
D
D
_
0
D
V
D
D
_
1
D
V
D
D
V
D
V
D
D
_
2
R826 33 0402 1 2
L25
120Z/100M 2012
1 2
R887 0/NA 0402 5%
1 2
C794
27P
0402
5%
1
2
R766 0 0402 1 2
R863 8.2K 0402
5%
1 2
C73
10U
6.3V
0805
10%
1
2
L718 120Z/100M 1608 1 2
R817 33 0402 1 2
C239
2.2U
0603
+/-10%
1
2
C70
0.1U
0402
50V
+80-20%
1
2
D S
Q712
2N7002
SOT23_FET
288227002006
G
D S
C792
10P/NA
0402
50V
+/-10%
1
2
R881 0 0402 5%
1 2
C812
0.1U
0402
16V
10%
1
2
C819
0.1U
0402
16V
10%
1
2
C20
100P
0402
50V
10%
1
2
C800
0.1U
0402
16V
10%
1
2
R875 33 0402 1 2
C56
20P
0402
50V
+/-10%
1
2
C834
10P/NA
0402
50V +/-10%
1 2
C15
270P
0402
50V
+/-10%
1
2
L43 120Z/100M 1608 1 2
R860
4.7K
0402
5%
1
2
R63
0
0805
1
2
C811
2.2U
0603
+/-10%
1
2
R825 33 0402 1 2
R73 0/NA
0402 5%
1 2
R821 0 0402 5%
1 2
R871 49.9/NA 0402 1 2
C825
10P/NA
0402
50V +/-10%
1 2
C782
270P
0402
50V
+/-10%
1
2
R816 33 0402 1 2
R53
8.2K/NA
0402
5%
1
2
R853
4.7K/NA
0402
5%
1
2
R824 33 0402 1 2
L56
120Z/100M
1 2
D719
BAV99/NA
1 2
3
C43
0.1U
0402
50V
+80-20%
1
2
C38
10U
6.3V
0805
10%
1
2
C821
0.1U
0402
16V
10%
1
2
R888
0/NA
0402 5% 1 2
R859 33 0402
5%
1 2
D S
Q702
2N7002
SOT23_FET
288227002006
G
D S
C804
27P
0402
5%
1
2
C18
100P
0402
50V
10%
1
2
R819 33/NA 0402 1 2
R54
330
0402
5%
1
2
C823
2.2U
0603
+/-10%
1
2
R1240 0 0402 1 2
C262
0.1U
0402
16V
10%
1
2
R820 0 0402 5%
1 2
R894
4.7K
0402
5%
1
2
X701
14.318MHZ
TXC8X4.5
1 2
X703
14.318MHZ
TXC8X4.5
1 2
R831
10K
0402
5%
1
2
R890 49.9 0402 1% 1 2
C344 33P
0402 25V +/-10%
1 2
C833
10P/NA
0402
50V +/-10%
1 2
C790
10P
0402
50V
+/-10%
1
2
C53
0.1U
0402
50V
+80-20%
1
2
C67
0.1U
0402
50V
+80-20%
1
2
R71
330/NA
0402
5%
1
2
R829 33 0402 1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Check Power Plane is 3VS or 5VS
Display (CRT / LCD)
0
1
1
0 1
PANEL TYPE
0
1
LCD_ID2 LCD_ID1
1
1
LCD_ID0
INVERTER
I
n
v
e
r
t
e
r
CRT
CLOSE TO CRT CONNECTOR
Pannel ID
0
0 1
0 1 0
Cover Switch
WHENUSEINTEGRATEVGADEL
R785 R138 R136 R137 R139 R135
R783
WHENUSEINTEGRATEVGA
ADDR384
DELR386
To SB
WHENUSEINTEGRATEVGA
ADDR22
NEED USE X7R ?
DELR20
When inverter use +5VADD
Q4,R398,R399,R4 and DELR323
When inverter use +3VADDR323
and DELQ4,R398,R399,R4
PCB 316680900001/ASSY 411680900011 R01
8050 MOTHERB/D
C
Title
Size
Document
Number
Rev
Date: Sheet of
ENABKL_VGA_C
CON_BLUE
CON_DDDA
CON_GREEN
CON_RED CON_DDDA
CON_HSYNC
CON_BLUE
CON_GREEN
H8_LIDSW#
H8_ENABKL
BATT_G#
BATT_R#
BLADJ
CRT_GREEN
CON_DDCK
CRT_RED
CRT_BLUE
ENABKL_VGA
ENABKL_VGA ENABKL_VGA_C
CON_RED
CON_VSYNC
AC_POWER#
BATT_POWER#
FPVEDEN
BLADJ 4,22
BATT_R# 22,23
BATT_G# 22,23
H8_ENABKL 22
ENABKL_NB 4
H8_LIDSW# 22
ATI_CRT_GREEN 7
855_CRT_BLUE 4
855_CRT_GREEN 4
ATI_CRT_RED 7
855_CRT_RED 4
ATI_CRT_BLUE 7
CRT_IN# 13,24
ATI_CRT_HSYNC 7
855_CRT_HSYNC 4
855_CRT_VSYNC 4
ATI_CRT_VSYNC 7
855_CRT_DDDA 4
ATI_CRT_DDDA 7
855_CRT_DDCK 4
ATI_CRT_DDCK 7
PWROK 4,13,17,25,31
ENABKL 7
AC_POWER# 22,23
BATT_POWER# 23
TXOUT1+ 4
TXCLK+ 4
TXOUT1- 4
PANEL_ID2 7,14,24
PANEL_ID3 7,14,24
PANEL_ID0 7,14,24
TXCLK- 4
FPVDEN 4
PANEL_ID1 7,14,24
TXOUT0+ 4
TXOUT3+ 4
TXOUT3- 4
TXOUT2- 4
TXOUT2+ 4
TXOUT0- 4
ENAVDD 7
GND
+5V_H
GND
+5V_H
+5V_H
+5V_H
GND
CHAGND
CHAGND
CHAGND GND
CHAGND
CHAGND
CHAGND
CHAGND
GND
CHAGND GND
CHAGND
CHAGND
GND
+3VS
GND
+3V +3V
VDD3S
GND
CHAGND
+3VS
+5V_H
DVMAIN
CHAGND
+3V
GND
GND
+3V
GND
+3V
GND
+5V_H
R20 0/NA
0402 5%
1 2
D15
BAT54
1 3
C10
100P
0402
50V
+/-10%
1
2
L74 120Z/100M 1608
1 2
R135 0/NA 0402 1 2
R384 0
0402 5%
1 2
R398
10K/NA
0402
5% 1
2
C340
1000P
0402
50V
+/-20%
1
2
G
D
S
Q9
SI4835DY
SO8
8 7 6
4
5
1 3 2
Q1
SLVU2.8/NA
SOT23N
1
2
3
C11
1U
0402
10V
+80-20%
1
2
C6
4.7U/NA
0805
+80-20%
1
2
D701
ESD41A/NA
1 2
3 4
5 6
7 8
L12 120Z/100M 1608 1 2
RP1
75*4/NA
1206
1 2 3 4
8 7 6 5
R380
10K
0402
5% 1
2
D16
BAT54
1 3
R138 0/NA 0402 1 2
L59 220Z/100M 1 2
R783 0/NA 0402 1 2
R4
10K/NA
0402
5% 1
2
C14
0.22U
0402
16V
+80-20%
1
2
C4 47P
0402 50V 10%
1 2
R139 0/NA 0402 1 2
L7 120Z/100M 1608 1 2
C339
0.01U
0402
50V
+80-20%
1
2
J1
MA/11PX1/RA
ACES
87213-1100
1
2
3
4
5
6
7
8
9
10
11
GND1
GND2
D S
Q7
2N7002
G
D S
L18
120Z/100M
2012
1 2
L17
120Z/100M 2012
1 2
R10 4.7K
0402 5%
1 2
R
1
Q4
DTC144TKA/NA
288202240001
2
1 3
R370
0/NA
0402
5%
1
2
R323
0
0402 5%
1 2
Q2
SLVU2.8/NA
SOT23N
1
2
3
Q3
SLVU2.8/NA
SOT23N
1
2
3
D S
Q5
2N7002
G
D S
D S
Q6
2N7002
G
D S
F1
2A
FUSE_1206
1 2
C7
0.1U
0402
50V
+80-20%
1
2
R136 0/NA 0402 1 2
R16
1M
0402 5%
1 2
L13
BEAD_600Z/100M
0603D
1 2
FA2
120OHM/100MHZ
273000610025
1
2
3
4 5
6
7
8
R5 0 0402 1 2
J2
MA/15PX2/ST
ACES
88107-300X
1
3
5
7
9
11
13
15
17
2
4
6
8
10
12
14
16
18
20 19
GND1
GND2
22
24
26
28
30
21
23
25
27
29
R6 4.7K
0402 5%
1 2
R19 10K
0402 5%
1 2
C8
0.1U/NA
0402
50V
+80-20%
1
2
D S
Q11
2N7002
SOT23_FET
G
D S
L15
120Z/100M
2012
1 2
L10 120Z/100M
1608
1 2
R383
0
0402
5%
1 2
D1
ESD0805A/NA
1 2
R365
0/NA
0402
5%
1
2
L11 120Z/100M 1608 1 2
U702
SMS05C/NA
SSOT6
1
2
3
6
5
4
R386 0/NA
0402 5%
1 2
R399
20K/NA
0402
1%
1
2
CP2
47PX4
1206
1 2 3 4
8 7 6 5
D2
BAT54
1 3
L58
220Z/100M 1 2
R22 0
0402 5%
1 2
SW1
30V/0.1A
DT006-P11AA-A
1
2
3
4
R9 1K
0402 5%
1 2
R379
0/NA
0402
5%
1 2
R785 0/NA 0402 1 2
C12
0.1U
0402
50V
+80-20%
1
2
D702
ESD41A/NA
1 2
3 4
5 6
7 8
R1
0
0805
1 2
R703
0
0805
1 2
L60 220Z/100M 1 2
R3
1K 0402 5%
1 2
C385
0.1U
0402
50V
+80-20%
1
2
R8
0/NA
0402
5%
1 2
C1 47P
0402 50V 10%
1 2
D S
Q8
2N7002
G
D S
L9
120Z/100M 1608
1 2
CP1
47PX4/NA
1206
1 2 3 4
8 7 6 5
R373
470K
0402
5%
1
2
R2
470K/NA
0402
5%
1
2
L8
120Z/100M/NA
2012 1 2
J702
15P/3R-FM
7312S-15G2T-DC
SUYIN
6
1
11
7
2
12
8
3
13
9
4
14
10
5
15
17
16
C2 47P
0402 50V 10%
1 2
R137 0/NA 0402 1 2
R372
10K
0402
5% 1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Spacing other signal 25 mils
SOUTHBRIDGE-ICH4-M(1/2)
PCB 316680900001/ASSY 411680900011 R01
8050 MOTHERB/D
C
Title
Size
Document
Number
Rev
Date: Sheet of
PCI_C/BE#[0..3]
PCI_C/BE#0
PCI_C/BE#1
PCI_C/BE#2
PCI_C/BE#3
SB_PME#
PCI_LOCK#
PCIRST#
INTRUDER#
V5REF
V5REF
V5REF_SUS
V5REF_SUS
ICH_GPI5
PCI_REQ4#
PCI_REQ0#
CRT_IN#
PCI_GNT4#
PCI_GNT0#
PCIRST#
PWROK
SLP_S4#
SLP_S5#
LDRQ1#
SB_SUSST#
SB_CARD_PME#
PCI_PME#
PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD[0..31]
PCI_AD3
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD4
PCI_AD9
PCI_AD10
PCI_AD12
PCI_AD8
PCI_AD13
PCI_AD11
PCI_AD14
PCI_AD15
PCI_AD17
PCI_AD18
PCI_AD28
PCI_AD20
PCI_AD16
PCI_AD25
PCI_AD26
PCI_AD24
PCI_AD31
PCI_AD21
PCI_AD19
PCI_AD29
PCI_AD27
PCI_AD30
PCI_AD22
PCI_AD23
C3_STAT#
CARDBUS_PME#
PCI_PME# SB_PME#
SB_CARD_PME#
LAD0
SUSA#
LAD3
LAD[0..3]
LAD1
SLP_S5#
RTC_X2
RTC_VBIAS
SUSCLK
HSTPCLK#
INTRUDER#
RTC_X1
LAD2
LDRQ1#
RTC_X1
SLP_S4#
RTC_RST#
A20_GATE
A20_GATE
ICH_VGATE
ICH_VGATE
C3_STAT#
RTC_VBIAS
SB_SUSST#
RTC_RST#
RTC_X2
GPIO27
GPIO28
PCI_INTE#
PCI_INTB#
PCI_INTG#
PCI_INTD#
PCI_INTF#
PCI_INTA#
PCI_INTC#
PCI_REQ3# 16,24
PCI_REQ2# 19,24
PCI_REQ1# 18,24
CRT_IN# 12,24
PCI_GNT3# 16,24
PCI_GNT2# 19,24
PCI_GNT1# 18,24
PCI_SERR# 16,17,19,24
PCICLK_ICH 11
VRMPWRGD 31
HDPSLP# 2,4
DPRSLPVR 14,31
RSMRST# 22,25
PWROK 4,12,17,25,31
LAD[0..3] 19,22,23
LFRAME# 19,22,23
SERIRQ 14,17,19,22
HINIT# 2,23
CPU_FERR# 14
HRCIN# 22
HSMI# 2
HINTR 2
HPWRGD 2
HSLP# 2
HA20M# 2
HSTPCLK# 2
PCI_FRAME# 16,17,18,19,24
PCI_PERR# 16,17,18,19,24
PCI_IRDY# 16,17,18,19,24
PCI_PAR 16,17,18,19
PCI_TRDY# 16,17,18,19,24
PCI_STOP# 16,17,18,19,24
HNMI 2
ICH_RI# 16
PCLKRUN# 16,17,19,24
CPUPERF# 24
STOP_CPU# 3,11,31
SUSA# 11
STOP_PCI# 11
WAKE_UP# 22,24
SCI# 22,24
EXTSMI# 22,24
KBD_US/JP# 22,24
MINIPCI_PCIRST# 19
CARD_PCIRST# 17
LAN_PCIRST# 16
KBC_PCIRST# 22
MCH_PCIRST# 4
1394_PCIRST# 18
ATI_PCIRST# 7
PCI_AD[0..31] 16,17,18,19
PCI_C/BE#[0..3] 16,17,18,19
AGPBUSY# 4,7,24
STP_AGP# 7,24
SBSPKR 14,20
ICH_LAN_RST# 14
SMLINK0 14
SMB_DATA 14
SMBALERT# 24
ICH_SYS_RESET# 14
SB_THRM# 22
SUSB# 17,22,23,25
14M_ICH 11
HIGNNE# 2
SMLINK1 14
ICH_PWRBTN# 22
CPU_THRMTRIP# 14
ICH_BATLOW# 14
SMB_CLK 14
PCI_REQ4# 24
SUSCLK 4
PCI_GNT4# 24
PCI_LOCK# 24
PCI_GNT0# 17,24
PCI_REQ0# 17,24
PCIRST#0 15,25
FWH_PCIRST# 23
SB_SUSST# 7
TV_PCIRST# 11
A20GATE 22
LRDQ0# 19
CARDBUS_PME# 17
SB_CARD_PME# 24
PCI_PME# 18
MINIPCI_PME# 19
SB_PME# 14,16
GPIO27 24
GPIO28 24
ICH_GPI5 24
SPK_OFF 21,24
PCI_INTA# 7,24
PCI_INTC# 17,24
PCI_INTG# 18,24
PCI_INTD# 19,24
PCI_INTE# 16,24
PCI_INTF# 17,19,24
PCI_INTB# 17,24
PCI_DEVSEL# 16,17,18,19,24
B/CB# 3,24
SUSC# 22,26,27
GND
GND
GND
GND
GND
+VCC_RTC
+VCC_RTC
+3V
+LAN_3V
VDD3S
+1.5V
+VHI_ICH
+1.5V
+LAN_1.5V
GND
VDD1.5
GND
+5V +3V
GND
VDD5 VDD3S
+1.5V
GND
+VCCP
+3V +LAN_3V
GND
GND
+VHI_ICH
+1.5V
GND
+LAN_1.5V
VDD3S
GND
+3V
GND
GND
GND
GND
+3V
+3V
+3V
+3V
GND
+3V
VDD3S
GND
+3V
GND GND GND
GND
VDD5S
+1.5V
GND
VDD3S
+3V
+VCC_RTC
+3VS
VDD1.5
+3V
VDD5S
C224
0.1U
0402
16V
1
2
C277
0.1U
0402
16V
10%
1
2
U715B
ICH4-M
BGA360_25_36
D5
C2
B4
A3
C8
D7
C3
C4
B6
B3
C7
A2
B1
A6
B5
D6
B7
A7
E6
C1
C5
E8
F1
L5
F2
F3
G1
U5
M2
K5
L4
W2
P5
M3
P4
D2
R1
D3
P2
E1
P1
E2
M5
E4
N3
E3
N2
E5
N1
F4
F5
L3
H2
L2
G4
L1
G2
K2
J5
H4
J4
G5
K1
H3
J3
H5
J2
K4
M4
N4
PIRQA#
PIRQB#
PIRQC#
PIRQD#
PIRQE#/GPI0 2
PIRQF#/GPIO 3
PIRQG#/GPIO 4
PIRQH#/GPIO 5
REQ# 4
REQ# 2
REQ# 3
REQ# 1
REQ# 0
REQB#/REQ5#/GPIO 1
REQA#/GPIO 0
GNT# 4
GNT# 3
GNT# 2
GNT# 1
GNT# 0
GNTB#/GNT5#/GPIO 17
GNTA#/GPIO 16
FRAME#
IRDY#
TRDY#
STOP#
PAR
PCIRST#
PLOCK#
SERR#
PERR#
PME#
PCICLK
DEVSEL#
AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
C/BE#0
C/BE#1
C/BE#2
C/BE#3
R805 0/NA 5%
0402G_DFS
1 2
C229
10U
6.3V
0805
10%
1
2
JL7
JP_NET10
1 2
R931 0 1 2
C245
1U
0402
10V
1
2
C307
0.1U
0402
16V
10%
1
2
R920 0/NA 5%
0402G_DFS
1 2
C228
10U
6.3V
0805
10%
1
2
C244
0.1U
0402
16V
1
2
C853
0.1U
0402
16V
10%
1
2
R240 0 1 2
U5
AME8800AEEV/NA
SOT25
1
2
3 4
5
GND0
VIN
VOUT NC1
NC0
C208
0.1U
0402
16V
10%
1
2
R939 10K/NA
0402 5%
1 2
C311
4.7U
0805
+80-20%
1
2
D10
BAT54
1
3
D704
BAW56
288100056017
2
1
3
U9B
74AHC08_V
TSSOP14
4
5
6
1
4
7
C253
0.1U
0402
16V
1
2
R296
10M
0402
5%
1
2
U715A
ICH4-M
BGA360_25_36
A5
B2
H6
J1
K6
M10
P6
U1
P12
V10
V16
V18
AC8
AC17
H18
J18
E9
F9
E11
F10
V9
V8
V7
F15
F16
F17
F18
K14
K10
K12
K18
K22
P10
T18
V14
U19
L23
M14
P18
T22
F6
F7
E12
R6
T6
U6
G18
E13
F14
E20
E7
V6
E15
P14
U18
AA23
C22
D1
C23
C21
C19
C17
C15
C6
B22
B20
B18
B16
B12
B9
A22
A20
A18
A16
A4
A1
D22
AC23
AC18
AC14
AC10
AC5
AC1
AB20
AB7
AA22
AA16
AA12
AA9
AA3
Y19
Y7
W22
W8
W5
V17
V15
V3
U20
T23
T19
T1
R21
R18
R5
P22
P20
D4
P13
P11
P3
N23
N21
N19
N14
N13
N12
N11
N10
N5
M13
M12
M11
M1
M22
L21
L14
L13
L12
L11
L10
K23
M20
K19
K13
K11
K3
J6
H1
G21
G19
G6
G3
F8
E22
E21
E19
E18
E17
E16
E14
E10
D23
D21
D19
D17
D15
D12
D8
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCCLAN3_3/VCCSUS3_3
VCCLAN3_3/VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCCHI0
VCCHI1
VCCHI2
VCCHI3
VCCLAN1_5/VCCSUS1_5
VCCLAN1_5/VCCSUS1_5
VCCSUS1_5
VCCSUS1_5
VCCSUS1_5
VCCSUS1_5
VCCSUS1_5
VCCSUS1_5
VCCSUS1_5
VCCSUS1_5
V5REF1
V5REF2
V5REF_SUS
V_CPU_IO
V_CPU_IO
V_CPU_IO
VCCPLL
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
R311 0/NA 1 2
C278
0.1U
0402
16V
1
2
C275
0.1U
0402
16V
10%
1
2
C292
10U
6.3V
0805
10%
1
2
C260
1U
0402
10V
1
2
R199 0/NA 5%
0402G_DFS
1 2
C306
0.1U
0402
16V
10%
1
2
C824
0.1U
0402
16V
10%
1
2
R276
0/NA
0805_DFS
1
2
R904 8.2K/NA 0402 1 2
C212
0.1U
0402
16V
1
2
R880 0 0402 1 2
C246
0.1U
0402
16V
1
2
R233
0/NA 0805
0805C
1 2
C315
0.1U
0402
16V
10%
1
2
R908 0/NA
0402
1 2
R867 0/NA
0805C_DFS
1 2
R896 0 0402 1 2
U9C
74AHC08_V
TSSOP14
9
10
8
1
4
7
D12
BAV70LT1
288100070006
1
2
3
C841
0.047U
0402
25V
10%
1
2
JL1
JP_NET10
1 2
R938
10M
0402
5%
1
2
C298
1U
0402
10V
1
2
C225
0.1U
0402
16V
10%
1
2
C233
10U
6.3V
0805
10%
1
2
R409
0/NA
1 2
R288
180K
0402
5%
1 2
D11
BAT54
1
3
R823 0/NA 5%
0402G_DFS
1 2
C210
1U
0402
10V
1
2
C305
0.1U
0402
16V
10%
1
2
R195 0/NA 5%
0402G_DFS
1 2
C213
0.1U
0402
16V
10%
1
2
C269
0.1U
0402
16V
10%
1
2
R932
10K
0402
5%
1
2
C211
0.1U
0402
16V
1
2
J710
1.25MM/ST/MA-2
ACES
85205-0200
1
2
R223
0/NA
0805C_DFS
1 2
R306
22
0402
5%
1 2
JL6
JP_NET10
1 2
C219
1U
0402
10V
1
2
TP34 1
JL3
JP_NET10
1 2
C223
0.1U
0402
16V
1
2
R164
1K/NA
0402
5%
1
2
R934 0 1 2
C207
0.1U
0402
16V
10%
1
2
R245
0/NA 0805
0805C
1 2
JL10
JP_NET10
1 2
R854 0/NA 5%
0402G_DFS
1 2
R
1
Q704
DTC144TKA
SOT23AN_1
288202240001
2
1 3
R917
1K
0402
5%
1
2
R287 10K 0402 5%
1 2
JL8
JP_NET10
1 2
X704
32.768KHZ
1
4
C261
0.1U
0402
16V
10%
1
2
C856
1U
0402
10V
+80-20%
1
2
R844 0/NA 5%
0402G_DFS
1 2
TP705 1
R926
4.7K
0402
5%
1
2
C304
0.1U
0402
16V
10%
1
2
C294
0.1U
0402
16V
1
2
C861 22P 0402
50V +/-10%
1 2
R397
1K
0402
5%
1
2
C274
10U
6.3V
0805
10%
1
2
C206
1U
0402
10V
1
2
R928
0/NA
5% 0402G_DFS
1 2
U9A
74AHC08_V
TSSOP14
1
2
3
1
4
7
R915 0/NA
5% 0402G_DFS
1 2
R252
1K
0402
5%
1
2
R274 0/NA 5%
0402G_DFS
1 2
JL2
JP_NET10
1 2
U715D
ICH4-M
BGA360_25_36
J19
H19
K20
AB23
U21
AA21
W21
V22
AB22
V21
W23
V23
U22
Y22
Y23
J22
T2
R4
T4
U2
U3
U4
T5
AA4
W6
W7
Y6
AC7
AC6
AB6
AA6
AB5
V20
U23
R2
R3
V4
V5
W3
Y21
W18
W19
T3
Y20
J21
AC2
V2
W1
W4
Y4
Y2
AA2
Y1
AA1
Y3
Y5
AB2
AB3
V19
W20
V1
AC3
AB1
AB4
AC4
AA5
H23
J23
APICCLK
APICD_0
APICD_1
A20M#
CPUSLP#
FERR#
IGNNE#
INIT#
INTR
NMI
SMI#
STPCLK#
RCIN#
A20GATE
CPUPWRGD
SERIRQ
LAD0/FWH0
LAD1/FWH1
LAD2/FWH2
LAD3/FWH3
LDRQ0#
LDRQ1#
LFRAME#/FWH4
SUSCLK
INTRUDER#
RTCRST#
VBIAS
RTCX1
RTCX2
PWROK
RSMRST#
VCCRTC
DPRSLPVR
DPSLP#
AGPBUSY#/GPIO 6
GPIO 7
GPIO 8
GPIO 12
GPIO 13
STP_PCI/GPIO 18
SLP_S1#/GPIO 19
STP_CPU#/GPIO 20
C3_STAT#/GPIO 21
CPUPERF#/GPIO 22
SSMUXSEL/GPIO 23
CLKRUN#/GPIO 24
GPIO 25
GPIO 27
GPIO 28
SLP_S3#
SLP_S4#
SLP_S5#
RI#
PWRBTN#
SYS_RESET#
LANRST#
BATLOW#/TP[ 0 ]
SUS_STAT#/LPCPD
VGATE/VRMPWRGD
THERMTRIP#
THRM#
SMILINK 0
SMLINK 1
SMBDATA
SMBCLK
SMBALERT#/GPIO 11
SPKR
CLK14
C289
2.2U/NA
0603
+/-10%
1
2
R270 10K/NA
0402 5%
1 2
JL9
JP_NET10
1 2
R921 0/NA
0402
1 2
R192 0/NA 5%
0402G_DFS
1 2
C308
0.1U
0402
16V
10%
1
2
JL5
JP_NET10
1 2
R234
0/NA
0805C_DFS
1 2
JL4
JP_NET10
1 2
C285
10U
6.3V
0805
10%
1
2
C221
0.1U
0402
16V
10%
1
2
C855 22P 0402
50V +/-10%
1 2
U9D
74AHC08_V
TSSOP14
12
13
11
1
4
7
R222 10K
0402 5%
1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
GPI[7]
GPIO[34]
GPO[17]
STOP_CPU#
GPIO[25]
MINIPCI_ACT#
RESUME POWER WELL
O
PANEL_ID0
GPO[18]
SBSPKR
STRAPPING PINS
GPI[0]
I
I/O GPIO[43]
I/O
GPIO[28]
MAIN POWER WELL
I/O
I
O
CPUPERF#
MAIN POWER WELL
GPI[8]
MAIN POWER WELL
I/O
GPO[23]
GPIO[37]
GPIO[42]
I
RESERVED
GPIO[27]
GPO[19]
MAIN POWER WELL
GPI[2]
PCI_INTG#
MAIN POWER WELL
RESUME POWER WELL
I/O
MAIN POWER WELL
O
OP-BLOCK SWAP OVERRIDE
I
SMBALERT#(Pull high only)
GPIO[41]
PCLKRUN#
SUSA#
MAIN POWER WELL
RESUME POWER WELL
GPIO[32] I/O
MAIN POWER WELL
O
HUB INTERFACE TERMINATION SCHEME
I
MAIN POWER WELL
GPIO[39]
MAIN POWER WELL
MAIN POWER WELL
O
SPK_OFF
I/O
HUB INTERFACE SCHEME(1.0 OR 1.5)
MAIN POWER WELL
MAIN POWER WELL
GPIO CHARACTERISTIC LIST
I
GPIO[38]
GPI[11]
I
MAIN POWER WELL
GPIO[40]
GPO[20]
MAIN POWER WELL
GPIO[35]
STRAPPING AT RISING EDGE OF PWROK
NO REBOOT
FUNCTIONS
CURRENT DEFINE
MAIN POWER WELL
MAIN POWER WELL
I
WAKE_UP#
MAIN POWER WELL
EXTSMI#
I/O
I/O
GPI[1]
RESUME POWER WELL
MAIN POWER WELL
EEDOUT
I/O
I/O
GPI[3]
MAIN POWER WELL
I
NAME
MAIN POWER WELL
GNTA#
O
ACSDOUT
GPO[16]
I/O
MAIN POWER WELL
GPI[5]
TYPE
I/O GPIO[33]
I
KBD_US/JP#
SCI#
MAIN POWER WELL
DPRSLPVR
I
GPO[21]
I/O
GPI[6]
PANEL_ID1
O
GPIO[24]
GPI[13]
IDERST#
STOP_PCI#
I/O
MAIN POWER WELL
MAIN POWER WELL
RESUME POWER WELL
MAIN POWER WELL
AGPBUSY# STRAPPING
POWER PLANE
GPIO[36]
I
GPI[12]
RESUME POWER WELL
OD
RESUME POWER WELL
MAIN POWER WELL
HUB_ICH_COMP
MAIN POWER WELL
I/O
PANEL_ID2
GPO[22]
PCI_INTE#
RESUME POWER WELL
SAFE MODE
WIRELESS_PD#
PCI_INTF#
SB_CARD_PME#
CRT_IN#
ICH_GPI5
C3_STAT#
X
X
X
PANEL_ID3
X
X
GPI[4]
B5
A6
C8
D7
C3
C4
R2
R3
V4
AA5
V5
W3
E8
C5
Y21
W18
W19
T3
Y20
J21
AC2
V2
W1
W4
J20
G22
F20
G20
F21
H20
F23
H22
G23
H21
F22
E23
MB_ID2
MB_ID0
MB_ID1
X
X
SOUTHBRIDGE-ICH4-M(2/2)
WHENUSEINTEGRATEVGA
ADDRP26
PCB 316680900001/ASSY 411680900011 R01
8050 MOTHERB/D
C
Title
Size
Document
Number
Rev
Date: Sheet of
HUB_HI[0..10]
SD_D[0..15] PD_D[0..15]
HUB_HI0
HUB_HI1
HUB_HI3
HUB_HI2
HUB_HI7
HUB_HI5
HUB_HI6
HUB_HI4
HUB_HI9
HUB_HI10
HUB_HI8
EE_DOUT
SD_D15
SD_D14
SD_D12
SD_D13
SD_D10
SD_D9
SD_D11
SD_D8
SD_D3
SD_D1
SD_D6
SD_D5
SD_D7
SD_D2
SD_D0
SD_D4
PD_D0
PD_D1
PD_D2
PD_D3
PD_D7
PD_D4
PD_D6
PD_D5
PD_D11
PD_D8
PD_D15
PD_D12
PD_D10
PD_D13
PD_D14
PD_D9
USBOC0#
USBOC4#
USBOC5#
EE_DOUT
ACSDOUT
SMLINK0
ICH_BATLOW#
SMLINK1
ICH_LAN_RST#
ICH_SYS_RESET#
USBOC1#
USBOC4#
USBOC5#
MB_ID2
HI_VREF
HI_COMP
HI_VSWING
HI_VSWING HI_VREF HI_COMP
GPIO43
MB_ID1
MB_ID0
USB_OC0# 15
USB_OC1# 15
WIRELESS_PD# 19,24
PANEL_ID0 7,12,24
PANEL_ID1 7,12,24
PANEL_ID2 7,12,24
IDERST# 15,24
MINIPCI_ACT# 19,24
USBCLK_ICH 11
PD_D[0..15] 15
PDIOW# 15
PDDACK# 15
PDDREQ 15
PDIOR# 15
PIORDY 15
PDA0 15
PDA1 15
PDA2 15
PDCS1# 15
PDCS3# 15
SBSPKR 13,20
DPRSLPVR 13,31
SMB_CLK 13
SMB_DATA 13
CPU_THRMTRIP_OUT# 2
HFERR# 2
ICH_LAN_RST# 13
SERIRQ 13,17,19,22
SMLINK1 13
SMLINK0 13
ICH_BATLOW# 13
ICH_SYS_RESET# 13
SMBDATA 6,11
SMBCLK 6,11
CPU_THRMTRIP# 13
CPU_FERR# 13
HUB_HI[0..10] 4
HUB_STB# 4
HUB_STB 4
66M_ICH 11
ACSYNC 20
ACSDOUT 20
ACBITCLK 20
ACRST# 20
ACSDIN0 20
ACSDIN1 20
SD_D[0..15] 15
SDIOW# 15
SDDACK# 15
SDDREQ 15
SDIOR# 15
SIORDY 15
SDA2 15
SDA1 15
SDA0 15
SDCS1# 15
SDCS3# 15
IRQ14 15
IRQ15 15
PANEL_ID3 7,12,24
USBP1- 15
USBP1+ 15
USBP0- 15
USBP0+ 15
THERM_ERR# 22,25
SB_PME# 13,16
MB_ID2 24
GPIO43 24
MB_ID1 24
MB_ID0 24
GPIO42 24
USBP2+ 15
USBP2- 15
GND
GND
GND
+3V
GND
+VHI_ICH
GND
+VCCP
VDD3S
GND
+3V
VDD3S
+3V
VDD3S +3V
+VCCP
+VCCP
VDD3S
GND
GND
+1.5V
+1.5V
+1.5V
GND
GND
C838
0.01U
0402
50V
10%
1
2
R392 8.2K
0402 5%
1 2
R813 4.7K/NA 0402 5%
1 2
TP28 1
R907 10K
0402 5%
1 2
R197
10K
0402
5%
1
2
R852
4.7K/NA
0402
5%
1 2
R185 0/NA 5% 0402G_DFS 1 2
R173 0/NA 5% 0402G_DFS 1 2
R937
56
0402
5%
1 2
R929 47K
0402 5%
1 2
D S
Q21
2N7002
G
D S
R307
10K/NA 0402
5% 1 2
R940 47K
0402 5%
1 2
R266
1K
0402
5%
1 2
R190 0/NA 5% 0402G_DFS 1 2
R290
0/NA
0402
5%
1
2
R273
56
0402
5%
1 2
R196 0/NA 5% 0402G_DFS 1 2
C787
10P/NA
0402
50V
+/-10%
1
2
R261 0/NA 5%
0402G_DFS
1 2
Q20
MMBT3904L
288203904022
B
E
C
R912
150
0402
1%
1
2
R811 10K
0402 5%
1 2
R933 10K
0402 5%
1 2
TP33 1
RP26
0*4
1206
1
2
3
4
8
7
6
5
R810
10
0402
5%
1
2
R275
4.7K/NA
0402
5%
1 2
R310 10K
0402 5%
1 2
R838
18.2
0402
1%
271061180101
1
2
R883
487
1%
1
2
D S
Q22
2N7002
G
D S
R856 56
0402 5%
1 2
C829
0.01U
0402
50V
10%
1
2
R205 0/NA 5% 0402G_DFS 1 2
TP704 1
U715E
ICH4-M
BGA360_25_36
C20
A21
C18
A19
C16
D20
B21
D18
B19
D16
B15
C14
A15
B14
A14
D14
J20
G22
F20
G20
F21
H20
F23
H22
G23
H21
F22
E23
F19
B23
A23
L19
L20
M19
M21
P19
R19
T20
R20
P23
L22
N22
K21
P21
N20
R23
R22
M23
T21
A10
A9
A11
B10
C10
A12
B11
C11
D11
D10
C12
A8
C9
D9
B8
C13
D13
A13
B13
A17
B17
USBP_0
USBP_1
USBP_2
USBP_3
USBP_4
USBP_0#
USBP_1#
USBP_2#
USBP_3#
USBP_4#
OC#0
OC#1
OC#2
OC#3
OC#4
OC#5
GPIO 32
GPIO 33
GPIO 34
GPIO 35
GPIO 36
GPIO 37
GPIO 38
GPIO 39
GPIO 40
GPIO 41
GPIO 42
GPIO 43
CLK48
USBRBIAS#
USBRBIAS
HI 0
HI 1
HI 2
HI 3
HI 4
HI 5
HI 6
HI 7
HI 8
HI 9
HI 10
HI 11
HI_STB/HI_STBS
HI_STB#/HI_STBF
HI_COMP
HIVSWING
HIREF
CLK66
LANRXD0
LANRXD1
LANRXD2
LANTXD0
LANTXD1
LANTXD2
LANRSTSYNC
LANCLK
EE_DIN
EE_CS
EE_SHCLK
EE_DOUT
ACSYNC
ACSDOUT
ACBITCLK
ACRST#
ACSDIN0
ACSDIN1
ACSDIN2
USBP_5
USBP_5#
R1113
4.7K/NA
0402
5%
1 2
R911
130
0603
1%
1
2
TP37 1
TP23 1
R884
150
0402
1%
1
2
TP24 1
TP29 1
R318
2.2K
0402
5%
1
2
R269
56
0402
5%
1
2
R936
56
0402
5%
1
2
R308 10K 0402 5%
1 2
R313 0/NA 0402 5%
1 2
R809
10K
0402
5%
1
2
C839
0.1U
0402
16V
10%
1
2
R317
10K
0402
5%
1
2
R900
48.7
1 2
U715C
ICH4-M
BGA360_25_36
AB11
AC11
Y10
AA10
AA7
AB8
Y8
AA8
AB9
Y9
AC9
W9
AB10
W10
W11
Y11
W17
AB17
W16
AC16
W15
AB15
W14
AA14
Y14
AC15
AA15
Y15
AB16
Y16
AA17
Y17
Y13 AB21
AB14 AC22
AA13
AB13
W13 AA20
AC20
AC21
AA11 AB18
Y12 AB19
AC12 Y18
W12 AA18
AB12 AC19
AC13
AA19
PDD 0
PDD 1
PDD 2
PDD 3
PDD 4
PDD 5
PDD 6
PDD 7
PDD 8
PDD 9
PDD 10
PDD 11
PDD 12
PDD 13
PDD 14
PDD 15
SDD 0
SDD 1
SDD 2
SDD 3
SDD 4
SDD 5
SDD 6
SDD 7
SDD 8
SDD 9
SDD 10
SDD 11
SDD 12
SDD 13
SDD 14
SDD 15
PDCS1# SDCS1#
PDCS3# SDCS3#
PDA0
PDA1
PDA2 SDA0
SDA1
SDA2
PDDREQ SDDREQ
PDDACK# SDDACK#
PDIOR# SDIOR#
PDIOW# SDIOW#
PIORDY SIORDY
IRQ14
IRQ15
R314 0/NA 0402 5%
1 2
R315
2.2K
0402
5%
1
2
R286 4.7K 0402 5%
1 2
R178 0/NA 5% 0402G_DFS 1 2
R316
10K
0402
5%
1
2
C828
0.1U
0402
16V
10%
1
2
R812 0 0402 5%
1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
HDD- PRIMARY IDE CONNECTOR
CDROM- SECONDARY IDE CONNECTOR
USB CONNECOTR
PCB 316680900001/ASSY 411680900011 R01
8050 MOTHERB/D
C
Title
Size
Document
Number
Rev
Date: Sheet of
PDA2
HDD_LED#
PD_D7
RSTDRV1#
PDCS3#
PDA1
PD_D5
PD_D1
PD_D2
IRQ14
PIORDY
PDDREQ
PD_D0
PDIOR#
PDCS1#
PD_D4
PDA0
PD_D6
PDDACK#
PDIOW#
PD_D3
PDDREQ
PDIOW#
PDIOR#
PDDACK#
IRQ14
PDA1
PDA0
PDA2
PDCS1#
PDCS3#
PD_D12
PD_D8
PD_D10
PD_D13
PD_D15
PD_D14
PD_D9
PD_D11
PIORDY
SDDREQ
SDIOR#
SDCS3#
SIORDY
SDDACK#
SDCS1#
SDIOW#
SDA2
SDA0
SDA1
IRQ15
SD_D[0..15]
PD_D4
PD_D12
PD_D6 SD_D3
SD_D1
PD_D11 SD_D8
SD_D5
SD_D4
PD_D15
PD_D7
PD_D10
SD_D2
SD_D6
PD_D14
SD_D0
SD_D15
SD_D7
PD_D3
SD_D12
PD_D1
PD_D8
PD_D0
SD_D9
SD_D10
PD_D2
PD_D13
PD_D5
PD_D9
SD_D11
PD_D[0..15]
SD_D13
SD_D14
SD_D5
SDA1
SD_D3
SD_D8
SDA2
CD_LED#
RSTDRV2#
SD_D7
SDIOW#
SDCS1#
CDROM_LEFT CDROM_RIGHT
SD_D14
SDCS3#
SD_D1
SDA0
IRQ15
SD_D9
SIORDY
SD_D11
SD_D4
SD_D2
SDIOR#
SDDACK#
SD_D15
SDDREQ
SD_D13
SD_D0
SD_D12
SD_D10 SD_D6
CDROM_COMM
+VCC_USB_0
+VCC_USB_1
+VCC_USB_0
USB_OC1#
+VCC_USB_2
USB_OC0#
+VCC_USB_2
+VCC_USB_1
PCIRST#0
RSTDRV1#
RSTDRV2#
HDD_LED# 23
PD_D[0..15] 14
PDDREQ 14
PDIOW# 14
PIORDY 14
PDIOR# 14
IRQ14 14
PDDACK# 14
PDA0 14
PDA1 14
PDCS1# 14
PDA2 14
PDCS3# 14
SDIOW# 14
IRQ15 14
SDDACK# 14
SDDREQ 14
SDCS3# 14
SDA1 14
SDA2 14
SDCS1# 14
SDIOR# 14
SIORDY 14
SD_D[0..15] 14
SDA0 14
CD_LED# 23
CDROM_COMM 20
CDROM_LEFT 20 CDROM_RIGHT 20
USB_OC0# 14
USBP2+ 14
USBP1+ 14
USBP1- 14
USBP0+ 14
USBP0- 14
USB_OC1# 14
USBP2- 14
PCIRST#0 13,25
IDERST# 14,24
GND GND
GND
+5V_HDD
GND
+3V
+3V
+3V
+3V
+3V
+3V
+5V_CDROM
GND
GND
GND
GND
GND
GND_USB1
GND_USB
GND_USB1
GND_USB
GND_USB
GND
GND_USB
+5VS
GND_USB GND
GND
GND
+5VS
GND_USB1
GND
GND
GND_USB
GND
GND
GND_USB1
GND
+5V
+5V
GND
+5V_HDD
GND GND
+5V_HDD
GND
+5V_CDROM
GND
+5V
GND
+5V_CDROM
GND
+5V
L733
120Z/100M 2012
1 2
JO17
SHORT-SMT4
1 2
JO15
1
2
C817
10U
10V
0805C
1
2
R706
33K
0402
5%
1
2
R1081 4.7K
0402 5%
1 2
U701
RT9701-CBL
SOT25
1
2
3
4 5
VOUT0
G
N
D
VIN0
VIN1 VOUT1
J706
USB/4PX1
SUYIN
2545A-04GXT
1
2
3
4
GND1
GND2
VCC
P-
P+
GND
GND1
GND2
R834 8.2K
0402 5%
1 2 C816
0.1U
0402
16V
10%
1
2
C709
1U
0402
10V
+80-20%
1
2
C872
0.1U
0402
16V
10%
1
2
R701
33K
0402
5%
1
2
JO13
SHORT-SMT4
1 2
+
C701
150U
7343
6.3V
1
2
R476
10K
0402
5%
1
2
L723
120Z/100M
2012
1 2
L708
120Z/100M
2012
1 2
J708
R/A-25PX2/0.8
SPEED
K22-102-150X
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
35
37
39
41
43
45
47
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
33
49 50
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
35
37
39
41
43
45
47
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
33
49 50
+
C702
150U/NA
7343
6.3V
1
2
R901
10K/NA
0402
5%
1 2
JO5
1
2
JO3
1
2
R1 Q41
DTC144TKA
288202240001
2
1
3
C703
1U
0402
10V
+80-20%
1
2
R927 10K/NA
0402 5%
1 2
C877
0.1U
0402
16V
10%
1
2
C5
0.1U
0402
50V
+80-20%
1
2
L3
BEAD/NA 0603D
1 2
R922
10K
0402 5%
1 2
L1
BEAD/NA 0603D
1 2
R1
Q703
DTC144TKA/NA
2
1
3
C704
1000P
0402
50V
+/-20%
1
2
R879 5.6K/NA
0402 5%
1 2
R1074 8.2K
0402 5%
1 2
C711
1000P
0402
50V
+/-20%
1
2
+
C713
150U
7343
6.3V
1
2
90Z/100M
CHOKE_ACM2012
L2
2
1
3
4
C813
0.1U
0402
16V
10%
1
2
JO14
1
2
JO702
SHORT-SMT4
1 2
R909
0
0402
5% 1
2
R919
10K/NA
0402
5%
1
2
L23
BEAD/NA 0603D
1 2
J701
USB/4PX2/DIP
SUYIN
2522A-08G1T-K
1
2
3
4
A1
A2
A3
A4
GND1
GND2
1
2
3
4
A1
A2
A3
A4
GND1
GND2
C878
10U
10V
0805C
1
2
L4
BEAD/NA 0603D
1 2
U705
RT9701-CBL
SOT25
1
2
3
4 5
VOUT0
G
N
D
VIN0
VIN1 VOUT1
L702
120Z/100M
2012
1 2
C3
0.1U
0402
50V
+80-20%
1
2
90Z/100M
CHOKE_ACM2012
L5
2
1
3
4
R708
47K
0402
5%
1
2
JO9
SHORT-SMT4
1 2
R833 4.7K
0402 5%
1 2
JO16
1
2
R295 5.6K/NA
0402 5%
1 2
JO4
1
2
L21
BEAD/NA 0603D
1 2
R836
470/NA
0402
5%
1 2
R1085
470
0402
5%
1 2
JO8
1
2
L6
BEAD/NA 0603D
1 2
L701
120Z/100M
2012
1 2
R436
10K/NA
0402
5%
1 2
R492
10K
0402
5%
1 2
JO7
1
2
R702
47K
0402
5%
1
2
90Z/100M
CHOKE_ACM2012
L22
2
1
3
4
JO6
1
2
C31
0.1U
0402
50V
+80-20%
1
2
R1 Q37
DTC144TKA
288202240001
2
1
3
J714
HDR/FM/22PX2/2MM
SPEED
ACE-1A2-0216
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
GND1
GND2
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
GND1
GND2
R1
Q705
DTC144TKA/NA
2
1
3
TP706 1
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
LAN-RTL8100CL/RTL8110S
Change to 2.49K when use
RTL8110S
3.Not to use via
USED IN 93C56
1.50/8/8/8/50
2.Parallel and
equal length
It's should be NA when
change to RTL8110S
ADD if use RTL8110S
Change DVDD to +1.8VS,
when use RTL8110S
ADD if use RTL8110S
Close to RTL8100C
ADD if use RTL8110S
ADD if use RTL8110S
GND_45
Change AVDDL to
+2.5VS_DDR , when
use RTL8110S
GND_45
ADD if use RTL8110S
Crystal should be placed
far away from I/O port and
Tx,Rx,power,magnetics.
GND_45
GND_45
GND_45
GND_45
GND_45
Pull high at EC side.
Add AVDDL to V_DAC, when
change to RTL8110S
Add thease caps when
use RTL8110S, and
C879 change to 0.01U
Use H1285 for RTL8100C
PCB 316680900001/ASSY 411680900011 R01
8050 MOTHERB/D
C
Title
Size
Document
Number
Rev
Date: Sheet of
MDI0-
EEDO
PCI_AD12
MDI3-
PCI_AD0
PCI_AD22
PCI_AD25
PCI_AD1
PCI_C/BE#3
PCI_AD20
EEDI
PCI_AD14
EECS
CTRL18
PCI_AD21
PCI_AD27
PCI_AD9
V_12P
PCI_AD19
MDI3+
PCI_AD5
PCI_AD15
PCI_AD16
PCI_AD13
PCI_AD6
MDI2+
LAN_XTAL1
PCI_AD17
PCI_AD23
EECK
MDI0+
PCI_AD8
PCI_AD18
PCI_AD10 MDI2-
LAN_XTAL2
MDI1+
PCI_AD24
PCI_AD4
PCI_AD3
PCI_AD11
PCI_AD26
PCI_AD7 MDI1-
ISOLATEB
PCI_AD18
PCI_AD2
DVDD
CTRL18
LAN_WAKE
MDI2+ MDI3+
MDI3- MDI2-
MDI0- MDI1-
MDI0+ MDI1+
MDI2+
MDI2-
MDI3+
MDI3- MDI1- MDI0-
MDI1+ MDI0+
MODEMN
MDO3-
MDO2-
MDO3+
AVDDL
EECK
EECS
EEDO
EEDI
LED3
LED1
LED0
LED2
PCI_C/BE#2
PCI_C/BE#0
PCI_AD30
PCI_AD29
PCI_AD28
PCI_C/BE#1
PCI_AD[0..31]
PCI_AD31
PCI_C/BE#[0..3]
MCT4
MCT3
MDO3-
MDO3+
MDO2+
MDO2-
MCT2
MCT4
MCT3
MCT1
V_DAC
V_DAC
PMDI0-
PMDI0+
PMDI1+
PMDI1-
LAN_XTAL2
LAN_XTAL1
LED2
LED0
LED3
LED1
MODEMP
MDO2+
PJRX+
PJRX+
LAN_WAKE
AVDDL
DVDD
V_DAC
V_DAC
MDO3-
PMDI0-
V_DAC
PMDI1-
PJRX+
PMDI3+
MCT1
MDO2-
PJRX-
PMDI2+ MDO2+
MCT3
PMDI2-
PMDI3-
MCT2
PMDI1+
MDO3+
PMDI0+
MCT4
V_DAC
V_DAC
PMDI2+
PMDI2- PMDI3-
PMDI3+ PMDI1+
PMDI1- PMDI0-
PMDI0+
PJRX-
PJTX+
PJRX-
PJTX1-
PJTX+
PJTX+ PJTX-
PJTX1-
PJTX1-
PCI_AD[0..31] 13,17,18,19
PCI_REQ3# 13,24
PCI_SERR# 13,17,19,24
PCI_TRDY# 13,17,18,19,24
PCI_DEVSEL# 13,17,18,19,24
PCI_INTE# 13,24
PCI_FRAME# 13,17,18,19,24
PCI_PAR 13,17,18,19
PCI_IRDY# 13,17,18,19,24
PCI_STOP# 13,17,18,19,24
LAN_PCIRST# 13
PCI_GNT3# 13,24
PCICLK_LAN 11
PCI_C/BE#[0..3] 13,17,18,19
PCI_PERR# 13,17,18,19,24
PCLKRUN# 13,17,19,24
SB_PME# 13,14
MODEMP 20
MODEMN 20
KBC_RI# 22
ICH_RI# 13
DVDD
+5V
+3VS
GND
GND
DVDD_A
GND
GND
AVDDH
DVDD
AVDDL
GND
+3VS
GND
GND
+1.8VS
+2.5VS_DDR DVDD
GND
+1.8VS
+3VS
GND
+3VS
GND
AVDDH
GND
GND
GND
GND
AVDDL +2.5VS_DDR
GND
+3VS
+3VS
GND
GND GND +3V
GND
GND
+3VS
GND
GND
GND
GND
GND
JO716
1
2
C835
0.1U
0402
1 2
C905
0.1U
0402
16V
10%
1
2
C867
0.1U
0402
16V
10%
1
2
JO718 1 2
C889
0.1U
0402
16V
10%
1
2
R1063
49.9/NA
0402
1%
1
2
C900
0.01U
0402
50V
+80-20%
1
2
R1114
0/NA
0402 5%
1 2
C863
0.1U
0402
16V
10%
1
2
C883
0.1U
0402
16V
10%
1
2
C879
0.1U
0402
16V
10%
1
2
R1107
510/NA
0402
1%
1
2
R1097
510/NA
0402
1%
1
2
R1082
49.9
0402
1%
1
2
R262 75/NA
0402
1 2
R943
0/NA
0805
1 2
Q707
2SB1188/NA
B
E
C
R1099
5.6K
0402
1%
1 2
C880
0.1U
0402
16V
10%
1
2
C884
0.01U/NA
0402
50V
+80-20%
1
2
R1 Q709
DTC144TKA
288202240001
2
1
3
C873
0.1U
0402
16V
10%
1
2
L51
120Z/100M
CORE_ACM2520U
1
4
2
3
JO715
1
2
C903
0.1U/NA
0402
16V
10%
1
2
JO719 1 2
L728
0
0603
1 2
U716
H5007/NA
H500X
1
2
3
24
23
22
4
5
6
21
20
19
7
8
9
10
11
12 13
14
18
17
16
15
D709
CL-190G/NA
A
K
X706
25MHZ
TXC8X4.5
274012500415
1 2
JO720 1 2
JO717
1
2
R944
0/NA
0805
1 2
U719
RTL8100CL
PQFP128A_0.5MM
127
113
114
115
117
8
125
121
122
1
2
5
6
14
15
18
19
31
23
105
33
34
36
37
39
40
42
43
47
49
50
53
55
57
58
59
79
82
83
85
86
87
89
90
93
95
96
97
98
102
103
104
111
109
108
106
2
4
3
2
4
5
5
4
6
4
7
8
9
9
1
1
0
1
1
6
1
2
6
2
6
4
1
5
6
7
1
8
4
9
4
1
0
7
3 7 1
6
2
0
1
0
1
2
0
2
2
3
5
4
8
5
2
6
2
7
3
8
0
1
0
0
1
1
2
1
1
8
2
1
3
8
5
1
6
6
8
1
9
1
1
0
1
1
1
9
1
3
1
7
9 4 1
2
3
1
2
4
1
2
8
11
12
72
74
92
77
60
44
28
65
68
61
29
30
46
25
63
67
76
88
70
75
69
27
RSET
NC_14
LED2
LED1
LED0
CTRL25
NC_13
XTAL1
XTAL2
TX+
TX-
RX+
RX-
NC_9
NC_10
NC_11
NC_12
PMEB
ISOLATEB
LANWAKE
AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
EESK
AUX/EEDI
EEDO
EECS
N
C
_
1
8
V
D
D
2
5
_
0
N
C
_
1
9
V
D
D
2
5
_
1
N
C
_
2
0
V
D
D
2
5
_
2
V
D
D
2
5
_
3
N
C
_
2
1
N
C
_
2
2
N
C
_
2
3
V
D
D
3
3
_
0
V
D
D
3
3
_
1
V
D
D
3
3
_
2
V
D
D
3
3
_
3
V
D
D
3
3
_
4
V
D
D
3
3
_
5
V
D
D
3
3
_
6
A
V
D
D
3
3
_
0
A
V
D
D
3
3
_
1
N
C
_
2
4
A
V
D
D
3
3
(R
E
G
)
N
C
_
2
5
N
C
_
2
6
N
C
_
0
G
N
D
_
0
N
C
_
1
G
N
D
_
1
N
C
_
2
N
C
_
3
G
N
D
_
2
G
N
D
_
3
N
C
_
4
N
C
_
5
G
N
D
_
4
G
N
D
_
5
G
N
D
_
6
G
N
D
_
7
G
N
D
_
8
G
N
D
_
9
G
N
D
_
1
0
G
N
D
_
1
1
N
C
_
6
G
N
D
_
1
2
N
C
_
7
G
N
D
_
1
3
G
N
D
_
1
4
G
N
D
_
1
5
G
N
D
_
1
6
NC_15
AVDD25
NC_16
NC_17
CBEB0
CBEB1
CBEB2
CBEB3
PCICLK
CLKRUNB
DEVSELB
FRAMEB
GNTB
REQB
IDSEL
INTAB
IRDYB
TRDYB
PAR
NC_8
PERRB
SERRB
STOPB
PCIRSTB
C894
0.1U
0402
16V
10%
1
2
L732
120Z/100M
2012
1 2
R303 0/NA 0603
1 2
JO721
1 2
C870
10U
16V
1206
1
2
L719
0
0603
1 2
C896
0.01U
0402
50V
+80-20%
1
2
C845
0.01U/NA
0402
1 2
R1090
49.9
0402
1%
1
2
C906
0.1U
0402
16V
10%
1
2
L735
120Z/100M
2012
1 2
R271
75
0402
1 2
R1111
0
0402
5%
1 2
C327
1000P
2KV
10%
1808
1
2
L736
120Z/100M/NA
2012
1 2
C895
0.1U
0402
16V
10%
1
2
C865
0.1U
0402
16V
10%
1
2
C890
0.1U/NA
0402
16V
10%
1
2
U717
LF-H80P
SOX16
7
6
8
10
11
9
1
3
2
16
14
15
4
5
12
13
TD+
TDC
TD-
TX+
TXC
TX-
RD+
RDC
RD-
RX+
RXC
RX-
NC0
NC1
NC2
NC3
R1108
10K/NA
0402
1 2
R297 0/NA 0603
1 2
R277
75
0402
1 2
D707
CL-190G/NA
A
K
R1070
1K/NA
0402
5%
1
2
U723
93C46
SO8
283467540002
1
2
3
4 5
6
7
8
CS
SK
DI
DO GND
NC0
NC1
VCC
R1067
49.9/NA
0402
1%
1
2
C854
0.01U/NA
0402
1 2
R263 0/NA 0603
1 2
C911
1U
0402
10V
+80-20%
1
2
C887
0.1U
0402
16V
10%
1
2
D708
CL-190G/NA
A
K
R278 0/NA 0603
1 2
R1109
510/NA
0402
1%
1
2
R1087
49.9
0402
1%
1
2
L48
120Z/100M/NA
CORE_ACM2520U
1
4
2
3
C893
0.1U
0402
16V
10%
1
2
C874
0.1U
0402
16V
10%
1
2
R1071
49.9/NA
0402
1%
1
2
R930 75
0402
1 2
R254 75/NA
0402
1 2
R1115
10K
0402
5%
1
2
L737
120Z/100M
2012
1 2
R1100
0/NA 0402
1 2
R1066
49.9/NA
0402
1%
1
2
C864
0.1U
0402
16V
10%
1
2
L738
120Z/100M/NA
2012
1 2
D710
CL-190G/NA
A
K
R285 0/NA 0603
1 2
R272 0/NA 0603
1 2
C915
27P
0402
5%
1
2
C882
0.01U/NA
0402
50V
+80-20%
1
2
R1086
49.9
0402
1%
1
2
C876
0.1U
0402
16V
10%
1
2
L731
120Z/100M/NA
2012
1 2
R1008
15K 0402
1 2
C914
27P
0402
5%
1
2
C862
0.1U
0402
16V
10%
1
2
C886
0.1U
0402
16V
10%
1
2
R1006
1K
0402
1
2
C891
0.1U
0402
16V
10%
1
2
RP27
0*4
1206
1
2
3
4
8
7
6
5
R1110
3.6K
0603
1 2
C866
0.1U
0402
16V
10%
1
2
R1102
510/NA
0402
1%
1
2
R305 0/NA 0603
1 2
R1101
1M
0402 1%
1 2
L49
120Z/100M
CORE_ACM2520U
1
4
2
3
RJ45
RJ11
J709
RJ11-2P/RJ45-8P
C10037-102XX
GND1
GND2
A2
A1
8
7
6
5
4
3
2
1
GND1
GND2
A2
A1
8
7
6
5
4
3
2
1
L44
120Z/100M/NA
CORE_ACM2520U
1
4
2
3
R152 75
0402
1 2
C849
0.01U/NA
0402
1 2
C904
0.1U
0402
16V
10%
1
2
R304 0/NA 0603
1 2
JO714
1
2
R947 100 0402 1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
CB710
(43K)
Multi Function pin need pull up.
IDSEL: AD20
PCI REQ0#
PCI GNT0#
PCI INTB#
INTC#
Ca r d Bu s &
Re a d e r ( CB7 1 0 )
PCB 316680900001/ASSY 411680900011 R01
8050 MOTHERB/D
C
Title
Size
Document
Number
Rev
Date: Sheet of
PCI_AD[0..31]
SD_CLK1
PCI_AD6
PCI_AD24
PCI_AD3
VCC5_EN#
MS_SDIO
SM_CE#
SD_LED#
SD_CMD
SD_CMD
VCC3_EN#
C
D
E
V
S
E
L
#
C
C
B
E
2
#
C
V
S
2
C
A
D
2
5
C
A
D
2
4
SERIRQ
PCI_AD0
SM_WP#
SM_SD2
SD_CLK
SD2
SD3
C
F
R
A
M
E
#
C
C
D
2
#
PCI_AD5
SERIRQ
CARD_ACT
VCC3_EN#
MS_PWREN#
MS_INS#
C
R
E
Q
#
R
2
_
A
1
8
C
A
D
1
0
C
A
D
2
PCI_AD19
PCI_AD10
CARD_MF1
CCLKRUN#
MS_LED#
SM_LVD
SM_SD6
SM_WPD#
C
P
E
R
R
#
C
T
R
D
Y
#
C
A
D
1
7
C
A
D
8
PCI_AD8
PCI_AD12
RI#
SM_SD1
SD_WP#
C
S
T
O
P
#
C
A
D
9
C
A
D
5
PCI_AD2
PCI_AD23
PCI_AD27
PCI_AD4
SM_ALE
SM_SD3
CARD_PCIRST#
CCLKRUN#
C
A
D
3
0
C
A
D
1
1
PCI_AD25
VPPD1
MS_INS#
SM_PWR3EN#
C
B
L
O
C
K
#
PCI_AD17
MS_CLK1
SDCD#
SD1
C
R
S
T
#
C
A
U
D
IO
R
2
_
D
1
4
C
V
S
1
C
A
D
1
8
C
A
D
2
0
PCI_AD21
PCI_AD14
PCI_AD20
PCI_AD13
PCI_AD16
SM_RE#
SD_WP#
VPPD1
C
A
D
2
9
C
A
D
2
8
C
A
D
1
PCI_AD29
PCI_AD15
CRST#
SM_PWR5EN#
SM_R/B#
SM_CLE
SM_SD4
SD_PWREN#
SM_R/B#
VPPD0
C
S
T
S
C
H
G
C
P
A
R
C
C
B
E
1
#
C
A
D
1
3
C
A
D
1
2
C
A
D
4
PCI_AD9
SM_CD#
SD_CLK1
SD3
SDCD#
SD0
SD0
CCLK
C
IR
D
Y
#
C
C
B
E
0
#
C
C
D
1
#
C
A
D
1
9
C
A
D
1
6
PCI_AD11
SM_SD0
SM_SD7
SD2
SM_CD#
CARD_ACT
C
IN
T
#
C
A
D
2
1
C
A
D
6
PCI_AD18
PCI_AD20
CARD_MF1
C
A
D
1
4
PCI_AD30
VPPD0
SD1
PCI_AD31
PCI_AD22
SM_WE#
C
G
N
T
#
C
C
B
E
3
#
C
A
D
2
7
C
A
D
3
1
C
A
D
3
C
A
D
0
CARD_PCIRST#
PCI_AD28
RI#
SM_WPD#
SM_SD5
C
S
E
R
R
#
R
2
_
D
2
C
A
D
2
2
C
A
D
2
3
PCI_AD7
PCI_AD26
PCI_AD1
CAD11
C
A
D
2
6
C
A
D
1
5
C
A
D
7
SC_PWR5EN#
SC_PWR3EN#
RI#
PCI_INTB#
PCI_INTC#
SD_PWREN#
MS_PWREN#
MS_CLK1
SM_RE#
SM_CE#
SM_WE#
CAD30
CAUDIO
CDEVSEL#
CAD10
R2_D2
CAD11
CCBE1#
CAD7
CAD28
CTRDY#
CAD8
CAD23
CPERR#
CVS2
CAD19
CCLKRUN#
CAD0
CAD17
R2_D14
CCBE0#
CAD5
CSERR#
CAD26
CPAR
CBLOCK#
CAD2
CCBE3#
CREQ#
CAD24
CAD22
CAD18
CIRDY#
CAD12
CAD9
CAD1
CFRAME#
CCD1#
CAD21
CCLK
CINT#
CAD3
CVS1
CAD4
CCD2#
CSTOP#
CAD13
CAD27
CAD14
R2_A18
CAD15
CAD20
CRST#
CCBE2#
CGNT#
CAD31
CAD6
CSTSCHG
CAD16
CAD29
CAD25
SD_LED#
MS_LED#
PCLKRUN#
VCC5_EN#
SD_WP#
MS_INS#
SD2
MS_SDIO
SM_LVD
MS_SCLK
MS_SCLK
MS_BS
MS_BS
PCI_INTF#
SD_CLK
SDCD#
SD_CLK
SD1
SD3
MS_SCLK
MS_SDIO
MS_BS
SD_CMD
SD0
SM_LED#
PCI_AD[0..31] 13,16,18,19
PCI_INTB# 13,24
PCI_C/BE#2 13,16,18,19
PCI_C/BE#3 13,16,18,19
PCI_C/BE#0 13,16,18,19
PCI_C/BE#1 13,16,18,19
PCI_REQ0# 13,24
PCI_GNT0# 13,24
PCI_TRDY# 13,16,18,19,24
PCI_FRAME# 13,16,18,19,24
PCI_PERR# 13,16,18,19,24
PCI_SERR# 13,16,19,24
PCI_DEVSEL# 13,16,18,19,24
PCI_IRDY# 13,16,18,19,24
PCI_STOP# 13,16,18,19,24
PCI_PAR 13,16,18,19
CARD_PCIRST# 13
SUSB# 13,22,23,25
PCLKRUN# 13,16,19,24
SERIRQ 13,14,19,22
PCICLK_CARD 11
CARDSPK# 20
CARDBUS_PME# 13
PWROK 4,12,13,25,31
PCI_INTC# 13,24
PCI_INTF# 13,19,24
GND
+SD_MSVDD
+CARD_VCC
+3V
+5V
GND
GND
GND
GND
+VPPOUT
+CARD_VCC
GND
+3V
+CARD_VCC
GND
+3V
GND
+3V
GND
GND
+VPPOUT
+3V
GND
+CARD_VCC
+3VS
+3V
GND
GND
+VPPOUT
GND
GND
+SD_MSVDD
GND
+3VS
GND
+SD_MSVDD
GND
+3V
+SD_MSVDD
+3V
GND_C3
GND_C2
GND
GND_C1
GND
GND_C4
GND_C1
GND_C2 GND_C4
GND_C3
GND
GND
GND
GND
+SD_MSVDD
+SD_MSVDD
+3V
GND
TP713 1
R1229
10K
0402
1
2
R1195 0/NA
0402 5%
1 2
C463
10U
6.3V
0805
10%
1
2
C996
0.1U
0402
16V
10%
1
2
C1002
1U
0402
10V
+80-20%
1
2
R378
1K
0402
5% 1
2
R1210 43.2K 0402 1% 1 2
U727
CB710
BGA_GHK_209
H5
G1
G3
H6
F1
G5
F2
E1
G6
F5
E3
C12
A4
E6
B5
F6
B8
A8
E9
F9
B9
A9
F10
E10
F11
E13
C11
B11
A12
B12
E12
A13
F15
E17
A16
C15
E14
F13
B15
E19
A10
F14
F
1
7
G15
C14
D19
A14
C13
B13
C10
F8
A7
B7
C7
F7
A6
B6
C6
E2
A5
C8
A15
R
8
W
7
V
7
W
6
V
6
U
6
V
5
U
5
N
1
M
3
L
1
M
1
T
1
N
3
P
1
P
5
P
6
M
6
N
2
N
6
N
5
R
1
R
2
R
3
W
4
R
6
W
1
0
U
1
0
P
1
0
H
2
J
1
J
3
K
1
K
3
V
1
0
R
1
0
W
1
1
H
1
J
2
J
6
K
2
K
5
H
3
R
9
K
6
L
2
L
6
L
5
M
2
P
3
U
9
V
9
W
9
W
8
V
8
U
8
P
7
P
8
R
7
W
5
J19
K14
K15
K19
L15
L17
L19
M15
W16
R14
W14
P14
N18
R17
N14
M14
P18
U15
T19
P15
R18
P
1
7
P19
N17
N19
M18
H14
G18
G14
U11
R11
U12
R12
V13
H15
G17
F
1
9
P11
V12
P12
W13
U13
V11
H17
P13
R
1
3
J18
M19
U14
W15
V15
R19
L18
H18
H19
J15
J14
J17
K17
L14
D
1
E
1
1
F
3
L
3
U
7
W
1
2
N15
G
1
9
B
1
4
A
1
1
C
9
E
7
F
1
8
M
1
7
M
5
G
2
J
5
P
2
P
9
V14
K
1
8
E
1
8
F
1
2
B
1
0
E
8
C
5
E
5
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
MFUNC0
MFUNC1
MFUNC2
MFUNC3
MFUNC4
MFUNC5
MFUNC6
VCCD0#
PCLK
VCCD1#
V
P
P
D
2
SPKROUT
RI_OUT#PME#
SUSPEND#
PRST#
GNT#
REQ#
IDSEL
FRAME#
IRDY#
TRDY#
DEVSEL#
STOP#
PERR#
SERR#
PAR
C/BE0#
C/BE1#
C/BE2#
C/BE3#
A
0
/C
A
D
2
6
A
1
/C
A
D
2
5
A
2
/C
A
D
2
4
A
3
/C
A
D
2
3
A
4
/C
A
D
2
2
A
5
/C
A
D
2
1
A
6
/C
A
D
2
0
A
7
/C
A
D
1
8
A
8
/C
C
B
E
1
#
A
9
/C
A
D
1
4
A
1
0
/C
A
D
9
A
1
1
/C
A
D
1
2
A
1
2
/C
C
B
E
2
#
A
1
3
/C
P
A
R
A
1
4
/C
P
E
R
R
#
A
1
5
/C
IR
D
Y
#
A
1
6
/C
C
L
K
A
1
7
/C
A
D
1
6
A
1
8
/R
S
V
D
(R
_
A
1
8
)
A
1
9
/C
B
L
O
C
K
#
A
2
0
/C
S
T
O
P
#
A
2
1
/C
D
E
V
S
E
L
#
A
2
2
/C
T
R
D
Y
#
A
2
3
/C
F
R
A
M
E
#
A
2
4
/C
A
D
1
7
A
2
5
/C
A
D
1
9
D
0
/C
A
D
2
7
D
1
/C
A
D
2
9
D
2
/R
S
V
D
(R
_
D
2
)
D
3
/C
A
D
0
D
4
/C
A
D
1
D
5
/C
A
D
3
D
6
/C
A
D
5
D
7
/C
A
D
7
D
8
/C
A
D
2
8
D
9
/C
A
D
3
0
D
1
0
/C
A
D
3
1
D
1
1
/C
A
D
2
D
1
2
/C
A
D
4
D
1
3
/C
A
D
6
D
1
4
/R
S
V
D
(R
_
D
1
4
)
D
1
5
/C
A
D
8
C
D
1
#
/C
C
D
1
#
C
D
2
#
/C
C
D
2
#
C
E
1
#
/C
C
B
E
0
#
C
E
2
#
/C
A
D
1
0
O
E
#
/C
A
D
1
1
IO
R
D
#
/C
A
D
1
3
IO
W
R
#
/C
A
D
1
5
W
E
#
/C
G
N
T
#
W
P
/C
C
L
K
R
U
N
#
B
V
D
1
/C
S
T
S
C
H
G
B
V
D
2
/C
A
U
D
IO
W
A
IT
#
/C
S
E
R
R
#
R
E
A
D
Y
/C
IN
T
#
V
S
1
#
/C
V
S
1
V
S
2
#
/C
V
S
2
R
E
G
#
/C
C
B
E
3
#
IN
P
A
C
K
/C
R
E
Q
#
R
E
S
E
T
/C
R
S
T
#
SM_ALE
SM_R/B#
SM_WE#
SM_LVD
SM_D7
SM_D1
SM_D2
SM_D4
SD_DAT2
SD_CMD
SD_LED#
SD_CLK
SC_OC#
SC_CLK
VCC_SC
SC_LED#
SC_PWR3EN#
SD_DAT3
SC_IO
SC_RST#
SC_C4
G
N
D
5
SC_CD#
GPIO9
SM_CD#
SM_D3
GPIO8
GPIO6
IRQSER
GPIO10
MS_SDIO
MS_SCLK
MS_LED#
SD_WP
GPIO7
GPIO5
V
P
P
D
0
MS_BS
MS_INS#
MS_PWREN#
MS_CLKIN
SD_CD#
GPIO11
SM_LED#
SD_PWREN#
G
N
D
4
SM_RE#
SM_D5
SD_DAT1
SD_DAT0
VCC_SD
SC_C8
SM_D6
SM_WPD#
SM_PWR3EN#
SM_PWR5EN#
SM_CE#
SM_CLE
SM_WP#
SM_D0
V
C
C
1
V
C
C
9
V
C
C
2
V
C
C
3
V
C
C
4
V
C
C
5
SC_PWR5EN#
V
C
C
7
V
C
C
8
G
_
R
S
T
V
C
C
1
0
V
C
C
1
1
V
P
P
D
1
V
C
C
6
V
C
C
A
G
N
D
0
G
N
D
1
G
N
D
2
G
N
D
3
SD_CLKIN
G
N
D
6
G
N
D
7
G
N
D
8
G
N
D
9
G
N
D
1
0
G
N
D
1
1
N
C
R1216 4.7K/NA 0402 1 2
R1214
0/NA
5%
0402G_DFS 1
2
R552
220
0402 5% 1 2
R1224 43.2K 0402 1% 1 2
JS5
SHORT-SMT4
1 2
C995
0.1U
0402
16V
10%
1
2
R1234 43.2K/NA 0402 1% 1 2
R1187
43.2K
0402
1%
1
2
J6
FM/34PX2/1.27MM
ACECON
MF-291000000008
291000256843
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
C341
0.1U
0402
16V
10%
1
2
TP712 1
C987
10P
0402
50V
5%
1
2
C989
0.1U/NA
0402
16V
10%
1 2
C994
0.1U
0402
16V
10%
1
2
R1190 0/NA 5%
0402G_DFS
1 2
R377
10K
0402
1
2
R435 0/NA 0402 5% 1 2
C993
0.1U
0402
16V
10%
1
2
TP711 1
R389 43.2K 0402 1% 1 2
C991
0.1U
0402
16V
10%
1
2
J716
MA/15PX2/ST
ACES
88025-3000
291000013027
1
3
5
7
9
11
13
15
17
2
4
6
8
10
12
14
16
18
20 19
GND1
GND2
21
23
25
27
29
22
24
26
28
30
GND3
GND4
GND5
GND6
R1204 0/NA
0402_DFS 5%
1 2
R1221
10K
0402
1
2
R1198
10
0402
5%
1 2
R1242 10K 0402 1 2
R1212
10K/NA
0402
1
2
TP16 1
R1209 43.2K 0402 1% 1 2
R1225 43.2K 0402 1% 1 2
R1200 4.7K 0402 1 2
R1194
0/NA 5%
0402G_DFS
1 2
R1202 100
0402 5%
1 2
JS7
SHORT-SMT4
1 2
R1228 8.2K 0402 1 2
R1192 10K 0402 1 2
R431 0 0402 5% 1 2
R1238
0/NA 0402
5%
1 2
TP708 1
TP716 1
R1188
10K
0402
1
2
C465
0.1U
0402
50V
+80-20%
1
2
R1230 8.2K 0402 1 2
R1220 4.7K/NA 0402 1 2
C992
0.1U
0402
16V
10%
1
2
C1001
2.2U
0603
+/-10%
1
2
R1213
33
0402
1
2
R1235 43.2K 0402 1% 1 2
R1231 8.2K 0402 1 2
JS8
SHORT-SMT4
1 2
R1226 43.2K 0402 1% 1 2
TP707 1
TP19 1
R1208 43.2K 0402 1% 1 2
D36
CL-190G
A K
C985
0.1U
0402
16V
10%
1
2
R1237 43.2K 0402 1% 1 2
D S
G
Q24
SI2301DS
G
D S
C983
0.1U
0402
16V
10%
1
2
R1241 10K 0402 1 2
TP709 1
R388 43.2K 0402 1% 1 2
C988
10P
0402
50V
5%
1
2
R1205 43.2K 0402 1% 1 2
R444 0/NA 0402 5% 1 2
R1196
10K/NA 0402
1 2
R1191 0/NA 5%
0402G_DFS
1 2
R1197 10K/NA 0402
1 2
R1217
0/NA
5%
0402G_DFS 1
2
R1193 0/NA 5%
0402G_DFS
1 2
TP715 1
R376
100K
0402
5%
1
2
R1211 43.2K 0402 1% 1 2
L54
120Z/100M
2012
273000150013
1
2
R440 0 0402 5% 1 2
R1199 10K 0402
1 2
R1203
10
0402
5%
1 2
U728
TPS2211A SSOP16
286302211006
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VCCD0
VCCD1
3.3VA
3.3VB
5VA
5VB
GND
OC
SHDN
VDDP0
VDDP1
AVCCA
AVCCB
AVCCC
AVPP
12V
R1218 4.7K/NA 0402 1 2
C986
0.1U
0402
16V
10%
1
2
C999
0.1U
0402
16V
10%
1
2
Q714
DTC144WK/NA
1
2
3
JS4
SHORT-SMT4
1 2
R1233 43.2K 0402 1% 1 2
C984
0.1U
0402
16V
10%
1
2
TP18 1
C998
0.1U
0402
16V
10%
1
2
C1000
0.1U
0402
16V
10%
1
2
D
S
Q716
2N7002
G
D
S
R1207 43.2K 0402 1% 1 2
R1189
43.2K
0402
1%
1
2
R1201 10K 0402
1 2
C997
0.1U
0402
16V
10%
1
2
R1206 43.2K 0402 1% 1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
IEEE1394(VT6307L)
Configuration Straps
I2CEEENA I2C EEPROM.
0: 4-wire EEPROM interface(Default)
1: 2-wire I2C EEPROM interface
using SCL/SDA
I2CFAST I2C EEPROM Fast Mode
0: Disable (Default)
1: Enable
CARDBUSENA CardBus Mode
0: Disable (PCI)(Default)
1: Enable
PHYCMC Programmable Contender / Bus Manager Capable
High specifies that the node is capable of
being a bus manager.
VT6307L
IDSEL: AD21
PCI REQ1#
PCI GNT1#
PCI INTG#
ALL Capacator must close to power pin
Because of EMC notice, change
L547 to 0 ohm 0805
1394_AVCC:Because of
suspend then resume
unknow, us suspend
power
PCB 316680900001/ASSY 411680900011 R01
8050 MOTHERB/D
C
Title
Size
Document
Number
Rev
Date: Sheet of
PCI_AD21
XI
XO
XI
EECS_1394
EEDO_1394
EEDI_1394
EECK_1394
EECS_1394
EECK_1394
EEDI_1394
EEDO_1394
TPBIAS
TPBIAS
XO
PCI_AD31
PCI_AD11
PCI_AD14
PCI_AD21
PCI_AD18
PCI_AD15
PCI_AD24
PCI_AD19
PCI_AD5
PCI_AD22
PCI_AD27
PCI_AD8
PCI_AD26
PCI_AD28
PCI_AD30
PCI_AD17
PCI_AD3
PCI_AD9
PCI_AD16
PCI_AD10
PCI_AD7
PCI_AD20
PCI_AD6
PCI_AD0
PCI_AD1
PCI_AD29
PCI_AD23
PCI_AD4
PCI_AD13
PCI_AD2
PCI_AD12
PCI_AD25
TPB-_6307
TPA- TPA-_6307
TPA+_6307
TPB-
TPA-_6307
TPB+_6307
TPA+
PCI_AD[0..31]
TPB-_6307
TPB+_6307 TPB+
TPA+_6307
PCI_AD[0..31] 13,16,17,19
PCI_C/BE#0 13,16,17,19
PCI_C/BE#1 13,16,17,19
PCI_C/BE#2 13,16,17,19
PCI_C/BE#3 13,16,17,19
PCI_FRAME# 13,16,17,19,24
PCI_DEVSEL# 13,16,17,19,24
PCI_TRDY# 13,16,17,19,24
PCI_IRDY# 13,16,17,19,24
PCI_GNT1# 13,24
PCI_REQ1# 13,24
PCI_INTG# 13,24
PCICLK_1394 11
PCI_PAR 13,16,17,19
PCI_PERR# 13,16,17,19,24
PCI_STOP# 13,16,17,19,24
1394_PCIRST# 13
PCI_PME# 13
GND
+3V
1394_AVCC
+3V
GND GND
GND
+3V
GND GND
GND
GND
GND
GND
GND
1394_AGND GND
1394_AGND
+PHYVDD
GND
+3VS +3V
+PHYVDD
1394_AVCC
GND
+PHYVDD
+3V
GND
+3V
GND
1394_GND
1394_GND
+3VS
1394_GND GND
+3V
1394_AGND
R1148
4.99K
0402
1%
1
2
R1142
54.9
0402
1%
1
2
C965
270P
0402
50V
+/-10%
1
2
C923
0.1U
0402
50V
+80-20%
1
2
C931
0.1U
0402
50V
+80-20%
1
2
R1146 1K/NA
0402 5%
1 2
L743
120Z/100M
2012
1 2
R534 0/NA 0402 5% 1 2
D711
ESD0805A/NA
A
K
C929
10P
0402
50V
5%
1
2
JO48
1
2
D706
ESD0805A/NA
A
K
R1117 100
0402 1%
1 2
C921
2.2U
+80-20%
0805C
1
2
C957
0.1U
0402
50V
+80-20%
1
2
D28
ESD0805A/NA
A
K
C919
0.1U
0402
50V
+80-20%
1
2
R1147
1K
0402
5%
1
2
D30
ESD0805A/NA
A
K
C922
0.1U
0402
50V
+80-20%
1
2
C954
0.1U
0402
50V
+80-20%
1
2
L83
120Z/100M
CORE_ACM2520U 1
4
2
3
U722
93C46
SO8
283467540002
1
2
3
4 5
6
7
8
CS
SK
DI
DO GND
NC0
NC1
VCC
C907
1U
0402
10V
+80-20%
1
2
R1139 0/NA 0402 5% 1 2
R1149 0/NA 0402 5% 1 2
JO52
1
2
L87
120Z/100M
2012
1 2
L742
120Z/100M/NA
2012
1 2
R1143
54.9
0402
1%
1
2
L739
120Z/100M/NA
1 2
JO53
1
2
C961
2.2U
+80-20%
0805C
1
2
C958
47P
0402
50V
+/-10%
1
2
C918
0.1U
0402
50V
+80-20%
1
2
C955
0.1U
0402
50V
+80-20%
1
2
C925
0.1U
0402
50V
+80-20%
1
2
C924
0.1U
0402
50V
+80-20%
1
2
L746
120Z/100M
2012
1 2
R1116
1M
0402
5%
1 2
R543 0/NA 0402 5% 1 2
C936
0.1U
0402
50V
+80-20%
1
2
C928
0.1U
0402
50V
+80-20%
1
2
R1141
54.9
0402
1%
1
2
R1145
6.34K
0402
1%
1
2
C917
0.1U
0402
50V
+80-20%
1
2
C920
0.1U
0402
50V
+80-20%
1
2
L747
120Z/100M
2012
1 2
C964
0.33U
0402
16V
+80-20%
1
2
J718
4PX1/0.8MM-MA
MOLEX
54030-0411
331000004009
1
2
3
4
5
6
1
2
3
4
GND0
GND1
L740
120Z/100M
CORE_ACM2520U 1
4
2
3
R1112
4.7K/NA 0402 5%
1 2
U724
VT6307L
PQFP128A_0.5MM
28
27
23
22
21
19
18
17
14
13
12
11
10
7
6
5
120
119
118
117
116
112
110
109
106
105
104
101
100
99
98
97
15
4
122
107
47
127
123
1 9 1
6
2
6
3
4
3
6
9
4
1
0
3
1
1
1
1
1
5
1
2
1
6
4
6
8
8
2
5
9
6
9
8
3
2
5
4
1
5
0
46
48
108
91
124
93
92
95
52
54
55
53
58
96
128
126
38
40
44
45
51
56
57
67
8 2
0
3
3
3
5
1
0
2
1
1
3
1
1
4
1
2
5
6
5
7
5
8
9
6
2
7
6
9
0
2
4
3
9
4
9
63
60
61
66
74
81
88
72
73
79
80
86
87
70
71
77
78
84
85
3
2
32
29
31
30
43
42
37
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
CBE0#
CBE1#
CBE2#
CBE3#
CARDBUSENA
DEVSEL#
FRAME#
G
N
D
0
G
N
D
1
G
N
D
2
G
N
D
3
G
N
D
4
G
N
D
5
G
N
D
6
G
N
D
7
G
N
D
8
G
N
D
9
G
N
D
1
0
G
N
D
A
R
X
0
G
N
D
A
R
X
1
G
N
D
A
R
X
2
G
N
D
A
T
X
0
G
N
D
A
T
X
1
G
N
D
A
T
X
2
G
N
D
R
A
M
G
N
D
S
U
S
[0
]
G
N
D
S
U
S
[1
]
12CEEENA
I2CFAST
IDSEL
INTA#
IRDY#
PCICLK
PCIRST#
PGNT#
PHYCMC
PHYPC0
PHYPC1
PHYPC2
PHYRST#
PREQ#
STOP#
TRDY#
NC0
NC1
NC2
NC3
NC4
NC5
NC6
NC7
V
C
C
0
V
C
C
1
V
C
C
2
V
C
C
3
V
C
C
4
V
C
C
5
V
C
C
6
V
C
C
7
V
C
C
A
R
X
0
V
C
C
A
R
X
1
V
C
C
A
R
X
2
V
C
C
A
T
X
0
V
C
C
A
T
X
1
V
C
C
A
T
X
2
V
C
C
R
A
M
V
C
C
S
U
S
[0
]
V
C
C
S
U
S
[1
]
XCPS
XI
XO
XRES
XTPBIAS0
XTPBIAS1
XTPBIAS2
XTPA0M
XTPA0P
XTPA1M
XTPA1P
XTPA2M
XTPA2P
XTPB0M
XTPB0P
XTPB1M
XTPB1P
XTPB2M
XTPB2P
PAR
PERR#
EECK/SCL/EEFAST
EECS/EEAUTO#
EEDI/SDA
EEDO
MODE0
MODE1
PME#
X707
24.576MHZ
TXC8X4.5
274012457406
1 2
C916
0.1U
0402
50V
+80-20%
1
2
C956
0.1U
0402
50V
+80-20%
1
2
C932
10P
0402
50V
5%
1
2
JO49
1
2
R1144
54.9
0402
1%
1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
MINI-PCI FROM LYNX-AMD
PIN24, 124 ARE AUX_POWER
REQ2#/GNT2#
AD17
PCI_INTD#
MINI-PCI
PCB 316680900001/ASSY 411680900011 R01
8050 MOTHERB/D
C
Title
Size
Document
Number
Rev
Date: Sheet of
PCI_AD[0..31]
MINIPCI_PCIRST#
PCICLK_MINIPCI
PCLKRUN#
PCI_CBE#3
PCI_AD20
PCI_AD12
PCI_SERR#
PCI_AD18
PCI_AD10
PCI_CBE#2
PCI_AD23
PCI_STOP#
PCI_PME#
PCI_AD27
PCI_PAR
PCI_AD17
PCI_AD11
PCI_AD16
PCI_AD8
PCI_AD17
PCI_AD15
PCI_AD7
PCI_TRDY#
PCI_AD9
PCI_PERR#
PCI_AD6
PCI_IRDY#
PCI_AD31
PCI_AD2
PCI_AD13
PCI_AD26
PCI_AD5
PCI_AD19
PCI_AD21
PCI_AD29
PCI_CBE#0
PCI_AD4
PCI_AD3
PCI_AD24
PCI_AD30
PCI_CBE#1
PCI_AD0
PCI_AD22
PCI_AD1
PCI_AD14
PCI_FRAME#
PCI_AD28 PCI_AD25
MINIPCI_PD
PCI_DEVSEL#
MINIPCI_PD
MINIPCI_GPORESET#
MINI_REQ2#
MINIPCI_LPCDRQ#
MINIPCI_LPCAD0
MINIPCI_PCISERIRQ
MINIPCI_LPCFRAME#
MINIPCI_LPCAD1
MINIPCI_LPCAD2
MINIPCI_LPCAD3
MINIPCI_LPCAD3
MINIPCI_LPCAD1
MINIPCI_LPCAD0
MINIPCI_LPCAD2
MINIPCI_LPCFRAME#
MINIPCI_LPCDRQ#
MINIPCI_PCISERIRQ
MINIPCI_SIO48M
MINIPCI_SIO48M
PCI_AD[0..31] 13,16,17,18
PCI_INTF# 13,17,24
PCI_PERR# 13,16,17,18,24
PCICLK_MINIPCI 11
PCI_REQ2# 13,24
PCI_C/BE#3 13,16,17,18
PCI_C/BE#2 13,16,17,18
PCI_IRDY# 13,16,17,18,24
PCI_SERR# 13,16,17,24
PCI_C/BE#1 13,16,17,18
PCI_INTD# 13,24
PCI_GNT2# 13,24
PCI_PAR 13,16,17,18
PCI_TRDY# 13,16,17,18,24
PCI_FRAME# 13,16,17,18,24
PCI_STOP# 13,16,17,18,24
PCI_DEVSEL# 13,16,17,18,24
PCI_C/BE#0 13,16,17,18
WIRELESS_PD# 14,24
MINIPCI_ACT# 14,24
MINIPCI_PCIRST# 13
MINIPCI_PME# 13
PCLKRUN# 13,16,17,24
LAD0 13,22,23
LAD1 13,22,23
LAD2 13,22,23
LAD3 13,22,23
LFRAME# 13,22,23
SERIRQ 13,14,17,22
LRDQ0# 13
SIO_48M 11
+3V
GND
GND
GND
+3VS
+3V
GND
+5V
GND
+3V
+3V GND
+3V
GND
+5V
GND
+5V
R1095 0/NA 0402 5% 1 2
J713
124P/0.8MM/H6
SPEED
SPEED-B27-101-0038
291000251246
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
GND1
GND2
TIP
RX+
RX-
PJ7
PJ8
LED1_GRNP
LED1_GRNN
CHSGND
INTB#
3.3V[0]
RESERVED0
GROUND0
CLK
GROUND1
REQ#
3.3V[1]
AD[31]
AD[29]
GROUND2
AD[27]
AD[25]
RESERVED1
C/BE[3]#
AD[23]
GROUND3
AD[21]
AD[19]
GROUND4
AD[17]
C/BE[2]#
IRDY#
3.3V[2]
CLKRUN#
SERR#
GROUND5
PERR#
C/BE[1]#
AD[14]
GROUND6
AD[12]
AD[10]
GROUND7
AD[8]
AD[7]
3.3V[3]
AD[5]
RESERVED2
AD[3]
5V[0]
AD[1]
GROUND8
AC_SYNC
AC_SDATA_IN
AC_BIT_CLK
AC_CODEC_ID1#
MOD_AUDIO_MON
AUDIO_GND0
SYS_AUDIO_OUT
SYS_AUDIO_OUT_GND
AUDIO_GND1
RESERVED3
VCC5VA
RING
TX+
TX-
PJ4
PJ5
LED2_YELP
LED2_YELN
RESERVED4
5V[1]
INTA#
RESERVED5
3.3VAUX[0]
RST#
3.3V[4]
GNT#
GROUND9
PME#
RESERVED6
AD[30]
3.3V[5]
AD[28]
AD[26]
AD[24]
IDSEL
GROUND10
AD[22]
AD[20]
PAR
AD[18]
AD[16]
GROUND11
FRAME#
TRDY#
STOP#
3.3V[6]
DEVSEL#
GROUND12
AD[15]
AD[13]
AD[11]
GROUND13
AD[9]
C/BE[0]#
3.3V[7]
AD[6]
AD[4]
AD[2]
AD[0]
RESERVED_WIP4[0]
RESERVED_WIP4[1]
GROUND14
M66EN
AC_SDATA_OUT
AC_CODEC_ID0#
AC_RESET#
RESERVED7
GROUND15
SYS_AUDIO_IN
SYS_AUDIO_IN_GND
AUDIO_GND2
MPCIACT#
3.3VAUX[1]
GND1
GND2
R1091 0 0402 5% 1 2
R1079 0
0402 5%
1 2
R1093
0/NA
0402
5% 1
2
R1003 0
0402 5%
1 2
R1118 0 0402 5% 1 2
TP721
TOUCHPAD_10
1
R1092 100
0402 1%
1 2
C910
0.1U
0402
50V
+80-20%
1
2
D38
CL-190G
LED_CL190
A
K
R1077 0 0402 5% 1 2
R1083 0
0402 5%
1 2
R1078 0/NA 0402 5% 1 2
R1064 0/NA
0402 5%
1 2
R1007 10K
0402 5%
1 2
R1065 0 0402 5% 1 2
R1096 0 0402 5% 1 2
C885
10P/NA
0402
50V
+/-10%
1
2
R1069 0 0402 5% 1 2
R1068 0 0402 5% 1 2
R1094 0 0402
5%
1 2
C892
0.1U
0402
50V
+80-20%
1
2
C901
0.1U
0402
50V
+80-20%
1
2
C899
0.1U
0402
50V
+80-20%
1
2
R1080 0 0402 5% 1 2
R1075 0 0402 5% 1 2
R1088 0 0402 5% 1 2
R1072 0/NA 5%
0402G_DFS
1 2
R1137 0 0402 5% 1 2
C875
2.2U
0603
+/-10%
1
2
R1076 0/NA 0402
5%
1 2
C888
0.1U
0402
50V
+80-20%
1
2
R1138 0 0402 5% 1 2
R1 Q710
DTC144TKA
288202240001
2
1
3
C909
0.1U
0402
50V
+80-20%
1
2
C881
0.1U
0402
50V
+80-20%
1
2
R558
470
0402
5%
1
2
C898
0.1U
0402
50V
+80-20%
1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
20mil
L.CH
R.CH
273000130006
JP, use 4pcs of 2kV 1000P cap
UK, use 4pcs of 3kV 1000P cap
GND_45
US, use 2pcs of 2kV 1000P cap
CLOSE TO MDC
AUDIO CODEC(ALC655)
MDC
FOR EMI REQUEST CHANGE TO 0 OHM
PCB 316680900001/ASSY 411680900011 R01
8050 MOTHERB/D
C
Title
Size
Document
Number
Rev
Date: Sheet of
MIC2
ACSYNC
CDROM_RIGHT
ACRST#
CDROM_COMM
ACSDOUT
MIC1
ACSDIN0
AOUT_R
CDROM_LEFT
PC_BEEP
ACBITCLK
JD0
MONO_OUT
AOUT_L
MODEM_SPK
AVDD
MIC
MIC_VREF
2464_VREF
MIC_INT
LINE_IN/L
LINE_IN/R
AOUT_R
SUB_OUTL
SUB_OUTR
AOUT_L
SBSPKR
CARDSPK# PC_BEEP
LINE_IN/L
LINE_IN/R
MODEMN
ACBITCLK
ACSDOUT
ACBITCLK
ACSDIN1
MODEM_SPK
ACSYNC
ACRST#
MONO_OUT
MODEMP
MIC_VREF MIC_EXT
ACRST# 14
ACSDOUT 14
ACSDIN0 14
ACSYNC 14
ACBITCLK 14
EAPD 21
14M_CODEC 11
CDROM_RIGHT 15
CDROM_LEFT 15
CDROM_COMM 15
2464_VREF 21
AMP_RIGHT 21
AMP_LEFT 21
SUB_OUTL 21
SUB_OUTR 21
SUB_RIGHT 21
SUB_LEFT 21
CARDSPK# 17
SBSPKR 13,14
MODEMP 16
MODEMN 16
ACSDIN1 14
SPDIFOUT 21
GND
AGND
AGND AGND
GND
AGND
AGND
GND
GND
AGND
AGND
+3V
GND
AGND
AGND
AGND
GND
GND
AGND
+5V
VA
AGND
CAGND
AGND
AGND
AGND AGND
AGND AGND
AGND
AGND
GND
AGND
AGND
GND
AGND
GND
GND
AGND
CAGND
CAGND
CAGND
AGND
GND
GND
VA
AGND
AGND
CAGND
CAGND
GND
GND
AGND
AGND
GND
+3VS
GND GND
+3V
+3V
GND
+5V
GND
AGND
AGND
CAGND
GND
L724
50UH
CHOKE_WLT04020201
2
1
3
5
R520
22K
0402
1%
1
2
C962 1000P
0402 50V 10%
1 2
R549
6.8K
0402
5%
1
2 C959 1U
0402 10V +80-20%
1 2
L64
120Z/100M/NA
2012 1 2
R537
6.8K
0402
5%
1
2
C975 1U
0402 10V +80-20%
1 2
C518
0.1U/NA
0402
16V
10%
1
2
R1155 0
0603
1 2
L62
120Z/100M
2012
1 2
C972
0.1U/NA
0402
50V
+80-20%
1
2
J10
1
2
C953 1U
0402 10V +80-20%
1 2
C948
100P/NA
0402
50V
+/-10%
1
2
R519
0 0402 5%
1 2
C460 0.1U
0402 16V
10%
1 2
L725
120Z/100M/NA
2012 1 2
J715
HDR/MA-2
ACES
85204-0200
291000020206
1
2
R1136
1K
0402
5%
1
2
R535 0
0402 5%
1 2
C475
10U
10V
1210
1
2
R1134
0/NA 0402 5%
1 2
L66
120Z/100M
2012
1
2 C455
100P
0402
50V
+/-10%
1
2
L57
BEAD_600Z/100M
0603D 1 2
C966
1U
0402
10V
+80-20%
1
2
C974 1U
0402 10V +80-20%
1 2
R1123 0/NA
0402 5%
1 2
R1129
27K/NA
0402
5%
1
2
R503 0/NA
0402 5%
1 2
R324
0 0402 5%
1 2
C481
0.1U
0402
16V
10%
1
2
C976 1U
0402 10V +80-20%
1 2
R547 6.8K 0402 5% 1 2
C912
10P/NA
0402
50V
+/-10%
1
2
R325
22K
0402
1%
1
2
X2
24.576MHZ/NA
TXC8X4.5
274012457406
1 2
R1153
0 0402 5%
1 2
R1127 4.42K
0402 5%
1 2
R849
560-2010/NA
0805
1
2
C515 0.22U
0402 16V +80-20%
1 2
L76
BEAD_600Z/100M
0603D 1 2
R1151
4.7/NA 0402 5%
1 2
C913
0.1U
0402
10V
10%
1
2
C960 1000P
0402 50V 10%
1 2
C507 1U
0402 10V +80-20%
1 2
R1130 4.42K
0402 5%
1 2
C969 1U
0402 10V +80-20%
1 2
R442
47K
0402
5%
1
2
C501
0.1U
0402
16V
10%
1
2
R484
180K/NA
0603
1%
1
2
R1124 0
0402 5%
1 2
L721
120Z/100M/NA
2012 1 2
J11
1
2
R472 0
0402 5%
1 2
R1120 22 0402 5% 1 2
L53
BEAD_600Z/100M
0603D 1 2
C970 1U
0402 10V +80-20%
1 2 R530 22
0402 5%
1 2
C940 1U
0402 10V +80-20%
1 2
C942
47P/NA
0402
50V
+/-10%
1
2
C939 1U
0402 10V +80-20%
1 2
C476
22P/NA
0402
50V
+/-10%
1
2
C926
0.1U
0402
10V
10%
1
2
C509
2200P
0402
50V
+/-20%
1
2
C938
0.1U
0402
50V
+80-20%
1
2
R1154
4.7K
0402
5%
1 2
R1133
0/NA
0402
5%
1
2
R1135 0
0402 5%
1 2
C467
0.01U
0402
50V
+80-20%
1
2
C980 1U/NA
0402 10V +80-20%
1 2
D718
ESD0805A/NA
0603B_0805C
1 2
L734
BEAD_600Z/100M
0603D 1 2
C968
0.1U
0402
50V
+80-20%
1
2
C927
0.1U
0402
10V
10%
1
2
C963
1U
0402
10V
+80-20%
1
2
C516 1U
0402 10V +80-20%
1 2
R1157
0 0402 5%
1 2
R1131 22 0402 5% 1 2
C504
22P/NA
0402
50V
+/-10%
1
2
C457
0.1U
0402
16V
10%
1 2
R1121 22/NA 0402 5% 1 2
R1126
27K/NA
0402
5%
1
2
U18
MIC5205BM5
SOT25
1
2
3 4
5
IN
GND
EN ADJ
OUT
C952 1U/NA
0402 10V +80-20%
1 2
U726
ALC655
PQFP48_0.5MM
2
3
5
6
8
10
11
17
16
45
46
47
48
27
28
31
12
13
14
15
18
19
20
21
22
23
24
34
32 35
36
37
39
41
43
44
29
30
33
40
2
6
4
2
4 7
2
5
3
8
1 9
XTL-IN
XTL-OUT
SDATA-OUT
BIT-CLK
SDATA-IN
SYNC
RESET#
JD1/GPIO1
JD2
JD0/GPIO0
XTLSEL
SPDIFI/EAPD
SPDIFO
VREF
VREFOUT
VRDA
PC-BEEP
PHONE
AUX-L
AUX-R
CD-L
CD-GND
CD-R
MIC1
MIC2
LINE-L
LINE-R
FRONT-MIC1
FRONT-MIC2 LINE-OUT-L
LINE-OUT-R
MONO-OUT
S-OUT-L
S-OUT-R
CEN-OUT
LFE-OUT
AFILT1
AFILT2
NC_0
NC_1
A
V
S
S
1
A
V
S
S
2
D
V
S
S
1
D
V
S
S
2
A
V
D
D
1
A
V
D
D
2
D
V
D
D
1
D
V
D
D
2
R1150 0
0603
1 2
R538 6.8K 0402 5% 1 2
C458
0.1U
0402
16V
10%
1 2
R546
6.8K
0402
5%
1
2
R438
10K
0402
5%
1 2
L741
120Z/100M/NA
CORE_ACM2520U
1
4
2
3
C330
100P
0402
50V
+/-10%
1
2
U17
NC7S32
SOT25
1
2
3
5
4
A
B
GND
VCC
Y
R437
1K
0402
5%
1
2
C937 0.1U
0402 16V 10%
1 2
R497 0/NA
0402 5%
1 2
C498
100P
0402
50V
+/-10%
1
2
R498 22
0402 5%
1 2
L70
BEAD_600Z/100M
0603D 1 2
D705
ESD0805A/NA
0603B_0805C
1
2
R516
1M/NA 0402
1 2
R532 0
0402 5%
1 2
C148 1000P 2KV10% 1808 1 2
R559 10K/NA
0402 5%
1 2
R550 0 0402 5% 1 2
C933
1000P/NA
0402
50V
10%
1
2
JO724
SPARKGAP_6
1
2
C159
100P/NA
0402
50V
+/-10%
1
2
R1164
22K/NA 0402 1%
1 2
C519 0.1U/NA
0402 16V 10%
1 2
L751
120Z/100M
1608
1 2 J717
FM/0.8MM/H2.4
AMP C-179373
291000023008
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
R452
470K/NA
0402
5%
1
2
C456
1U
0402
10V
+80-20%
1 2
R1128 0
0402 5%
1 2
+
-
MIC1
D5.8/H2.0
EM147TK
339115000046
1
2
R1132
4.7K
0402
5%
1 2
C491
10U
6.3V
0805
10%
1
2
C477
22P/NA
0402
50V
+/-10%
1
2
L744
BEAD_600Z/100M
0603D
1
2
C971
0.1U/NA
0402
50V
+80-20%
1
2
C967
0.1U
0402
16V
10%
1
2
C945 0.1U/NA
0402 16V 10%
1 2
C499
100P/NA
0402
50V
+/-10%
1
2
L65
120Z/100M
2012
1 2
L88
120Z/100M
2012
1 2
R560
1K/NA
0402
5%
1
2
JO725
SPARKGAP_6
1 2
L73
120Z/100M
2012
1 2
F2
MINISMDC014-2
POLYSW_MINISMDC110
1 2
J719
RA/D6/6P
2SJ-SB2014D3
CONN_JACK_SB2014
291000920605
1
6
2
3
4
5
L69 0 1608
1 2
C806 1000P 2KV 10% 1808 1 2
R443
47K
0402
5%
1
2
C973
4.7U/NA
6.3V
0603
+80-20%
1
2
C513 1U
0402 10V +80-20%
1 2
C979 1U/NA
0402 10V +80-20%
1 2
R542
5.6K
0402
5%
1
2
J721
RA/D6/6P
2SJ-SB2014D3
CONN_JACK_SB2014
291000920605
1
6
2
3
4
5
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
USE 3K 1%
USE 2200P
10%
USE 2200P
10%
USE 3K 1%
SUBWOOFER AMP(LM4871)
AUDIO AMPLIFIER
on device
0
OPT in 0
HP in
1
REMARK
1
0
no this condition
0
DEVICE_DECT#
1
DECT_HP#/OPT
1
PCB 316680900001/ASSY 411680900011 R01
8050 MOTHERB/D
C
Title
Size
Document
Number
Rev
Date: Sheet of
SUB_OUTR
SUB_OUTL
2464VREF1
2464VREF2
SUB_OUTR
SUB_OUTL
SUB_OUTL
SUB_OUTR
RIN_2464
2464VREF1
SUB_RIGHT
2464VREF2
SUB_LEFT SUB_OUTL
SUB_OUTR
ROUT+
AMPVDD
AMP_RIGHT
SPK_OFF#
AMPVDD
AMP_LEFT
AMP_OFF
AMP_SHUTDOWN
ROUT-
DEVICE_DECT#
AGND
DECT_HP#OPT
DECT_HP#OPT
DEVICE_DECT#
DEVICE_DECT#
DEVICE_DECT
DEVICE_DECT
AMP_SHUTDOWN
OPTIN#
OPTIN#
SPK_OFF#
AMPVDD
AMP_OFF
SUB_LEFT 20
SUB_RIGHT 20
2464_VREF 20
SUB_OUTL 20
SUB_OUTR 20
AMP_LEFT 20
AMP_RIGHT 20
EAPD 20
SPK_OFF 13,24
SPDIFOUT 20
KBC_MUTE 22
AGND
GND
+5V
GND
AGND AGND
AGND
VA
VA
AGND
VA
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND AGND
CAGND
AGND
AGND
+5V
AGND
AGND
GND
GND
+5V +3V
+5V
+5VS_SUBAMP
AGND
AGND
AGND
AGND
AGND
VA
AGND
GND
+3V
AGND
VA
+5V
GND
CAGND CAGND
GND
CAGND
CAGND
AGND
R1183
10K
0402
1
2
L758
600Z/100M
1608
1
2
D
S
Q36
2N7002/NA
G
D
S
C490
0.15U
0603
1 2
R454
1K
0402
5%
1
2
R1 Q52
DTC144TKA
288202240001
2
1
3
JO10
1 2
R329 22 0402 5% 1 2
R461
3K/NA
0402 5%
1 2
+ C489
100U
6.3V
20%
1
2
C496 0.22U
0402 16V +80-20%
1 2
R1 Q23
DTC144TKA
288202240001
2
1
3
D6
ESD0603/NA
1 2
C483 0.22U
0402 16V +80-20%
1 2
R463
22.1K 0402 1%
1 2
R1161 100K 0402 5% 1 2
C470
2200P
0402
50V
+/-20%
1
2
R391 100K/NA 0402 5% 1 2
D27
RLS4148
A K
R1160 100K/NA 0402 5% 1 2
D22
BAT54C
1
2
3
L63
120Z/100M
2012
1 2
R510
22.1K 0402 1%
1 2
C493 1U
0402 10V
1 2
L52
600Z/100M 1608 1 2
D19
RLS4148
A K
L757
600Z/100M
1608
1 2
R451 10K/NA
0402 5% 1 2
C492 1U
0402 10V +80-20%
1 2
C484 1U
0402 10V
1 2
+ C951
100U
6.3V
20%
1
2
C356
100P/NA
0402
50V
10%
1
2
R460
47K/NA
0402
5%
1
2
+ C474
100U
6.3V
20%
1
2
J3
HDR/MA-2
ACES
85204-0200
291000020206
1
2
L50
600Z/100M 1608 1 2
R509
22.1K 0402 1%
1 2
R507
18K
0402
1%
1
2
R506
3K/NA
0402 5%
1 2
L759
600Z/100M
1608
1
2
R489
1M/NA
0402
5%
1
2
C485 1U
0402 10V +80-20%
1 2
R322
4.7K
0402
5%
1
2
L80 600Z/100M 1608 1 2
R491 0/NA 0402 5% 1 2
D5
ESD0603/NA
1 2
R26 0 0805 1 2
R27 0 0805 1 2
R1302 0
0402
1 2
R1122 22.1K
0603 1%
1 2
C354
100P/NA
0402
50V
10%
1
2
C487
1U/NA
10V
0805
1 2 R521 0
0402
1 2
C941
4.7U
0805
+80-20%
1
2
C977
1U
0402
10V
1
2
U524
TPA0212_GND
TSSOP24_TPA0102
2
3
4
5
6
7 8
9 10
11
14
15
16
17
18
19
20 21
22
23
1
12
13
24
25
26
27
28
29
30
31
32
33
34
GAIN0
GAIN1
LOUT+
LLINEIN
LHPIN
PVDD0 RIN
LOUT- LIN
BYPASS
PC-BEEP
SEBTL
ROUT-
HP/LINE
PVDD1
VDD
RHPIN ROUT+
SHUTDOWN
RLINEIN
GND0
GND1
GND2
GND3
G1
G2
G3
G4
G5
G6
G7
G8
G9
G10
R471
1M/NA
0402
5%
1
2
C494
2200P
0402
50V
+/-20%
1
2
R529
1K
0402
1%
1
2
R511 100 0402
1%
1 2
R1
Q30
DTC144TKA/NA
2
1
3
R1185
10K
0402
1
2
C934
0.1U
0402
16V
10%
1
2
L14 600Z/100M 1608 1 2
C949
0.1U
0402
16V
10%
1
2
C930
1U
0402
10V
+80-20%
1
2
C462
0.1U/NA
0402
50V
+80-20%
1
2
C935 1U
0402 10V +80-20%
1 2
R512 0/NA 0402 5% 1 2
C482
0.15U
0603
1 2
D
S
Q35
2N7002/NA
G
D
S
C150
100P
0402
50V
10%
1
2
L55
600Z/100M
1608 1 2
C1003
100P/NA
0402
50V
+/-10%
1
2
L755
600Z/100M
1608 1 2
D715
BAW56
288100056017
2
1
3
C345
1U/NA
0402
10V
+80-20%
1
2
C469
0.1U
0402
50V
+80-20%
1
2
R1158
1.3M
0402
1%
1
2
C500
10U
6.3V
0805
10%
1
2
L16 600Z/100M 1608 1 2
C480 1U
0402 10V
1 2
TP49
1
J705
HDR/MA-2
ACES
85204-0200
291000020206
1
2
L67
120Z/100M 2012
1 2
LED
Drive
IC
J720
GP1FD310TP
SHARP
CONN_GP1FD310TP
5
4
2
3
1
8
7
9
L754
600Z/100M
1608 1 2
R496 10.2K
0402 1%
1 2
R1125 0
0402
1 2
+
-
U19A
LMV822
MSOP8
3
2
1
8
4
C497 1U
0402 10V +80-20%
1 2
R478 0
0402
1 2
J7
HDR/MA-2
ACES
85204-0200
291000020206
1
2
R528 22 0402 5% 1 2
R477
100K
0402
5%
1
2
R
1
Q38
DTC144TKA
288202240001
2
1 3
Q711
DTA144WK
SOT23AN_1
288221371002
1
2
3
U725
LM4871
LLP8A
3
4
5
8
2
1
7 6
9
10
11
12
13
14
15
+IN
-IN
VO1
VO2
BYPASS
SHDWN
GND VDD
GND1
GND2
GND3
GND4
GND5
GND6
GND7
L78 600Z/100M 1608 1 2
C471
1000P
0603
10%
1 2
L752
120Z/100M 2012
1 2
C950 1U
0402 10V +80-20%
1 2
R1239
4.7K
0402
5%
1
2
C978
1U/NA
0402
10V
+80-20%
1
2
R462
18K
0402
1%
1
2
C479
1U/NA
10V
0805
1 2
C503
100P
0402
50V
10%
1
2
+
-
U19B
LMV822
MSOP8
5
6
7
8
4
R459 10K/NA
0402 5% 1 2
R1159 100K 0402 5% 1 2
R328
1K
0402
1%
1
2
R367
10K
0402
1
2
R1
Q713
DTC144TKA
288202240001 2
1
3
+ C466
100U
6.3V
20%
1
2
JO12
1 2
R479
22.1K 0402 1%
1 2
R502 10.2K
0402 1%
1 2
D17
RLS4148
A K
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
For External
flash
10MIL
1:external flash
0:internal flash
20MIL
Pull HIGH at Other End
X7R
3V LEVEL
WINBOND KBC
PULL HIGH at SB END
0:for external flash
POWER BUTTON
ADD-->R0B
Closed to KB CONN
R0A
add C Version 284583950002
KBC IC :284583950002
F/W
ASSY:481677700002
Processor Hot Protection
THERMAL SENSOR / FAN CONTROLLER
F
A
N
PCB 316680900001/ASSY 411680900011 R01
8050 MOTHERB/D
C
Title
Size
Document
Number
Rev
Date: Sheet of
KI4
KI7
KI0
KI1
KO5
KO6
KI5
KO14
KO0
KI3
KO1
KO0
KI0
KO3
KO1
KI7
KI1
KO12
KI2
KO4
KI7
KI1
KO12
KO15
KO8
KI3
KO11
KO14
KO7
KO2
KI6
KO9 KO9
KO2
KI5
KI4
KO15
KO8
KO11
KO10
KO6
KO4
KO13
KI3
KI2 KI5
KI6
A20GATE
BAT_DATA
BAT_CLK
H8_HRCIN#
T_CLK
T_DATA
H8_RSMRST
BAT_DATA
BAT_CLK H8_THRM_CLK
H8_I_LIMIT I_LIMIT
H8_SCI
H8_I_CTR I_CTRL
H8_THRM#
KI5
H8_ENABKL
KI4
KO7
H8_I_LIMIT
T_DATA
KBC_X+
KO11
KO4
BAT_DATA
AC_POWER#
LAD2
NUM#
KO15
KO2
LAD1
H8_THRM#
KO13
LAD3
KO6
KI1
KO12
BLADJ
KO3
KI7
LAD0
CAP#
KO14
H8_I_CTR
H8_ADEN#
BLADJ
PWRBTN#
KBC_X-
KI5
KO5
H8_RSMRST
EXTSMI#
SCROLL#
KBC_X-
KI3
BAT_CLK
ICH_PWRBTN
H8_PWRON
BATT_R#
H8_ENABKL
BAT_TEMP
KI6
KO10
KO0
BATT_G#
H8_RESET#
KI0
BAT_VOLT
H8_SCI
PWRBTN#
KI2
KO1
SW_VDD3
KBC_X+
KO9
KO8
T_CLK
BATT_DEAD#
H8_WAKE_UP#
H8_SUSB
CHARGING
KBC_RI#
H8_PROCHOT#
H8_RSMRST
H8_ADEN#
H8_SUSB
ICH_PWRBTN
H8_SUSB
PWRBTN#
BATT_DEAD#
H8_PROCHOT# HPROCHOT#
H8_PROCHOT#
BAT_CLK
BAT_DATA
BAT_DATA
LAD[0..3]
LEARNING
FAN_SPEED
H8_THRM_DATA
FAN#
THERM_ERR#
H8_THRM_CLK
ICH_PWRBTN
BATT_DEAD#
H8_THRM_DATA
BAT_CLK
FAN_SPEED
FAN#
KBC_RI#
H8_SCI
H8_WAKE_UP# WAKE_UP#
H8_THRM#
H8_HRCIN#
KI0
KI2
KO10
KO3
KO5
KO7
KO13
KI6
KI4
LAD[0..3] 13,19,23
PCICLK_KBC 11
SERIRQ 13,14,17,19
KBC_PCIRST# 13
LFRAME# 13,19,23
ADEN# 25,32
LEARNING 32
SUSB# 13,17,23,25
SCI# 13,24
BAT_D 32
BAT_C 32
BAT_T 32
BAT_V 32
SUSC# 13,26,27
CHARGING 33
H8_LIDSW# 12
H8_ENABKL 12
T_CLK 23
T_DATA 23
A20GATE 13
BLADJ 4,12
I_CTRL 33
I_LIMIT 32
KBD_US/JP# 13,24
BATT_R# 12,23
NUM# 23
BATT_G# 12,23
CAP# 23
SCROLL# 23
ICH_PWRBTN# 13
BATT_DEAD 33
EXTSMI# 13,24
SB_THRM# 13
SW_VDD3 25
CPU_THERMDC 2
CPU_THERMDA 2
VGA_THERMDA 9
VGA_THERMDC 9
HPROCHOT# 2
H8_PWRON 26,27
RSMRST# 13,25
BATT_LED# 23
KBC_PWRON_VDD3S 25
AC_POWER# 12,23
H8_PWRON_SUSB# 25
THERM_ERR# 14,25
H8_RESET# 25
KBC_RI# 16
WAKE_UP# 13,24
HRCIN# 13
KBC_MUTE 21
GND
GND
GND
GND
GND GND
GND
H8AGND H8AGND
VDD3
VDD3
VDD3
+KBC_CPUCORE
GND
+VCC_CORE
VDD3 VDD3_AVREF
+5V
GND
GND
+5VS +5VS
GND GND
+3V
GND
VDD3
GND
VDD3
VDD3_AVREF
+VCC_CORE
+3VS
VDD3
VDD5
+2.5VS_DDR
+3VS
+3VS
GND
+KBC_CPUCORE
GND
VDD3S
GND
GND +3VS
VDD3_AVREF
VDD3
+5V
GND
GND
+3V
GND
GND
+3VS
+3V
VDD3
GND H8AGND
+3V +3V
+3V
R
1
Q706
DTC144TKA
SOT23AN_1
288202240001
2
1 3
R925
10K
0402
1
2
RP719
10K*4 1206
1
2
3
4
8
7
6
5
R99
33
0402
5%
1 2
C728
2200P
0402
50V
+/-20%
1
2
R450 10K/NA
0402
1 2
C453
0.1U
0402
50V
+80-20%
1
2
R475 10K
0402 5%
1 2
R1 Q39
DTC144TKA
SOT23AN_1
288202240001
2
1
3
R1
Q32
DTC144TKA
SOT23AN_1
288202240001
2
1
3
R413 10K 0402 5% 1 2
C534
100P
0402
50V
1 2
C9
1000P
0402
50V
+/-20%
1
2
C524
100P
0402
50V
1 2
RP45
22*4
RPSOA_8C
1
2
3
4
8
7
6
5
C538
100P
0402
50V
1 2
R395
10K
0402
1
2
C537
100P
0402
50V
1 2
R453
10K
0402
5%
1
2
R455 2.7K/NA 0402 1% 1 2
U706
ADT7460
QSOP16B
11
1
2
16
3
4
15
10
14
6
5
13
8
7
12
9
D2+
SCL
GND
SDA
VCC
TACH3
PWM1
D2-
+2.5VIN/SMBALERT
TACH1
PWM2/SMBALERT
D1+
PWM3/ADDRESS ENABLE
TACH2
D1-
TACH4/ADDRESS SELECT/THERM
C449
0.1U
0402
50V
+80-20%
1
2
D S
Q40
2N7002
G
D S
D21 RLS4148 A K
C450
22P
0402
50V
+/-10%
1
2
D703
RLS4148
A K
C527
100P
0402
50V
1 2
R95
10K
0402
5%
1
2
C133
0.1U
0402
50V
+80-20%
1
2
C454
0.1U
0402
50V
+80-20%
1
2
C94
0.1U
0402
50V
+80-20%
1
2
R439 0
0402
1 2
R
1
Q27
DTC144TKA
SOT23AN_1
288202240001
2
1 3
R482 10K 0402 5% 1 2
R449 2.7K 0402 1% 1 2
C526
100P
0402
50V
1 2
R448 2.7K 0402 1% 1 2
C540
100P
0402
50V
1 2
R481 10K 0402 5% 1 2
SW2
TC010-PSS11CET
297004010001
1
3
2
4
5
D20 RLS4148/NA
A K
R445 0
0402
1 2
C104
0.1U
0402
50V
+80-20%
1
2
R473 0
0402
1 2
R385 0/NA
0402 5%
1 2
C539
100P
0402
50V
1 2
C448
0.1U
0402
50V
+80-20%
1
2
C478
0.1U
0402
50V
+80-20%
1
2
TP719 1
L61
120Z/100M/NA
0805C
1 2
C459
0.1U
0402
50V
+80-20%
1
2
C445
10U
6.3V
0805
10%
1
2
R428 0 0402 1 2
R414 0/NA 5%
0402G_DFS
1 2
C529
100P
0402
50V
1 2
C528
100P
0402
50V
1 2
R404
1M
0402 5%
1 2
C542
100P
0402
50V
1 2
R425 10K/NA
0402 5%
1 2
TP720 1
D18
BAV70LT1
SOT23N
288100070006 1 2
3
R486 0
0402
1 2
R447
0/NA
0402
5% 1
2
D
S G
Q14
SI2301DS
G
D
S
R7 1K
0402 5%
1 2
R390 10K/NA
0402 5%
1 2
D S
Q33
2N7002
G
D S
C869
2200P
0402
50V
+/-20%
1
2
J707
1.25MM/ST/MA-3
ACES
85205-0300
291000010303
1
2
3
D
S
Q42
FDV301N
SOT23_FET
G
D
S
R1
Q49
DTC144TKA
SOT23AN_1
288202240001
2
1
3
C541
100P
0402
50V
1 2
TP718 1
R381 0/NA
0402 5%
1 2
R1002
0
1
2
RP46
RP10KX8
RPSOE_10
1
2
3
4
5 6
7
8
9
10
C530
100P
0402
50V
1 2
C531
100P
0402
50V
1 2
C523
100P
0402
50V
1 2
C871
4.7U
0805
+80-20%
1
2
R483 0 0402 1 2
R87
0
0402
5%
1 2
R394 0/NA
0402
1 2
RP44
4.7K*8 1206
1
2
3
4
5 6
7
8
9
10
C93
10U
16V
1206
1
2
L68
BEAD_600Z/100M
0603D 1 2
C447
22P
0402
50V
+/-10%
1
2
C522
100P
0402
50V
1 2
C520
100P
0402
50V
1 2
U16
W83L950D
PQFP80_0.5MM
31
32
33
34
35
36
37
38
1
20
70
69
68
67
66
65
64
63
17
15
14
23
22
19
21
16
18
9
8
7
6
5
4
55
11
10
80
79
78
77
76
75
74
3
2
27
26
13
12
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
62
61
60
59
58
57
56
24
25
28
29
30
71
72
73
GP27/FD7
GP26/FD6
GP25/FD5
GP24/FD4
GP23/FD3/SCL1/TXD1
GP22/FD2/SDA1/RXD1
GP21/FD1
GP20/FD0/LPCEN
GP60/AN0/INT5
GP45/TXD
GP80/SD0
GP81/SD1
GP82/SD2
GP83/SD3
GP84/SD4
GP85/SD5
GP86/SD6
GP87/SD7
GP50/A0
GP52/INT30#/R
GP53/INT40#/W
GP42/INT0/OBF00
GP43/INT1/OBF01
GP46/SCLK1/OBF1
GP44/RXD
GP51/INT20#/S0
GP47/SRDY1#/S1
GP70/SIN2
P71/SOUT2
GP72/SCLK2
GP73/SRDY2#/INT21
GP74/INT31
GP75/INT41
GP37/OE#
GP56/DA1/PWM01
GP57/DA2/PWM11
GP61/AN1/INT6
GP62/AN2/INT7
GP63/AN3/INT8
GP64/AN4/INT9
GP65/AN5/INT10
GP66/AN6/INT11
GP67/AN7/INT12
GP76/SDA
GP77/SCL
GP40/XOUT/PWM2
GP41/XCIN/PWM3
GP54/CNTR0
GP55/CNTR1
GP0/P3REF/FA0
GP1/FA1
GP2/FA2
GP3/FA3
GP4/FA4
GP5/FA5
GP6/FA6
GP7/FA7
GP10/FA8
GP11/FA9
GP12/FA10
GP13/FA11
GP14/FA12
GP15/FA13
GP16/FA14
GP17/FA15
GP30/PWM0/FCTRL0
GP31/PWM10/FCTRL1
GP32/FCTRL2
GP33/FCTRL3#
GP34/BANK0
GP35/BANK1
GP36/CE#
CNVSS
RESET#
XIN
XOUT
VSS
VCC
VREF
AVSS
R419 2.7K/NA 0402 1% 1 2
R424 22
0402 5%
1 2
R96
1M/NA
0402
5%
1
2
C543
100P
0402
50V
1 2
C521
100P
0402
50V
1 2
R88
10K
0402
5%
1
2
C532
100P
0402
50V
1 2
R393 0
0402
1 2
R446
150
0402
1%
1
2
X1
8MHZ
TXC8X4.5
1 2
C536
100P
0402
50V
1 2
C535
100P
0402
50V
1 2
C533
100P
0402
50V
1 2
R
1
Q26
DTC144TKA
SOT23AN_1
288202240001
2
1 3
R1
Q31
DTC144TKA
SOT23AN_1
288202240001
2
1
3
J5
FPC/FFC/1MM/26P
ACES
85202-26-00
291000152603
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
R
1
Q29
DTC144TKA
288202240001
2
1 3
R267 0/NA
0402 5%
1 2
C525
100P
0402
50V
1 2
R430
10K
0402
5% 1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
TOUCH_PAD
SW_RIGHT
SW_LEFT
miniSMDC050
LED
FWH
SYS BIOS Vendor List:
SST49LF004A : 283467490001
When 8050N ADD J722 and DEL J4
When 8050 ADD J4 and DEL J722
PCB 316680900001/ASSY 411680900011 R01
8050 MOTHERB/D
C
Title
Size
Document
Number
Rev
Date: Sheet of
TP_RIGHT
TP_LEFT
TP_CLK
AC_BATT_LED#
NUM#
SCROLL#
LAD2
LAD0
INIT#
LAD1
TP_DATA
TP_VDD
LAD3
INIT#
CAP#
AC_BATT_LED# IDE_LED#
IDE_LED#
BATT_POWER#
BATT_LED#
TP_DATA
TP_RIGHT
TP_VDD
TP_LEFT
TP_CLK
SUSB# 13,17,22,25
HDD_LED# 15
CD_LED# 15
SCROLL# 22
CAP# 22
NUM# 22
BATT_LED# 22
PCICLK_FWH 11
LFRAME# 13,19,22
FWH_PCIRST# 13
LAD1 13,19,22
LAD0 13,19,22
LAD3 13,19,22
LAD2 13,19,22
T_CLK 22
T_DATA 22
HINIT# 2,13
CAP# 22
NUM# 22
CD_LED# 15
HDD_LED# 15
BATT_G# 12,22
BATT_POWER# 12
AC_POWER# 12,22
BATT_R# 12,22
GND
GND
+5V
GND
GND
+3VS +3VS +3VS
GND GND GND
+3V
+5V
+5V
GND
GND
+3V
GND
+3V
GND
GND
GND
GND GND
GND
+3V
GND
+5V
VDD3S
VDD3S
VDD3S
GND
R422 8.2K 0402 5% 1 2
D37
CL-190G
A K
R415
0/NA
0402 1 2
R427 8.2K 0402 5% 1 2
J8
HDR/MA-12/NA
ACES
87151-1207
291000141204
1
2
3
4
5
6
7
8
9
10
11
12
D23
ESD0805A/NA
1 2
R364 4.7K 0402
5%
1 2
R554
470
0402 5% 1 2
C144
47P
0402
50V
+/-10%
1
2
R432
0/NA
0402 1 2
R458
0
0402 1 2
R429
0
0402 1 2
R1 Q719
DTC114TKA
288202215001
2
1
3
U703C
74AHC14_V
TSSOP14
5 6
1
4
7
R1303
0/NA
0402 1 2
R433
220/NA
0402
5%
1 2
U703B
74AHC14_V
TSSOP14
3 4
1
4
7
R468
0
0402 1 2
R556
220
0402 5% 1 2
JO19
1
2
R434
220/NA
0402
5%
1 2
C143
47P
0402
50V
+/-10%
1
2
R151 0/NA 5%
0402G_DFS
1 2
F701
0.5A/POLYSW
1 2
R1073
330
0402
5%
1 2
R420
0
0402 1 2
JO18
1
2
JO20
1
2
R417 4.7K 0402 5% 1 2
JO21
1
2
R132 0/NA 5%
0402G_DFS
1 2
R441
470/NA
0402 5% 1 2
D35
CL-190G
A K
Q708
MMBT3904L
288203904022
B
E
C
R426
0/NA
0402 1 2
R555
220
0402 5% 1 2
C902
0.1U
0402
10V
10%
1
2
C154
47P
0402
50V
+/-10%
1
2
R402 8.2K 0402 5% 1 2
R1
Q720
DTC114TKA
288202215001
2
1
3
D33
CL-190G
A K
R1140 180K 0402 5%
1 2
R416
0
0402 1 2
C771 0.1U
0402
50V +80-20%
1 2
L716
120Z/100M
2012
1 2
L36
120Z/100M
1608
1 2
R465
0/NA
0402 1 2
R466
0/NA
0402 1 2
R1089
330
0402
5% 1
2
D32
CL-190G
A K
R411 8.2K 0402 5% 1 2 C897
0.1U
0402
10V
10%
1
2
TP56 1
C172
47P
0402
50V
+/-10%
1
2
U703D
74AHC14_V
TSSOP14
9 8
1
4
7
U15
SST49LF004A
4 3
5
6
7
8
9
10
11
12
13
1
4
1
5
1
6
1
7
1
8
1
9
2
0
21
22
23
24
25
26
27
28
29
2 1 3
2
3
1
3
0
A
8
/R
S
V
A
9
/R
S
V
A7/RSV
A6/RSV
A5/RSV
A4/RSV
A3/RSV
A2/RSV
A1/RSV
A0/RSV
LAD0/DQ0
D
Q
1
/L
A
D
1
D
Q
2
/L
A
D
2
G
N
D
D
Q
3
/L
A
D
3
D
Q
4
/R
S
V
D
Q
5
/R
S
V
D
Q
6
/R
S
V
DQ7/RSV
NC
WE#/LFRAME#
OE#/INIT#
VDD
GND
VCCA
GNDA
MODE
R
E
S
E
T
#
V
P
P
V
D
D
R
-C
#
/C
L
K
A
1
0
/G
P
I4
R423 8.2K 0402 5% 1 2
R408 4.7K 0402 5% 1 2
D721
BAW56/NA
2
1
3
D34
CL-190G
A K
R418 8.2K 0402 5% 1 2
D29
ESD0805A/NA
1 2
R457
0/NA
0402 1 2
R557
220
0402 5% 1 2
R553
470
0402 5% 1 2
R412 8.2K 0402 5% 1 2
Q718
MMBT3904L
288203904022
B
E
C
J4
HDR/MA-6
ACES
87151-0607
1
2
3
4
5
6
C947
4.7U
0805
+80-20%
1
2
C908
4.7U
6.3V
0603
+80-20%
1
2
R1152 1M
0402
5%
1 2
SW4
TC010-PSS11CET
297004010001
1
3
2
4
5
R403 8.2K 0402 5% 1 2
R467
220/NA
0402 5% 1 2
SW5
TC010-PSS11CET
297004010001
1
3
2
4
5
TP57 1
VG
SR
D31
19-22SRVGC/TR8/NA
3 4
1 2
L37
120Z/100M
1608
1 2
R387 8.2K 0402 5% 1 2
R1084
1.5K
0402
5%
1
2
R421
0
0402 1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PULL -HIGH
1.05V
AGP PULL HIGH PCI PULL HIGH
GPIO PULL HIGH
WHENUSEINTEGRATEVGA
DELALLRESISTOR
PCB 316680900001/ASSY 411680900011 R01
8050 MOTHERB/D
C
Title
Size
Document
Number
Rev
Date: Sheet of
MB_ID0
MB_ID1
MB_ID2
PANEL_ID1
PANEL_ID0
PANEL_ID3
PANEL_ID2
KBD_US/JP#
SMBALERT#
AGPBUSY#
GPIO28
SPK_OFF
STP_AGP#
GPIO27
CRT_IN#
ICH_GPI5
PCI_INTA# 7,13
PCI_INTC# 13,17
PCI_INTD# 13,19
PCI_INTB# 13,17
PCI_INTE# 13,16
PCI_INTG# 13,18
PCI_LOCK# 13
PCI_INTF# 13,17,19
PCI_REQ2# 13,19
PCI_REQ0# 13,17
PCI_REQ1# 13,18
PCI_REQ3# 13,16
PCI_GNT3# 13,16
PCI_GNT1# 13,18
PCI_GNT0# 13,17
PCI_GNT4# 13
PCI_REQ4# 13
PCI_GNT2# 13,19
PCI_FRAME# 13,16,17,18,19
PCI_SERR# 13,16,17,19
PCI_IRDY# 13,16,17,18,19
PCI_PERR# 13,16,17,18,19
PCI_DEVSEL# 13,16,17,18,19
PCI_TRDY# 13,16,17,18,19
PCI_STOP# 13,16,17,18,19
AGP_AD30 4,7
AGP_AD13 4,7
MB_ID0 14
MB_ID1 14
MB_ID2 14
PANEL_ID0 7,12,14
PANEL_ID2 7,12,14
PANEL_ID1 7,12,14
PANEL_ID3 7,12,14
SMBALERT# 13
CRT_IN# 12,13
GPIO28 13
MINIPCI_ACT# 14,19
PCLKRUN# 13,16,17,19
WIRELESS_PD# 14,19
GPIO43 14
GPIO27 13
STP_AGP# 7,13
EXTSMI# 13,22
GPIO42 14
KBD_US/JP# 13,22
IDERST# 14,15
WAKE_UP# 13,22
AGPBUSY# 4,7,13
SPK_OFF 13,21
SCI# 13,22
ICH_GPI5 13
SB_CARD_PME# 13
CPUPERF# 13
B/CB# 3,13
+1.5V
+1.35V_P
+1.8V_P
+1.5V_P
+1.05V_P
+1.8V
+1.35V
+VCCP
+2.5VS_DDR +2.5VS_DDR_P
+3V
+3V
+3V
+3V
+3V
+3VS +3VS_P
+5VS +5VS_P
+1.2V/1.0V_M10 VGA_1.2/1.0
+1.5V
GND
+3V
GND
+3V
VDD3S
+3V
+3V
VDD3S
+3V
+3V
+3VS
+VCCP
+3V
VDD3S
+1.25V_DDR_P +1.25V_DDR
R410 8.2K/NA 0402 1 2
JS721
SHORT-SMT4
1 2
JS715
SHORT-SMT4
1 2
R11 10K 0402 1 2
R282 8.2K 0402 1 2
JS709
SHORT-SMT4
1 2
R194 8.2K 0402 1 2
JS729
SHORT-SMT4
1 2
R814 8.2K 0402 1 2
R842 10K 0402 5% 1 2
R230 8.2K 0402 1 2
JS722
SHORT-SMT4
1 2
JS723
SHORT-SMT4
1 2
R788 20K 0402
1%
1 2
JS710
SHORT-SMT4
1 2
R845 10K/NA 0402 1 2
JS12
SHORT-SMT4
1 2
R165 10K 0402
5%
1 2
R12 10K 0402 1 2
R187 8.2K 0402 1 2
R179 8.2K 0402 1 2
JS728
SHORT-SMT4
1 2
R841 8.2K 0402 1 2
R837 100K/NA 0402 5% 1 2
R396 10K 0402
5%
1 2
R284 0/NA 5%
0402G_DFS
1 2
JS11
SHORT-SMT4
1 2
R843 10K 0402 5% 1 2
R231 8.2K 0402 1 2
JS720
SHORT-SMT4
1 2
R803 8.2K 0402 1 2
R280 200 0402
5%
1 2
R232 10K 0402 1 2
R215 10K/NA 0402 1 2
R815 8.2K 0402 1 2
JS730
SHORT-SMT4
1 2
JS717
SHORT-SMT4
1 2
R847 8.2K 0402 1 2
R1005 8.2K 0402 1 2
R382 10K 0402
5%
1 2
R13 10K 0402 1 2
R802 8.2K 0402 1 2
R1119 8.2K 0402 1 2
R464 10K 0402
5%
1 2
R868 8.2K 0402 1 2
R846 10K 0402 1 2
JS711
SHORT-SMT4
1 2
R180 8.2K 0402 1 2
JS718
SHORT-SMT4
1 2
R244 8.2K 0402 1 2
JS716
SHORT-SMT4
1 2
JS726
SHORT-SMT4
1 2
R211 8.2K 0402 1 2
R283 0/NA 0402 1 2
R221 10K 0402 1 2
R14 10K 0402 1 2
R808 8.2K 0402 1 2
R218 8.2K 0402 1 2
R207 8.2K 0402 1 2
JS719
SHORT-SMT4
1 2
R191 8.2K 0402 1 2
R780 20K/NA 0402
1%
1 2
R851 10K 0402 5% 1 2
R1098 10K
0402 5%
1 2
JS727
SHORT-SMT4
1 2
R241 8.2K 0402 1 2
JS713
SHORT-SMT4
1 2
R281 8.2K 0402 1 2
R804 8.2K 0402 1 2
R866 100K/NA 0402 5% 1 2
R239 10K/NA 0402 1 2
R212 8.2K 0402 1 2
R201 8.2K 0402 1 2
R200 8.2K 0402 1 2
R905 8.2K 0402 1 2
R1004 8.2K 0402
5%
1 2
R186 8.2K 0402 1 2
JS724
SHORT-SMT4
1 2
JS708
SHORT-SMT4
1 2
R897 0/NA 0402 1 2
R906 0 0402 1 2
R916 10K 0402
5%
1 2
JS725
SHORT-SMT4
1 2
R309 10K 0402
5%
1 2
R840 10K 0402 5% 1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
For Lan
For ATI VRAM
POWER ON PERPHERIAL CIRCUIT
809S
2.93V
H8 RESET# / RSMRST#
PCB 316680900001/ASSY 411680900011 R01
8050 MOTHERB/D
C
Title
Size
Document
Number
Rev
Date: Sheet of
PWRON_SUSB# VCC_ON
VCC_ON
OD3
OD5
PWRON_SUSB#
ADEN#
PWRON_SUSB#
PWRON_SUSB#
OD3
PWRON_SUSB#
SW_VDD3
OD5
PWROK
THERM_ERR#
ADEN#
H8_RESET#
ADEN# 22,32
PWROK 4,12,13,17,31
KBC_PWRON_VDD3S 22
SUSB# 13,17,22,23
H8_PWRON_SUSB# 22 PWRON_SUSB# 26,28,29,30,31
PCIRST#0 13,15
SW_VDD3 22
THERM_ERR# 14,22
RSMRST# 13,22
H8_RESET# 22
PWROK 4,12,13,17,31
VDD1.5
VDD5
GND
GND
GND
VDD5S
GND
+5VS +3VS
GND
GND
+3VS VDD3
GND GND
+3VS +5VS +2.5VS_DDR
GND
GND
GND
GND
+3V
GND
+5V
GND GND
+2.5V_M10
GND
GND
GND
+3VS
GND
+3V
GND GND
GND GND
VDD3_AVREF
GND GND
VDD5
GNDGND
PWR_VDDIN
VDD3S
VDD3
GND
+3VS
GND GND
PWR_VDDIN
+3VS
VDD3S
GND
GND
VDD3
GND GND
GND
+3VS VDD3
VDD3
DVMAIN
DVMAIN
GND
GND
GND
VDD3S
VDD3S
GND
GND
VDD5
+5V_H
GND GND
C329
1U
0402
10V
+80-20%
1
2
F3
FUSE_1206
1A-1206
3216FF-1
1 2
C284
10U
6.3V
0805
10%
1
2
D S
G
Q48
SI2301DS
G
D S
R456
4.7K/NA
0402
5%
1
2
R548 0/NA 0402
5%
1 2
D
S
Q19
2N7002
G
D
S
C486
10U/NA
6.3V
0805
10%
1
2
C710
1U
0402
10V
+80-20%
1
2
R17 0 0402
5%
1 2
R551 0/NA 5%
0402G_DFS
1 2
D
S
Q701
2N7002
G
D
S
R374
10K/NA
0402
5%
1
2
R1248
0/NA
0805
1
2
L707 120Z/100M
2012
1 2
C16
0.1U
0402
50V
+80-20%
1
2
D
S G
Q722
SI2301DS/NA
G
D
S
L703 120Z/100M
2012
1 2
C508
2.2U
0603
+/-10%
1
2
U10
MAX809
SOT23N
286300690001
2 3
1
RESET# VCC
G
N
D
R1249
0/NA
0805
1
2
R523
0
0402
5%
1 2
C717
2.2U
0603
+/-10%
1
2
R
1
Q44
DTC144TKA
288202240001
2
1 3
R1
Q50
DTC144TKA
288202240001
2
1
3
C13
0.1U
0402
50V
+80-20%
1
2
R251
220K
0402
5%
1
2
R25 0/NA 5%
0402G_DFS
1 2
D
S
Q17
2N7002/NA
G
D
S
G
D S
U707
AO4403
SO8 8
7
6
4
5 1
3
2
C355
10U
10V
1206
1
2
C517
4.7U
0805
+80-20%
1
2
R18 0 0402
5%
1 2
R531
10K
0402
5%
1
2
R250 1M
0402 5%
1 2
R21
1K
0402
5%
1
2
D S
G
Q43
SI2301DS
G
D S
R522
0/NA
0402
5%
1 2
C283
2.2U
0603
+/-10%
1
2
C706
1U
0402
10V
+80-20%
1
2
R259
1K
0402
1%
1 2
R501
0
0402
5%
1 2
R561
100K
0402
5%
1
2
C712
0.1U
0402
50V
+80-20%
1
2
U11
LP2951-02
SO8
8
2
7
3
6
1
5
4
IN
SENSE
F/B
SHUTDN
5VTAP
OUT
ERR-
GND
R508
100K
0402
5%
1
2
U8
SI4788CY/NA
SO8
1
2
3
4 5
7
6
8
VIN
SOURCE1
SOURCE2
SOURCE3 DRAIN3
DRAIN2
DRAIN1
GND
G
D S
U7 SI4800DY
SO8
8
7
6
4
5
2
3
1
R15
100K
0402
5%
1 2
L71
120Z/100M
2012
1 2
C295
2.2U
0603
+/-10%
1
2
Q18
DTA144WK/NA
SOT23AN_SC70_1
1
2
3
U14
LP2951-3.3/NA
SO8
8
2
7
3
6
1
5
4
IN
SENSE
F/B
SHUTDN
5VTAP
OUT
ERR-
GND
D
S
Q10
2N7002
G
D
S
C708
0.1U
0402
50V
+80-20%
1
2
C383
10U
6.3V
0805
10%
1
2
R28
100K
0402
5%
1
2
C342
10U
6.3V
0805
10%
1
2
G
D S
U704
AO4403
SO8 8
7
6
4
5 1
3
2
R
1
Q34
DTC144TKA/NA
2
1 3
U13
AMS3107
SOT223
286303107001
1
2
3
INPUT
G
N
D
OUTPUT
L704 120Z/100M
2012
1 2
U21
IMP811
SOT143
1
2
4
3
GND
RESET
VCC
MN
C381
0.1U
0402
50V
+80-20%
1
2
R705
100K
0402
5%
1 2
D S
G
Q51
SI2301DS
G
D S
C715
10U
6.3V
0805
10%
1
2
R480 0/NA 5%
0402G_DFS
1 2
U6
AME1117
SOT223
1
2
3
GND/ADJ
VOUT
VIN
R355
0/NA
0402
5%
1 2
C313
0.047U 0603
1 2
C24
2.2U
0603
+/-10%
1
2
D26
UDZS3.6B/NA
SOD323
A
K
R321
10K
0402
5%
1
2
C705
10U
10V
0805C
1
2
R1
Q12
DTC144TKA
288202240001
2
1
3
R358
4.7K
0402
5%
1
2
C326
0.1U
0402
10V
10%
1
2
L46
120Z/100M
2012
1 2
D
S G
Q721
SI2301DS/NA
G
D
S
L72
120Z/100M/NA
2012
1 2
R375
10K
0402
5%
1
2
C707
2.2U
0603
+/-10%
1
2
R525
100K
0402
5%
1
2
R474
294K/NA
0402
1%
1
2
R368
10K/NA
0402
5%
1
2
R362
10K
0402
5%
1
2
D25
RLZ3.6B/NA
MLL34B
A
K
D7
BAS32L
A K
C310
0.1U
0402
10V
10%
1
2
R366
10K/NA
0402
5%
1
2
R260
22K/NA
0402 1%
1 2
L47
120Z/100M
2012
1 2
R707
1K
0402
5%
1
2
R312
100K
0402
5%
1
2
C506
0.01U
0402
50V
+80-20%
1
2
Q47
DTC144WK
288202237002
1
2
3
R253
200
0402
1%
1
2
D S
G
Q13
SI2301DS
G
D S
D13
UDZ5.6B
SOD323
A
K
L706 120Z/100M
2012
1 2
D24
BAS32L
A K
R
1
Q25
DTC144TKA/NA
2
1 3
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
+2.5VS_DDR_P/+1.25V_DDR_P
PCB 316680900001/ASSY 411680900011 R01
8050 MOTHERB/D
C
Title
Size
Document
Number
Rev
Date: Sheet of
INTVCC1
SENSE2.5-
SENSE1.25-
INTVCC1
SENSE2.5+
SENSE1.25+
1.25V_2
H8_PWRON 22,27
SUSC# 13,22,27
PWRON_SUSB# 25,28,29,30,31
+1.25V_DDR_P
SGND1
GND
GND
GND
VDD5
GND
GND
GND
GND
SGND1
DVMAIN
GND
GND
GND
+2.5VS_DDR_P
VDD5
SGND1
SGND1
+5VS_P
PR112
100K
0402
1%
1
2
PD723
BZV55C3V3/NA
A
K
PR121
1K
0402
1%
1
2
D
S
PQ21
2N7002 G
D
S
PR122
15K
0402
1%
1
2
PR124
2K
0402
1%
1
2
G
D
S
PU708B
AO4900
SO8
2
8 7
1
PR110
4.7
0603
1%
1 2
C367
0.1U/NA
0402
50V
+80-20%
1
2
PR123
1M
0402
1%
1
2
PR115
1M
0402
1%
1
2
PC797
10U
10V
1210
1
2
PC792
0.01U
0402
50V
10%
1
2
PC68
0.1U
0402
50V
+80-20%
1
2
R371 0/NA
0402 5%
1 2
PR111
0
0402
5%
1 2
PC796
10U
25V
1210
20%/X5R
1
2
PC69
1000P
0402
50V
10%
1
2
JS6
SHORT-SMT1
1 2
PC72
1000P
0402
50V
10%
1 2
PR118
43.2K
0402
1%
1 2
PU15
LTC3728L
HVQFN32_1
1 2 3 4 5 6 7 8
9
10
11
12
13
14
15
16
1
7
1
8
32
31
30
29
28
27
26
25
2
4
2
3
2
2
2
1
2
0
1
9
33
34
35
36
37
V
O
S
E
N
S
E
1
P
L
L
F
L
T
R
P
L
L
IN
F
C
B
IT
H
1
S
G
N
D
3
.3
V
O
U
T
IT
H
2
VOSENSE2
NC0
SENSE2-
SENSE2+
RUN/SS2
TG2
SW2
NC1
B
O
O
S
T
2
B
G
2
NC3
SENSE1-
SENSE1+
NC2
RUN/SS1
PGOOD
TG1
SW1
B
O
O
S
T
1
V
IN
B
G
1
E
X
T
V
C
C
IN
T
V
C
C
P
G
N
D
SGND1
SGND2
SGND3
SGND4
SGND5
+
PC788
330U
7343
4V
1
2
PR744
.012
2010
1%
1 2
PC801
0.01U
0402
50V
10%
1
2
PR114
100K
0402
1%
1
2
PC790
0.1U
0402
50V
+80-20%
1
2
PC65
0.1U
0805
10%
1
2
PR117
20K
0402
1%
1
2
PC799
10U
25V
1210
20%/X5R
1
2
PC66
0.1U
0805
10%
1
2
+
PC798
150U
7243
6.3V
1
2
PR109
4.7
0603
1%
1 2
PD724
BZV55C2V4/NA
A
K
PL716
120Z/100M
2012
1 2
PC74
47P
0402
50V
10%
1
2
JS703
SHORT-SMT4
1 2
D
S
PQ23
2N7002 G
D
S
D
G
S
PU709A
AO4900
SO8
4
5 6
3
R356 0
0402 5%
1 2
PR120
0
0402
5%
1
2
PR116
11.8K
0402
1%
1 2
PR113
20.5K
0402
1%
1
2
D
S
PQ22
2N7002 G
D
S
+
PC789
330U/NA
7343
4V
1
2
PJL2
JP_NET20
1
2
PC67
10U
16V
1206
1 2
PJL1
JP_NET20
1
2
PC800
0.1U
0402
50V
+80-20%
1
2
R369 0
0402 5%
1 2
G
D
S
PU709B
AO4900
SO8
2
8 7
1
PC791
0.01U
0402
50V
10%
1
2
PL715
3.9UH
SPC-08045
30%
1 2
PC71
1000P
0402
50V
10%
1 2
PR119
10K
0402
1%
1 2
PC76
100P
0402
50V
+/-10%
1
2
D
G
S
PU708A
AO4900
SO8
4
5 6
3
PC795
1000P
0402
50V
10%
1
2
PD7
BAW56
SOT23N
288100056017
2 1
3
PR742
0.008
2512
1%
1 2
PC75
220P
0402
50V
10%
1
2
PC793
1000P
0402
50V
10%
1
2
PC794
10U
25V
1210
20%/X5R
1
2
D
S
PQ20
2N7002 G
D
S
PL717
3.0UH
SPC-05703
30%
1 2
C382
0.1U/NA
0402
50V
+80-20%
1
2
+
PC787
330U
7343
4V
1
2
PC73
220P
0402
50V
10%
1
2
PC70
1000P
0402
50V
10%
1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
+3VS_P/+5VS_P
PCB 316680900001/ASSY 411680900011 R01
8050 MOTHERB/D
C
Title
Size
Document
Number
Rev
Date: Sheet of
5V_2
SENSE3-
SENSE3+
INTVCC0
SENSE5V-
SENSE5V+
INTVCC0
H8_PWRON 22,26 H8_PWRON 22,26
SUSC# 13,22,26
VDD5
GND
+5VS_P
DVMAIN
GND
GND
GND
GND
+3VS_P
GND
GND
GND
SGND0
GND
GND
SGND0
SGND0
SGND0
+5VS_P
SGND0
VDD5
PR47
10K
0402
1%
1
2
PR707
.012
2010
1%
1 2
PL701
120Z/100M
2012
1 2
PC24
180P
0402
50V
10%
1
2
PR9
100K
0402
1%
1
2
JS1
SHORT-SMT1
1 2
PR26
1M
0402
1%
1
2
PR3
4.7
0603
1%
1 2
PR35
107K
0402
1%
1 2
R23 0/NA
0402 5%
1 2 C23
0.1U/NA
0402
50V
+80-20%
1
2
PC19
1000P
0402
50V
10%
1 2
PR41
20K
0402
1%
1
2
G
D
S
PU702B
AO4900
SO8
2
8 7
1
PJL4
JP_NET20
1
2
PJL3
JP_NET20
1
2
PR55
200K
0402
1%
1
2
PC20
1000P
0402
50V
10%
1 2
PD708
BZV55C4V3/NA
A
K
PC4
0.1U
0805
10%
1
2
D
G
S
PU701A
AO4914
SO8
4
5 6
3 PR711
.012
2010
1%
1 2
+
PC719
150U
7343
6.3V
1
2
PD1
BAW56
SOT23N
288100056017
2 1
3
PU2
LTC3728L
HVQFN32_1
1 2 3 4 5 6 7 8
9
10
11
12
13
14
15
16
1
7
1
8
32
31
30
29
28
27
26
25
2
4
2
3
2
2
2
1
2
0
1
9
33
34
35
36
37
V
O
S
E
N
S
E
1
P
L
L
F
L
T
R
P
L
L
IN
F
C
B
IT
H
1
S
G
N
D
3
.3
V
O
U
T
IT
H
2
VOSENSE2
NC0
SENSE2-
SENSE2+
RUN/SS2
TG2
SW2
NC1
B
O
O
S
T
2
B
G
2
NC3
SENSE1-
SENSE1+
NC2
RUN/SS1
PGOOD
TG1
SW1
B
O
O
S
T
1
V
IN
B
G
1
E
X
T
V
C
C
IN
T
V
C
C
P
G
N
D
SGND1
SGND2
SGND3
SGND4
SGND5
D
S
PQ3
2N7002 G
D
S
PR54
200K
0402
1%
1
2
PC705
10U
25V
1210
20%/X5R
1
2
PR11
0
0402
5%
1 2
PC709
0.01U
0402
50V
10%
1
2
D
S
PQ1
2N7002 G
D
S
+
PC713
150U/NA
7343
6.3V
1
2
PR46
2K
0402
1%
1
2
PC707
1000P
0402
50V
10%
1
2
+
PC712
150U
7343
6.3V
1
2
+
PC725
150U/NA
7343
6.3V
1
2
PC10
0.1U
0402
50V
+80-20%
1
2
PC8
10U
16V
1206
1 2
G
D
S
PU701B
AO4914
SO8
2
8 7
1
PC704
10U
25V
1210
20%/X5R
1
2
PR10
100K
0402
1%
1
2
PC708
0.01U
0402
50V
10%
1
2
PR2
4.7
0603
1%
1 2
PR25 0
0402 5%
1 2
PC717
0.1U
0402
50V
+80-20%
1
2
PC7
0.1U
0805
10%
1
2
PC703
10U
25V
1210
20%/X5R
1
2
PC710
0.01U
0402
50V
10%
1
2
PR36
19.6K
0402
1%
1
2
JS704
SHORT-SMT4
1 2
PC737
0.1U
0402
50V
+80-20%
1
2
PC26
47P
0402
50V
10%
1
2
PL702
10UH
D124C
20%
1 2
D
S
PQ2
2N7002
G
D
S
PR27
1M
0402
1%
1
2
PC706
1000P
0402
50V
10%
1
2
PR48
0/NA
0402
5%
1
2
PC14
1000P
0402
50V
10%
1
2
D
G
S
PU702A
AO4900
SO8
4
5 6
3
PC721
10U
10V
1210
1
2
R24 0
0402 5%
1 2
C22
0.1U/NA
0402
50V
+80-20%
1
2
PC17
1000P
0402
50V
10%
1
2
PL703
10UH
D124C
20%
1 2
PC25
180P
0402
50V
10%
1
2 PR42
63.4K
0402
5%
1 2
D
S
PQ4
2N7002 G
D
S
PD707
BZV55B5V6/NA
A
K
PC23
47P
0402
50V
10%
1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
+1.5V_P/+1.05V_P
PCB 316680900001/ASSY 411680900011 R01
8050 MOTHERB/D
C
Title
Size
Document
Number
Rev
Date: Sheet of
SENSE1.5+
SENSE1.05-
INTVCC3
SENSE1.05+
INTVCC3
SENSE1.5-
VCCP_PWRGD 31
PWRON_SUSB# 25,26,29,30,31
GND
+1.5V_P
GND
GND
SGND3
SGND3
GND
DVMAIN
SGND3
GND
VDD5
SGND3
GND
GND
GND
+1.05V_P
GND
+3VS_P
GND
+5VS_P
PL706
3.9UH
SPC-08045
30%
1 2
PC738
180P
0402
25V
10%
1
2
PR730
1M
0402
1%
1
2
PC718
0.1U
0402
50V
+80-20%
1
2
G
D
S
PU4B
AO4900
SO8
2
8 7
1
PC727
1000P
0402
50V
10%
1 2
PC736
100P
0402
50V
+/-10%
1
2
PR725
2K
0402
1%
1
2
PJL5
JP_NET20
1
2
R714 0
0402 5%
1 2
PC31
0.01U
0402
50V
10%
1
2
D
S
PQ703
2N7002 G
D
S
PR719
.012
2010
1%
1 2
PR724
10K
0402
1%
1 2
PR718
18K
0402
1%
1 2
PR733
100K
0402
1%
1
2
PR722
20K
0402
1%
1
2
PD705
BAW56
SOT23N
288100056017
2 1
3
PC730
0.1U
0402
50V
+80-20%
1
2
+
PC728
220U/NA
7343
4V
1
2
PU703
LTC3728L
HVQFN32_1
1 2 3 4 5 6 7 8
9
10
11
12
13
14
15
16
1
7
1
8
32
31
30
29
28
27
26
25
2
4
2
3
2
2
2
1
2
0
1
9
33
34
35
36
37
V
O
S
E
N
S
E
1
P
L
L
F
L
T
R
P
L
L
IN
F
C
B
IT
H
1
S
G
N
D
3
.3
V
O
U
T
IT
H
2
VOSENSE2
NC0
SENSE2-
SENSE2+
RUN/SS2
TG2
SW2
NC1
B
O
O
S
T
2
B
G
2
NC3
SENSE1-
SENSE1+
NC2
RUN/SS1
PGOOD
TG1
SW1
B
O
O
S
T
1
V
IN
B
G
1
E
X
T
V
C
C
IN
T
V
C
C
P
G
N
D
SGND1
SGND2
SGND3
SGND4
SGND5
PR721
6.49K
0402
1%
1 2
+
PC742
220U/NA
7343
4V
1
2
PC734
220P
0402
50V
10%
1
2
PC40
1000P
0402
50V
10%
1
2
JS10
SHORT-SMT4
1 2
PR709
4.7
0603
1%
1 2
PR717
0
0402
5%
1 2
PR727
15K
0402
1%
1
2
PC731
1000P
0402
50V
10%
1 2
PC724
1000P
0402
50V
10%
1
2
PC30
1000P
0402
50V
10%
1
2
PC743
10U
25V
1210
20%/X5R
1
2
PC746
0.1U
0402
50V
+80-20%
1
2
PR723
0/NA
0402
5%
1
2
PC726
1000P
0402
50V
10%
1
2
PL3
120Z/100M
2012
1 2
PR728
15K
0402
1%
1
2
+
PC749
220U
7343
4V
1
2 PD716
BZV55C2V4/NA
A
K
PR713
0
0402
5%
1 2
PC38
0.01U
0402
50V
10%
1
2
PR715
100K
0402
1%
1
2
D
G
S
PU4A
AO4900
SO8
4
5 6
3
PR726
20K
0402
1%
1
2
G
D
S
PU6B
AO4900
SO8
2
8 7
1
PC715
0.1U
0805
10%
1
2
PD710
BZV55C2V4/NA
A
K
PR732
.012
2010
1%
1 2
PC739
10U
25V
1210
20%/X5R
1
2
D
S
PQ706
2N7002 G
D
S
PJL6
JP_NET20
1
2
PC735
100P
0402
50V
+/-10%
1
2
PC716
10U
16V
1206
1 2
+
PC729
220U
7343
4V
1
2
JS701
SHORT-SMT1
1 2
PL707
3.9UH
SPC-08045
30%
1 2
PC714
0.1U
0805
10%
1
2
C714
0.1U/NA
0402
50V
+80-20%
1
2
PR708
4.7
0603
1%
1 2
PC32
0.01U
0402
50V
10%
1
2
PC744
10U
25V
1210
20%/X5R
1
2
D
S
PQ705
2N7002 G
D
S
D
G
S
PU6A
AO4900
SO8
4
5 6
3
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
+1.8V_P/+1.35V_P
PCB 316680900001/ASSY 411680900011 R01
8050 MOTHERB/D
C
Title
Size
Document
Number
Rev
Date: Sheet of
SENSE1.2-
SENSE1.2+
INTVCC2
SENSE1.8+
1.2V_2
INTVCC2
SENSE1.8-
MCH_PG 31
PWRON_SUSB# 25,26,28,30,31
GND
DVMAIN
+3VS_P
GND
SGND2
SGND2
GND
VDD5
GND
GND
GND
GND
SGND2
GND
SGND2
+1.35V_P
+1.8V_P
GND
+5VS_P
PR101
2K
0402
1%
1
2
PR105
15K
0402
1%
1
2
PC765
0.01U
0402
50V
10%
1
2
PC52
0.1U
0805
10%
1
2
PR97
19.6K
0402
1%
1
2
PC779
10U
25V
1210
20%/X5R
1
2
PC53
10U
16V
1206
1 2
PR99
19.6K
0402
1%
1
2
PL714
3.0UH
SPC-06703
30%
1 2
PC61
180P
0402
50V
10%
1
2
PR741
.012
2010
1%
1 2
PR93
100K
0402
1%
1
2
PC60
100P
0402
50V
+/-10%
1
2
PC767
0.1U
0402
50V
+80-20%
1
2
PR107
15K
0402
1%
1
2
C142
0.1U/NA
0402
50V
+80-20%
1
2
PR102
10K
0402
1%
1 2
PJL7
JP_NET20
1
2
PR103
0
0402
5%
1
2
PL712
120Z/100M
2012
1 2
PD6
BAW56
SOT23N
288100056017
2 1
3
PC774
10U
25V
1210
20%/X5R
1
2
G
D
S
PU707B
AO4900
SO8
2
8 7
1
PR98
24.9K
0402
1%
1 2
D
S
PQ18
2N7002 G
D
S
D
G
S
PU705A
AO4900
SO8
4
5 6
3
PR92
0
0402
5%
1 2
PJL8
JP_NET20
1
2
PC51
0.1U
0805
10%
1
2
D
S
PQ16
2N7002 G
D
S
PC777
1000P
0402
50V
10%
1
2
+
PC783
150U/NA
7343
6.3V
1
2
PC780
0.1U
0402
50V
+80-20%
1
2
R103 0
0402 5%
1 2
PC62
100P
0402
50V
+/-10%
1
2
PR96
13.7K
0402
1%
1 2
PC776
1000P
0402
50V
10%
1
2
D
S
PQ17
2N7002 G
D
S
PC63
180P
0402
50V
10%
1
2
G
D
S
PU705B
AO4900
SO8
2
8 7
1
+
PC770
150U
7343
6.3V
1
2
PC55
1000P
0402
50V
10%
1
2
PD722
BZV55C2V4/NA
A
K
+
PC782
150U
7343
6.3V
1
2
PC59
1000P
0402
50V
10%
1 2
JS706
SHORT-SMT4
1 2
PC50
0.01U
0402
50V
10%
1
2
PR95
100K
0402
1%
1
2
PL713
3.0UH
SPC-06703
30%
1 2
PR94
0
0402
5%
1 2
PR106
1M
0402
1%
1
2
JS3
SHORT-SMT1
1 2
PC57
1000P
0402
50V
10%
1 2
PC54
0.1U
0402
50V
+80-20%
1
2
PR91
4.7
0603
1%
1 2
PR90
4.7
0603
1%
1 2
PC766
0.01U
0402
50V
10%
1
2
PR739
.012
2010
1%
1 2
PD719
BZV55C2V4/NA A
K
D
G
S
PU707A
AO4900
SO8
4
5 6
3
PU14
LTC3728L
HVQFN32_1
1 2 3 4 5 6 7 8
9
10
11
12
13
14
15
16
1
7
1
8
32
31
30
29
28
27
26
25
2
4
2
3
2
2
2
1
2
0
1
9
33
34
35
36
37
V
O
S
E
N
S
E
1
P
L
L
F
L
T
R
P
L
L
IN
F
C
B
IT
H
1
S
G
N
D
3
.3
V
O
U
T
IT
H
2
VOSENSE2
NC0
SENSE2-
SENSE2+
RUN/SS2
TG2
SW2
NC1
B
O
O
S
T
2
B
G
2
NC3
SENSE1-
SENSE1+
NC2
RUN/SS1
PGOOD
TG1
SW1
B
O
O
S
T
1
V
IN
B
G
1
E
X
T
V
C
C
IN
T
V
C
C
P
G
N
D
SGND1
SGND2
SGND3
SGND4
SGND5
PC56
3300P
0402
50V
10%
1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
+1.2V/1.0V_M10
PCB 316680900001/ASSY 411680900011 R01
8050 MOTHERB/D
C
Title
Size
Document
Number
Rev
Date: Sheet of
SW_1.5V/1.25V 7
PWRON_SUSB# 25,26,28,29,31
DVMAIN
GND
SGND7
GND
GND
SGND7
GND
GND
SGND7 SGND7
+5VS_P
GND
+1.2V/1.0V_M10
GND
PC78
0.01U/NA
0402
50V
10%
1
2
PD727
EC31QS04-TE12L/NA
DC2010
A
K
G
D
S
PU712
AO4410/NA
SO8
288204410010
8 7 6
4
5
2 3 1
PC64
10U/NA
16V
1206
1
2
JS707
SHORT-SMT4
1 2
PC807
1000P/NA
0402
50V
10%
1
2
G
D
S
PU710
SI4800DY/NA
SO8
8 7 6
4
5
2 3 1
PR130
100K/NA
0402
1%
1 2
PC37
0.1U/NA
0402
50V
+80-20%
1
2
PD725
EC10QS04/NA
A
K
PR100
10/NA
0402
5%
1 2
PC802
0.01U/NA
0402
50V
10%
1
2
PR72
1M/NA
0402
5%
1
2
PR127
10K/NA
0402
1%
1 2
PR108
4.7/NA
0603
1% 1
2
+
PC814
330U/NA
7343
4V
1
2
PC816
0.1U/NA
0402
50V
+80-20%
1
2
PU16
SC1470/NA
TSSOP14
3
4
8 7
6
2
5
1
9
10
11
12
13
14
VOUT
VCCA
PGND AGND
PGOOD
VIN
FB
EN/PSV
DL
VDDP
ILIM
LX
DH
BST
PC803
10U/NA
25V
1210
20%/X5R
1
2
PC805
10U/NA
25V
1210
20%/X5R
1
2
PL718
120Z/100M/NA
2012
1 2
PL719
2.2UH/NA
IHLP5050CE-01
20%
1 2
JS9
SHORT-SMT1
1 2
PC804
10U/NA
25V
1210
20%/X5R
1
2
PC79
0.1U/NA
0402
50V
+80-20%
1
2
PR125
0/NA
0402
5%
1 2
PC77
0.1U/NA
0402
50V
+80-20%
1
2
PC81
0.1U/NA
0805
10%
1
2
D
S
PQ19
2N7002/NA G
D
S
PC806
0.01U/NA
0402
50V
10%
1
2
+
PC815
330U/NA
7343
4V
1
2
PR129
10K/NA
0402
1%
1
2
PJL10
JP_NET20
1
2
PC80
0.1U/NA
0402
10V
10%
1
2
PD726
BZV55C2V4/NA
A
K
PR126
8.2K/NA
0402
5%
1 2
+
PC811
330U/NA
7343
4V
1
2
PR128
24.9K/NA
0402
1%
1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
CPU_CORE
PCB 316680900001/ASSY 411680900011 R01
8050 MOTHERB/D
C
Title
Size
Document
Number
Rev
Date: Sheet of
VID[0..5]
S1+
S1-
VID5 RUN/SS
VID4
VID3
VID2
VID1
VID0
S1+
S1-
VOS-
VOS-
RUN/SS
VID4
VID5
VID0
VID1
VID2
VID3
MCH_PG 29
VRMPWRGD 13
VCCP_PWRGD 28
PWROK 4,12,13,17,25
VID[0..5] 3
PM_PS 2
DPRSLPVR 13,14
STOP_CPU# 3,11,13
CORE_CLKEN# 11
PWRON_SUSB# 25,26,28,29,30
GND_A
VDD5
GND
+3V
GND_A
GND_A
GND_A
GND
DVMAIN
GND_A
GND_A
GND_A
GND
+VCC_CORE
DD_CPU
GND
GND_A
VDD3
GND
GND_A
GND_A
GND_A
GND_A
VDD3
VDD3
+5VS_P
+5VS_P
+5VS_P
+3V
+3VS
GND_A
PR44
0
0402
5%
1
2
PR50
1M
0402
1%
1
2
PC15
100P
0402
50V
+/-10%
1
2
G
D
S
PU12
FDS7788
SO8
8 7 6
4
5
2 3 1
+
PC778
220U
7243
2V
1
2 PR31
0
0402
5%
1
2
PC6
1U
0402
10V
+80-20%
1 2
PR52
0
0402
5%
1
2
PC752
10U
25V
1210
20%
1
2
PR40
0
0402
5%
1
2
+
PC785
220U
7243
2V
1
2
PD720
BZV55C2V4/NA
A
K
PR62
1M
0402
1%
1
2
D
S
PQ8
2N7002
SOT23_FET
G
D
S
PR16
1.3M
0402
1%
1 2
PR38
10
0402
1%
1 2
PR19
13.3K
0402
1%
1 2
G
D
S
PU13
FDS7788
SO8
8 7 6
4
5
2 3 1
PD718
EC31QS04-TE12L
DC2010
A
K
PR5
10
0402
1%
1
2
PR56
0
0402
5%
1 2
PC21
1000P
0402
50V
10%
1
2
PL5
120Z/100M
2012
1 2
PQ10
MMBT3904L
288203904022
B
E
C
+
PC784
220U
7243
2V
1
2
PC751
0.01U
0402
50V
10%
1
2
PC5
1000P
0402
50V
+80-20%
1
2
PR43
499K
0402
1%
1 2
PC773
0.1U
0402
50V
+80-20%
1
2
PC750
10U
25V
1210
20%
1
2
PR39
2.32K
0402
1%
1
2
PR68
1.91K/NA
0402
1%
1
2
PR59
1M
0402
1%
1
2
PC41
1000P
0402
50V
+/-20%
1
2
PR32
0
0402
5%
1 2
G
D
S
PU10
FDS6694
SO8
8 7 6
4
5
2 3 1
PR60
43.2K
0402
1%
1 2
G
D
S
PU8
FDS6694/NA
SO8
8 7 6
4
5
2 3 1
PR58
4.12K
0402
1%
1
2
PU3
LTC3734
HVQFN32
1
2
3
5
6
7
8
4
9 1
0
1
1
1
2
1
3
1
4
1
5
1
6
17
18
19
20
21
22
23
24
2
5
2
6
2
7
2
8
2
9
3
0
3
1
3
2
3
3
VOA+
VOA-
OAOUT
SGND
SENSE+
SENSE-
RDPRSLP
STP_CPUB
R
D
P
S
L
P
R
U
N
/S
S
IT
H
R
B
O
O
T
V
ID
0
V
ID
1
V
ID
2
N
C
VID3
VID4
VID5
PGND
BG
PVCC
SW
TG
B
O
O
S
T
P
G
O
O
D
M
C
H
_
P
G
V
F
B
S
V
C
C
D
P
R
S
L
P
V
R
F
R
E
Q
S
E
T
P
S
IB
S
G
N
D
1
PF2
7A/24VDC
1 2
PR13
0
0402
5%
1 2
PD4
BAT54C
1
2
3
PR73
0/NA
0402
5%
1 2
+
PC786
220U/NA
7243
2V
1
2
PJL9
JP_NET20
1
2
PC18
1000P
0402
50V
+80-20%
1 2
PC9
0.1U
0805
X7R
1 2
PR740
.001
2512C
1%
1 2
PC757
10U
25V
1210
20%
1
2
PC29
1000P
0402
50V
10%
1
2
G
D
S
PU9
FDS6694
SO8
8 7 6
4
5
2 3 1
PR8
4.7
0603
1%
1
2
PC13
10U
10V
1206
1
2
PR6
2.2K
0402
1%
1 2
PR64
249K/NA
0402
1%
1
2
PR7
0
0402
5%
1
2
PC755
10U
25V
1210
20%
1
2
PC753
10U
25V
1210
20%
1
2
+
PC781
220U
7243
2V
1
2
PR4
10K
0402
1%
1
2
PC22
100P/NA
0402
50V
+/-10%
1
2
PR14
0
0402
5%
1 2
PD706
EC10QS04
A
K
PC754
10U
25V
1210
20%
1
2
PC28
3300P
0402
50V
10%
1
2
PL711
0.68UH
IHLP-5050CE
15%
1 2
PR731
2K
0402
1%
1 2
PR37
10
0402
1%
1 2
PC11
220P
0402
50V
10%
1
2
PR710
1.96K
0402
1%
1
2
PR49
100K
0402
1%
1
2
PR15
56.2K
0402
1%
1 2
PR12
100K
0402
1%
1 2
PR712
0
0402
5%
1
2
PR51
2K/NA
0402
1%
1 2
PR17
12.7K
0402
1%
1 2
D
S
PQ7
2N7002
SOT23_FET
G
D
S
+
PC775
220U
7243
2V
1
2
PC58
1000P
0402
50V
+/-20%
1
2
C26
0.1U/NA
0402
50V
+80-20%
1
2
PR28
576K
0402
1%
1 2
PR66
80.6K
0402
1%
1
2
PC12
0.1U
0402
50V
+80-20%
1
2 PR33
0
0402
5%
1
2
D
S
PQ5
2N7002
SOT23_FET
G
D
S
PR29
13.3K
0402
1%
1 2
PC27
100P
0402
50V
+/-10%
1
2
PR729
249K
0402
1%
1
2
PR18
1
0402
1%
1
2
PR61
0
0402
5%
1 2
PC35
1U
0402
10V
+80-20%
1
2
PR104
0
0402
5%
1 2
PR30
100K
0402
1%
1 2
G
D
S
PU11
FDS7788
SO8
8 7 6
4
5
2 3 1
PR34
0
0402
5%
1
2
PL4
120Z/100M
2012
1 2
JS2
SHORT-SMT1
1 2
PR57
0
0402
5%
1 2
PQ9
MMBT3904L
288203904022
B
E
C
PR53
1K
0402
1%
1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
VMAIN/DISCHARGE
PCB 316680900001/ASSY 411680900011 R01
8050 MOTHERB/D
C
Title
Size
Document
Number
Rev
Date: Sheet of
B1
A1
LEARNING
A2 A4
B2 B3
A3
I_LIMIT 22
LEARNING 22
BATT 33
BAT_V 22
BAT_T 22
BAT_C 22
BAT_D 22
ADEN# 22,25
BATT 33
ADINP 33
VDD3
VDD3
GND
GND
GND
GNDB
PWR_VDDIN
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VDD3S
DVMAIN
GND
GND
GND
GND
VDD5
GND
PR703
100K
0402
5%
1
2
PC1
0.01U
0402
50V
10%
1
2 PR1
10
0402
5%
1
2
PR716
499K
0402
1%
1
2
PD702
BAV70LT1
288100070006
1
2
3
PR720
100K
0402
5%
1 2
PD701
RLZ24D
MLL34B
A
K
PD3
BAV99
288100099012
1
2
3
PQ24
DTC144WK
288202237002
1
2
3
PR24
0
0402
5%
1 2
PC819
0.01U
0402
50V
+80-20%
1
2
PC86
0.01U
0402
50V
+80-20%
1
2
PL1
120Z/100M
2012
1 2
PC3
1U
10V
0805
1
2
+
-
PU5A
LMV393M
SSOP8
3
2
1
8
4
JP1
SPARKGAP_6
1
2
JO11
SPARKGAP_6
1
2
PC701
1U
25V
0805
1
2
PJ701
JACK-2P
2DC-S107B200
331910002006
2
1
3 4
PC740
0.01U
0402
50V
10%
1
2
PC85
1000P
0402
50V
+/-20%
1
2
PC820
1000P
0402
50V
+/-20%
1
2
PR701
.01
2512
1%
1 2
PJO701
OPEN-SMT4
1
2
PC720
0.01U
0402
50V
10%
1
2
D
S
PQ6
2N7002
SOT23_FET
G
D
S
PR71
226K
0402
1%
1
2
JO701
OPEN-SMT4
1 2
G
D S
PQ701
AO4407
SO8
8
7
6
4
5 1
3
2
J703
R/A-7P-2.5MM
SUYIN
250233-MR007G123ZU
1
2
3
4
5
6
7
1
2
3
4
5
6
7
PC82
0.01U
0402
50V
+80-20%
1
2
PC733
0.01U
0402
50V
+80-20%
1
2
PD704
BAV70LT1
288100070006
1
2
3
JO1
SPARKGAP_6
1
2
PF702 7A/24VDC
1 2
PC732
1000P
0402
50V
+/-20%
1
2
JO2
SPARKGAP_6
1
2
PD2
BAV99
288100099012
1
2
3
D
S
PQ702
2N7002 G
D
S
PC818
0.01U
0402
50V
+80-20%
1
2
PR714
100K
0402
1%
1
2
PC722
0.01U
0402
50V
10%
1
2
PC2
0.01U
0402
50V
10%
1
2
PD703
SBM1040
1
2
3
PR21
20K
0402
1%
1
2
PL705
120Z/100M
2012
1 2
PR20
4.99K
0402
1%
1
2
PL2
120Z/100M
2012
1 2
PR23
0
0402
5%
1 2
PC723
0.1U
0402
50V
+80-20%
1
2
PR704
4.7K
0805
1
2
PR705
1M
0402
5%
1
2
PF1 7A/24VDC
1 2
PC83
0.01U
0402
50V
+80-20%
1
2
PR45
33K
0402
5%
1
2
PC16
0.1U
0402
50V
+80-20%
1
2
PC821
1000P
0402
50V
+/-20%
1
2
PC702
0.01U
0402
50V
10%
1
2
PC84
1000P
0402
50V
+/-20%
1
2
PL704
120Z/100M
2012
1 2
PR706
4.7K
0805
1
2
PR702
470K
0402
5%
1
2
PU1
MAX4173FEUT-T
SOT26
1 6
2
3
5
4
GND0 OUT
GND1
VCC
RS-
RS+
G
D
S
PQ704
AO4407
SO8
8 7 6
4
5
1 3 2
PC711
1000P
0402
50V
+/-20%
1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
CHARGING
=8.56V
12.65V
PCB 316680900001/ASSY 411680900011 R01
8050 MOTHERB/D
C
Title
Size
Document
Number
Rev
Date: Sheet of
1.25V
L2
REF
2IN+
L4 L3 L5
2IN+
ADINP 32 BATT 32
BATT_DEAD 22
I_CTRL 22
CHARGING 22
CHARGING 22
VDD5
GND
GND GNDB
GND
GND
GND
GND
GND
GND
DVMAIN
GND
D
S
PQ14
2N7002
SOT23_FET G
D
S
+
-
PU5B
LMV393M
SSOP8
5
6
7
8
4
PC42
0.01U
0402
50V
+80-20%
1 2
PC39
1000P
0402
50V
10%
1
2
PC48
0.01U
0402
50V
10%
1
2
PC34
0.01U
0402
50V
10%
1
2
PR65
590K
0402
1%
1
2
PC49
0.01U/NA
0402
50V
+80-20%
1 2
PD713
EC31QS04
DC2010
A K
PR69
100K
0402
5%
1
2
PR76
249K
0402
1%
1
2
PR63
80.6K
0402
5%
1
2
PC43
0.01U
0402
50V
+80-20%
1 2
PD5
BAS32L
MLL34B
A K
PR84
7.5K
0402
5%
1
2
PR85
0
0402
5%
1 2
PR79
124K
0402
1%
1
2
PL708
BEAD_120Z/100M
0805D
1 2
D
S
PQ12
2N7002
SOT23_FET G
D
S
PR82
10K
0402
1%
1
2
PC741
10U
25V
1210
1
2
PC45
0.1U
0402
50V
+80-20%
1 2
PJ1
OPEN-SMT4
1
2
PR70
3.3K
0402
5%
1
2
PC745
10U
25V
1210
1
2
PL709
3.0UH
SPC-06703
30%
1 2
PD714
EC31QS04
DC2010
A
K
PR80
63.4K/NA
0402
5%
1 2
PC748
0.01U
0402
50V
10%
1
2
PR81
6.19K
0402
1%
1 2
PR86
0
1206
5%
1 2
PC46
1U
10V
0805
1
2
PC756
10U
25V
1210
1
2
PR77
2.49K
0402
1%
1
2
PC33
0.1U
0402
50V
+80-20%
1
2
PR74
13.7K
0402
0.1%
1
2
PR22
.02
2512
1%
1 2
PC47
1000P
0402
50V
10%
1
2
PU7
TL594C
SO16
1
2
3
4
5
6
7
8 9
10
11
12
13
14
15
16
1IN+
1IN-
FEEDBACK
DTC
CT
RT
GND
C1 E1
E2
C2
VCC
OUTPUTCTRL
REF
2IN-
2IN+
PC44
0.1U
0402
16V
10%
1 2
G
D S
PQ707
AO4407
SO8
8
7
6
4
5 1
3
2
PR89
100K
0402
5%
1
2
PJS1
SHORT-SMT3
1 2
PC36
0.01U
0402
50V
10%
1
2
PF703
TR/3216FF-3A
1 2
PR87
4.7K
0603
1
2
PQ15
MMBT2222A
288202222019
B
E
C
PR83
100K
0402
5%
1
2
PD711
RLZ20C/NA
MLL34B
A
K
PQ11
SCK431LCSK-.5
SOT23N
3
2
1
PC747
0.01U
0402
50V
10%
1
2
PC758
0.01U
0402
50V
10%
1
2 PR75
20K
0402
0.1%
1
2
PQ13
DTA144WK
SOT23AN_1
1
2
3
PR78
0
0402
5%
1 2
PD709
BZV55C15V
A
K
PL710
33UH
CDRH124
1 2
PR88
4.7K
0603
1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
855GME
MINIPCI
3
3
M
H
Z
CLOCK GENERATOR
Keyboard BIOS
S
M
B
U
S
IEEE1394
ICS950810
CPU_THRMDA/CPU_THRMDC
HDD
North Bridge
W83L950D
HP JACK
25MHZ
BATT-Adapter
VIA
VT6307L
D/D Power
LTC3728L
DDR 266
WINBOND
I-LIMIT OP
D/D Power
LTC3728L
USBCLK_ICH
HCLK_NB+/- 100MHZ
PRIMARY IDE
EXT
MIC.
Sourth Bridge
D/D Charger
TL-594C
P
C
I
C
L
K
_
M
I
N
I
P
C
I
RGB
24.576MHZ
32.768KHZ
+3V/+5V
SECONDARY IDE
PCMCIA
D/D
SYSTEM
MAX4173F
AUDIO
48MHZ
ALC655
66M_MCH
3
3
M
H
Z
512K
LVDS
MODULE
ICH4-M
Internal
Keyboard
AC-Adapter
PCICLK_ICH 33MHZ
P
C
I P
C
I
_
1
3
9
4
_
C
L
K
I -LIMIT
BIOS
Fan
INT
MIC
MDC
LPC BUS
CPU
INTEL
BANIAS/DOTHAN
24.576MHZ / NA
P
S
/
2
(XGA)
CODEC
I -LIMIT
8MHZ
P
C
I
_
C
R
A
D
_
C
L
K
66M_ICH
DREFCLK_48MHZ
AMPLIFIER
AC97
3
3
M
H
Z
PCMCIA/
CARDBUS
SLOT
D/D CPU Core
LTC3734
K
E
Y
M
A
T
R
I
X
TPA0212
SPEAKER
TOUCH
LCD PANEL
CDROM
ADT7460
66MHZ
PAD
+2.5V/+1.25V
VGA_M10
AGP
27MHZ
LVDS/NA
RGB/NA
CRT
TV
CH7011
HCLK_CPU+/- 100MHZ
CLK_ITP_CPU+/- 100MHZ
66M_AGP
14M_CODEC
14M_CODEC (CLK GEN)
14.318MHZ
P
C
I
C
L
K
_
F
W
H
USB 0~2
x3
14M_ICH
CARD READER
NA
RTL8100CL
PCICLK_LAN
RJ45/ RJ11
PH163112
SIO_48M
(DEBUG CARD ONLY)
DIMM0
CLK_DDR4+/-
CLK_DDR5+/-
CLK_DDR3+/-
CLK_DDR0+/-
DIMM1
CLK_DDR1+/-
CLK_DDR2+/-
VGA_THRMDA/VGA_THRMDC
VRAM
16MBx4
SPEAKER
LM4871
SUB WOOFER
LINE
IN
HOST
400MHZ
66MHZ
D/D Power
LTC3728L
+1.5V/+1.05V
D/D Power
LTC3728L
8050 BLOCK DIAGRAM
CARD
REARDER
SOCKET
CardReader
Transition
Board
CABLE
CB710
CP2211
D/D Power
SC1470
+1.2V/1.0V +1.8V /+1.35V
PCB 316680900001/ASSY 411680900011 R01
8050 MOTHERB/D
C
Title
Size
Document
Number
Rev
Date: Sheet of
REFERENCE MATERIAL
System Explode View
Intel Mobile Pentium-M Processor/BANIAS Processor Intel, INC.
Intel 855GME North Bridge Intel, INC.
Intel ICH-4 South Bridge
8050 Hardware Specification
WINBOND, LTD.
Intel, INC.
Technology Corp / MiTAC
WINBOND KBC
Technology Corp / MiTAC
VT6307L IEEE1394 Host Controller AMPRO Computers, INC
Clock Syntherizer ICS,INC
SERVICE MANUAL FOR 8050 SERVICE MANUAL FOR SERVICE MANUAL FOR 8050
Sponsoring Editor : Jesse Jan
Author : Grass Ren
Assistant Editor : Ping.Xie
Publisher : MiTAC International Corp.
Address : 1, R&D Road 2, Hsinchu Science-Based Industrial, Hsinchu, Taiwan, R.O.C.
Tel : 886-3-5779250 Fax : 886-3-5781245
First Edition : Feb.2004
E-mail : Willy .Chen @ mic.com.tw
Web : http: //www.mitac.com http: //www.mitacservice.com
Sponsoring Editor : Jesse Jan
Author : Grass Ren
Assistant Editor : Ping.Xie
Publisher : MiTAC International Corp.
Address : 1, R&D Road 2, Hsinchu Science-Based Industrial, Hsinchu, Taiwan, R.O.C.
Tel : 886-3-5779250 Fax : 886-3-5781245
First Edition : Feb.2004
E-mail : Willy .Chen @ mic.com.tw
Web : http: //www.mitac.com http: //www.mitacservice.com

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BY: Grass Grass.Ren .

2.1 System View

Line Out Connector

2.1.4 Rear View

Hard Disk Drive

Device LED Indicators

Stereo Speaker Set

Stereo Speaker Set

Figure 2-13 Remove the Wireless card

ISSUES CHECK DESIGN DRAWN

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