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    Cisco Interview

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    vlsi_asic
    This document contains interview questions about setup and hold timing, timing models, congestion, block libraries, process-voltage-temperature effects on timing, jitter, debugging timing violations, block-related challenges including floorplanning, congestion fixes, timing closure techniques, design rule checks, and output file handoff.

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    Download as TXT, PDF, TXT or read online from Scribd

    Cisco Interview

    Uploaded by

    vlsi_asic
    268 views1 page
    This document contains interview questions about setup and hold timing, timing models, congestion, block libraries, process-voltage-temperature effects on timing, jitter, debugging timing violations, block-related challenges including floorplanning, congestion fixes, timing closure techniques, design rule checks, and output file handoff.

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    © Attribution Non-Commercial (BY-NC)

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    This document contains interview questions about setup and hold timing, timing models, congestion, block libraries, process-voltage-temperature effects on timing, jitter, debugging timing violations, block-related challenges including floorplanning, congestion fixes, timing closure techniques, design rule checks, and output file handoff.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as TXT, PDF, TXT or read online from Scribd
    Download as txt, pdf, or txt
    268 views1 page

    Cisco Interview

    Uploaded by

    vlsi_asic
    This document contains interview questions about setup and hold timing, timing models, congestion, block libraries, process-voltage-temperature effects on timing, jitter, debugging timing violations, block-related challenges including floorplanning, congestion fixes, timing closure techniques, design rule checks, and output file handoff.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as TXT, PDF, TXT or read online from Scribd
    Download as txt, pdf, or txt
    of 1

    Cisco Intervew Questions What is setup and hold ? What are timing models ? What is conjestion ?

    What is block lib and what it contains ? What is Process in PVT and how it affects design timing ? What is jitter and how it affects? If you do all the techniques you told to meet setup and if still setup is violat ing what will you do ? If you taped out a chip and it's not functing properly how will you say that it' s because of setup or hold ? Block related questions What was major challange in your block ? You had any Floorplan related issues in ur block ? How did you fix conjestion in your block ? How did you fix setup and hold in your block ? How to analyse timing report? and timing closure techniques. What were the types of DRC's in your block ? What are the output files you provided to the top level team after you finished your block ?

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