FAN6755W

May 2013
2009 Fairchild Semiconductor Corporation www.fairchildsemi.com

FAN6755W / FAN6755UW Rev. 1.0.7
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FAN6755W / FAN6755UW
mWSaver
PWM Controller
Features
mWSaver
Technology Provides Industrys Best-

in-Class Standby Power
- <100 mW at 25-mW Load for LCDM Adaptor
- Internal High-Voltage JFET Startup
- Low Operating Current: Under 2 mA
- Adaptively Decrease PWM Frequency to
23 kHz at Light-Load Condition for Better
Efficiency
- Feedback Impedance Switching During
Minimum Load or No Load
Proprietary Asynchronous Frequency Hopping
Technique that Reduces EMI
Fixed PWM Frequency: 65 kHz (FAN6755W),
130 kHz (FAN6755UW)
Internal Leading-Edge Blanking
Built-in Synchronized Slope Compensation
Auto-Restart Protection: Feedback Open-Loop
Protection (OLP), VDD Over-Voltage Protection
(OVP), Over-Temperature Protection (OTP), and
Line Over-Voltage Protection
Soft Gate Drive with Clamped Output Voltage: 18 V
VDD Under-Voltage Lockout (UVLO)
Programmable Constant Power Limit
(Full AC Input Range)
Internal OTP Sensor with Hysteresis
Build-in 5-ms Soft-Start Function
Input Voltage Sensing (VIN Pin) for Brown-In/Out
Protection with Hysteresis and Line Over-Voltage
Protection
Applications
General-purpose switched-mode power supplies and
flyback power converters, including:
LCD Monitor Power Supply
Open-Frame SMPS

Description
This highly integrated PWM controller provides several
features to enhance the performance of flyback
converters.
To minimize standby power consumption, a proprietary
adaptive green-mode function reduces switching
frequency at light-load condition. To avoid acoustic-
noise problems, the minimum PWM frequency is set
above 23 kHz. This green-mode function enables the
power supply to meet international power conservation
requirements, such as Energy Star
. With the internal

high-voltage startup circuitry, the power loss caused by
bleeding resistors is also eliminated. To further reduce
power consumption, FAN6755W/UW uses the BiCMOS
process, which allows an operating current of only
2 mA. The standby power consumption can be under
100 mW for most of LCD monitor power supply designs.
FAN6755W/UW integrates a frequency-hopping
function that reduces EMI emission of a power supply
with minimum line filters. The built-in synchronized
slope compensation achieves a stable peak-current-
mode control and improves noise immunity. The
proprietary line compensation ensures constant output
power limit over a wide AC input voltage range from
90 VAC to 264 VAC.
FAN6755W/UW provides many protection functions.
The internal feedback open-loop protection circuit
protects the power supply from open-feedback-loop
condition or output-short condition. It also has line
under-voltage protection (brownout protection) and
over-voltage protection using an input voltage sensing
pin (VIN).
FAN6755W/UW is available in a 7-pin SOP package.

ENERGY STAR is a registered trademark of the U.S. Department of Energy and the U.S. Environmental Protection Agency.

FAN6755W / FAN6755UW Rev. 1.0.7 2
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Ordering Information
Part Number
Operating
Temperature
Range
Package
PWM
Frequency
Packing
Method
FAN6755WMY -40 to +105C
7-Lead, Small Outline Integrated Circuit
(SOIC), Depopulated JEDEC MS-112, .150
Inch Body
65 kHz Reel & Tape
FAN6755UWMY -40 to +105C 130 kHz Reel & Tape

Application Diagram
L
N
EMI
Filter
+
+
HV VDD
FAN6755W
5
2
7
+
FB
VIN
SENSE
GATE
6
3
4
1
Vo+
Vo-

Figure 1. Typical Application

FAN6755W / FAN6755UW Rev. 1.0.7 3
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Internal Block Diagram

Figure 2. Internal Block Diagram

Marking Information

Figure 3. Top Mark

Z: Plant Code
X: 1-Digit Year Code
Y: 1-Digit Week Code
TT: 2-Digit Die Run Code
T: Package Type (M:SOP)
P: Y=Green Package
M: Manufacture Flow Code
ZXYTT
6755
WTPM

7
ZXYTT
6755U
WTPM

7
GATE
FB
SENSE
GND
VDD
VIN 1
5.3V
Soft
Driver
Q S
R
VIN-Protect
UVLO
Blanking
Circuit
OLP
OVP
Delay
Debounce
VDD-OVP
6
7
5
2
3
HV
Brownout Protection
OLP
3R
OLP
Comparator
PWM
Comparator
Internal
BIAS
Soft-Start
VLimit
Slope
Compensation
R
Current Limit
Comparator
Soft-Start
Comparator
4
VIN-ON / VIN-OFF
VLimit
Brownout Protection
High/Low
Line Compensation
Debounce
OLP
Re-start
Protection
OVP
VDD
OTP
V
D
D
-
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N

/
V
D
D
-
O
F
F
V
FB-OLP
V
IN
-OVP
Green
Mode
OSC
Pattern
Generator
V
RESET
V
PWM
VRESET
Max.
Duty
VPWM
VIN-OVP

FAN6755W / FAN6755UW Rev. 1.0.7 4
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Pin Configuration

Figure 4. Pin Configuration (Top View)
Pin Definitions
Pin # Name Description
1 VIN
Line-voltage detection. The line-voltage detection is used for brownout protection with
hysteresis. Constant output power limit over universal AC input range is also achieved using this
VIN pin. It is suggested to add a low-pass filter to filter out line ripple on the bulk capacitor.
Pulling VIN HIGH also triggers auto-restart protection.
2 FB
The signal from the external compensation circuit is fed into this pin. The PWM duty cycle is
determined in response to the signal on this pin and the current-sense signal on the SENSE pin.
3 SENSE
Current sense. The sensed voltage is used for peak-current-mode control and cycle-by-cycle
current limiting.
4

GND Ground
5 GATE The totem-pole output driver. Soft-driving waveform is implemented for improved EMI.
6 VDD
Power supply. The internal protection circuit disables PWM output as long as VDD exceeds the
OVP trigger point.
7 HV For startup, this pin is connected to the line input or bulk capacitor in series with resistors.

SOP-7
VIN
VDD
GATE
HV
GND
SENSE
FB
1 7
6
5 4
2
3

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Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device
reliability. The absolute maximum ratings are stress ratings only.
Symbol Parameter Min. Max. Unit
VVDD DC Supply Voltage
(1, 2)
30 V
VFB FB Pin Input Voltage -0.3 7.0 V
VSENSE SENSE Pin Input Voltage -0.3 7.0 V
VVIN VIN Pin Input Voltage -0.3 7.0 V
VHV HV Pin Input Voltage 700 V
PD Power Dissipation (TA50C) 400 mW
JA Thermal Resistance (Junction-to-Air) 150 C/W
TJ Operating Junction Temperature -40 +125 C
TSTG Storage Temperature Range -55 +150 C
TL Lead Temperature (Wave Soldering or IR, 10 Seconds) +260 C
ESD
Human Body Model,
JEDEC: JESD22-A114
All Pins Except HV Pin 5.5
kV
Charged Device Model,
JEDEC: JESD22-C101
All Pins Except HV Pin 2.0
Notes:
1. All voltage values, except differential voltages, are given with respect to the network ground terminal.
2. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
3. ESD with HV pin: CDM=2000 V (FAN6755W) or 1500 V (FAN6755UW), and HBM=3500 V.

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Electrical Characteristics
VDD=15 V, TA=25C, unless otherwise noted.
Symbol Parameter Conditions Min. Typ. Max. Unit
V
DD
Section
VOP Continuously Operating Voltage Full Load 22 V
VDD-ON Start Threshold Voltage 15 16 17 V
VDD-OFF Protection Mode 9 10 11 V
UVLO Normal Mode 6.8 7.8 8.8 V
IDD-ST Startup Current VDD-ON 0.16 V 30 A
IDD-OP Operating Supply Current VDD=15 V, GATE Open 2 mA
IDD-OLP Internal Sink Current VDD-OLP+0.1 V 30 60 90 A
VDD-OLP
Threshold Voltage on VDD for HV
JFET Turn-On
6.5 7.5 8.0 V
VDD-OVP VDD Over-Voltage Protection 25 26 27 V
tD-VDDOVP
VDD Over-Voltage Protection
Debounce Time
75 125 200 s
HV Section
IHV Supply Current Drawn from HV Pin
VDC=120 V, VDD=10 F,
VDD=0 V
2.0 3.5 5.0 mA
IHV-LC Leakage Current after Startup
HV=700 V, VDD=VDD-
OFF+1 V
1 20 A

VDD-ON
V
DD
UVLO
t
Normal Mode
VDD-ON
V
DD
VDD-OFF
t
VDD-OLP
Protection Mode

Figure 5. VDD Behavior
Continued on the following page

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Oscillator Section
fOSC Frequency in Normal Mode
Center
Frequency
FAN6755W 62 65 68
kHz
FAN6755UW 124 130 136
Hopping
Range
FAN6755W 4.5 5.2 5.9
FAN6755UW 9 10.4 11.8
fOSC-G Green-Mode Frequency 20 23 26 kHz
tHOP Hopping Period 10 12 14 ms
fDV
Frequency Variation vs. VDD
Deviation
VDD=11 V to 22 V 5 %
fDT
Frequency Variation vs.
Temperature Deviation
TA=-40 to 85C=TJ 5 %
V
IN
Section
VIN-OFF
PWM Turn-Off (Brown-out)
Threshold Voltage

0.66 0.70 0.74
V
VIN-ON
PWM Turn-On (Brown in)
Threshold Voltage

VIN-OFF+
0.17
VIN-OFF+
0.20
VIN-OFF+
0.23
V
VIN-Protect
Threshold Voltage of VIN Over-
Voltage Protection
5.1 5.3 5.5 V
tVIN-Protect
Debounce Time of VIN Over-
Voltage Protection
60 100 140 s
Current-Sense Section
VLIMIT at
VIN=1 V
Threshold Voltage for Current Limit VIN=1 V 0.80 0.83 0.86 V
VLIMIT at
VIN=3 V
Threshold Voltage for Current Limit VIN=3 V 0.67 0.70 0.73 V
tPD Delay to Output 100 200 ns
tLEB Leading-Edge Blanking Time
Soft-Start (FAN6755UW) 125 150 175
ns
Steady State 240 290 340
tSS Period During Soft-Start Time Startup Time 4.0 5.5 7.0 ms
V
Limit
VIN
VIN-OFF VIN-Protect
=3V VIN VIN=1V
VSENSE=0.83V
VSENSE =0.7V
=0.92V =5.3V

Figure 6. VIN vs. VSENSE

FAN6755W / FAN6755UW Rev. 1.0.7 8
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Feedback Input Section
AV Internal FB Voltage Attenuation 1/4.5 1/4.0 1/3.5 V/V
ZFB Input Impedance V
FB
=4 V 10 15 19 k
VFB-OPEN The Maximum Clamp of FB Voltage FB Pin Open 5.1 5.3 5.5 V
VFB-OLP
FB Open-Loop Protection Triggering
Level
4.4 4.6 4.8 V
tD-OLP
Delay Time of FB Pin Open-loop
Protection
45.0 62.5 70.0 ms
VFB-N Green-Mode Entry FB Voltage 2.8 3.0 3.2 V
VFB-G Green-Mode Ending FB Voltage VFB-N - 0.6 V
VFB-ZDCR
FB Threshold Voltage for Zero-Duty
Recovery
1.6 1.8 2.0 V
VFB-ZDC FB Threshold Voltage for Zero-Duty 1.4 1.6 1.8 V
VFB-ZDCR -
VFB-ZDC
ZDC Hysteresis 0.12 0.15 0.19 V

f
OSC
f
OSC-G
V V
FB-N FB-G FB
V
Frequency
PWM
Frequency
FB-ZDC
V
FB-ZDCR
V
+ hopping range
- hopping range
+1.76KHz
-1.76KHz

Figure 7. VFB vs. PWM Frequency


FAN6755W / FAN6755UW Rev. 1.0.7 9
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GATE Section
DCYMAX Maximum Duty Cycle 60 75 90 %
VGATE-L Gate Low Voltage VDD=15 V, IO=50 mA 1.5 V
VGATE-H Gate High Voltage VDD=12 V, IO=50 mA 8 V
tr Gate Rising Time VDD=15 V, CL=1 nF
100 ns
tf Gate Falling Time VDD=15 V, CL=1 nF
30 ns
IGATE-
SOURCE
Gate Source Current VDD=15 V, GATE=6 V 700 mA
VGATE-
CLAMP
Gate Output Clamping Voltage VDD=22 V 18 V
Over-Temperature Protection Section (OTP)
TOTP Protection Junction Temperature
(4,6)
140 C
TRestart Restart Junction Temperature
(5,6)
TOTP-25 C
Notes:
4. When OTP is activated, the PWM switching is shut down.
5. When junction temperature is lower than this level, IC resumes PWM switching.
6. These parameters are guaranteed by design.

FAN6755W / FAN6755UW Rev. 1.0.7 10
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Typical Performance Characteristics

Figure 8. Startup Current (IDD-ST) vs. Temperature
Figure 9. Operation Supply Current (IDD-OP)
vs. Temperature

Figure 10. Start Threshold Voltage (VDD-ON)
vs. Temperature
Figure 11. Minimum Operating Voltage (VDD-OFF)
vs. Temperature

Figure 12. Supply Current Drawn from HV Pin (IHV)
vs. Temperature
Figure 13. HV Pin Leakage Current After Startup
(IHV-LC) vs. Temperature

Figure 14. Frequency in Normal Mode (fOSC)
vs. Temperature
Figure 15. Maximum Duty Cycle (DCYMAX)
vs. Temperature

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Typical Performance Characteristics

Figure 16. FB Open-Loop Trigger Level (VFB-OLP)
vs. Temperature
Figure 17. Delay Time of FB Pin Open-Loop Protection
(tD-OLP) vs. Temperature

Figure 18. PWM Turn-Off Threshold Voltage
(VIN-OFF & VIN-ON) vs. Temperature
Figure 19. VDD Over-Voltage Protection (VDD-OVP)
vs. Temperature

Figure 20. VIN vs. VLIMIT

FAN6755W / FAN6755UW Rev. 1.0.7 12
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Functional Description
Startup Current
For startup, the HV pin is connected to the line input or
bulk capacitor in series with diodes and/or resistors. If HV
pin is connected to the line input, a 1-kV/ 1-A diode and a
100 k resistor are recommended. If HV pin is connected
to the bulk capacitor, only the resistor is required. Startup
current drawn from pin HV (typically 3.5 mA) charges the
hold-up capacitor through the diode and resistor. When
the VDD capacitor level reaches VDD-ON, the startup current
switches off. At this moment, only the VDD capacitor
supplies the FAN6755W/UW to maintain VDD before the
auxiliary winding of the main transformer to provide the
operating current.
Operating Current
Operating current is below 2 mA. The low operating
current enables better efficiency and reduces the
requirement of VDD hold-up capacitance.
Green-Mode Operation
The proprietary green-mode function provides an off-
time modulation to reduce the switching frequency in
light-load and no-load conditions. The on time is limited
for better abnormal or brownout protection. VFB, which is
derived from the voltage feedback loop, is taken as the
reference. Once VFB is lower than the threshold voltage,
switching frequency is continuously decreased to the
minimum green-mode frequency of around 23 kHz.
Current Sensing / PWM Current Limiting
Peak-current-mode control is utilized to regulate output
voltage and provide pulse-by-pulse current limiting. The
switching current is detected by the current-sensing
resistor of SENSE pin. The PWM duty cycle is
determined by this current sense signal and VFB, the
feedback voltage. When the voltage on the SENSE pin
reaches around VCOMP=(VFB0.6)/4, the PWM switching
turns off immediately.
Leading-Edge Blanking (LEB)
Each time the power MOSFET is switched on, a turn-on
spike occurs on the sense resistor. To avoid premature
termination of the switching pulse, a leading-edge
blanking time is built in. During this blanking period, the
current-limit comparator is disabled and cannot switch
off the gate driver.
Under-Voltage Lockout (UVLO)
The turn-on and turn-off thresholds are fixed internally
at 16 V and 7.8 V in normal mode. During startup, the
hold-up capacitor must be charged to 16 V through the
startup resistor to enable the IC. The hold-up capacitor
continues to supply VDD before the energy can be
delivered from auxiliary winding of the main transformer.
VDD must not drop below 7.8 V during startup. This
UVLO hysteresis window ensures that the hold-up
capacitor is adequate to supply VDD during startup.
Gate Output / Soft Driving
The BiCMOS output stage is a fast totem-pole gate
driver. Cross conduction has been avoided to minimize
heat dissipation, increase efficiency, and enhance
reliability. The output driver is clamped by an internal
18 V Zener diode to protect power MOSFET transistors
against undesirable gate over voltage. A soft-driving
circuit is implemented to minimize EMI.
Soft-Start
For many applications, it is necessary to minimize the
inrush current at startup. The built-in 5.5 ms soft-start
circuit significantly reduces the startup current spike
and output voltage overshoot.
Slope Compensation
The sensed voltage across the current-sense resistor is
used for peak-current-mode control and pulse-by-pulse
current limiting. Built-in slope compensation improves
stability and prevents sub-harmonic oscillation.
FAN6755W/UW inserts a synchronized positive-going
ramp at every switching cycle as slope compensation.
Constant Output Power Limit
For constant output power limit over universal input-
voltage range, the peak-current threshold is adjusted by
the voltage of the VIN pin. Since the VIN pin is
connected to the rectified AC input line voltage through
the resistive divider, a higher line voltage generates a
higher VIN voltage. The threshold voltage decreases as
VIN increases, making the maximum output power at
high-line input voltage equal to that at low-line input.
The value of R-C network should not be so large that it
affects the power limit (shown in Figure 21). R and C
should be less than 100 and 470 pF, respectively.
FAN6755W
SENSE
GATE
Blanking
Circuit
R
C

Figure 21. Current-Sense R-C Filter

FAN6755W / FAN6755UW Rev. 1.0.7 13
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V
DD
Over-Voltage Protection
VDD over-voltage protection prevents damage due to
abnormal conditions. Once the VDD voltage is over the
over-voltage protection voltage (VDD-OVP), and lasts for tD-
VDDOVP, the PWM pulses are disabled. When the VDD
voltage drops below the UVLO, the internal startup circuit
turns on, and VDD is charged to VDD-ON to restart IC.
Feedback Impedance Switching
FAN6755W/UW actively varies FB-pin impedance
(ZFB) to reduce no-load power consumption. This
technique can further reduce operating current of the
controller when FB-pin voltage drops below VFB-ZDC.
Figure 22 exhibits the range that ZFB changes. When
VFB is lower than VFB-ZDC, PWM switching is stopped
and ZFB is switched from 15 k to 90 k. On the other
hand, ZFB is switched from 90 k to 15 k when VFB is
higher than VFB-ZDCR.
V
FB
(V)
f
osc
(kHz)
VFB-ZDCR VFB-ZDC
Z
FB
=90k
Z
FB
=15k
Proprietary

Figure 22. ZFB-Switching Activating Range
Brownout Protection
Since the VIN pin is connected through a resistive
divider to the rectified AC input line voltage, it can also
be used for brownout protection. If VIN is less than
0.7 V, the PWM output is shut off. When VIN reaches
over 0.9 V, the PWM output is turned on again. The
hysteresis window for ON/OFF is around 0.2 V. The
brownout voltage setting is determined by the potential
divider formed with RUpper and RLower. Equations to
calculate the resistors are shown below:
) V unit ( , V
R R
R
V
AC
Upper Lower
Lower
IN

2
(1)
Thermal Overload Protection
Thermal overload protection limits total power
dissipation. When the junction temperature exceeds TJ=
+140C, the thermal sensor signals the shutdown logic
and turns off most of the internal circuitry. The thermal
sensor turns internal circuitry on again after the ICs
junction temperature drops by 25C. Thermal overload
protection is designed to protect the FAN6755W/UW in
the event of a fault condition. For continual operation,
the controller should not exceed the absolute maximum
junction temperature of TJ = +140C.
Limited Power Control
The FB voltage is saturated HIGH when the power
supply output voltage drops below its nominal value and
shut regulator (KA431) does not draw current through
the opto-coupler. This occurs when the output feedback
loop is open or output is short circuited. If the FB
voltage is higher than a built-in threshold for longer than
tD-OLP, PWM output is turned off. As PWM output is
turned off, VDD begins decreasing since no more energy
is delivered from the auxiliary winding.
As the protection is triggered, VDD enters into UVLO
mode. This protection feature continues as long as the
over loading condition persists. This prevents the power
supply from overheating due to overloading conditions.
Noise Immunity
Noise on the current sense or control signal may cause
significant pulse-width jitter, particularly in continuous-
conduction mode. Slope compensation helps alleviate
this problem. Good placement and layout practices
should be followed. Avoiding long PCB traces and
component leads, locating compensation and filter
components near the FAN6755W/UW, and increasing
the gate resistor from GATE pin to MOSFET improve
performance.

FAN6755W / FAN6755UW Rev. 1.0.7 14
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Typical Application Circuit
2
1
3
4
BD1
F1

+
C11
R9
C17
R19
C16
R18
1
2
3
Q1
R28
R12
2
1
D4
+ C18
C4
2
1
D3
1
2
4
3
U2
A
K
R
U3
R21 C20
R26
R23 R24
12V 5V
R20
+ C8 + C9
12V
+ C14
5V
R5
R7
C7
C6
1
2
3
CN1
AC IN
1
3
2
D5
1
3
2
D1
R6
R4
1 2
L2
1 2
L3
R16
7
10
2
1
6
4 12
11
9
8
TX1
1
2 3
4
L1
C5
M1

2
1
D2 R11
C15
C10
R1

R2
C3
C1
C2
R8
R17
L
N
N1 N2
N3
N4
N5 N6
N7
N8
N9
VDD FB
SENSE
GATE
HV
N10
N12 N13
N14 N15
N16
N17
N18
N20
N21
N1A
N28
N29
P1
12V
P2
5V
P3
SGND
+ C13
C19
R15
12V1
R27
R25
R13
R10
N30
C12
R3
R14
VIN
VIN
2
1
ZD1
R22
5V1
5V1
VIN
1
FB
2
SENSE
3
GND
4
GATE
5
VDD
6
HV
7
U1
FAN6755

FAN6755W

Figure 23. 44 W Flyback 12 V/2 A, 5 V/4 A Application Circuit

FAN6755W / FAN6755UW Rev. 1.0.7 15
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Bill of Materials
Designator Part Type Designator Part Type
BD1 BD 4 A/600 V Q1 MOS 9 A/600 V
C1 YC 2200 pF/Y1 R1 R 1.5 M 1/4 W
C2 YC 2200 pF/Y1 R2 R 1.5 M 1/4 W
C3 XC 0.33 F/300 V R3 R 10 M 1/4 W
C4 NC R4, R5, R6, R7 R 47 1/4 W
C5 YC 2200 pF/Y1 R8, R17, R25, R27 NC
C6 CC 2200 pF/100 V R9 R 50 K 1/4 W
C7 CC 1000 pF/100 V R10 R 50 K 1/4 W
C8 EC 1000 F/25 V R11 R 0 1/8 W
C9 EC 470 F/25 V R12 R 47 1/8 W
C10 CC 100 pF/50 V R13 R 100 K 1/8 W
C11 EC 100 F/400 V R14 R 0 1/4 W
C12 C 1 F/50 V R15 R 10 K 1/8 W
C13 EC 1000 F/10 V R16 R 1 1/8 W
C14 EC 470 F/10 V R18 R 0 1/8 W
C15 CC 100 pF/50 V R19 R 100 1/8 W
C16 C 1 nF/50 V R20 R 1 K 1/8 W
C17 C 470 pF/50 V R21 R 4.7 K 1/8 W
C18 EC 47 F/50 V R22 R 7.5 K 1/8 W
C19 C 0.01 F/50 V R23 R 120 K 1/8 W
C20 C 0.1 F/50 V R24 R 15 K 1/8 W
D1 FYP1010 R26 R 10 K 1/8 W
D2 1N4148 R28 R 0.43 2 W
D3 FR107 TX1 800 H(ERL-28)
D4 FR103 U1 IC FAN6755W
D5 FYP1010 U2 IC PC817
ZD1 P6KE150A U3 IC TL431
F1 FUSE 4A/250V
M1 VZ 9G
L1 13 mH
L2 Inductor (2 H)
L3 Inductor (2 H)

FAN6755W / FAN6755UW Rev. 1.0.7 16
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Physical Dimensions
PIN #1
FRONT VIEW
TOP VIEW
8
0
SEE DETAIL A
LAND PATTERN RECOMMENDATION
SEATING PLANE
C
GAGE PLANE
x 45
DETAIL A
SCALE: 2:1
4
7
1
B
5
A
3.85
0.65TYP
1.75TYP
1.27
6.20
5.80
3.81
4.00
3.80
5.00
4.80
(0.33)
1.27
0.51
0.33
0.25
0.10
1.75 MAX
0.25
0.19
0.36
0.50
0.25
R0.10
R0.10
0.90
0.406 (1.04)
OPTION A - BEVEL EDGE
OPTION B - NO BEVEL EDGE
7.35
3.81
NOTES:
A) THIS PACKAGE DOES NOT FULLY CONFORMS
TO JEDEC MS-012, VARIATION AA, ISSUE C,
DATED MAY 1990.
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE MOLD
FLASH OR BURRS.
D) STANDARD LEAD FINISH:
200 MICROINCHES / 5.08 MICRONS MIN.
LEAD/TIN (SOLDER) ON COPPER.
E) DRAWING FILENAME : M07Arev3
2 3
6
0.25 C B A
0.10 C

Figure 24. 7-Lead, Small Outline Package (SOP)
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify
or obtain the most recent revision. Package specifications do not expand the terms of Fairchilds worldwide terms and conditi ons,
specifically the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductors online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
7

FAN6755W / FAN6755UW Rev. 1.0.7 17
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May 2013

2009 Fairchild Semiconductor Corporation www.fairchildsemi.com

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