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LP38798
SNOSCT6E MARCH 2013 REVISED SEPTEMBER 2016
3 Description
2 Applications
PART NUMBER
LP38798
PACKAGE
WSON (12)
4.00 mm 4.00 mm
space
space
space
space
Simplified Schematic
1
VIN
3
+
VEN
IN
OUT
IN
OUT
OUT(FB)
IN(CP)
12
VOUT
11
10
COUT
LP38798
CIN
CP
SET
EN
FB
CCP
R1
5
ON
OFF
R2
GND
GND(CP)
DAP
GND
GND
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LP38798
SNOSCT6E MARCH 2013 REVISED SEPTEMBER 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
4
4
5
7
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
Programming...........................................................
14
14
14
15
16
20
20
20
20
21
21
21
21
21
21
4 Revision History
Changes from Revision D (June 2016) to Revision E
Page
Page
Changed "Value for R2 = 12.9 k and 100 k" to "R2 = 12.9 k minimum to 100 k maximum"..................................... 18
Changed "for R1 is" to "needed for R1 to provide an output voltage of 5 V is" ................................................................... 18
Page
Changed "linear regulator" to "LDO" on page 1; add top nav icon for reference design ....................................................... 1
Changed Handling Ratings table to ESD Ratings table; move storage temperature to Abs Max table ............................... 4
Page
Added Device Information and Handling Rating tables, Feature Description, Device Functional Modes, Application
and Implementation, Power Supply Recommendations, Layout, Device and Documentation Support, and
Mechanical, Packaging, and Orderable Information sections; updated Thermal Information; moved some curves to
Application Curves section ..................................................................................................................................................... 1
LP38798
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12 OUT
IN
11 OUT
IN(CP)
CP
EN
GND(CP)
Exposed Pad
on Bottom
(DAP)
LP38798SD
IN
10 OUT(FB)
9
SET
FB
GND
Pin Functions
PIN
NUMBER
1, 2
NAME
I/O
DESCRIPTION
IN
Device unregulated input voltage pins. Connect pins together at the package.
IN(CP)
Charge pump input voltage pin. Connect directly to pins 1 and 2 at the package.
CP
Charge pump output. See Charge Pump section in Application and Implementation for more
information.
EN
Enable pin. This pin has an internal pull-up to turn the LDO output On by default. A logic low
level will turn the LDO output Off, and reduce the operating current of the device. See Enable
Input Operation section in Application and Implementation for more information.
GND(CP)
GND
FB
SET
I/O
10
OUT(FB)
OUT buffer feedback input pin. Connect directly to pins 11 and 12 at the package.
11, 12
OUT
Device regulated output voltage pins. Connect pins together at the package.
Exposed Pad
DAP
The exposed die attach pad on the bottom of the package must be connected to a copper
thermal pad on the PCB at ground potential. Connect to ground potential or leave floating. Do
not connect to any potential other than the same ground potential seen at device pins 6
(GND(CP)) and 7 (GND). See Thermal Considerations section in Layout for more information.
LP38798
SNOSCT6E MARCH 2013 REVISED SEPTEMBER 2016
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
VIN, VIN(CP)
0.3
22
VOUT, VOUT(FB)
0.3
VIN + 0.3
VSET
0.3
VIN + 0.3
VFB
0.3
VIN + 0.3
VEN
0.3
Internally Limited
IOUT (Survival)
Internally Limited
65
150
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The value of RJA for the WSON package is dependent on PCB copper area, copper thickness, the number of copper layers in the PCB,
and the number of thermal vias under the exposed thermal pad (DAP). Exceeding the maximum allowable power dissipation will cause
excessive die temperature, and the regulator may go into thermal shutdown. See Thermal Considerations.
Electrostatic discharge
200
250
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
MAX
UNIT
20
1.2
(VIN VDO)
40
125
(1)
DNT (WSON)
UNIT
12 PINS
RJA
35.4
C/W
RJC(top)
29.4
C/W
RJB
12.6
C/W
JT
0.2
C/W
JB
12.8
C/W
RJC(bot)
2.6
C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
LP38798
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TYP (2)
MAX (1)
VIN = 5.5 V
TJ = 25C
1.188
1.2
1.212
5.5 V VIN 20 V
1.176
1.2
1.224
3.5
16
mV
67.8
PARAMETER
VFB
Feedback voltage
VOS
VOUT VSET
IFB
ISET
TEST CONDITIONS
VFB = 1.2 V
VIN = 3 V, VSET = 2.5 V
VIN = 5.5 V, VSET = 5 V
52
71
VOUT /
VIN
5.5 V VIN 20 V
IOUT = 10 mA
VOUT /
IOUT
VIN = 5.5 V
10 mA IOUT 800 mA
VDO
IOUT = 800 mA
UVLO
Undervoltage lock-out
UVLO
UVLO hysteresis
180
IGND
IOUT = 800 mA
1.4
2.25
1.6
2.51
IQ
IOUT = 0 mA
1.4
2.1
VIN = 20 V, IOUT = 0 mA
1.5
2.2
ISD
VEN = 0 V
ISC
Short-circuit current
RLOAD = 0
VCP VIN
tSTART
Start-up time
PSRR
(1)
(2)
(3)
(4)
(5)
(6)
46
25.2
VCP
UNIT
2.47
VIN = 20 V, VEN = 0 V
850
0.005
%/V
0.2
%/A
200
420
mV
2.65
2.83
V
mV
20
12
40
1200
1600
2.8
VIN = 20 V
2.3
155
110
VOUT = 5 V, f = 10 kHz
90
90
60
70
VOUT = 5 V, f = 1 MHz
60
mA
mA
A
mA
V
300
dB
Minimum and maximum limits are ensured through test, design, or statistical correlation over the operating junction temperature (TJ )
range of 40C to 125C, unless otherwise stated.
Typical values represent the most likely parametric norm at TJ = 25C, and are provided for reference purposes only.
Line Regulation: % change in VOUT(NOM) for every 1V change in VIN= (( VOUT / VOUT(NOM)) / VIN ) 100%
Load Regulation: % change in VOUT(NOM) for every 1A change in IOUT = (( VOUT / VOUT(NOM) ) / IOUT ) 100%
Dropout voltage (VDO) is defined as the differential voltage measured between VOUT and VIN when VIN, falling from VIN = VOUT + 1 V,
causes VOUT to drop 2% below the value measured with VIN = VOUT + 1 V. Dropout voltage specification does not apply when the
programmed output voltage is below the Minimum Operating Input Voltage.
Ground pin current is the sum of the current in both GND pins (pin 4 and pin 5) only, and does not include current from the SET pin.
Submit Documentation Feedback
LP38798
SNOSCT6E MARCH 2013 REVISED SEPTEMBER 2016
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eN
TEST CONDITIONS
MIN (1)
TYP (2)
4.96
5.21
11.53
VIN = 6 V, VOUT = 5 V
COUT = 1 F X7R
BW = 10 Hz to 100 kHz
5.38
VIN = 6 V, VOUT = 5 V
BW = 10 Hz to 100 kHz
5.43
VIN = 6 V, VOUT = 5 V
BW = 10 Hz to 10 MHz
11.58
MAX (1)
UNIT
V(RMS)
ENABLE INPUT
VEN(ON)
Enable ON threshold
voltage
VEN
IEN(IL)
VEN = 500 mV
IEN(IH)
VEN = 2 V
VEN(CLAM
EN pin = Open
1.14
1.24
1.34
110
V
mV
A
V
P)
THERMAL SHUTDOWN
TSD
Thermal shutdown
TSD
Thermal shutdown
hysteresis
170
12
LP38798
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120
120
110
110
100
100
90
90
80
80
PSRR (dB)
PSRR (dB)
Unless otherwise specified: VIN = 5.5 V, VOUT = 5 V, IOUT = 10 mA, COUT = 10 F MLCC 16 V X7R, and TJ = 25C.
70
60
10 mA
50
100 mA
40
30
200 mA
20
400 mA
10
70
60
10 mA
50
100 mA
40
VIN = 5.5 V
VOUT = 5.0 V
COUT = 10 F MLCC
800 mA
30
200 mA
20
400 mA
10
VIN = 6.0 V
VOUT = 5.0 V
COUT = 10 F MLCC
800 mA
0
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
10
100
1k
Figure 1. PSRR
1M
10M
C008
1
Cout = 1 F
Cout = 1 F
Cout = 10 F
Cout = 10 F
100k
Figure 2. PSRR
0.1
0.01
VIN = 3.0 V
VOUT = 1.2 V
IOUT = 500 mA
0.001
0.1
0.01
VIN = 6.0 V
VOUT = 5.0 V
IOUT = 500 mA
0.001
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
10M
10
100
110
100
100
90
90
80
80
PSRR (dB)
110
70
VOUT = 5.0 V
COUT = 10 F MLCC
IOUT = 10 mA
40
100k
1M
10M
C010
50
10k
FREQUENCY (Hz)
120
60
1k
C009
PSRR (dB)
10k
FREQUENCY (Hz)
C007
70
VOUT = 5.0 V
COUT = 10 F MLCC
IOUT = 100 mA
60
50
40
30
30
20
10
Vin = 5.5V
20
Vin = 6.0V
10
Vin = 5.5V
Vin = 6.0V
0
10
100
1k
10k
100k
FREQUENCY (Hz)
1M
10M
10
C001
Figure 5. PSRR
100
1k
10k
100k
1M
FREQUENCY (Hz)
10M
C002
Figure 6. PSRR
LP38798
SNOSCT6E MARCH 2013 REVISED SEPTEMBER 2016
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120
110
110
100
100
90
90
80
80
PSRR (dB)
PSRR (dB)
Unless otherwise specified: VIN = 5.5 V, VOUT = 5 V, IOUT = 10 mA, COUT = 10 F MLCC 16 V X7R, and TJ = 25C.
70
VOUT = 5.0 V
COUT = 10 F MLCC
IOUT = 200 mA
60
50
40
70
VOUT = 5.0 V
COUT = 10 F MLCC
IOUT = 400 mA
60
50
40
30
30
20
10
Vin = 5.5V
20
Vin = 5.5V
Vin = 6.0V
10
Vin = 6.0V
0
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
10M
10
100
1k
110
110
100
100
90
90
80
80
70
VOUT = 5.0 V
COUT = 10 F MLCC
IOUT = 800 mA
50
40
10M
C004
VIN = 5.5 V
VOUT = 5.0 V
IOUT = 800 mA
60
50
30
20
20
Vin = 5.5V
10
Cout = 10 F
10
Vin = 6.0V
Cout = 50 F
0
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
10M
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
C005
Figure 9. PSRR
10M
C006
3.0
1.40
2.9
Rising VIN (ON)
2.8
1M
70
40
30
2.7
2.6
2.5
2.4
2.3
2.2
1.35
Rising VEN (ON)
1.30
1.25
1.20
1.15
1.10
1.05
2.1
2.0
1.00
-50
-25
25
50
75
100
TEMPERATURE, TJ (C)
125
-50
C023
100k
Figure 8. PSRR
120
PSRR (dB)
PSRR (dB)
Figure 7. PSRR
120
60
10k
FREQUENCY (Hz)
C003
-25
25
50
75
100
TEMPERATURE, TJ (C)
125
C024
LP38798
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1.35
2.0
Rising VEN (ON)
1.30
VIN = 5.5 V
VOUT = 1.2 V
1.5
1.25
VOLTS (V)
1.40
1.20
1.15
1.0
Ven
0.5
Vout 125C
1.10
0.0
1.05
Vout 25C
Vout -40C
1.00
-0.5
0
10
12
14
16
18
TIME (50s/DIV)
20
C025
C026
2.5
5.5
5.0
2.0
4.0
VIN = 5.5 V
VOUT = 1.5 V
3.5
VOLTS (V)
1.5
VOLTS (V)
VIN = 5.5 V
VOUT = 5.0 V
4.5
1.0
Ven
0.5
0.0
2.5
2.0
Ven
1.5
Vout 125C
1.0
Vout -40C
Vout 25C
0.5
Vout 25C
0.0
Vout -40C
-0.5
3.0
Vout 125C
-0.5
TIME (50s/DIV)
TIME (50s/DIV)
C027
C028
6.0
0.5
Vout = 5.0V
0.4
Vout = 3.3V
Vout = 1.2V
4.0
VOUT (V)
VIN = 5.5 V
Normalized to TJ = 25C
0.3
VFB VARIATION (%)
5.0
3.0
2.0
UVLO
0.2
0.1
0.0
-0.1
-0.2
-0.3
1.0
-0.4
0.0
-0.5
0.0
1.0
2.0
3.0
4.0
VIN (V)
5.0
6.0
-50
C038
-25
25
50
75
100
TEMPERATURE, TJ (C )
125
C029
LP38798
SNOSCT6E MARCH 2013 REVISED SEPTEMBER 2016
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5.5
5.0
VEN = 0.0V
16
4.5
14
4.0
VEN(CLAMP) (V)
18
12
10
8
6
4
2
3.5
3.0
2.5
2.0
125C
1.5
125C
25C
1.0
25C
0.5
-40C
-40C
0.0
0
10
12
14
16
18
20
10
12
14
16
18
C030
20
C031
3.0
350
DROPOUT VOLTAGE, VDO (mV)
125C
2.5
2.0
1.5
1.0
125C
0.5
25C
300
25C
250
-40C
200
VOUT = 3.0V
150
100
50
-40C
0.0
0
10
12
14
16
18
0
0.01
20
25C
250
-40C
200
VOUT = 5.0V
VIN = 5.5 V
VOUT = 5.0 V
IOUT = 800 mA
Normalized to 25C
1.5
VOUT VARIATION (%)
1
C033
350
150
100
50
1.0
0.5
0.0
-0.5
-1.0
-1.5
0
0.01
-2.0
0.1
-50
C034
10
0.1
OUTPUT CURRENT (A)
C032
-25
25
50
75
TEMPERATURE, TJ (C)
100
125
C035
LP38798
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0.05
1.8
0.04
LINE REGULATION (%/V)
Unless otherwise specified: VIN = 5.5 V, VOUT = 5 V, IOUT = 10 mA, COUT = 10 F MLCC 16 V X7R, and TJ = 25C.
1.6
1.4
1.2
1.0
0.8
0.6
VIN = 5.5 V
VOUT = 5.0 V
IOUT = 10 mA to 800 mA
0.4
0.2
VIN = 5.5 V to 15 V
VOUT = 5.0 V
IOUT = 10 mA
0.03
0.02
0.01
0.00
-0.01
-0.02
-0.03
-0.04
0.0
-0.05
-50
-25
25
50
75
100
TEMPERATURE, TJ (C)
125
-50
-25
25
50
75
100
TEMPERATURE, TJ (C)
C036
125
C037
1.5
1.4
VIN
1V
/DIV
1.3
VIN = 7.0 V
VIN = 6.0 V
VOUT = 5.0 V
COUT = 10 F
IOUT = 800 mA
1.2
1.1
VOUT
1.0
VOUT
20 mV
/DIV
0.9
0.8
-50
-25
25
50
75
100
TEMPERATURE (C)
TIME (500s/DIV)
125
C039
C022
VIN
1V
/DIV
VIN
1V
/DIV
VIN = 7.0V
VIN = 6.0V
VOUT = 5.0 V
COUT = 10 F
IOUT = 400 mA
VIN = 7.0 V
VOUT = 5.0 V
COUT = 10 F
IOUT = 10 mA
VOUT
VOUT
20 mV
/DIV
VIN = 6.0 V
VOUT
VOUT
20 mV
/DIV
TIME (500s/DIV)
TIME (500s/DIV)
C021
C020
11
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VIN
1V
/DIV
VOUT = 1.2 V
COUT = 10 F
IOUT = 800 mA
VOUT = 1.2 V
COUT = 10 F
IOUT = 400 mA
VIN = 4.3 V
VIN = 3.3 V
VIN = 4.3 V
VIN = 3.3 V
VIN
1V
/DIV
VOUT
VOUT
VOUT
20 mV
/DIV
VOUT
20 mV
/DIV
TIME (500s/DIV)
TIME (500s/DIV)
C019
C018
VIN
1V
/DIV
VOUT = 1.2 V
COUT = 10 F
IOUT = 10 mA
IOUT
200 mA
/DIV
VIN = 4.3 V
VIN = 3.3 V
IOUT = 800 mA
IOUT = 400 mA
VIN = 5.5 V
VOUT = 5.0 V
COUT = 10 F
VOUT
VOUT
20 mV
/DIV
VOUT
20 mV
/DIV
VOUT
TIME (500s/DIV)
TIME (500s/DIV)
C017
C016
IOUT
200 mA
/DIV
VIN = 5.5 V
VOUT = 5.0 V
COUT = 10 F
IOUT
200 mA
/DIV
IOUT = 800 mA
VIN = 5.5 V
VOUT = 5.0 V
COUT = 10 F
IOUT = 400 mA
IOUT = 10 mA
IOUT = 10 mA
VOUT
20 mV
/DIV
VOUT
20 mV
/DIV
VOUT
TIME (500s/DIV)
VOUT
TIME (500s/DIV)
C015
12
C014
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IOUT
200 mA
/DIV
IOUT
200 mA
/DIV
IOUT = 800 mA
VIN = 3.3 V
VOUT = 1.2 V
COUT = 10 F
VIN = 3.3 V
VOUT = 1.2 V
COUT = 10 F
IOUT = 800 mA
IOUT = 400 mA
IOUT = 10 mA
VOUT
20 mV
/DIV
VOUT
20 mV
/DIV
VOUT
VOUT
TIME (500s/DIV)
TIME (500s/DIV)
C013
C012
IOUT
200 mA
/DIV
IOUT = 400 mA
IOUT = 10 mA
VOUT
20 mV
/DIV
VOUT
TIME (500s/DIV)
C011
13
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7 Detailed Description
7.1 Overview
The LP38798 is a positive voltage (20 V), ultra-low-noise (5 VRMS), low-dropout (LDO) regulator capable of
supplying a well-regulated, low-noise voltage to an 800-mA load. The LP38798 uses an advanced design with a
CMOS process to deliver ultra low output noise and high PSRR at switching power supply (SMPS) frequencies.
OUT
Active Ripple
Rejection
IN
UVLO
+
-
200 mV
IN(CP)
OUT
PMOS
Current
Limit
OUT(FB)
Thermal
Shutdown
98%
Charge Pump
3.5 MHz
tau= 2s
CP
SET
IEN
2 PA
99.5%
+
-
ISET
52 PA
EN
FB
5V
1.24V
VREF
1.200V
GND(CP)
GND
14
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(1)
(2)
(3)
NOTE
Thermal shutdown is provided as a safety feature and is outside the specified Operating
Ratings temperature range. Operation with a junction temperature (TJ) above 125C is not
recommended as the device behavior is not specified.
15
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7.5 Programming
7.5.1 Programming the Output Voltage
Current sourced from the SET pin, through R1 and R2, must be kept to less than 100 A. The minimum allowed
value for R2 is 12.9 k.
ISET = VFB / R2
R2MIN = VFB(MAX) / 100 A
R2MIN = 12.9 k;
(4)
(5)
(6)
The values for R1 and R2 may be adjusted as needed to achieve the desired output voltage as long as the value
for R2 is no less than 12.9 k. The maximum recommended value for R2 is 100 k.
Equation 7 is used to determine the output voltage:
VOUT = (VFB (1 + ( R1 / R2 ))) + VOS
(7)
Alternately, Equation 8 can be used to determine the appropriate R1 value for a given R2 value:
R1 = R2 (((VOUT) / VFB) 1)
(8)
Table 1 suggests some 1% values for R1 and R2 for a range of output voltages using the typical VFB value of
1.200V. This is not a definitive list, as other combinations exist that will provide similar, possibly better,
performance.
Table 1. Typical R1 and R2 Values for Assorted Output Voltages
TARGET VOUT
16
R1
R2
TYPICAL VOUT
1.2 V
15 k
1.2 V
1.5 V
4.22 k
16.9 k
1.5 V
1.8 V
10.5 k
21.0 k
1.8 V
2.0 V
10.0 k
15.0 k
2.0 V
2.5 V
16.2 k
15.0 k
2.496 V
3.0 V
21.0 k
14.0 k
3.0 V
3.3 V
23.2 k
13.3 k
3.293 V
5.0 V
47.5 k
15.0 k
5.0 V
LP38798
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5.50V
VIN
3
CIN
1 PF
MLCC
OUT
IN
OUT
IN(CP)
OUT(FB)
12
VOUT
11
CP
SET
EN
FB
+ COUT
10 PF
9 (5.00V)
8 (1.20V)
R1
47.5k
R2
15.0k
7
GND(CP)
5.00V
10
LP38798
4
CCP
10 nF
VEN
IN
GND
DAP
GND
GND
EXAMPLE VALUE
Input voltage
5.5 V, 10%
Output voltage
5. V, 3.5%
Output current
500 mA
17
LP38798
SNOSCT6E MARCH 2013 REVISED SEPTEMBER 2016
www.ti.com
The input capacitor must be located as close as physically possible to the input pin and returned to a clean
analog ground. Any good quality tantalum capacitor may be used, while a ceramic capacitor should be X5R or
X7R rated with appropriate adjustments due to the loss of capacitance value from the applied DC voltage.
Attention must be given to the input capacitance value to minimize transient input voltage droop during load
current steps at the OUT pin. Larger input capacitor values are necessary for good transient load response, and
have no detrimental influence on the stability of the device. Note, however, that using large value ceramic input
capacitances can also cause unwanted ringing at the output if the input capacitor, in combination with the trace
inductance, creates a high-Q peaking effect during transients. Short, well-designed interconnect leads to the upstream supply minimize this effect without adding damping. Damping of unwanted ringing can be accomplished
by using a tantalum capacitor, with a few hundred milli-ohms of ESR, in parallel with the ceramic input capacitor.
8.2.2.2 Output Capacitor Recommendations
The LP38798 requires an output capacitance of at least 1 F, ceramic or tantalum; however, a minimum output
capacitance of 10 F is strongly recommended if fast load transient conditions are expected. While the LP38798
is designed to work with Ceramic output capacitors, the output capacitor can be Ceramic, Tantalum, or a
combination. The total output capacitance must be sized appropriately to handle any fast load current steps.
Capacitance type, tolerance, ESR, as well as temperature and voltage characteristics, must be considered when
selecting an output capacitor for the application.
Note especially that the output capacitances must be located as near as practical to the OUT pins.
Even though the LP38798 is stable with an output capacitance of 1 F to 10 F, a single output capacitor will
generally not be able to provide the best PSRR performance across a wide frequency range. Multiple parallel
capacitors, each with a different self-resonance frequency will provide better performance over a wider frequency
range.
The LP38798 is characterized with a ceramic capacitor of 10 F, or greater, at the output. Noise performance is
characterized using a single output capacitor of 10 F 10%, 16V, X7R, 1206.
8.2.2.3 Charge Pump
The charge pump is running when both the input voltage is above the UVLO threshold (2.65 V typical) and the
EN pin voltage is above the VEN(ON) threshold (1.24 V typical). The typical charge pump operating frequency is
3.5 MHz.
A low leakage 10 nF X7R storage capacitor is required between the CP pin and ground to store the energy
required for gate drive of the internal NMOS pass device. Larger values of capacitance may slow start-up times,
while smaller capacitance values may result in degraded dynamic performance.
Do not make any other connection to the CP pin. Loading this pin in any manner will degrade regulator
performance. No external biasing may be applied to, or derived from, this pin, as permanent damage to the
internal charge pump circuitry may occur.
8.2.2.4 Setting the Output Voltage
The output voltage is buffered from the SET pin. The output voltage is defined as:
VOUT = VSET = (VFB (1 + (R1 / R2))
where
(9)
Selecting a standard 1% resistor value of 15 k for R2, the resistor value needed for R1 to provide an output
voltage of 5V is calculated from:
R1 = R2 (( VOUT / VFB) 1 )
R1 = 15 k ((5 V / 1.2 V) 1)
R1 = 47.5 k
18
(10)
(11)
(12)
LP38798
www.ti.com
(13)
(14)
(15)
Given 250 mW of device power dissipation, a maximum operating junction temperature (TJ) of 125C, and
presuming a RJA of 35.4C/W, the maximum ambient temperature (TA) is defined as:
TA(MAX) = TJ(MAX) (PD RJA)
TA(MAX) = (125C (0.25 W 35.4C/W))
TA(MAX) = 116C
(16)
(17)
(18)
VIN = 5.5 V
VOUT = 5.0 V
4.0
VOLTS (V)
3.5
3.0
2.5
2.0
Ven
1.5
1.0
Vout -40C
0.5
Vout 25C
0.0
-0.5
Vout 125C
TIME (50s/DIV)
C028
19
LP38798
SNOSCT6E MARCH 2013 REVISED SEPTEMBER 2016
www.ti.com
10 Layout
10.1 Layout Guidelines
The dynamic performance of the LP38798 is dependant on the layout of the PCB. PCB layout practices that are
adequate for typical LDOs may degrade the PSRR, noise, or transient performance of the LP38798.
Best performance is achieved by placing all of the components on the same side of the PCB as the LP38798,
and as close as is practical to the LP38798 package. All component ground connections must be back to the
LP38798 analog ground connection using as wide and short of a copper trace as is practical. The connection
from the FB pin to the VSET resistors must be as short as possible as the FB pin is a high impedance input. Any
trace length on the FB pin acts as an antenna.
Connections using long trace lengths, narrow trace widths; avoid connections through vias, which add parasitic
inductances and resistance that results in inferior performance especially during transient conditions.
A ground plane, either on the opposite side of a two-layer PCB, or embedded in a multi-layer PCB, is strongly
recommended. This Ground Plane serves two purposes :
1. Provides a circuit reference plane to assure accuracy, and
2. Provides a thermal plane to remove heat from the LP38798 through thermal vias under the package DAP.
CIN
COUT
GND
GND
VIN
VOUT
CCP
VEN
R1
R2
GND
GND
20
LP38798
www.ti.com
11.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.6 Glossary
SLYZ022 TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
21
www.ti.com
26-Aug-2016
PACKAGING INFORMATION
Orderable Device
Status
(1)
Eco Plan
Lead/Ball Finish
(2)
(6)
(3)
Op Temp (C)
Device Marking
(4/5)
LP38798SD-ADJ/NOPB
ACTIVE
WSON
DNT
12
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
L00075B
LP38798SDE-ADJ/NOPB
ACTIVE
WSON
DNT
12
250
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
L00075B
LP38798SDX-ADJ/NOPB
ACTIVE
WSON
DNT
12
4500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
L00075B
(1)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
Samples
www.ti.com
26-Aug-2016
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
26-Aug-2016
Device
LP38798SD-ADJ/NOPB
WSON
DNT
12
LP38798SDE-ADJ/NOPB
WSON
DNT
LP38798SDX-ADJ/NOPB
WSON
DNT
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
1000
178.0
12.4
4.3
4.3
1.3
8.0
12.0
Q1
12
250
178.0
12.4
4.3
4.3
1.3
8.0
12.0
Q1
12
4500
330.0
12.4
4.3
4.3
1.3
8.0
12.0
Q1
Pack Materials-Page 1
26-Aug-2016
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LP38798SD-ADJ/NOPB
WSON
DNT
12
1000
210.0
185.0
35.0
LP38798SDE-ADJ/NOPB
WSON
DNT
12
250
210.0
185.0
35.0
LP38798SDX-ADJ/NOPB
WSON
DNT
12
4500
367.0
367.0
35.0
Pack Materials-Page 2
MECHANICAL DATA
DNT0012B
SDA12B (Rev A)
4214928/A 03/2013
NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This package is designed to be soldered to a thermal pad on the board for thermal and mechanical performance.
For more information, refer to QFN/SON PCB application note in literature No. SLUA271 (www.ti.com/lit/slua271).
www.ti.com
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