Arithmetic logic unit

An arithmetic logic unit (ALU) is a digital electronic and match the native word size of the encapsulating CPU
circuit that performs arithmetic and bitwise logical op- (or other processor).
erations on integer binary numbers. This is in contrast
to a oating-point unit (FPU), which operates on oating
point numbers. An ALU is a fundamental building block 1.2 Opcode
of many types of computing circuits, including the central
processing unit (CPU) of computers, FPUs, and graphics The opcode input is a parallel bus that conveys to the
processing units (GPUs). A single CPU, FPU or GPU ALU an operation selection code, which is an enumer-
may contain multiple ALUs. ated value that species the desired arithmetic or logic
operation to be performed by the ALU. The opcode size
The inputs to an ALU are the data to be operated on, (its bus width) is related to the number of dierent oper-
called operands, and a code indicating the operation to ations the ALU can perform; for example, a four-bit op-
be performed; the ALUs output is the result of the code can specify up to sixteen dierent ALU operations.
performed operation. In many designs, the ALU also Generally, an ALU opcode is not the same as a machine
exchanges additional information with a status register, language opcode, though in some cases it may be directly
which relates to the result of the current or previous op- encoded as a bit eld within a machine language opcode.
erations.

1.3 Status
1 Signals
The status outputs are various individual signals that con-
vey supplemental information about the result of an ALU
operation. These outputs are usually stored in registers so
they can be used in future ALU operations or for control-
ling conditional branching. The collection of bit registers
that store the status outputs are often treated as a single,
multi-bit register, which is referred to as the status regis-
ter or condition code register. General-purpose ALUs
commonly have status signals such as:

Carry-out, which conveys the carry resulting from

an addition operation, the borrow resulting from a
A symbolic representation of an ALU and its input and output subtraction operation, or the overow bit resulting
signals, indicated by arrows pointing into or out of the ALU, re- from a binary shift operation.
spectively. Each arrow represents one or more signals.
Zero, which indicates all bits of the Y bus are logic
An ALU has a variety of input and output nets, which are zero.
the shared electrical connections used to convey digital Negative, which indicates the result of an arithmetic
signals between the ALU and external circuitry. When operation is negative.
an ALU is operating, external circuits apply signals to the
ALU inputs and, in response, the ALU produces and con- Overow, which indicates the result of an arithmetic
veys signals to external circuitry via its outputs. operation has exceeded the numeric range of the Y
bus.

1.1 Data Parity, which indicates whether an even or odd num-

ber of bits on the Y bus are logic one.
A basic ALU has three parallel data buses consisting of
two input operands (A and B) and a result output (Y). The status input allows additional information to be made
Each data bus is a group of signals that conveys one binary available to the ALU when performing an operation.
integer number. Typically, the A, B and Y bus widths Typically, this is a carry-in bit that is the stored carry-
(the number of signals comprising each bus) are identical out from a previous ALU operation.

1
2 3 FUNCTIONS

2 Circuit operation 3 Functions

A number of basic arithmetic and bitwise logic func-
tions are commonly supported by ALUs. Basic, general
purpose ALUs typically include these operations in their
repertoires:

3.1 Arithmetic operations

Add: A and B are summed and the sum appears at
Y and carry-out.

Add with carry: A, B and carry-in are summed and

the sum appears at Y and carry-out.

Subtract: B is subtracted from A (or vice-versa) and

the dierence appears at Y and carry-out. For this
function, carry-out is eectively a borrow indica-
tor. This operation may also be used to compare the
magnitudes of A and B; in such cases the Y output
The combinational logic circuitry of the 74181 integrated circuit, may be ignored by the processor, which is only in-
which is a simple four-bit ALU terested in the status bits (particularly zero and neg-
ative) that result from the operation.

Subtract with borrow: B is subtracted from A (or

vice-versa) with borrow (carry-in) and the dier-
An ALU is a combinational logic circuit, meaning that ence appears at Y and carry-out (borrow out).
its outputs will change asynchronously in response to in-
put changes. In normal operation, stable signals are ap- Twos complement (negate): A (or B) is subtracted
plied to all of the ALU inputs and, when enough time from zero and the dierence appears at Y.
(known as the "propagation delay") has passed for the sig-
nals to propagate through the ALU circuitry, the result of Increment: A (or B) is increased by one and the re-
the ALU operation appears at the ALU outputs. The ex- sulting value appears at Y.
ternal circuitry connected to the ALU is responsible for
Decrement: A (or B) is decreased by one and the
ensuring the stability of ALU input signals throughout the
resulting value appears at Y.
operation, and for allowing sucient time for the signals
to propagate through the ALU before sampling the ALU Pass through: all bits of A (or B) appear unmodied
result. at Y. This operation is typically used to determine
In general, external circuitry controls an ALU by apply- the parity of the operand or whether it is zero or
ing signals to its inputs. Typically, the external circuitry negative.
employs sequential logic to control the ALU operation,
which is paced by a clock signal of a suciently low fre-
quency to ensure enough time for the ALU outputs to set- 3.2 Bitwise logical operations
tle under worst-case conditions.
AND: the bitwise AND of A and B appears at Y.
For example, a CPU begins an ALU addition operation
by routing operands from their sources (which are usu- OR: the bitwise OR of A and B appears at Y.
ally registers) to the ALUs operand inputs, while the
Exclusive-OR: the bitwise XOR of A and B appears
control unit simultaneously applies a value to the ALUs
at Y.
opcode input, conguring it to perform addition. At the
same time, the CPU also routes the ALU result output Ones complement: all bits of A (or B) are inverted
to a destination register that will receive the sum. The and appear at Y.
ALUs input signals, which are held stable until the next
clock, are allowed to propagate through the ALU and to
the destination register while the CPU waits for the next 3.3 Bit shift operations
clock. When the next clock arrives, the destination reg-
ister stores the ALU result and, since the ALU operation ALU shift operations cause operand A (or B) to shift
has completed, the ALU inputs may be set up for the next left or right (depending on the opcode) and the shifted
ALU operation. operand appears at Y. Simple ALUs typically can shift
 3

the operand by only one bit position, whereas more com- 5 History
plex ALUs employ barrel shifters that allow them to shift
the operand by an arbitrary number of bits in one opera-
Mathematician John von Neumann proposed the ALU
tion. In all single-bit shift operations, the bit shifted out
concept in 1945 in a report on the foundations for a new
of the operand appears on carry-out; the value of the bit
computer called the EDVAC.[1]
shifted into the operand depends on the type of shift.
The cost, size, and power consumption of electronic cir-
cuitry was relatively high throughout the infancy of the
Arithmetic shift: the operand is treated as a twos
information age. Consequently, all serial computers and
complement integer, meaning that the most signi-
many early computers, such as the PDP-8, had a simple
cant bit is a sign bit and is preserved.
ALU that operated on one data bit at a time, although
Logical shift: a logic zero is shifted into the operand. they often presented a wider word size to programmers.
This is used to shift unsigned integers. One of the earliest computers to have multiple discrete
single-bit ALU circuits was the 1948 Whirlwind I, which
Rotate: the operand is treated as a circular buer of employed sixteen of such math units to enable it to op-
bits so its least and most signicant bits are eec- erate on 16-bit words.
tively adjacent.
In 1967, Fairchild introduced the rst ALU implemented
Rotate through carry: the carry bit and operand are as an integrated circuit, the Fairchild 3800, consisting of
collectively treated as a circular buer of bits. an eight-bit ALU with accumulator.[2] Other integrated-
circuit ALUs soon emerged, including four-bit ALUs
such as the Am2901 and 74181. These devices were typ-
ically "bit slice" capable, meaning they had carry look
4 Complex operations ahead signals that facilitated the use of multiple inter-
connected ALU chips to create an ALU with a wider
Although an ALU can be designed to perform complex word size. These devices quickly became popular and
functions, the resulting higher circuit complexity, cost, were widely used in bit-slice minicomputers.
power consumption and larger size makes this imprac-
tical in many cases. Consequently, ALUs are often lim- Microprocessors began to appear in the early 1970s.
ited to simple functions that can be executed at very high Even though transistors had become smaller, there was
speeds (i.e., very short propagation delays), and the ex- often insucient die space for a full-word-width ALU
ternal processor circuitry is responsible for performing and, as a result, some early microprocessors employed a
complex functions by orchestrating a sequence of simpler narrow ALU that required multiple cycles per machine
ALU operations. language instruction. Examples of this include the origi-
nal Motorola 68000, which performed a 32-bit add in-
For example, computing the square root of a number struction in two cycles with a 16-bit ALU, and the popu-
might be implemented in various ways, depending on lar Zilog Z80, which performed eight-bit additions with a
ALU complexity: four-bit ALU.[3] Over time, transistor geometries shrank
further, following Moores law, and it became feasible to
Calculation in a single clock: a very complex ALU build wider ALUs on microprocessors.
that calculates a square root in one operation. Modern integrated circuit (IC) transistors are orders of
Calculation pipeline: a group of simple ALUs that magnitude smaller than those of the early microproces-
calculates a square root in stages, with intermedi- sors, making it possible to t highly complex ALUs on
ate results passing through ALUs arranged like a ICs. Today, many modern ALUs have wide word widths,
factory production line. This circuit can accept and architectural enhancements such as barrel shifters
new operands before nishing the previous ones and and binary multipliers that allow them to perform, in a
produces results as fast as the very complex ALU, single clock cycle, operations that would have required
though the results are delayed by the sum of the multiple operations on earlier ALUs.
propagation delays of the ALU stages.

Iterative calculation: a simple ALU that calculates

the square root through several steps under the di- 6 See also
rection of a control unit.
Adder (electronics)
The implementations above transition from fastest and
most expensive to slowest and least costly. The square
root is calculated in all cases, but processors with simple Address generation unit (AGU)
ALUs will take longer to perform the calculation because
multiple ALU operations must be performed. Binary multiplier
4 8 EXTERNAL LINKS

7 References
[1] Philip Levis (November 8, 2004). Jonathan von Neu-
mann and EDVAC (PDF). cs.berkeley.edu. pp. 1, 3. Re-
trieved January 20, 2015.

[2] Lee Boysel (2007-10-12). Making Your First Million

(and other tips for aspiring entrepreneurs)". U. Mich.
EECS Presentation / ECE Recordings.

[3] Ken Shirri. The Z-80 has a 4-bit ALU. Heres how it
works. 2013.

Hwang, Enoch (2006). Digital Logic and Micropro-

cessor Design with VHDL. Thomson. ISBN 0-534-
46593-5.

Stallings, William (2006). Computer Organization

& Architecture: Designing for Performance (7th
ed.). Pearson Prentice Hall. ISBN 0-13-185644-8.

8 External links
ALU and its Micro-operations: Bitwise, Arithmetic
and Shift
A Simulator of Complex ALU in MATLAB
 5

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