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 L4970A

10A SWITCHING REGULATOR

10A OUTPUT CURRENT

5.1V TO 40V OUTPUT VOLTAGE RANGE MULTIPOWER BCD TECHNOLOGY
0 TO 90% DUTY CYCLE RANGE
INTERNAL FEED-FORWARD LINE REGULA-
TION
INTERNAL CURRENT LIMITING
PRECISE 5.1V ± 2% ON CHIP REFERENCE
RESET AND POWER FAIL FUNCTIONS
SOFT START
INPUT/OUTPUT SYNC PIN Multiwatt15V
UNDER VOLTAGE LOCK OUT WITH HYS- ORDERING NUMBER: L4970A
TERETIC TURN-ON
PWM LATCH FOR SINGLE PULSE PER PE-
RIOD
VERY HIGH EFFICIENCY Realized with BCD mixed technology, the device
uses a DMOS output transistor to obtain very high
SWITCHING FREQUENCY UP TO 500KHz efficiency and very fast switching times. Features
THERMAL SHUTDOWN of the L4970A include reset and power fail for mi-
CONTINUOUS MODE OPERATION croprocessors, feed forward line regulation, soft
start, limiting current and thermal protection. The
device is mounted in a 15-lead multiwatt plastic
DESCRIPTION power package and requires few external compo-
The L4970A is a stepdown monolithic power nents. Efficient operation at switching frequencies
switching regulator delivering 10A at a voltage up to 500KHz allows reduction in the size and
variable from 5.1 to 40V. cost of external filter components.
BLOCK DIAGRAM

November 1991 1/21

This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
L4970A

ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Value Unit
V9 Input Voltage 55 V
V9 Input Operating Voltage 50 V
V7 Output DC Voltage -1 V
Output Peak Voltage at t = 0.1µs f = 200KHz -7 V
I7 Maximum Output Current Internally Limited
V6 Bootstrap Voltage 65 V
Bootstrap Operating Voltage V9 + 15 V
V3, V12 Input Voltage at Pins 3, 12 12 V
V4 Reset Output Voltage 50 V
I4 Reset Output Sink Current 50 mA
V5, V10, V11, V13 Input Voltage at Pin 5, 10, 11, 13 7 V
I5 Reset Delay Sink Current 30 mA
I10 Error Amplifier Output Sink Current 1 A
I12 Soft Start Sink Current 30 mA
Ptot Total Power Dissipation at Tcase < 120°C 30 W
Tj, Tstg Junction and Storage Temperature -40 to 150 °C

PIN CONNECTION (Top view)

THERMAL DATA
Symbol Parameter Value Unit
Rth j-case Thermal Resistance Junction-case max 1 °C/W
R th j-amb Thermal Resistance Junction-ambient max 35 °C/W

2/21
 L4970A

PIN FUNCTIONS
o
N Name Function
1 OSCILLATOR Rosc. External resistor connected to ground determines the constant charging
current of C osc.
2 OSCILLATOR Cosc. External capacitor connected to ground determines (with R osc) the
switching frequency.
3 RESET INPUT Input of Power Fail Circuit. The threshold is 5.1V. It may be connected via a
divider to the input for power fail function. It must be connected to the pin 14 an
external 30KΩ resistor when power fail signal not required.
4 RESET OUT Open Collector Reset/power Fail Signal Output. This output is high when the
supply and the output voltages are safe.
5 RESET DELAY A C d capacitor connected between this terminal and ground determines the
reset signal delay time.
6 BOOTSTR AP A C boot capacitor connected between this terminal and the output allows to
drive properly the internal D-MOS transistor.
7 OUTPUT Regulator Output.
8 GROUND Common Ground Terminal
9 SUPPLY VOLTAGE Unregulated Input Voltage.
10 FREQUENCY A series RC network connected between this terminal and ground determines
COMPENSATION the regulation loop gain characteristics.
11 FEEDBACK INPUT The Feedback Terminal of the Regulation Loop. The output is connected
directly to this terminal for 5.1V operation; It is connected via a divider for higher
voltages.
12 SOFT START Soft Start Time Constant. A capacitor is connected between thi sterminal and
ground to define the soft start time constant.
13 SYNC INPUT Multiple L4970A are synchronized by connecting pin 13 inputs together or via
an external syncr. pulse.
14 Vref 5.1V Vref Device Reference Voltage.
15 Vstart Internal Start-up Circuit to Drive the Power Stage.

CIRCUIT OPERATION (refer to the block dia- Device turn on is around 11V with a typical 1V
gram) hysteresis, this threshold provides a correct volt-
The L4970A is a 10A monolithic stepdown switching age for the driving stage of the DMOS gate and
regulator working in continuous mode realized in the the hysteresis prevents instabilities.
new BCD Technology. This technology allows the in- An external bootstrap capacitor charged to 12V
tegration of isolated vertical DMOS power transistors by an internal voltage reference is needed to pro-
plus mixed CMOS/Bipolar transistors. vide correct gate drive to the power DMOS. The
The device can deliver 10A at an output voltage driving circuit is able to source and sink peak cur-
adjustable from 5.1V to 40V, and contains diag- rents of around 0.5A to the gate of the DMOS
nostic and control functions that make it particu- transistor. A typical switching time of the current
larly suitable for microprocessor based systems. in the DMOS transistor is 50ns. Due to the fast
commutation switching frequencies up to 500kHz
are possible.
BLOCK DIAGRAM The PWM control loop consists of a sawtooth os-
The block diagram shows the DMOS power tran- cillator, error amplifier, comparator, latch and the
sistor and the PWM control loop. Integrated func- output stage. An error signal is produced by com-
tions include a reference voltage trimmed to 5.1V paring the output voltage with the precise 5.1V ±
± 2%, soft start, undervoltage lockout, oscillator 2% on chip reference. This error signal is then
with feedforward control, pulse by pulse current compared with the sawtooth oscillator, in order to
limit, thermal shutdown and finally the reset and generate a fixed frequency pulse width modulated
power fail circuit. The reset and power fail circuit drive for the output stage. A PWM latch is in-
provides an output signal for a microprocessor in- cluded to eliminate multiple pulsing within a pe-
dicating the status of the system. riod even in noisy environments. The gain and
3/21
L4970A

Figure 1: Feedforward Waveform

Figure 2: Soft Start Function

Figure 3: Limiting Current Function

4/21
 L4970A

stability of the loop can be adjusted by an exter- a constant current output when the system is
nal RC network connected to the output of the er- overloaded or short circuited and limits the
ror amplifier. A voltage feedforward control has switching frequency, in this condition, to 40kHz.
been added to the oscillator, this maintains supe- The Reset and Power fail circuitry (fig 4) gener-
rior line regulation over a wide input voltage ates an output signal when the supply voltage ex-
range. Closing the loop directly gives an output ceeds a threshold programmed by an external
voltage of 5.1V, higher voltages are obtained by voltage divider. The reset signal, is generated
inserting a voltage divider. with a delay time programmed by an external ca-
At turn on output overcurrents are prevented by pacitor on the delay pin. When the supply voltage
the soft start function (fig. 2). The error amplifier is falls below the threshold or the output voltage
initially clamped by an external capacitor Css and goes below 5V the reset output goes low immedi-
allowed to rise linearly under the charge of an in- ately. The reset output is an open collector-drain.
ternal constant current source. Fig 4A shows the case when the supply voltage is
Output overload protection is provided by a cur- higher than the threshold, but the output voltage
rent limit circuit (fig. 3). The load current is sensed is not yet 5V.
by an internal metal resistor connected to a com- Fig 4B shows the case when the output is 5.1V
parator. When the load current exceeds a preset but the supply voltage is not yet higher than the
threshold the output of the comparator sets a flip fixed threshold.
flop which turns off the power DMOS. The next
clock pulse, from an internal 40kHz oscillator will The thermal protection disables circuit operation
reset the flip flop and the power DMOS will again when the junction temperature reaches about
conduct. This current protection method, ensures 150°C and has an hysterysis to prevent unstable
conditions.
Figure 4: Reset and Power Fail Functions.

5/21
L4970A

ELECTRICAL CHARACTERISTICS (Refer to the test circuit, Tj = 25°C, Vi = 35V, R4 = 16KΩ,

C9 = 2.2nF, fSW = 200KHz typ, unless otherwise specified)
DYNAMIC CHARACTERISTICS
Symbol Parameter Test Condition Min. Typ. Max. Unit Fig.
Vi input Voltage Range (pin 9) Vo = Vref to 40V 15 50 V 5
Io = 10A
Vo Output Votage Vi = 15V to 50V 5 5.1 5.2 V 5
Io = 5A; Vo = Vref
∆Vo Line Regulation Vi = 15V to 50V 12 30 mV 5
Io = 5A; Vo = Vref
∆Vo Load Regulation Vo = Vref 5
Io = 3A to 6A 10 30 mV
Io = 2A to 10A 20 50 mV
Vd Dropout Voltage Between Io = 5A 0.55 0.8 V 5
Pin 9 and 7 Io = 10A 1.1 1.6 V
I7L Max. Limiting Current Vi = 15 to 50V 11 13 15 A 5
η Efficiency Io = 5A 5
Vo = Vref 80 85 %
Vo = 12V 92 %
Io = 10A 5
Vo = Vref 75 80 %
Vo = 12V 87 %
SVR Supply Voltage Ripple Vi = 2VRMS; Io = 5A 56 60 dB 5
Reject. f = 100Hz; Vo = Vref
f Switching Frequency 180 200 220 KHz 5
∆f Voltage Stability of Vi = 15V to 45V 2 6 % 5
∆ Vi Swiching Frequency
∆f Temperature Stability of T j = 0 to 125°C 1 % 5
Tj Swiching Frequency
fmax Maximum Operating Vo = Vref; R4 = 10KΩ 500 KHz 5
Switching Frequency Io = 10A; C9 = 1nF
Vref SECTION (pin 14)
Symbol Parameter Test Condition Min. Typ. Max. Unit Fig.
V14 Reference Voltage 5 5.1 5.2 V 7
∆V14 Line Regulation Vi = 15V to 50V 10 25 mV 7
∆V14 Load Regulation I14 = 0 to 1mA 20 40 mV 7
∆ V14 Average Temperature T j = 0°C to 125°C 0.4 mV/°C 7
∆T Coefficient Reference
Voltage
I14 sho rt Short Circuit Current Limit V14 = 0 70 mA 7
VSTART SECTION (pin 15)
Symbol Parameter Test Condition Min. Typ. Max. Unit Fig.
V15 Reference Voltage 11.4 12 12.6 V 7
∆V15 Line Regulation Vi = 15 to 50V 0.6 1.4 V 7
∆V15 Load Regulation I15 = 0 to 1mA 50 200 mV 7
I15 sho rt Short Circuit Current Limit V15 = 0V 80 mA 7

6/21
 L4970A

ELECTRICAL CHARACTERISTICS (continued)

DC CHARACTERISTICS
Symbol Parameter Test Condition Min. Typ. Max. Unit Fig.
V9on Turn-on Threshold 10 11 12 V 7A
V9 Hyst Turn-off Hysteresys 1 V 7A
I9Q Quiescent Current V12 = 0; S1 = D 13 19 mA 7A
I9OQ Operating Supply Current V12 = 0; S1 = C; S2 = B 16 23 mA 7A
I7L Out Leak Current Vi = 55V; S3 = A; V12 = 0 2 mA 7A
SOFT START
Symbol Parameter Test Condition Min. Typ. Max. Unit Fig.
I12 Soft Start Source Current V12 = 3V; V11 = 0V 70 100 130 µA 7B
V12 Output Saturation Voltage I12 = 20mA; V9 = 10V 1 V 7B
I12 = 200µA; V9 = 10V 0.7 V 7B
ERROR AMPLIFIER
Symbol Parameter Test Condition Min. Typ. Max. Unit Fig.
V10H High Level Out Voltage I10 = -100µA; S1 = C 6 V 7C
V11 = 4.7V
V10L Low Level Out Voltage I10 = +100µA; S1 = C 1.2 V 7C
V11 = 5.3V;
I10H Source Output Current V10 = 1V; S1 = E 100 150 µA 7C
V11 = 4.7V
I10L Sink Output Current V10 = 6V; S1 = D 100 150 µA 7C
V11 = 5.3V
I11 Input Bias Current R S = 10KΩ 0.4 3 µA –
GV DC Open Loop Gain VVCM = 4V; 60 dB –
R S = 10Ω
SVR Supply Voltage Rejection 15 < Vi < 50V; 60 80 dB –
R S = 10Ω
VOS Input Offset Voltage R S = 50Ω 2 10 mV –
RAMP GENERATOR (pin 2)
Symbol Parameter Test Condition Min. Typ. Max. Unit Fig.
V2 Ramp Valley S1 = C; S2 = B 1.2 1.5 V 7A
V2 Ramp Peak S1 = C; Vi = 15V 2.5 V 7A
S2 = B; Vi = 45V 5.5 V 7A
I2 Min. Ramp Current S1 = A; I1 = 100µA 270 300 µA 7A
I2 Max. Ramp Current S1 = A; I1 = 1mA 2.4 2.7 mA 7A
SYNC FUNCTION (pin 13)
Symbol Parameter Test Condition Min. Typ. Max. Unit Fig.
V13 Low Input Voltage Vi = 15V to 50V; V12 = 0; –0.3 0.9 V 7A
S1 = C; S2 = B; S4 = B
V13 High Input voltage V12 = 0; 3.5 5.5 V 7A
S1 = C; S2 = B; S4 = B
I13L Sync Input Current with V13 = V2 = 0.9V; S4 = A; 0.4 mA 7A
Low Input Voltage S1 = C; S2 = B
I13H Input Current with High V13 = 3.5V; S4 = A; 1.5 mA 7A
Input Voltage S1 = C; S2 = B
V13 Output Amplitude 4 5 V –
tW Output Pulse Width Vthr = 2.5V 0.3 0.5 0.8 µs –

7/21
L4970A

ELECTRICAL CHARACTERISTICS (continued)

RESET AND POWER FAIL FUNCTIONS
Symbol Parameter Test Condition Min. Typ. Max. Unit Fig.
V11R Rising Threshold Voltage Vi = 15 to 50V Vref Vref Vref V 7D
(pin 11) V3 = 5.3V –120 –100 –80 mV
V11F Falling Threshold Voltage Vi = 15 to 50V 4.77 Vref Vref V 7D
(pin 11) V3 = 5.3V –200 –160 mV
V5H Delay High Threshold Vi = 15 to 50V 4.95 5.1 5.25 V 7D
Voltage V14 = V11 V3 = 5.3V
V5L Delay Low Threshold Vi = 15 to 50V 1 1.1 1.2 V 7D
Voltage V14 = V11 V3 = 5.3V
–I5SO Delay Source Current V3 = 5.3V; V5 = 3V 40 60 80 µA 7D
I5SI Delay Sink Current V3 = 4.7V; V5 = 3V 10 mA 7D
V4S Out Saturation Voltage I4 = 15mA; S1 = B 0.4 V 7D
V3 = 4.7V
I4 Output Leak Current V4 = 50V; S1 = A 100 µA 7D
V3 = 5.3V
V3R Rising Threshold Voltage V11 = V14 4.95 5.1 5.25 V 7D
V3H Hysteresys 0.4 0.5 0.6 V 7D
I3 Input Bias Current 1 3 µA 7D

Figure 5: Test and Evaluation Board Circuit

TYPICAL PERFORMANCES (using evaluation board) :

n = 83% (Vi = 35V ; Vo = VREF ; Io = 10A ; fSW = 200KHz)
Vo RIPPLE = 30mV (at 10A) with output filter capacitor ESR ≤ 60mΩ
Line regulation = 5mV (Vi = 15 to 50V)
Load regulation = 15mV (Io = 2 to 10A)
For component values, refer to test circuit part list.

8/21
 L4970A

Figure 6a: P.C. Board (components side) and Components Layout of Figure 5 (1:1 scale).

PARTS LIST
Table A
R1 = 30KΩ C 1, C2 = 3300µF 63VL EYF (ROE
V0 R9 R7
R2 = 10KΩ C 3, C4, C5, C6 = 2.2µF
12V 4.7kΩ 6.2kW
R3 = 15KΩ C 7 = 390pF Film 15V 4.7kΩ 9.1kΩ
R4 = 16KΩ C 8 = 22nF MKT 1817 (ERO) 18V 4.7kΩ 12kΩ
R5 = 22Ω 0,5W 24V 4.7kΩ 18kΩ

R6 = 4K7 C 9 = 2.2nF KP1830

R7 = 10Ω C 10 = 220nF MKT
R8 = see tab. A C 11 = 2.2nF MP1830
R9 = OPTION **C12 , C13, C14 = 220µF 40VL EKR Table B
SUGGESTED BOOTSTRAP CAPACITORS
R10 = 4K7 C 15 = 1µF Film
R11 = 10Ω Operating Frequency Bootstrap Cap.c10
D1 = MBR 1560CT (or 16A/60V or equivalent) f = 20KHz ≥680nF
L1 = 40µH core 58071 MAGNETICS f = 50KHz ≥470nF
27 TURNS Ø 1,3mm (AWG 16) f = 100KHz ≥330nF
COGEMA 949178
f = 200KHz ≥220nF
* 2 capacitors in parallel to increase input RMS current capability f = 500KHz ≥100nF
** 3 capacitors in parallel to reduce total output ESR

9/21
L4970A

Figure 6b: P.C. Board (Back side) and Components Layout of the Circuit of Fig. 5. (1:1 scale)

Figure 7: DC Test Circuits

10/21
 L4970A

Figure 7A

Figure 7B

11/21
L4970A

Figure 7D

Figure 7C

12/21
 L4970A

Figure 8: Quiescent Drain Current vs. Supply Figure 9: Quiescent Drain Current vs. Junction
Voltage (0% duty cycle - see fig. 7A). Temperature (0% duty cycle).

Figure 10: Quiescent Drain Current vs. Duty Figure 11: Reference Voltage (pin14) vs. Vi (see
Cycle fig. 7)

Figure 12: Reference Voltage (pin 14) vs. Figure 13: Reference Voltage (pin15) vs. Vi (see
Junction Temperature (see fig. 7) fig. 7)

13/21
L4970A

Figure 14: Reference Voltage (pin 15) vs. Figure 15: Reference Voltage 5.1V (pin 14)
Junction Temperature (see fig. 7) Supply Voltage Ripple Rejection vs.
Frequency

Figure 16: Switching Frequency vs. Input Figure 17: Switching Frequency vs. Junction
Voltage (see fig. 5) Temperature (see fig 5)

Figure 18: Switching Frequency vs. R4 (see fig. 5) Figure 19: Max. Duty Cycle vs. Frequency

14/21
 L4970A

Figure 20: Supply Voltage Ripple Rejection vs. Figure 21: Line Transient Response (see fig. 5)
Frequency (see fig. 5)

Figure 22: Load Transient Response (see fig. 5) Figure 23: Dropout Voltage Between Pin 9 and
Pin 7 vs. Current at Pin 7

Figure 24: Dropout Voltage Between Pin 9 and Figure 25: Power Dissipation (device only) vs.
Pin 7 vs. Junction Temperature Input Voltage

15/21
L4970A

Figure 26: Power Dissipation (device only) vs. Figure 27: Heatsink Used to Derive the Device’s
Output Voltage Power Dissipation
Tcase − Tamb
Rth - Heatsink =
Pd

Figure 28: Efficiency vs. Output Current

Figure 29: Efficiency vs. Output Voltage

Figure 30: Efficiency vs. Output Voltage Figure 31: Open Loop Frequency and Phase
Response of Error Amplifier (see
fig.7C)

16/21
 L4970A

Figure 32: Power Dissipation Derating Curve

Figure 33: A5.1V/12V Multiple Supply. Note the Synchronization between the L4970A and the L4974A

17/21
L4970A

Figure 34: 5.1V / 10A Low Cost Application

Figure 35: 10A Switching Regulator, Adjustable from 0V to 25V.

18/21
 L4970A

Figure 36: L4970A’sSync. Example

19/21
L4970A

MULTIWATT15 PACKAGE MECHANICAL DATA

mm inch
DIM.
MIN. TYP. MAX. MIN. TYP. MAX.
A 5 0.197
B 2.65 0.104
C 1.6 0.063
D 1 0.039
E 0.49 0.55 0.019 0.022
F 0.66 0.75 0.026 0.030
G 1.14 1.27 1.4 0.045 0.050 0.055
G1 17.57 17.78 17.91 0.692 0.700 0.705
H1 19.6 0.772
H2 20.2 0.795
L 22.1 22.6 0.870 0.890
L1 22 22.5 0.866 0.886
L2 17.65 18.1 0.695 0.713
L3 17.25 17.5 17.75 0.679 0.689 0.699
L4 10.3 10.7 10.9 0.406 0.421 0.429
L7 2.65 2.9 0.104 0.114
M 4.2 4.3 4.6 0.165 0.169 0.181
M1 4.5 5.08 5.3 0.177 0.200 0.209
S 1.9 2.6 0.075 0.102
S1 1.9 2.6 0.075 0.102
Dia1 3.65 3.85 0.144 0.152

20/21
 L4970A

Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No
license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications men-
tioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied.
SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without ex-
press written approval of SGS-THOMSON Microelectronics.

 1994 SGS-THOMSON Microelectronics - All Rights Reserved

MULTIWATT  is a Registered Trademark of SGS-THOMSON Microelectronics

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