M24256

M24128
256/128 Kbit Serial I²C Bus EEPROM
Without Chip Enable Lines
PRELIMINARY DATA

■ Compatible with I2C Extended Addressing

■ Two Wire I2C Serial Interface
Supports 400 kHz Protocol
■ Single Supply Voltage:
– 4.5V to 5.5V for M24xxx 8
– 2.5V to 5.5V for M24xxx-W
■ Hardware Write Control 1
■ BYTE and PAGE WRITE (up to 64 Bytes)
PSDIP8 (BN)
■ RANDOM and SEQUENTIAL READ Modes 0.25 mm frame
■ Self-Timed Programming Cycle
■ Automatic Address Incrementing
■ Enhanced ESD/Latch-Up Behavior
8 8
■ 100,000 Erase/Write Cycles (minimum)
■ 40 Year Data Retention (minimum) 1 1
SO8 (MN) SO8 (MW)
DESCRIPTION 150 mil width 200 mil width
These I 2C-compatible electrically erasable pro-
grammable memory (EEPROM) devices are orga-
nized as 32Kx8 bits (M24256) and 16Kx8 bits
(M24128), and operate down to 2.5 V (for the -W
version of each device).
The M24256 and M24128 are available in Plastic Figure 1. Logic Diagram
Dual-in-Line and Plastic Small Outline packages.
These memory devices are compatible with the
I2C extended memory standard. This is a two wire
serial interface that uses a bi-directional data bus VCC
and serial clock. The memory carries a built-in 4-
bit unique Device Type Identifier code (1010) in
accordance with the I2C bus definition.
SCL SDA
M24256
Table 1. Signal Names M24128
WC
SDA Serial Data/Address Input/
Output

SCL Serial Clock

WC Write Control VSS

AI01882
VCC Supply Voltage

VSS Ground

November 1999 1/16

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
M24256, M24128

Figure 2A. DIP Connections Figure 2B. SO Connections

M24256 M24256
M24128 M24128

NC 1 8 VCC NC 1 8 VCC
NC 2 7 WC NC 2 7 WC
NC 3 6 SCL NC 3 6 SCL
VSS 4 5 SDA VSS 4 5 SDA
AI01883 AI01884

Note: 1. NC = Not Connected Note: 1. NC = Not Connected

The memory behaves as a slave device in the I2C held active until the V CC voltage has reached the
protocol, with all memory operations synchronized POR threshold value, and all operations are dis-
by the serial clock. Read and Write operations are abled – the device will not respond to any com-
initiated by a START condition, generated by the mand. In the same way, when VCC drops from the
bus master. The START condition is followed by a operating voltage, below the POR threshold value,
Device Select Code and RW bit (as described in all operations are disabled and the device will not
Table 3), terminated by an acknowledge bit. respond to any command. A stable and valid V CC
When writing data to the memory, the memory in- must be applied before applying any logic signal.
serts an acknowledge bit during the 9th bit time,
following the bus master’s 8-bit transmission. SIGNAL DESCRIPTION
When data is read by the bus master, the bus Serial Clock (SCL)
master acknowledges the receipt of the data byte The SCL input pin is used to strobe all data in and
in the same way. Data transfers are terminated by out of the memory. In applications where this line
a STOP condition after an Ack for WRITE, and af- is used by slaves to synchronize the bus to a slow-
ter a NoAck for READ. er clock, the master must have an open drain out-
Power On Reset: V CC Lock-Out Write Protect put, and a pull-up resistor must be connected from
In order to prevent data corruption and inadvertent the SCL line to V CC. (Figure 3 indicates how the
write operations during power up, a Power On Re- value of the pull-up resistor can be calculated). In
set (POR) circuit is included. The internal reset is most applications, though, this method of synchro-
nization is not employed, and so the pull-up resis-

Table 2. Absolute Maximum Ratings 1

Symbol Parameter Value Unit
TA Ambient Operating Temperature –40 to 125 °C
TSTG Storage Temperature –65 to 150 °C
PSDIP8: 10 sec 260
TLEAD Lead Temperature during Soldering °C
SO8: 40 sec 215
VIO Input or Output range –0.6 to 6.5 V
VCC Supply Voltage –0.3 to 6.5 V

VESD Electrostatic Discharge Voltage (Human Body model) 2 4000 V

Note: 1. Except for the rating “Operating Temperature Range”, stresses above those listed in the Table “Absolute Maximum Ratings” may
cause permanent damage to the device. These are stress ratings only, and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-
tions for extended periods may affect device reliability. Refer also to the ST SURE Program and other relevant quality documents.
2. MIL-STD-883C, 3015.7 (100 pF, 1500 Ω)

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 M24256, M24128

tor is not necessary, provided that the master has device is always a slave device in all communica-
a push-pull (rather than open drain) output. tion.
Serial Data (SDA) Start Condition
The SDA pin is bi-directional, and is used to trans- START is identified by a high to low transition of
fer data in or out of the memory. It is an open drain the SDA line while the clock, SCL, is stable in the
output that may be wire-OR’ed with other open high state. A START condition must precede any
drain or open collector signals on the bus. A pull data transfer command. The memory device con-
up resistor must be connected from the SDA bus tinuously monitors (except during a programming
to VCC. (Figure 3 indicates how the value of the cycle) the SDA and SCL lines for a START condi-
pull-up resistor can be calculated). tion, and will not respond unless one is given.
Write Control (WC) Stop Condition
The hardware Write Control pin (WC) is useful for STOP is identified by a low to high transition of the
protecting the entire contents of the memory from SDA line while the clock SCL is stable in the high
inadvertent erase/write. The Write Control signal is state. A STOP condition terminates communica-
used to enable (WC=VIL) or disable (WC=V IH) tion between the memory device and the bus mas-
write instructions to the entire memory area. When ter. A STOP condition at the end of a Read
unconnected, the WC input is internally read as command, after (and only after) a NoAck, forces
VIL, and write operations are allowed. the memory device into its standby state. A STOP
When WC=1, Device Select and Address bytes condition at the end of a Write command triggers
are acknowledged, Data bytes are not acknowl- the internal EEPROM write cycle.
edged. Acknowledge Bit (ACK)
Please see the Application Note AN404 for a more An acknowledge signal is used to indicate a suc-
detailed description of the Write Control feature. cessful byte transfer. The bus transmitter, whether
it be master or slave, releases the SDA bus after
DEVICE OPERATION sending eight bits of data. During the 9th clock
The memory device supports the I2C protocol. pulse period, the receiver pulls the SDA bus low to
This is summarized in Figure 4, and is compared acknowledge the receipt of the eight data bits.
with other serial bus protocols in Application Note Data Input
AN1001. Any device that sends data on to the bus During data input, the memory device samples the
is defined to be a transmitter, and any device that SDA bus signal on the rising edge of the clock,
reads the data to be a receiver. The device that SCL. For correct device operation, the SDA signal
controls the data transfer is known as the master, must be stable during the clock low-to-high transi-
and the other as the slave. A data transfer can only tion, and the data must change only when the SCL
be initiated by the master, which will also provide line is low.
the serial clock for synchronization. The memory

Figure 3. Maximum R L Value versus Bus Capacitance (CBUS) for an I2C Bus

VCC
20
Maximum RP value (kΩ)

16
RL RL
12
SDA

8 MASTER CBUS
fc = 100kHz SCL

4
fc = 400kHz CBUS

0
10 100 1000
CBUS (pF)
AI01665

3/16
M24256, M24128

Figure 4. I2C Bus Protocol

SCL

SDA

START SDA SDA STOP

CONDITION INPUT CHANGE CONDITION

SCL 1 2 3 7 8 9

SDA MSB ACK

START
CONDITION

SCL 1 2 3 7 8 9

SDA MSB ACK

STOP
CONDITION

AI00792

Memory Addressing To address the memory array, the 4-bit Device

To start communication between the bus master Type Identifier is 1010b.
and the slave memory, the master must initiate a The 8th bit is the RW bit. This is set to ‘1’ for read
START condition. Following this, the master sends and ‘0’ for write operations. If a match occurs on
the 8-bit byte, shown in Table 3, on the SDA bus the Device Select Code, the corresponding mem-
line (most significant bit first). This consists of the ory gives an acknowledgment on the SDA bus dur-
7-bit Device Select Code, and the 1-bit Read/Write ing the 9th bit time. If the memory does not match
Designator (RW). The Device Select Code is fur- the Device Select Code, it deselects itself from the
ther subdivided into: a 4-bit Device Type Identifier, bus, and goes into stand-by mode.
and a 3-bit Chip Enable “Address” (0, 0, 0). There are two modes both for read and write.
These are summarized in Table 4 and described

Table 3. Device Select Code 1

Device Type Identifier Chip Enable RW
b7 b6 b5 b4 b3 b2 b1 b0
Device Select Code 1 0 1 0 0 0 0 RW
Note: 1. The most significant bit, b7, is sent first.

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 M24256, M24128

Table 4. Operating Modes

Mode RW bit WC 1 Data Bytes Initial Sequence

Current Address Read 1 X 1 START, Device Select, RW = ‘1’

0 X START, Device Select, RW = ‘0’, Address
Random Address Read 1
1 X reSTART, Device Select, RW = ‘1’
Sequential Read 1 X ≥1 Similar to Current or Random Address Read
Byte Write 0 VIL 1 START, Device Select, RW = ‘0’
Page Write 0 VIL ≤ 64 START, Device Select, RW = ‘0’
Note: 1. X = VIH or VIL.

later. A communication between the master and the byte in memory. Bit b15 is treated as a Don’t
the slave is ended with a STOP condition. Care bit on the M24256 memory. Bits b15 and b14
Each data byte in the memory has a 16-bit (two are treated as Don’t Care bits on the M24128
byte wide) address. The Most Significant Byte (Ta- memory.
ble 5) is sent first, followed by the Least significant
Byte (Table 6). Bits b15 to b0 form the address of

Figure 5. Write Mode Sequences with WC=1 (data write inhibited)

WC

ACK ACK ACK NO ACK

BYTE WRITE DEV SEL BYTE ADDR BYTE ADDR DATA IN

START

STOP

R/W

WC

ACK ACK ACK NO ACK

PAGE WRITE DEV SEL BYTE ADDR BYTE ADDR DATA IN 1 DATA IN 2
START

R/W

WC (cont'd)

NO ACK NO ACK

PAGE WRITE DATA IN N

(cont'd)
STOP

AI01120B

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M24256, M24128

Figure 6. Write Mode Sequences with WC=0 (data write enabled)

WC

ACK ACK ACK ACK

BYTE WRITE DEV SEL BYTE ADDR BYTE ADDR DATA IN

START

STOP
R/W

WC

ACK ACK ACK ACK

PAGE WRITE DEV SEL BYTE ADDR BYTE ADDR DATA IN 1 DATA IN 2
START

R/W

WC (cont'd)

ACK ACK

PAGE WRITE DATA IN N

(cont'd)
STOP

AI01106B

Table 5. Most Significant Byte condition until the end of the two address bytes)
b15 b14 b13 b12 b11 b10 b9 b8 will not modify the memory contents, and the ac-
Note: 1. b15 is treated as Don’t Care on the M24256 series.
companying data bytes will not be acknowledged,
b15 and b14 are Don’t Care on the M24128 series. as shown in Figure 5.
Byte Write
Table 6. Least Significant Byte In the Byte Write mode, after the Device Select
Code and the address bytes, the master sends
b7 b6 b5 b4 b3 b2 b1 b0
one data byte. If the addressed location is write
protected by the WC pin, the memory replies with
a NoAck, and the location is not modified. If, in-
Write Operations stead, the WC pin has been held at 0, as shown in
Following a START condition the master sends a Figure 6, the memory replies with an Ack. The
Device Select Code with the RW bit set to ’0’, as master terminates the transfer by generating a
shown in Table 4. The memory acknowledges this, STOP condition.
and waits for two address bytes. The memory re- Page Write
sponds to each address byte with an acknowledge The Page Write mode allows up to 64 bytes to be
bit, and then waits for the data byte. written in a single write cycle, provided that they
Writing to the memory may be inhibited if the WC are all located in the same ’row’ in the memory:
input pin is taken high. Any write command with that is the most significant memory address bits
WC=1 (during a period of time from the START (b14-b6 for the M24256 and b13-b6 for the
M24128) are the same. If more bytes are sent than

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 M24256, M24128

Figure 7. Write Cycle Polling Flowchart using ACK

WRITE Cycle
in Progress

START Condition

DEVICE SELECT
with RW = 0

NO ACK
Returned

First byte of instruction YES

with RW = 0 already
decoded by M24xxx

Next
NO Operation is YES
Addressing the
Memory
Send
Byte Address
ReSTART

STOP

Proceed Proceed
WRITE Operation Random Address
READ Operation

AI01847

will fit up to the end of the row, a condition known During the internal write cycle, the SDA input is
as ‘roll-over’ occurs. Data starts to become over- disabled internally, and the device does not re-
written (in a way not formally specified in this data spond to any requests.
sheet).
The master sends from one up to 64 bytes of data, Minimizing System Delays by Polling On ACK
each of which is acknowledged by the memory if
During the internal write cycle, the memory discon-
the WC pin is low. If the WC pin is high, the con-
tents of the addressed memory location are not nects itself from the bus, and copies the data from
its internal latches to the memory cells. The maxi-
modified, and each data byte is followed by a
mum write time (t w) is shown in Table 10, but the
NoAck. After each byte is transferred, the internal
byte address counter (the 6 least significant bits typical time is shorter. To make use of this, an Ack
only) is incremented. The transfer is terminated by polling sequence can be used by the master.
the master generating a STOP condition. The sequence, as shown in Figure 7, is:
When the master generates a STOP condition im- – Initial condition: a Write is in progress.
mediately after the Ack bit (in the “10th bit” time – Step 1: the master issues a START condition
slot), either at the end of a byte write or a page followed by a Device Select Code (the first byte
write, the internal memory write cycle is triggered. of the new instruction).
A STOP condition at any other time does not trig- – Step 2: if the memory is busy with the internal
ger the internal write cycle. write cycle, no Ack will be returned and the mas-
ter goes back to Step 1. If the memory has ter-

7/16
M24256, M24128

Figure 8. Read Mode Sequences

ACK NO ACK
CURRENT
ADDRESS DEV SEL DATA OUT
READ
START

STOP
R/W

ACK ACK ACK ACK NO ACK

RANDOM
ADDRESS DEV SEL * BYTE ADDR BYTE ADDR DEV SEL * DATA OUT
READ
START

START

STOP
R/W R/W

ACK ACK ACK NO ACK

SEQUENTIAL
CURRENT DEV SEL DATA OUT 1 DATA OUT N
READ
START

STOP
R/W

ACK ACK ACK ACK ACK

SEQUENTIAL
RANDOM DEV SEL * BYTE ADDR BYTE ADDR DEV SEL * DATA OUT 1
READ
START

START

R/W R/W

ACK NO ACK

DATA OUT N
STOP

AI01105C
st th
Note: 1. The seven most significant bits of the Device Select Code of a Random Read (in the 1 and 4 bytes) must be identical.

minated the internal write cycle, it responds with the Device Select Code, with the RW bit set to ‘1’.
an Ack, indicating that the memory is ready to The memory acknowledges this, and outputs the
receive the second part of the next instruction contents of the addressed byte. The master must
(the first byte of this instruction having been sent not acknowledge the byte output, and terminates
during Step 1). the transfer with a STOP condition.
Read Operations Current Address Read
Read operations are performed independently of The device has an internal address counter which
the state of the WC pin. is incremented each time a byte is read. For the
Random Address Read Current Address Read mode, following a START
condition, the master sends a Device Select Code
A dummy write is performed to load the address
with the RW bit set to ‘1’. The memory acknowl-
into the address counter, as shown in Figure 8. edges this, and outputs the byte addressed by the
Then, without sending a STOP condition, the mas-
internal address counter. The counter is then in-
ter sends another START condition, and repeats

8/16
 M24256, M24128

Table 7. DC Characteristics
(TA = –40 to 85 °C; VCC = 4.5 to 5.5 V or 2.5 to 5.5 V)
Symbol Parameter Test Condition Min. Max. Unit
Input Leakage Current
ILI 0 V ≤ VIN ≤ VCC ±2 µA
(SCL, SDA)
ILO Output Leakage Current 0 V ≤ VOUT ≤ VCC, SDA in Hi-Z ±2 µA
VCC=5V, fc=400kHz (rise/fall time < 30ns) 2 mA
ICC Supply Current
-W series: VCC =2.5V, fc=400kHz (rise/fall time < 30ns) 1 mA

Supply Current VIN = VSS or VCC , VCC = 5 V 10 µA

ICC1
(Stand-by) -W series: VIN = VSS or VCC , VCC = 2.5 V 2 µA
Input Low Voltage
VIL –0.3 0.3VCC V
(SCL, SDA)
Input High Voltage
VIH 0.7VCC VCC+1 V
(SCL, SDA)
VIL Input Low Voltage (WC) –0.3 0.5 V
VIH Input High Voltage (WC) 0.7VCC VCC+1 V

Output Low IOL = 3 mA, VCC = 5 V 0.4 V

VOL
Voltage -W series: IOL = 2.1 mA, VCC = 2.5 V 0.4 V

Table 8. Input Parameters 1 (TA = 25 °C, f = 400 kHz)

Symbol Parameter Test Condition Min. Max. Unit
CIN Input Capacitance (SDA) 8 pF
CIN Input Capacitance (other pins) 6 pF
ZL Input Impedance (WC) VIN ≤ 0.5 V 5 kΩ

ZH Input Impedance (WC) VIN ≥ 0.7VCC 500 kΩ

Low Pass Filter Input Time

tNS 100 ns
Constant (SCL and SDA)
Note: 1. Sampled only, not 100% tested.

Table 9. AC Measurement Conditions Figure 9. AC Testing Input Output Waveforms

Input Rise and Fall Times ≤ 50 ns 0.8VCC
0.7VCC
Input Pulse Voltages 0.2VCC to 0.8VCC
0.3VCC
Input and Output Timing 0.2VCC
0.3VCC to 0.7VCC
Reference Voltages
AI00825

9/16
M24256, M24128

Table 10. AC Characteristics

M24256 / M24128
VCC=4.5 to 5.5 V VCC=2.5 to 5.5 V
Symbol Alt. Parameter Unit
TA=–40 to 85°C TA=–40 to 85°C

Min Max Min Max

tCH1CH2 tR Clock Rise Time 300 300 ns
tCL1CL2 tF Clock Fall Time 300 300 ns

tDH1DH2 2 tR SDA Rise Time 20 300 20 300 ns

tDL1DL2 2 tF SDA Fall Time 20 300 20 300 ns

tCHDX 1 tSU:STA Clock High to Input Transition 600 600 ns

tCHCL tHIGH Clock Pulse Width High 600 600 ns

tDLCL tHD:STA Input Low to Clock Low (START) 600 600 ns
tCLDX tHD:DAT Clock Low to Input Transition 0 0 µs
tCLCH tLOW Clock Pulse Width Low 1.3 1.3 µs
tDXCX tSU:DAT Input Transition to Clock Transition 100 100 ns
tCHDH tSU:STO Clock High to Input High (STOP) 600 600 ns
tDHDL tBUF Input High to Input Low (Bus Free) 1.3 1.3 µs

tCLQV 3 tAA Clock Low to Data Out Valid 200 900 200 900 ns

tCLQX tDH Data Out Hold Time After Clock Low 200 200 ns
fC fSCL Clock Frequency 400 400 kHz
tW tWR Write Time 10 10 ms
Note: 1. For a reSTART condition, or following a write cycle.
2. Sampled only, not 100% tested.
3. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA.

cremented. The master terminates the transfer Acknowledge in Read Mode

with a STOP condition, as shown in Figure 8, with- In all read modes, the memory waits, after each
out acknowledging the byte output. byte read, for an acknowledgment during the 9th
Sequential Read bit time. If the master does not pull the SDA line
This mode can be initiated with either a Current low during this time, the memory terminates the
Address Read or a Random Address Read. The data transfer and switches to its stand-by state.
master does acknowledge the data byte output in
this case, and the memory continues to output the
next byte in sequence. To terminate the stream of
bytes, the master must not acknowledge the last
byte output, and must generate a STOP condition.
The output data comes from consecutive address-
es, with the internal address counter automatically
incremented after each byte output. After the last
memory address, the address counter ‘rolls-over’
and the memory continues to output data from
memory address 00h.

10/16
 M24256, M24128

Figure 10. AC Waveforms

tCHCL tCLCH

SCL

tDLCL tDXCX tCHDH

SDA IN

tCHDX tCLDX tDHDL

START SDA SDA STOP &

CONDITION INPUT CHANGE BUS FREE

SCL

tCLQV tCLQX

SDA OUT DATA VALID

DATA OUTPUT

SCL

tW

SDA IN

tCHDH tCHDX

STOP WRITE CYCLE START

CONDITION CONDITION

AI00795B

11/16
M24256, M24128

Table 11. Ordering Information Scheme

Example: M24256 – W MN 1 T

Memory Capacity Option

256 256 Kbit (32K x 8) T Tape and Reel Packing

128 128 Kbit (16K x 8)

Temperature Range
6 –40 °C to 85 °C
5 –20 °C to 85 °C
Operating Voltage

blank1 4.5 V to 5.5 V Package

W 2.5 V to 5.5 V BN PSDIP8 (0.25 mm frame)

MN2 SO8 (150 mil width)

MW3 SO8 (200 mil width)

Note: 1. Available only on request.
2. Available for M24128 only.
3. Available for M24256 only.

ORDERING INFORMATION
Devices are shipped from the factory with the
memory content set at all ‘1’s (FFh).
The notation used for the device number is as
shown in Table 11. For a list of available options
(speed, package, etc.) or for further information on
any aspect of this device, please contact your
nearest ST Sales Office.

12/16
 M24256, M24128

Table 12. PSDIP8 - 8 pin Plastic Skinny DIP, 0.25mm lead frame
mm inches
Symb.
Typ. Min. Max. Typ. Min. Max.
A 3.90 5.90 0.154 0.232
A1 0.49 – 0.019 –
A2 3.30 5.30 0.130 0.209
B 0.36 0.56 0.014 0.022
B1 1.15 1.65 0.045 0.065
C 0.20 0.36 0.008 0.014
D 9.20 9.90 0.362 0.390
E 7.62 – – 0.300 – –
E1 6.00 6.70 0.236 0.264
e1 2.54 – – 0.100 – –
eA 7.80 – 0.307 –
eB 10.00 0.394
L 3.00 3.80 0.118 0.150
N 8 8

Figure 11. PSDIP8 (BN)

A2 A

A1 L
B e1 C
B1 eA
D eB

E1 E

1
PSDIP-a

Note: 1. Drawing is not to scale.

13/16
M24256, M24128

Table 13. SO8 - 8 lead Plastic Small Outline, 150 mils body width
mm inches
Symb.
Typ. Min. Max. Typ. Min. Max.
A 1.35 1.75 0.053 0.069
A1 0.10 0.25 0.004 0.010
B 0.33 0.51 0.013 0.020
C 0.19 0.25 0.007 0.010
D 4.80 5.00 0.189 0.197
E 3.80 4.00 0.150 0.157
e 1.27 – – 0.050 – –
H 5.80 6.20 0.228 0.244
h 0.25 0.50 0.010 0.020
L 0.40 0.90 0.016 0.035
α 0° 8° 0° 8°
N 8 8
CP 0.10 0.004

Figure 12. SO8 narrow (MN)

h x 45˚

A
C
B
e CP

E H
1

A1 α L

SO-a

Note: 1. Drawing is not to scale.

14/16
 M24256, M24128

Table 14. SO8 - 8 lead Plastic Small Outline, 200 mils body width
mm inches
Symb.
Typ. Min. Max. Typ. Min. Max.
A 2.03 0.080
A1 0.10 0.25 0.004 0.010
A2 1.78 0.070
B 0.35 0.45 0.014 0.018
C 0.20 – – 0.008 – –
D 5.15 5.35 0.203 0.211
E 5.20 5.40 0.205 0.213
e 1.27 – – 0.050 – –
H 7.70 8.10 0.303 0.319
L 0.50 0.80 0.020 0.031
α 0° 10° 0° 10°
N 8 8
CP 0.10 0.004

Figure 13. SO8 wide (MW)

A2 A
C
B
e CP

E H
1
A1 α L

SO-b

Note: 1. Drawing is not to scale.

15/16
M24256, M24128

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
© 1999 STMicroelectronics - All Rights Reserved
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