A Novel FPGA-based LVDT Signal Conditioner

Kumardeb Banerjee, Bivas Dam, Kalyan Majumdar

Dept. of Instrumentation & Electronics Engineering
Jadavpur University, Salt Lake Campus
Kolkata, India, PIN - 700098
kdb@iee.jusl.ac.in

Abstract — This paper presents a phase compensated novel synchronous demodulator [5]. The work in [6] reports a DSP-
signal conditioner for a linear variable differential transformer based implementation of a typical I/Q demodulator for LVDT
(LVDT) and its FPGA based implementation. The LVDT output signal conditioning. The scheme accommodates both 4-wire
signal is a double-sideband suppressed-carrier amplitude-
modulated (DSB-SC-AM) waveform, where the LVDT sinusoidal
and 5-wire LVDTs, is insensitive to sensor induced phase
excitation is the carrier signal and the LVDT core position is the errors, and its performance is comparable with the
modulating signal. The proposed signal conditioner locates the commercially available LVDT signal conditioner ICs.
carrier peaks in the LVDT output signal and provides a direct However, this scheme necessitates the use of high
digital demodulation of the same at the said instants. Since the performance floating point DSPs, and hence, may not be
carrier component at the sampling instants equals the carrier commercially viable for single channel LVDT signal
amplitude, a simple gain scaling converts the read data to the
LVDT core position measurement. The peak sensitive
conditioning. The DSP-based approach reported in [7] and the
demodulation is insensitive to sensor induced phase lag and does implementation of a multi-channel DSP-based Instrument for
not require external phase compensation network. This displacement measurement using differential variable
conditioner has better dynamic response than existing LVDT reluctance transducers (DVRT) reported in [8], both use
signal conditioners. Its overall error figures are also comparable spectral estimation technique to estimate sensor primary and
with those of the existing solutions. secondary amplitudes. The final position measurement is
Keywords: Linear variable differential transformer; signal obtained from ration of the two. However, spectral estimation
conditioner; FPGA based implementation; direct digital technique works with a large number of signal samples,
demodulation; peak sensitive demodulation. thereby compromising the system bandwidth. The work
reported in [9] uses a system-on-chip microcontroller
I. INTRODUCTION MSP43OF149 from Texas Instruments to build a precision
The LVDT is a displacement sensor that gives an accurate LVDT signal conditioner. However, driving the LVDT primary
measurement of position. Detailed description of an LVDT and winding with a square wave necessitates incorporation of
its operation can be found in [1-2]. Commercially available additional filter chains to suppress the higher harmonics.
LVDTs are either the 4-wire type or the 5-wire type and work It is also worth noting the salient features of the two
with a primary excitation that varies from a few kHz (iron commercially available monolithic LVDT signal conditioners -
core) to hundreds of kHz (ferrite core). AD598 and AD698 from Analog Devices. The AD598 and
AD698 employ the ratio-based method and their
There are two existing and well documented approaches implementation details are documented in their respective
for LVDT signal conditioning – the ratio-based method [3] and datasheets [10-11]. Both implementations generate a low
the synchronous demodulation method [4]. The ratio-based distortion primary excitation that varies from 20 Hz to 20 kHz,
method directly computes position as the ratio of the LVDT and generates a dc voltage proportional to the LVDT core
secondary output and input primary excitation. However, position. The AD598 works only with 5-wire LVDTs and is
ratio-based methods are inherently noisy and in case there is a insensitive to sensor induced phase errors. The AD698 can
sensor induced phase lag in the secondary differential work with both 4-wire and 5-wire LVDTs. However, it
waveform, the secondary to primary ratio does not give an requires external RC network to eliminate sensor induced
exact measure of position, and a phase correction becomes phase lag.
mandatory to produce the correct output. The strength of this
method is that the measurement is insensitive to the variations In this paper we propose a robust phase-compensated
in the amplitude of the primary excitation. LVDT signal conditioner that implements a modified
homodyne detector that carries out a phase compensated
The second approach applies the standard phase-sensitive synchronous demodulation of the LVDT secondary differential
demodulation technique to the LVDT secondary output, a output. The proposed scheme implements a direct digitization
double-sideband suppressed-carrier amplitude modulated of the DSB-SC-AM output at the carrier peaks, as seen in the
(DSB-SC-AM) waveform. Various well documented variants LVDT output signal. This makes the process insensitive to
of the synchronous demodulation technique are available but sensor induced phase lags and less hardware intensive than
the more popular variant is the in-phase/quadrature (I/Q) existing solutions. An FPGA-based prototype of the proposed
signal conditioner is also implemented and tested on a standard
test bench. The results show linearity and bandwidth figures
comparable with existing commercial solutions.

II. THE PROPOSED LVDT SIGNAL CONDITIONER

A. Principle of operation
The proposed LVDT signal conditioner implements a
modified version of the standard synchronous demodulator that
eliminates the necessity of implementing multipliers, low pass
filters (LPFs), and subsequent signal processing for the
extraction of the core position. The basic idea behind the
proposed demodulation scheme is based on a technique Fig. 1: Functional block diagram of the proposed LVDT signal conditioner.
reported in [12].
The proposed demodulation scheme implements a carrier The proposed LVDT signal conditioner first converts the
peak synchronous direct readout method. At any instant of LVDT output to an equivalent digital pulse train, the modulated
time, the LVDT secondary output, a DSB-SC-AM waveform is pulse train. As the primary excitation is available locally, a
the product of the instantaneous values of the carrier signal and carrier pulse train, coherent with the primary excitation, is
the modulating signal. If the waveform is read at the carrier generated. Both pulse trains are then passed through two
peaks, as seen in the modulated signal, the carrier component is identical digital noise filters (DNFs). The filters remove noise
simply its amplitude that can be removed by appropriate glitches from the pulse trains but add some time lag, Tf, to
scaling of the read data. Moreover, this readout mechanism each. Next, to ascertain the phase mismatch between the carrier
also eliminates the phase error that creeps in due to phase and the modulated pulse trains, it measures the time lags, Td1
mismatch between the carrier and the modulated signals. To and Td2, between the rising edge of the filtered carrier pulse
instrument this, one has to identify the carrier-peaks in the train and the subsequent rising and falling edges of the filtered
modulated signal, read the modulated signal at the said instants modulated pulse train, and computes Td, the minimum of Td1
and scale them properly to remove the carrier amplitude and Td2. In DSB-SC-AM waveforms, whenever the modulating
component. The final output is thus the modulating signal, read signal becomes negative, the carrier component in the
at the carrier-peaks in the modulated signal. modulated signal suffers a phase inversion. In such cases, for
the filtered modulated pulse train, the falling edge precedes the
However, the following features need to be embedded in rising edge. Therefore, finding the minimum between the two
the said demodulator to ensure an error-free peak synchronous time lags ensures a correct measure of the LVDT primary to
demodulation: secondary phase lag. It then generates a quadrature pulse train
• The LVDT secondary output is first converted to a with a period that equals Tc, the carrier signal time period, with
digital pulse train for subsequent signal conditioning rising edges delayed by (Td + Tc /4 – Tf) from the
by comparators with built-in hysteresis. High level corresponding rising edges of the filtered carrier pulse train. A
noise glitches present in the sensor output, however, delay of Td from the carrier rising edge finds the corresponding
generates short duration pulses at the output of the carrier edge in the LVDT output signal. A further delay of (Tc /4
comparator. These noise pulses may corrupt the peak- – Tf) finds the corresponding carrier peak, as seen in the LVDT
detection mechanism and hence must be filtered out. output signal. The LVDT output signal, if sampled and
digitized at the rising edges of the said quadrature pulse-train,
• The LVDT secondary output signal, read at the carrier gives a direct digital read-out of the LVDT core position with
peaks, needs to the scaled. Since the scaling factor is correct sign.
proportional to the amplitude of the primary
excitation, a tight tracking of the same is essential to B. Design Overview
maintain measurement accuracy and repeatability.
Fig. 1 illustrates a functional block diagram of the
• The proposed demodulator regenerates the primary proposed LVDT signal conditioner. The outer section consists
excitation from the modulated signal. Moreover, it of an analog front-end hardware necessary for sensor
requires a periodic updating of the process to track interfacing. The inner core is the block level implementation
any drift in the frequency of the same. If the LVDT of the proposed demodulator along with a serial interface for
core is at the null position, the secondary differential uploading the measurement data to a host processor. The
voltage is zero. Hence, if the peak detection process of sensor interface section consists of a digital to analog
the carrier, as seen in the modulated signal, is initiated converter (DAC) driven by SW, the output of the
at this time, it fails. A watch-dog mechanism is thus SW_GENERATOR block that uses direct digital synthesis
necessary that, during start-up, will start the said (DDS) technique [13] to implement a sinusoidal waveform.
process only after sensing a non-zero LVDT output The output of the DAC is the LVDT primary excitation signal.
and will hold the last period data if the same incident The SW is a 12-bit sine data in 2’s compliment form. The MSB
occurs during periodic updating of the same. of SW is buffered and taken out as CLKA, the carrier pulse
train. CLKA is coherent with the carrier signal, with its rising
 data and loads the same on a 16-bit parallel-input serial-output
shift register, PISO_16. On receipt of sixteen serial clocks at
SCLK from the host processor, it outputs the 16-bit data,
serially, through SDO, to the host processor. Data bits are
shifted at every rising edge of SCLK, with the LSB transmitted
first. The serial clock frequency is decided by the host
processor; but from the design point of view, the maximum
permissible clock frequency is set to be 1 MHz.
Fig. 2: Functional block diagram of the PHASE_DELAY_LATCH
III. IMPLEMENTATION ISSUES
and falling edges matching exactly with the positive and This section documents a brief overview of the
implementation of the analog front-end hardware and the
negative zero crossing points of the carrier signal. A zero- mapping of the functional blocks of the inner core on the
crossing detector (ZCD) circuit converts the LVDT secondary target FPGA board.
output signal into modulated signal pulse train CLKB.
A functional block diagram of the A. Analog front-end hardware
PHASE_DELAY_LATCH, as presented in Fig. 2, shows the The sensor interface comprises of a low-distortion sine
sub-blocks that implement the aforesaid functionalities. Two wave generator to drive the LVDT primary winding and an
identical digital noise filters DNF1 and DNF2 remove noise ADC to read the secondary differential voltage. The sine wave
glitches from CLKA and CLKB, the incoming pulse trains and generator consists of a 12-bit full four quadrant multiplying
generate the filtered equivalents, viz. CLK1 and CLK2. Noise DAC, AD7541A driven by the FPGA-based DDS module.
glitches are very short duration spikes, with pulse widths Since the DAC provides a unipolar current output, a dual
negligible compared to that of the pulse train CLKA or CLKB. JFET-input op-amp IC, TL082 is used for current to voltage
The DNFs are designed to reject pulses of width below a conversion and level-shifting to generate a bipolar sinusoid of
preset time period, PD_FILT. The CNT_POS_EDGE block 5.0V peak-to-peak excursion. The VREF of the DAC is taken
starts a counter at the rising edge of CLK1, stops the same at from the on-chip VREF of the ADC. The ADC used in this setup
the rising edge of CLK2, and latches the same as DCNT1. The is a 12-bit SA-type ADC, AD574A that comes with an on-chip
CNT_NEG_EDGE block starts another counter at the rising stable 10.0V VREF (maximum 0.2% error and typical
edge of CLK1, stops the same at the subsequent falling edge of temperature coefficient of 15ppm/°C) which is available
CLK2, and latches the same as DCNT2. The WATCH_DOG externally and can drive up to 1.5 mA. As a single stable
block checks whether a valid rising edge and a falling edge of voltage reference source is used to drive both the DAC and
CLK2 occur prior to the next rising edge of CLK1. If yes, it ADC, any drift in the same will introduce changes in the DAC
latches the count values DCNT1 and DCNT2. If no, it clears and ADC outputs such that one nullifies the other. This, in
both the counters and restarts the delay count process from the effect, implements an auto correction mechanism that keeps the
next rising edge of CLK1. The MIN_COUNT block finds the scaling factor independent of the drifts in the carrier amplitude
minimum of DCNT1 and DCNT2, PD_FILT is subtracted due to changes in the reference voltage.
from it, and finally latched as DCNT. The ADC does not come with a SHA and hence a SHA unit
The CARRIER_PRD_GEN block counts the period of is implemented using the monolithic sample-and-hold IC,
CLK1 and latches the same as PD_CNT on an output latch. LF398. The input to the SHA is the LVDT secondary
The next block in the chain, QDR_PULSE_GEN, takes as its differential output and the sample-and-hold pulse comes as
inputs DCNT and PD_CNT to generate CLK3, a pulse train STB. The SHA output, SH0, is fed to the input of the ADC,
whose time period equals that of CLK2 but is in quadrature calibrated for a ± 5.0V bipolar input.
with CLK2. This is done by delaying the rising edges of CLK3 In addition to the ADC and DAC, the signal conditioner
by DCNT and a quarter of PD_CNT from those of CLK1. requires a ZCD unit for converting the LVDT secondary output
The final block, STB_GEN generates sampling pulses, to a pulse train. In this setup the ZCD unit is implemented
STB, whose falling edges coincide with the rising edges of using the monolithic comparator IC, LM311. Adequate
CLK3. STB drives a sample and hold amplifier, SHA. The on- hysteresis (≈150 mV) is provided in the ZCD unit for input
time of STB depends upon the acquisition time of the SHA and noise rejection. By design, the rising edges of the pulse train at
should be designed accordingly. The input to the SHA is the the ZCD output occur at the positive zero crossing points of
LVDT secondary output signal. The SHA output, SH0, is fed to the input analog waveform.
the input of a successive approximation (SA) type ADC, which
digitizes the LVDT secondary output signal at the carrier B. FPGA mapped blocks
peaks. Block RD_ADC_DATA generates the ADC handshake The inner core of the LVDT signal conditioner is designed
signal R/C~, reads the status signal EOC, and latches the and implemented on a MEMEC FPGA Evaluation Board that
converted data, DATA12, on an output latch. uses a Xilinx XC2S100 SPARTAN-II FPGA chip using the
Block SPI_SLAVE implements a 16-bit SPI slave channel, Xilinx PC-based ISE 9.1i Design Development System. The
a synchronous serial interface of the signal conditioner with system clock fCLK is derived from the on-board 25.0 MHz
the host processor. The module converts DATA12 to a 16-bit crystal and the I/O pins are made LVTTL compatible. The gate
 TABLE I: GATE UTILIZATION OF THE DEVICE

Target Device xc2s100-6pq208

Total equivalent gate count 19,656
f utilization
Gate d i 19.656%

Fig. 4: Functional block diagram of the WATCH_DOG

binary counter in CARRIER_PRD_GEN block counts

the SYS_CLK between two successive rising edges of
CLK1, the carrier pulse train, and latches the same as
Fig. 3: Functional block diagram of the DNF
PD_CNT. The binary counter in
CARRIER_PRD_GEN block is implemented as a 16-
complexity of the design, as generated by design software bit counter. Hence, the minimum carrier frequency it
tool, is reported in Table I. As the implementation details of can handle is fMIN = fCLK / 216 ≈ 381 Hz. So, the
the basic demodulator are documented in [12], this section minimum carrier frequency the implemented LVDT
explains the implementation of the additional blocks necessary signal conditioner can tune to is 381 Hz. On the next
to implement the proposed LVDT signal conditioner. rising edge of CLK1, the GEN_START_PULSE
• The Digital Noise Filter: Implementation details of circuit generates a ST_DELAY pulse. Triggered by
the DNF block is illustrated in Figure 3. At every the ST_DELAY pulse, two binary counters in
power-on reset the N-bit shift register and the T flip- CNT_POS_EDGE and CNT_NEG_EDGE blocks
flop are reset. The input pulse train at FIN is start counting the SYS_CLK. The binary counters stop
compared with the DNF output, FOUT. If the input is counting – the first one at the rising edge of CLK2
initially 0, the shift register remains reset. Whenever and the second one at the falling edge of CLK2, and
the input changes to logic 1, the transition propagates hold the corresponding count values DCNT1 and
to the output only if the input level remains high for DCNT2 respectively. Triggered by the same
at least N rising edges of SYS_CLK. However, if the ST_DELAY pulse, The EDGE_DETECT circuit waits
input changes to 0 prior to the Nth rising edge, the for one CLK1 period for occurrence of a rising as
register CLR logic is asserted and all stages of the well as a falling edge of CLK2. On receipt of both, it
shift register are reset. Thus any pulse train at FIN generates a LE pulse and a two SYS_CLK delayed
with on-time/off-time less than N periods of the LE1 pulse. LE latches the delay counts DCNT1 and
SYS_CLK will not propagate to the filter output. In DCNT2 and LE1 latches DCNT, the difference of the
this setup N is chosen to be 5, and since the on board minimum of these two counts (i.e. DCNT1 and
system clock is 25 MHz, the DNF eliminates all DCNT2) and PD_FILT, at the output of
noise glitches of width less than 200 nsec. This, PHASE_DELAY_LATCH block. If either of the edges
however, sets the maximum frequency limit for the of CLK2 is missing within one period of CLK1, the
primary excitation signal. Since generation of the EDGE_DETECT unit generates a CLR pulse instead
quadrature pulse train, CLK3, fails if the filter delay that resets the two binary counters in
Tf is greater than Tc/4, the quarter period of the CNT_POS_EDGE and CNT_NEG_EDGE blocks.
carrier signal, the maximum carrier frequency fMAX So, if during start-up, CLK2 edges are missing
that the implementation can handle is fMAX = 1/(4*Tf) (condition (i)), DCNT1 and DCNT2 are zeros, and
= 1.25 MHz. hence DCNT is not updated and holds the initial
value of zero. CLK1 and CLK3 are in coherence and
• The Watch-Dog Circuit: The WATCH_DOG unit, as the pulse train generated by the QDR_PULSE_GEN
illustrated in Figure 4, resolves two constraints in the block is in quadrature with CLK1. Hence the LVDT
generation mechanism of the CLK3 pulse, (i) if secondary output is read at the primary excitation
during start-up the LVDT core is at the null position, peaks. Similarly, if during the periodic update of the
a zero secondary differential voltage is obtained and frequency and phase information of CLK3, CLK2
(ii) if the same incident occurs during the periodic edges are missing (condition (ii)), DCNT1 and
update of the frequency and phase information of DCNT2 are zeros, but the output of
CLK3. In both cases the ZCD fails to generate CLK2 PHASE_DELAY_LATCH block holds DCNT, the
and hence the phase and frequency information of delay count as generated in the previous update cycle.
CLK3 cannot be generated and hence updated. At a
preset update rate set up by a timer module (60 sec in • The DDS module in the SW_GENERATOR block in
this setup), the GEN_START_PULSE circuit the proposed LVDT conditioner needs to be
generates a ST_UP pulse. Triggered by ST_UP a programmed to generate a sinusoid of frequency fSW
that satisfies the condition fMIN ≤ fSW ≤ fMAX. The DDS
 block can be programmed to any frequency in the
said range in steps of 1 Hz, and the performance of
the signal conditioner is independent of this choice.
For the implementation reported in this paper, the
primary excitation frequency is arbitrarily chosen to
be 12.5 kHz.

IV. TEST RESULTS

The prototype setup for the proposed LVDT signal
conditioner is tested for:
Fig 5: LVDT Emulator and demodulator outputs for zero
• Design verification of the proposed demodulator: sensor induced phase lag
These tests verify the design of the peak synchronous
demodulation scheme implemented in the proposed
LVDT signal conditioner. First we evaluate the design
of the phase-compensated synchronous demodulation
process. This is done for two test cases – (i) with no
sensor induced phase lag and (ii) with sensor induced
phase lag.
• Computation of the overall error: This test is to
compute the overall error of the proposed LVDT
signal conditioner for comparison of the same with
those of the commercially available solutions. The
transfer characteristics of the system is first obtained
Fig. 6: LVDT Emulator and demodulator outputs for 18°
by driving its input over its entire range in small steps sensor induced phase lag
and then the maximum and average deviations of the
same from the ideal transfer characteristics are that there is no attenuation in the peak-to-peak excursion of
computed. V_DMOD, which ensures a true phase insensitive detection.
• Bandwidth estimation: This test evaluates the
dynamic characteristics of the LVDT signal B. Computation of overall error
conditioner. A magnitude and phase plot of the LVDT Although it is customary to specify the linearity error of an
signal conditioner output, for simulated sinusoidal LVDT signal conditioner, in this setup it is impossible to
core movements to ascertain the –3dB is presented decouple the same from the linearity, gain and offset errors of
for estimation of the system bandwidth. the commercial grade analog amplifiers, analog multiplier,
SHA, ADC and DAC chips. So, the overall error is computed
The test setup required for performance analysis of the instead by comparing the actual transfer characteristics of the
demodulator and bandwidth estimation of the proposed signal signal conditioner with its ideal transfer curve. The LVDT
conditioner necessitates the generation of sinusoidal vibrations emulator is set to generate a DSB-SC-AM waveform with zero
of the LVDT core position. In absence of one such setup, we sensor induced phase lag, with modulating signal (core
worked with an LVDT emulator, built in line with [14], position) varying from –12V to +12V in steps of 0.5V
involving linear ICs, a programmable dc power supply and an (resulting in 49 data points). Each step thus emulates an
arbitrary waveform generator. incremental change in the LVDT core position. The
demodulator analog outputs for the corresponding signal
A. Design verification of the proposed demodulator conditioner inputs generate the actual transfer characteristics.
In the first test run, the LVDT emulator is set to generate a Finally for each measured data, the deviation from the ideal
7.0V peak-to-peak DSB-SC-AM waveform with zero sensor transfer characteristics is computed. The maximum deviation
induced phase lag, which is subsequently used to drive the (maximum overall error) and the average deviation
LVDT signal conditioner. The test results are shown in Fig. 5; (average/typical overall error) are computed and listed in
the LVDT emulator output (V_MOD) and the demodulator Table II. The overall errors of the monolithic LVDT signal
output (V_DMOD). The plot shows V_DMOD, a 50 Hz conditioners are also included in Table II for ready reference.
sinusoid with a peak-to-peak excursion of 7.02V, to be a The overall error figures of the proposed solution are slightly
perfect envelope detected form of V_MOD. on the higher side but are comparable with those of the
monolithic solutions.
In the second test run, the LVDT emulator is set to generate a
7.0V peak-to-peak DSB-SC-AM waveform with a sensor C. Bandwidth Estimation
induced phase lag of 18°. Fig. 6 shows the LVDT emulator
output (V_MOD) and the demodulator output (V_DMOD). The LVDT responds very fast to changes in its core position.
The plot shows a perfect synchronous demodulation of The dynamic response of an LVDT sensor itself is actually
V_MOD with no phase lag between the envelope of the limited by the characteristics of the signal conditioner. As
modulated waveform and the demodulated output. Also note reported in [6], the –3dB bandwidths of AD598 and AD698 are
 TABLE II: OVERALL ERROR FIGURES OF LVDT SIGNAL CONDITIONERS input digital filter chain and watch-dog circuit add to the
Proposed robustness of the signal conditioner. The range of primary
AD598 AD698 excitation frequency that it can generate makes it suitable for
scheme
Maximum Overall iron core as well as ferrite core LVDTs, that too for both the 4-
2.35 1.64 2.6 wire and 5-wire variants.
Error (%of FS)
Average/Typical 0.6 0.4 0.7 Performance analysis of the proposed scheme shows that
Overall Error (%of FS) the total error figure of the same is comparable with the
monolithic LVDT signal conditioners. Its dynamic
characteristic is better than those of the monolithic LVDT
signal conditioners and processor based solutions. Moreover,
cost wise, it is more economical than standard processor based
solutions. The minimal analog hardware requirement makes
the process suitable for integration into a complete system
including the sensor, operating from a dual dc power supply.

ACKNOWLEDGMENT
The authors wish to thank the members of the Centre for
Embedded Systems in Instrumentation, Dept. of
Instrumentation & Electronics Engineering, Jadavpur
University for the facilities made available to them for
fabricating and testing the hardware setups.

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