Technical Reference Manual: TMS320F2837xD Dual-Core Delfino Microcontrollers

TMS320F2837xD Dual-Core Delfino
Microcontrollers
Technical Reference Manual
Literature Number: SPRUHM8G

December 2013 – Revised September 2017
Contents
Preface....................................................................................................................................... 81
1 C28x Processor .................................................................................................................. 82
1.1 Overview..................................................................................................................... 83
1.1.1 Floating-Point Unit ................................................................................................ 83
1.1.2 Trigonometric Math Unit ......................................................................................... 83
1.1.3 Viterbi, Complex Math, and CRC Unit II (VCU-II) ............................................................ 84
2 System Control .................................................................................................................. 85
2.1 Introduction .................................................................................................................. 86
2.2 System Control Functional Description .................................................................................. 86
2.2.1 Device Identification .............................................................................................. 86
2.2.2 Device Configuration Registers ................................................................................. 87
2.3 Resets ....................................................................................................................... 87
2.3.1 Reset Sources ..................................................................................................... 87
2.3.2 External Reset (XRS) ............................................................................................. 88
2.3.3 Power-On Reset (POR) .......................................................................................... 88
2.3.4 Debugger Reset (SYSRS) ....................................................................................... 88
2.3.5 Watchdog Reset (WDRS) ........................................................................................ 89
2.3.6 NMI Watchdog Reset (NMIWDRS) ............................................................................. 89
2.3.7 DCSM Safe Code Copy Reset (SCCRESET) ................................................................. 89
2.3.8 Hibernate Reset (HIBRESET) ................................................................................... 89
2.3.9 Hardware BIST Reset (HWBISTRS)............................................................................ 89
2.3.10 Test Reset (TRST) ............................................................................................... 89
2.4 Peripheral Interrupts ....................................................................................................... 89
2.4.1 Interrupt Concepts................................................................................................. 90
2.4.2 Interrupt Architecture.............................................................................................. 90
2.4.3 Interrupt Entry Sequence ......................................................................................... 91
2.4.4 Configuring and Using Interrupts ................................................................................ 92
2.4.5 PIE Channel Mapping ............................................................................................ 95
2.4.6 Vector Tables ...................................................................................................... 96
2.5 Exceptions and Non-Maskable Interrupts ............................................................................. 102
2.5.1 Configuring and Using NMIs ................................................................................... 102
2.5.2 Emulation Considerations ...................................................................................... 102
2.5.3 NMI Sources ...................................................................................................... 103
2.5.4 Illegal Instruction Trap (ITRAP) ................................................................................ 103
2.6 Safety Features ........................................................................................................... 103
2.6.1 Write Protection on Registers .................................................................................. 103
2.6.2 Missing Clock Detection Logic ................................................................................. 104
2.6.3 PLLSLIP Detection .............................................................................................. 105
2.6.4 CPU1 and CPU2 PIE Vector Address Validity Check ...................................................... 105
2.6.5 NMIWDs .......................................................................................................... 106
2.6.6 ECC and Parity Enabled RAMs, Shared RAMs Protection ................................................ 106
2.6.7 ECC Enabled Flash Memory ................................................................................... 106
2.6.8 ERRORSTS Pin.................................................................................................. 106
2.7 Clocking ................................................................................................................... 107
2.7.1 Clock Sources .................................................................................................... 109
2 Contents SPRUHM8G – December 2013 – Revised September 2017

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2.7.2 Derived Clocks ................................................................................................... 111

2.7.3 Device Clock Domains .......................................................................................... 111
2.7.4 XCLKOUT......................................................................................................... 112
2.7.5 Clock Connectivity ............................................................................................... 113
2.7.6 Clock Source and PLL Setup .................................................................................. 114
2.8 32-Bit CPU Timers 0/1/2 ................................................................................................. 117
2.9 Watchdog Timers ......................................................................................................... 119
2.9.1 Servicing the Watchdog Timer ................................................................................. 119
2.9.2 Minimum Window Check ....................................................................................... 120
2.9.3 Watchdog Reset or Watchdog Interrupt Mode ............................................................... 120
2.9.4 Watchdog Operation in Low Power Modes .................................................................. 121
2.9.5 Emulation Considerations ...................................................................................... 121
2.10 Low Power Modes ........................................................................................................ 122
2.10.1 IDLE .............................................................................................................. 122
2.10.2 STANDBY ....................................................................................................... 122
2.10.3 HALT ............................................................................................................. 123
2.10.4 HIB ................................................................................................................ 123
2.11 Memory Controller Module .............................................................................................. 125
2.11.1 Functional Description ......................................................................................... 125
2.12 Flash and OTP Memory ................................................................................................. 133
2.12.1 Features.......................................................................................................... 133
2.12.2 Flash Tools ...................................................................................................... 133
2.12.3 Default Flash Configuration ................................................................................... 134
2.12.4 Flash Bank, OTP and Pump .................................................................................. 134
2.12.5 Flash Module Controller (FMC) ............................................................................... 134
2.12.6 Flash and OTP Power-Down Modes and Wakeup ......................................................... 135
2.12.7 Flash and OTP Performance .................................................................................. 137
2.12.8 Flash Read Interface ........................................................................................... 137
2.12.9 Erase/Program Flash ........................................................................................... 139
2.12.10 Error Correction Code (ECC) Protection ................................................................... 140
2.12.11 Reserved Locations Within Flash and OTP ............................................................... 144
2.12.12 Procedure to Change the Flash Control Registers ....................................................... 144
2.12.13 Flash Pump Ownership Semaphore ........................................................................ 144
2.13 Dual Code Security Module (DCSM) ................................................................................... 146
2.13.1 Functional Description ......................................................................................... 146
2.13.2 CSM Impact on Other On-Chip Resources ................................................................. 152
2.13.3 Incorporating Code Security in User Applications .......................................................... 153
2.14 JTAG ....................................................................................................................... 157
2.15 Registers ................................................................................................................... 159
2.15.1 Base Addresses ................................................................................................ 159
2.15.2 CPUTIMER_REGS Registers ................................................................................. 160
2.15.3 PIE_CTRL_REGS Registers .................................................................................. 167
2.15.4 WD_REGS Registers .......................................................................................... 219
2.15.5 NMI_INTRUPT_REGS Registers ............................................................................. 225
2.15.6 XINT_REGS Registers ......................................................................................... 238
2.15.7 DMA_CLA_SRC_SEL_REGS Registers .................................................................... 247
2.15.8 FLASH_PUMP_SEMAPHORE_REGS Registers .......................................................... 254
2.15.9 DEV_CFG_REGS Registers .................................................................................. 256
2.15.10 CLK_CFG_REGS Registers ................................................................................. 323
2.15.11 CPU_SYS_REGS Registers ................................................................................. 346
2.15.12 ROM_PREFETCH_REGS Registers ....................................................................... 386
2.15.13 DCSM_Z1_OTP Registers ................................................................................... 388
2.15.14 DCSM_Z2_OTP Registers ................................................................................... 395
SPRUHM8G – December 2013 – Revised September 2017 Contents 3

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2.15.15 DCSM_Z1_REGS Registers ................................................................................. 402

2.15.16 DCSM_Z2_REGS Registers ................................................................................. 422
2.15.17 DCSM_COMMON_REGS Registers ....................................................................... 442
2.15.18 MEM_CFG_REGS Registers ................................................................................ 449
2.15.19 ACCESS_PROTECTION_REGS Registers ............................................................... 497
2.15.20 MEMORY_ERROR_REGS Registers ...................................................................... 520
2.15.21 ROM_WAIT_STATE_REGS Registers ..................................................................... 537
2.15.22 FLASH_CTRL_REGS Registers ............................................................................ 539
2.15.23 FLASH_ECC_REGS Registers ............................................................................. 548
2.15.24 CPU_ID_REGS Registers ................................................................................... 571
2.15.25 UID_REGS Registers ......................................................................................... 573
3 ROM Code and Peripheral Booting ..................................................................................... 582
3.1 Introduction ................................................................................................................ 583
3.2 Device Boot Philosophy .................................................................................................. 583
3.3 Device Boot Modes ....................................................................................................... 583
3.4 Configuring Boot Mode Pins ............................................................................................ 584
3.5 Configuring Get Boot Options ........................................................................................... 585
3.6 Configuring Emulation Boot Options ................................................................................... 586
3.7 Device Boot Flow Diagrams ............................................................................................. 588
3.7.1 Emulation Boot Flow Diagrams ................................................................................ 589
3.7.2 Standalone and Hibernate Boot Flow Diagrams ............................................................. 591
3.8 Device Reset and Exception Handling ................................................................................. 593
3.8.1 Reset Causes and Handling.................................................................................... 593
3.8.2 Exceptions and Interrupts Handling ........................................................................... 594
3.9 Boot ROM Description ................................................................................................... 594
3.9.1 Entry Points ....................................................................................................... 594
3.9.2 Wait Points........................................................................................................ 595
3.9.3 Memory Maps .................................................................................................... 595
3.9.4 Boot Modes ....................................................................................................... 598
3.9.5 Boot Data Stream Structure .................................................................................... 611
3.9.6 GPIO Assignments .............................................................................................. 613
3.9.7 Boot IPC .......................................................................................................... 615
3.9.8 Clock Initializations .............................................................................................. 618
3.9.9 Wait State Configuration ........................................................................................ 619
3.9.10 Boot Status information ........................................................................................ 619
3.9.11 ROM Version .................................................................................................... 621
4 Direct Memory Access (DMA) ............................................................................................. 623
4.1 Introduction ................................................................................................................ 624
4.2 Architecture ................................................................................................................ 625
4.2.1 Block Diagram .................................................................................................... 625
4.2.2 Common Peripheral Architecture .............................................................................. 625
4.2.3 Peripheral Interrupt Event Trigger Sources .................................................................. 627
4.2.4 DMA Bus .......................................................................................................... 632
4.3 Pipeline Timing and Throughput ........................................................................................ 632
4.4 CPU Arbitration ........................................................................................................... 633
4.5 Channel Priority ........................................................................................................... 634
4.5.1 Round-Robin Mode .............................................................................................. 634
4.5.2 Channel 1 High Priority Mode .................................................................................. 635
4.6 Address Pointer and Transfer Control ................................................................................. 636
4.7 Overrun Detection Feature .............................................................................................. 640
4.8 Register Descriptions..................................................................................................... 642
4.8.1 DMA Control Register (DMACTRL) — EALLOW Protected ............................................... 643
4.8.2 Debug Control Register (DEBUGCTRL) — EALLOW Protected .......................................... 644

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4.8.3 Revision Register (REVISION)................................................................................. 644

4.8.4 Priority Control Register 1 (PRIORITYCTRL1) — EALLOW Protected .................................. 645
4.8.5 Priority Status Register (PRIORITYSTAT) ................................................................... 646
4.8.6 Mode Register (MODE) — EALLOW Protected ............................................................. 647
4.8.7 Control Register (CONTROL) — EALLOW Protected ...................................................... 649
4.8.8 Burst Size Register (BURST_SIZE) — EALLOW Protected ............................................... 651
4.8.9 BURST_COUNT Register ...................................................................................... 651
4.8.10 Source Burst Step Register Size (SRC_BURST_STEP) — EALLOW Protected ...................... 652
4.8.11 Destination Burst Step Register Size (DST_BURST_STEP) — EALLOW Protected ................. 653
4.8.12 Transfer Size Register (TRANSFER_SIZE) — EALLOW Protected ..................................... 653
4.8.13 Transfer Count Register (TRANSFER_COUNT) .......................................................... 654
4.8.14 Source Transfer Step Size Register (SRC_TRANSFER_STEP) — EALLOW Protected ............. 654
4.8.15 Destination Transfer Step Size Register (DST_TRANSFER_STEP) — EALLOW Protected ........ 655
4.8.16 Source/Destination Wrap Size Register (SRC/DST_WRAP_SIZE) — EALLOW protected) ......... 655
4.8.17 Source/Destination Wrap Count Register (SCR/DST_WRAP_COUNT) ............................... 656
4.8.18 Source/Destination Wrap Step Size Registers (SRC/DST_WRAP_STEP) — EALLOW Protected . 656
4.8.19 Shadow Source Begin and Current Address Pointer Registers
(SRC_BEG_ADDR_SHADOW/DST_BEG_ADDR_SHADOW) — All EALLOW Protected ............ 657
4.8.20 Active Source Begin and Current Address Pointer Registers
(SRC_BEG_ADDR/DST_BEG_ADDR) ....................................................................... 657
4.8.21 Shadow Destination Begin and Current Address Pointer Registers
(SRC_ADDR_SHADOW/DST_ADDR_SHADOW) — All EALLOW Protected .......................... 658
4.8.22 Active Destination Begin and Current Address Pointer Registers (SRC_ADDR/DST_ADDR) ....... 658
5 Control Law Accelerator (CLA) ........................................................................................... 659
5.1 Control Law Accelerator (CLA) Overview ............................................................................. 660
5.2 CLA Interface .............................................................................................................. 662
5.2.1 CLA Memory ..................................................................................................... 662
5.2.2 CLA Memory Bus ................................................................................................ 663
5.2.3 Shared Peripherals and EALLOW Protection ................................................................ 663
5.2.4 CLA Tasks and Interrupt Vectors .............................................................................. 664
5.2.5 CLA Software Interrupt to CPU ................................................................................ 666
5.3 CLA and CPU Arbitration ................................................................................................ 666
5.3.1 CLA and CPU Arbitration ....................................................................................... 666
5.3.2 CLA Message RAM ............................................................................................. 666
5.4 CLA Configuration and Debug .......................................................................................... 668
5.4.1 Building a CLA Application ..................................................................................... 668
5.4.2 Typical CLA Initialization Sequence ........................................................................... 668
5.4.3 Debugging CLA Code ........................................................................................... 670
5.4.4 CLA Illegal Opcode Behavior .................................................................................. 671
5.4.5 Resetting the CLA ............................................................................................... 671
5.5 Pipeline ..................................................................................................................... 672
5.5.1 Pipeline Overview ................................................................................................ 672
5.5.2 CLA Pipeline Alignment ......................................................................................... 672
5.5.3 Parallel Instructions .............................................................................................. 675
5.6 Instruction Set ............................................................................................................. 677
5.6.1 Instruction Descriptions ......................................................................................... 677
5.6.2 Addressing Modes and Encoding.............................................................................. 679
5.6.3 Instructions ....................................................................................................... 681
5.7 Registers ................................................................................................................... 792
5.7.1 CLA Base Addresses............................................................................................ 792
5.7.2 CLA_REGS Registers ........................................................................................... 793
5.7.3 CLA_SOFTINT_REGS Registers .............................................................................. 828
6 Inter-Processor Communication (IPC) ................................................................................. 833

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6.1 Inter-Processor Communication ........................................................................................ 834

6.2 Message RAMs ........................................................................................................... 835
6.3 IPC Flags and Interrupts ................................................................................................. 835
6.4 IPC Command Registers ................................................................................................ 835
6.5 Free-Running Counter ................................................................................................... 836
6.6 IPC Communication Protocol............................................................................................ 837
6.7 Registers ................................................................................................................... 838
6.7.1 IPC Base Addresses ............................................................................................ 838
6.7.2 IPC_REGS_CPU1 Registers ................................................................................... 839
6.7.3 IPC_REGS_CPU2 Registers ................................................................................... 872
7 General-Purpose Input/Output (GPIO) ................................................................................. 905
7.1 GPIO Overview ........................................................................................................... 906
7.2 Configuration Overview .................................................................................................. 907
7.3 Digital General-Purpose I/O Control.................................................................................... 907
7.4 Input Qualification ......................................................................................................... 909
7.4.1 No Synchronization (Asynchronous Input) ................................................................... 909
7.4.2 Synchronization to SYSCLKOUT Only........................................................................ 909
7.4.3 Qualification Using a Sampling Window ...................................................................... 909
7.5 USB Signals ............................................................................................................... 912
7.6 SPI Signals ................................................................................................................ 912
7.7 GPIO and Peripheral Muxing ............................................................................................ 914
7.8 Internal Pullup Configuration Requirements........................................................................... 919
7.9 Registers ................................................................................................................... 921
7.9.1 GPIO Base Addresses .......................................................................................... 921
7.9.2 GPIO_CTRL_REGS Registers ................................................................................. 922
7.9.3 GPIO_DATA_REGS Registers ............................................................................... 1087
8 Crossbar (X-BAR)............................................................................................................ 1137
8.1 GPIO Input X-BAR ...................................................................................................... 1138
8.2 ePWM and GPIO Output X-BAR ...................................................................................... 1139
8.2.1 ePWM X-BAR ................................................................................................... 1139
8.2.2 GPIO Output X-BAR ........................................................................................... 1142
8.2.3 X-BAR Flags .................................................................................................... 1143
8.3 X-BAR Registers ........................................................................................................ 1145
8.3.1 X-BAR Base Addresses ....................................................................................... 1145
8.3.2 INPUT_XBAR_REGS Registers ............................................................................. 1146
8.3.3 XBAR_REGS Registers ....................................................................................... 1165
8.3.4 EPWM_XBAR_REGS Registers ............................................................................. 1178
8.3.5 OUTPUT_XBAR_REGS Registers .......................................................................... 1271
9 Analog Subsystem .......................................................................................................... 1372
9.1 Analog Subsystem ...................................................................................................... 1373
9.1.1 Features ........................................................................................................ 1373
9.1.2 Block Diagram .................................................................................................. 1373
9.1.3 Lock Registers .................................................................................................. 1376
9.2 Registers ................................................................................................................. 1377
9.2.1 Analog Subsystem Base Addresses ......................................................................... 1377
9.2.2 ANALOG_SUBSYS_REGS Registers ....................................................................... 1378
10 Analog-to-Digital Converter (ADC)..................................................................................... 1387
10.1 Analog-to-Digital Converter (ADC) .................................................................................... 1388
10.1.1 Features ........................................................................................................ 1388
10.1.2 ADC Block Diagram ........................................................................................... 1388
10.1.3 ADC Configurability ........................................................................................... 1389
10.1.4 SOC Principle of Operation .................................................................................. 1393

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10.1.5 SOC Configuration Examples ............................................................................... 1396

10.1.6 ADC Conversion Priority ..................................................................................... 1398
10.1.7 Burst Mode ..................................................................................................... 1401
10.1.8 EOC and Interrupt Operation ................................................................................ 1403
10.1.9 Post-Processing Blocks ...................................................................................... 1403
10.1.10 Opens/Shorts Detection Circuit (OSDETECT) ........................................................... 1406
10.1.11 Power-Up Sequence ........................................................................................ 1407
10.1.12 ADC Calibration .............................................................................................. 1407
10.2 ADC Timings ............................................................................................................. 1408
10.2.1 ADC Timing Diagrams ........................................................................................ 1408
10.3 Additional Information ................................................................................................... 1413
10.3.1 Ensuring Synchronous Operation ........................................................................... 1413
10.3.2 Choosing an Acquisition Window Duration ................................................................ 1417
10.3.3 Achieving Simultaneous Sampling .......................................................................... 1418
10.3.4 Designing an External Reference Circuit .................................................................. 1418
10.3.5 Internal Temperature Sensor ................................................................................ 1420
10.4 Registers ................................................................................................................. 1421
10.4.1 ADC Base Addresses ........................................................................................ 1421
10.4.2 ADC_REGS Registers ........................................................................................ 1422
10.4.3 ADC_RESULT_REGS Registers............................................................................ 1560
11 Buffered Digital to Analog Converter (DAC) ....................................................................... 1581
11.1 Buffered Digital to Analog Converter (DAC) Overview ............................................................. 1582
11.1.1 Features ........................................................................................................ 1582
11.1.2 Block Diagram ................................................................................................. 1582
11.2 Using the DAC ........................................................................................................... 1582
11.3 Lock Registers ........................................................................................................... 1583
11.4 Registers ................................................................................................................. 1583
11.4.1 DAC Base Addresses ........................................................................................ 1583
11.4.2 DAC_REGS Registers ........................................................................................ 1584
12 Comparator Subsystem (CMPSS) ...................................................................................... 1592
12.1 CMPSS Overview ....................................................................................................... 1593
12.1.1 Features ........................................................................................................ 1593
12.1.2 Block Diagram ................................................................................................. 1593
12.2 Comparator............................................................................................................... 1594
12.3 Internal DAC ............................................................................................................. 1594
12.4 Ramp Generator ......................................................................................................... 1595
12.5 Digital Filter .............................................................................................................. 1596
12.6 Registers ................................................................................................................. 1598
12.6.1 CMPSS Base Addresses..................................................................................... 1598
12.6.2 CMPSS_REGS Registers .................................................................................... 1599
13 Sigma Delta Filter Module (SDFM) ..................................................................................... 1624
13.1 SDFM Module Overview ............................................................................................... 1625
13.1.1 SDFM Features ................................................................................................ 1625
13.1.2 Block Diagram ................................................................................................. 1626
13.2 Configuring Device Pins ................................................................................................ 1627
13.3 Input Control Unit ........................................................................................................ 1628
13.4 Comparator Unit ......................................................................................................... 1629
13.5 Data Filter Unit ........................................................................................................... 1630
13.5.1 32-bit or 16-bit Data Filter Output Representation ........................................................ 1632
13.5.2 Data Rate and Latency of the Sinc Filter .................................................................. 1633
13.6 Interrupt Unit ............................................................................................................. 1634
13.7 Register Descriptions ................................................................................................... 1636
13.8 Registers ................................................................................................................. 1637

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13.8.1 SDFM Base Addresses....................................................................................... 1637

13.8.2 SDFM_REGS Registers ...................................................................................... 1638
14 Enhanced Pulse Width Modulator (ePWM) ......................................................................... 1674
14.1 Introduction ............................................................................................................... 1675
14.1.1 Submodule Overview ......................................................................................... 1677
14.3 Overview.................................................................................................................. 1682
14.4 Time-Base (TB) Submodule ........................................................................................... 1684
14.4.1 Purpose of the Time-Base Submodule ..................................................................... 1684
14.4.2 Controlling and Monitoring the Time-Base Submodule .................................................. 1685
14.4.3 Calculating PWM Period and Frequency .................................................................. 1686
14.4.4 Phase Locking the Time-Base Clocks of Multiple ePWM Modules..................................... 1690
14.4.5 Simultaneous Writes to TBPRD and CMPx Registers Between ePWM Modules .................... 1690
14.4.6 Time-Base Counter Modes and Timing Waveforms ...................................................... 1691
14.4.7 Global Load .................................................................................................... 1693
14.5 Counter-Compare (CC) Submodule .................................................................................. 1695
14.5.1 Purpose of the Counter-Compare Submodule ............................................................ 1695
14.5.2 Controlling and Monitoring the Counter-Compare Submodule .......................................... 1695
14.5.3 Operational Highlights for the Counter-Compare Submodule ........................................... 1696
14.5.4 Count Mode Timing Waveforms ............................................................................ 1698
14.6 Action-Qualifier (AQ) Submodule ..................................................................................... 1701
14.6.1 Purpose of the Action-Qualifier Submodule ............................................................... 1702
14.6.2 Action-Qualifier Submodule Control and Status Register Definitions .................................. 1702
14.6.3 Action-Qualifier Event Priority ............................................................................... 1705
14.6.4 AQCTLA and AQCTLB Shadow Mode Operations ....................................................... 1706
14.6.5 Waveforms for Common Configurations ................................................................... 1708
14.7 Dead-Band Generator (DB) Submodule ............................................................................. 1714
14.7.1 Purpose of the Dead-Band Submodule .................................................................... 1715
14.7.2 Dead-band Submodule Additional Operating Modes ..................................................... 1715
14.7.3 Operational Highlights for the Dead-Band Submodule ................................................... 1716
14.8 PWM Chopper (PC) Submodule ..................................................................................... 1721
14.8.1 Purpose of the PWM Chopper Submodule ................................................................ 1721
14.8.2 Operational Highlights for the PWM Chopper Submodule............................................... 1721
14.8.3 Waveforms ..................................................................................................... 1722
14.9 Trip-Zone (TZ) Submodule ............................................................................................. 1725
14.9.1 Purpose of the Trip-Zone Submodule ...................................................................... 1725
14.9.2 Operational Highlights for the Trip-Zone Submodule ..................................................... 1725
14.9.3 Generating Trip Event Interrupts ............................................................................ 1728
14.10 Event-Trigger (ET) Submodule........................................................................................ 1730
14.10.1 Operational Overview of the ePWM Type 4 Event-Trigger Submodule .............................. 1731
14.11 Digital Compare (DC) Submodule .................................................................................... 1736
14.11.1 Purpose of the Digital Compare Submodule ............................................................. 1737
14.11.2 Enhanced Trip Action ....................................................................................... 1738
14.11.3 Using CMPSS to Trip the ePWM on a Cycle-by-Cycle Basis ......................................... 1738
14.11.4 Operation Highlights of the Digital Compare Submodule .............................................. 1738
14.12 EPWM X-BAR ........................................................................................................... 1744
14.13 Applications to Power Topologies .................................................................................... 1745
14.13.1 Overview of Multiple Modules ............................................................................. 1745
14.13.2 Key Configuration Capabilities ............................................................................. 1746
14.13.3 Controlling Multiple Buck Converters With Independent Frequencies ................................ 1747
14.13.4 Controlling Multiple Buck Converters With Same Frequencies ........................................ 1750
14.13.5 Controlling Multiple Half H-Bridge (HHB) Converters ................................................... 1751
14.13.6 Controlling Dual 3-Phase Inverters for Motors (ACI and PMSM) ..................................... 1753

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14.13.7 Practical Applications Using Phase Control Between PWM Modules ................................ 1755
14.13.8 Controlling a 3-Phase Interleaved DC/DC Converter ................................................... 1756
14.13.9 Controlling Zero Voltage Switched Full Bridge (ZVSFB) Converter................................... 1759
14.13.10 Controlling a Peak Current Mode Controlled Buck Module ........................................... 1760
14.13.11 Controlling H-Bridge LLC Resonant Converter......................................................... 1761
14.14 Registers ................................................................................................................. 1763
14.14.1 EPWM Base Addresses .................................................................................... 1763
14.14.2 EPWM_REGS Registers ................................................................................... 1764
14.14.3 EPWM_XBAR_REGS Registers ........................................................................... 1900
14.14.4 SYNC_SOC_REGS Registers ............................................................................. 1993
15 High-Resolution Pulse Width Modulator (HRPWM) .............................................................. 2001
15.1 Introduction ............................................................................................................... 2002
15.2 Operational Description of HRPWM .................................................................................. 2004
15.2.1 Controlling the HRPWM Capabilities ....................................................................... 2004
15.2.2 Configuring the HRPWM ..................................................................................... 2007
15.2.3 Configuring Hi-Res in Deadband Rising Edge and Falling Edge Delay ............................... 2008
15.2.4 Principle of Operation ......................................................................................... 2008
15.2.5 Deadband High Resolution Operation ..................................................................... 2018
15.2.6 Scale Factor Optimizing Software (SFO) .................................................................. 2019
15.2.7 HRPWM Examples Using Optimized Assembly Code. .................................................. 2019
15.3 Appendix A: SFO Library Software - SFO_TI_Build_V7.lib........................................................ 2025
15.3.1 Scale Factor Optimizer Function - int SFO() .............................................................. 2025
15.3.2 Software Usage ............................................................................................... 2026
16 Enhanced Capture (eCAP) ................................................................................................ 2028
16.1 Introduction ............................................................................................................... 2029
16.2 Description ............................................................................................................... 2029
16.3 Configuring Device Pins for the eCAP ............................................................................... 2029
16.4 Capture and APWM Operating Mode ................................................................................ 2030
16.5 Capture Mode Description ............................................................................................. 2031
16.5.1 Event Prescaler ................................................................................................ 2032
16.5.2 Edge Polarity Select and Qualifier .......................................................................... 2033
16.5.3 Continuous/One-Shot Control ............................................................................... 2033
16.5.4 32-Bit Counter and Phase Control .......................................................................... 2034
16.5.5 CAP1-CAP4 Registers ....................................................................................... 2035
16.5.6 Using SWSYNC with the ECAP Module ................................................................... 2035
16.5.7 Interrupt Control ............................................................................................... 2036
16.5.8 Shadow Load and Lockout Control ......................................................................... 2038
16.5.9 APWM Mode Operation ...................................................................................... 2038
16.6 Application of the ECAP Module ..................................................................................... 2039
16.6.1 Example 1 - Absolute Time-Stamp Operation Rising Edge Trigger .................................... 2039
16.6.2 Example 2 - Absolute Time-Stamp Operation Rising and Falling Edge Trigger ...................... 2042
16.6.3 Example 3 - Time Difference (Delta) Operation Rising Edge Trigger .................................. 2044
16.6.4 Example 4 - Time Difference (Delta) Operation Rising and Falling Edge Trigger .................... 2046
16.7 Application of the APWM Mode ....................................................................................... 2048
16.7.1 Example 1 - Simple PWM Generation (Independent Channel/s) ....................................... 2048
16.8 Registers ................................................................................................................. 2050
16.8.1 eCAP Base Addresses ....................................................................................... 2050
16.8.2 ECAP_REGS Registers ...................................................................................... 2051
17 Enhanced QEP (eQEP) ..................................................................................................... 2068
17.1 Introduction ............................................................................................................... 2069
17.3 Description ............................................................................................................... 2071
17.3.1 EQEP Inputs ................................................................................................... 2071

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17.3.2 Functional Description ........................................................................................ 2072

17.3.3 eQEP Memory Map ........................................................................................... 2073
17.4 Quadrature Decoder Unit (QDU) ...................................................................................... 2074
17.4.1 Position Counter Input Modes ............................................................................... 2074
17.4.2 eQEP Input Polarity Selection ............................................................................... 2077
17.4.3 Position-Compare Sync Output ............................................................................. 2077
17.5 Position Counter and Control Unit (PCCU) .......................................................................... 2077
17.5.1 Position Counter Operating Modes ......................................................................... 2077
17.5.2 Position Counter Latch ....................................................................................... 2079
17.5.3 Position Counter Initialization ................................................................................ 2081
17.5.4 eQEP Position-compare Unit ................................................................................ 2082
17.6 eQEP Edge Capture Unit .............................................................................................. 2083
17.7 eQEP Watchdog ......................................................................................................... 2087
17.8 Unit Timer Base ......................................................................................................... 2087
17.9 eQEP Interrupt Structure ............................................................................................... 2088
17.10 Registers ................................................................................................................. 2089
17.10.1 eQEP Base Addresses ..................................................................................... 2089
17.10.2 EQEP_REGS Registers .................................................................................... 2090
18 Serial Peripheral Interface (SPI) ........................................................................................ 2124
18.1 SPI Module Overview ................................................................................................... 2125
18.1.1 Features ........................................................................................................ 2125
18.1.2 CPU Interface .................................................................................................. 2125
18.2 System-Level Integration ............................................................................................... 2126
18.2.1 SPI Module Signals ........................................................................................... 2126
18.2.2 Configuring Device Pins ...................................................................................... 2127
18.2.3 SPI Interrupts .................................................................................................. 2127
18.2.4 DMA Support .................................................................................................. 2129
18.3 SPI Operation ............................................................................................................ 2130
18.3.1 Introduction to Operation ..................................................................................... 2130
18.3.2 Master Mode ................................................................................................... 2131
18.3.3 Slave Mode .................................................................................................... 2132
18.3.4 Data Format .................................................................................................... 2133
18.3.5 Baud Rate Selection ......................................................................................... 2134
18.3.6 SPI Clocking Schemes ....................................................................................... 2135
18.3.7 SPI FIFO Description ......................................................................................... 2136
18.3.8 SPI DMA Transfers ........................................................................................... 2137
18.3.9 SPI High-Speed Mode ........................................................................................ 2138
18.3.10 SPI 3-Wire Mode Description .............................................................................. 2138
18.4 Programming Procedure ............................................................................................... 2139
18.4.1 Initialization Upon Reset ..................................................................................... 2139
18.4.2 Configuring the SPI ........................................................................................... 2140
18.4.3 Configuring the SPI for High-Speed Mode ................................................................. 2140
18.4.4 Data Transfer Example ....................................................................................... 2141
18.4.5 SPI STEINV Bit in Digital Audio Transfers ................................................................. 2142
18.5 Registers ................................................................................................................. 2144
18.5.1 SPI Base Addresses .......................................................................................... 2144
18.5.2 SPI_REGS Registers ......................................................................................... 2145
19 Serial Communications Interface (SCI) .............................................................................. 2164
19.1 Enhanced SCI Module Overview ...................................................................................... 2165
19.2 Architecture .............................................................................................................. 2166
19.3 SCI Module Signal Summary .......................................................................................... 2167
19.5 Multiprocessor and Asynchronous Communication Modes........................................................ 2167

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19.6 SCI Programmable Data Format ...................................................................................... 2168

19.7 SCI Multiprocessor Communication .................................................................................. 2168
19.7.1 Recognizing the Address Byte .............................................................................. 2169
19.7.2 Controlling the SCI TX and RX Features .................................................................. 2169
19.7.3 Receipt Sequence............................................................................................. 2169
19.8 Idle-Line Multiprocessor Mode......................................................................................... 2169
19.8.1 Idle-Line Mode Steps ......................................................................................... 2170
19.8.2 Block Start Signal ............................................................................................. 2170
19.8.3 Wake-UP Temporary (WUT) Flag .......................................................................... 2170
19.8.4 Receiver Operation ........................................................................................... 2171
19.9 Address-Bit Multiprocessor Mode ..................................................................................... 2171
19.9.1 Sending an Address .......................................................................................... 2171
19.10 SCI Communication Format ........................................................................................... 2172
19.10.1 Receiver Signals in Communication Modes.............................................................. 2173
19.10.2 Transmitter Signals in Communication Modes........................................................... 2173
19.11 SCI Port Interrupts ...................................................................................................... 2174
19.12 SCI Baud Rate Calculations ........................................................................................... 2174
19.13 SCI Enhanced Features................................................................................................ 2175
19.13.1 SCI FIFO Description ....................................................................................... 2175
19.13.2 SCI Auto-Baud ............................................................................................... 2176
19.13.3 Autobaud-Detect Sequence ................................................................................ 2177
19.14 Registers ................................................................................................................. 2178
19.14.1 SCI Base Addresses ........................................................................................ 2178
19.14.2 SCI_REGS Registers ....................................................................................... 2179
20 Inter-Integrated Circuit Module (I2C) .................................................................................. 2199
20.1 Introduction to the I2C Module ........................................................................................ 2200
20.1.1 Features ........................................................................................................ 2200
20.1.2 Features Not Supported ...................................................................................... 2200
20.1.3 Functional Overview .......................................................................................... 2201
20.1.4 Clock Generation .............................................................................................. 2202
20.1.5 I2C Clock Divider Registers (I2CCLKL and I2CCLKH) .................................................. 2203
20.3 I2C Module Operational Details ....................................................................................... 2204
20.3.1 Input and Output Voltage Levels ............................................................................ 2204
20.3.2 Data Validity ................................................................................................... 2204
20.3.3 Operating Modes .............................................................................................. 2204
20.3.4 I2C Module START and STOP Conditions ................................................................ 2205
20.3.5 Serial Data Formats........................................................................................... 2206
20.3.6 NACK Bit Generation ......................................................................................... 2208
20.3.7 Clock Synchronization ........................................................................................ 2209
20.3.8 Arbitration ...................................................................................................... 2209
20.3.9 Digital Loopback Mode ....................................................................................... 2210
20.4 Interrupt Requests Generated by the I2C Module .................................................................. 2211
20.4.1 Basic I2C Interrupt Requests ................................................................................ 2211
20.4.2 I2C FIFO Interrupts ........................................................................................... 2212
20.5 Resetting or Disabling the I2C Module ............................................................................... 2213
20.6 Registers ................................................................................................................. 2214
20.6.1 I2C Base Addresses .......................................................................................... 2214
20.6.2 I2C_REGS Registers ......................................................................................... 2215
21 Multichannel Buffered Serial Port (McBSP) ........................................................................ 2239
21.1 Overview.................................................................................................................. 2240
21.1.1 Features of the McBSPs ..................................................................................... 2240
21.1.2 McBSP Pins/Signals .......................................................................................... 2241

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21.3 McBSP Operation ....................................................................................................... 2242
21.3.1 Data Transfer Process of McBSPs ......................................................................... 2243
21.3.2 Companding (Compressing and Expanding) Data........................................................ 2244
21.3.3 Clocking and Framing Data .................................................................................. 2245
21.3.4 Frame Phases ................................................................................................. 2248
21.3.5 McBSP Reception ............................................................................................. 2250
21.3.6 McBSP Transmission ......................................................................................... 2251
21.3.7 Interrupts and DMA Events Generated by a McBSP ..................................................... 2252
21.4 McBSP Sample Rate Generator ...................................................................................... 2252
21.4.1 Block Diagram ................................................................................................. 2253
21.4.2 Frame Synchronization Generation in the Sample Rate Generator .................................... 2256
21.4.3 Synchronizing Sample Rate Generator Outputs to an External Clock ................................. 2256
21.4.4 Reset and Initialization Procedure for the Sample Rate Generator .................................... 2258
21.5 McBSP Exception/Error Conditions ................................................................................... 2259
21.5.1 Types of Errors ................................................................................................ 2259
21.5.2 Overrun in the Receiver ...................................................................................... 2259
21.5.3 Unexpected Receive Frame-Synchronization Pulse ..................................................... 2261
21.5.4 Overwrite in the Transmitter ................................................................................. 2263
21.5.5 Underflow in the Transmitter ................................................................................. 2264
21.5.6 Unexpected Transmit Frame-Synchronization Pulse ..................................................... 2265
21.6 Multichannel Selection Modes ......................................................................................... 2267
21.6.1 Channels, Blocks, and Partitions ............................................................................ 2267
21.6.2 Multichannel Selection ........................................................................................ 2268
21.6.3 Configuring a Frame for Multichannel Selection .......................................................... 2268
21.6.4 Using Two Partitions .......................................................................................... 2268
21.6.5 Using Eight Partitions ......................................................................................... 2270
21.6.6 Receive Multichannel Selection Mode...................................................................... 2271
21.6.7 Transmit Multichannel Selection Modes ................................................................... 2271
21.6.8 Using Interrupts Between Block Transfers ................................................................. 2273
21.7 SPI Operation Using the Clock Stop Mode .......................................................................... 2274
21.7.1 SPI Protocol .................................................................................................... 2274
21.7.2 Clock Stop Mode .............................................................................................. 2275
21.7.3 Bits Used to Enable and Configure the Clock Stop Mode ............................................... 2275
21.7.4 Clock Stop Mode Timing Diagrams ......................................................................... 2276
21.7.5 Procedure for Configuring a McBSP for SPI Operation .................................................. 2278
21.7.6 McBSP as the SPI Master ................................................................................... 2278
21.7.7 McBSP as an SPI Slave...................................................................................... 2280
21.8 Receiver Configuration ................................................................................................. 2281
21.8.1 Programming the McBSP Registers for the Desired Receiver Operation ............................. 2281
21.8.2 Resetting and Enabling the Receiver ....................................................................... 2282
21.8.3 Set the Receiver Pins to Operate as McBSP Pins ....................................................... 2282
21.8.4 Enable/Disable the Digital Loopback Mode ................................................................ 2283
21.8.5 Enable/Disable the Clock Stop Mode....................................................................... 2283
21.8.6 Enable/Disable the Receive Multichannel Selection Mode .............................................. 2284
21.8.7 Choose One or Two Phases for the Receive Frame ..................................................... 2284
21.8.8 Set the Receive Word Length(s) ............................................................................ 2285
21.8.9 Set the Receive Frame Length .............................................................................. 2285
21.8.10 Enable/Disable the Receive Frame-Synchronization Ignore Function ................................ 2286
21.8.11 Set the Receive Companding Mode ...................................................................... 2287
21.8.12 Set the Receive Data Delay ................................................................................ 2288
21.8.13 Set the Receive Sign-Extension and Justification Mode ............................................... 2290
21.8.14 Set the Receive Interrupt Mode ............................................................................ 2291

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21.8.15 Set the Receive Frame-Synchronization Mode .......................................................... 2291

21.8.16 Set the Receive Frame-Synchronization Polarity........................................................ 2293
21.8.17 Set the Receive Clock Mode ............................................................................... 2295
21.8.18 Set the Receive Clock Polarity ............................................................................. 2296
21.8.19 Set the SRG Clock Divide-Down Value................................................................... 2298
21.8.20 Set the SRG Clock Synchronization Mode ............................................................... 2298
21.8.21 Set the SRG Clock Mode (Choose an Input Clock) ..................................................... 2299
21.8.22 Set the SRG Input Clock Polarity .......................................................................... 2300
21.9 Transmitter Configuration .............................................................................................. 2300
21.9.1 Programming the McBSP Registers for the Desired Transmitter Operation .......................... 2300
21.9.2 Resetting and Enabling the Transmitter .................................................................... 2301
21.9.3 Set the Transmitter Pins to Operate as McBSP Pins .................................................... 2302
21.9.4 Enable/Disable the Digital Loopback Mode ................................................................ 2302
21.9.5 Enable/Disable the Clock Stop Mode....................................................................... 2302
21.9.6 Enable/Disable Transmit Multichannel Selection ......................................................... 2303
21.9.7 Choose One or Two Phases for the Transmit Frame .................................................... 2305
21.9.8 Set the Transmit Word Length(s) ........................................................................... 2305
21.9.9 Set the Transmit Frame Length ............................................................................. 2306
21.9.10 Enable/Disable the Transmit Frame-Synchronization Ignore Function ............................... 2307
21.9.11 Set the Transmit Companding Mode ...................................................................... 2308
21.9.12 Set the Transmit Data Delay ............................................................................... 2309
21.9.13 Set the Transmit DXENA Mode ............................................................................ 2311
21.9.14 Set the Transmit Interrupt Mode ........................................................................... 2311
21.9.15 Set the Transmit Frame-Synchronization Mode ......................................................... 2312
21.9.16 Set the Transmit Frame-Synchronization Polarity ....................................................... 2313
21.9.17 Set the SRG Frame-Synchronization Period and Pulse Width ........................................ 2314
21.9.18 Set the Transmit Clock Mode .............................................................................. 2315
21.9.19 Set the Transmit Clock Polarity ............................................................................ 2315
21.10 Emulation and Reset Considerations ................................................................................ 2316
21.10.1 McBSP Emulation Mode .................................................................................... 2317
21.10.2 Resetting and Initializing McBSPs ......................................................................... 2317
21.11 Data Packing Examples ................................................................................................ 2319
21.11.1 Data Packing Using Frame Length and Word Length .................................................. 2319
21.11.2 Data Packing Using Word Length and the Frame-Synchronization Ignore Function ............... 2321
21.12 Interrupt Generation .................................................................................................... 2321
21.12.1 McBSP Receive Interrupt Generation ..................................................................... 2322
21.12.2 McBSP Transmit Interrupt Generation .................................................................... 2322
21.12.3 Error Flags ................................................................................................... 2323
21.13 McBSP Modes........................................................................................................... 2323
21.14 McBSP Registers ...................................................................................................... 2325
21.14.1 McBSP Base Addresses .................................................................................... 2325
21.14.2 Data Receive Registers (DRR[1,2]) ....................................................................... 2326
21.14.3 Data Transmit Registers (DXR[1,2]) ...................................................................... 2326
21.14.4 Serial Port Control Registers (SPCR[1,2]) ............................................................... 2327
21.14.5 Receive Control Registers (RCR[1, 2]) .................................................................. 2332
21.14.6 Transmit Control Registers (XCR1 and XCR2) .......................................................... 2334
21.14.7 Sample Rate Generator Registers (SRGR1 and SRGR2) ............................................. 2337
21.14.8 Multichannel Control Registers (MCR[1,2]) .............................................................. 2339
21.14.9 Pin Control Register (PCR) ................................................................................. 2344
21.14.10 Receive Channel Enable Registers (RCERA, RCERB, RCERC, RCERD, RCERE, RCERF,
RCERG, RCERH) .............................................................................................. 2346
21.14.11 Transmit Channel Enable Registers (XCERA, XCERB, XCERC, XCERD, XCERE, XCERF,
XCERG, XCERH) .............................................................................................. 2348
21.14.12 McBSP Interrupt Enable Register ........................................................................ 2350

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22 Controller Area Network (CAN) ......................................................................................... 2351

22.1 Overview.................................................................................................................. 2352
22.1.1 Features ....................................................................................................... 2352
22.1.2 Functional Description ....................................................................................... 2352
22.1.3 Block Diagram ................................................................................................ 2353
22.3 Address/Data Bus Bridge .............................................................................................. 2354
22.4 Operating Modes ........................................................................................................ 2355
22.4.1 Initialization .................................................................................................... 2355
22.4.2 CAN Message Transfer (Normal Operation) .............................................................. 2356
22.4.3 Test Modes .................................................................................................... 2357
22.5 Multiple Clock Source .................................................................................................. 2360
22.6 Interrupt Functionality .................................................................................................. 2360
22.6.1 Message Object Interrupts .................................................................................. 2360
22.6.2 Status Change Interrupts .................................................................................... 2360
22.6.3 Error Interrupts ................................................................................................ 2360
22.6.4 PIE Nomenclature for DCAN Interrupts .................................................................... 2361
22.7 Parity Check Mechanism .............................................................................................. 2361
22.7.1 Behavior on Parity Error ..................................................................................... 2361
22.8 Debug Mode ............................................................................................................ 2361
22.9 Module Initialization .................................................................................................... 2362
22.10 Configuration of Message Objects ................................................................................... 2362
22.10.1 Configuration of a Transmit Object for Data Frames ................................................... 2362
22.10.2 Configuration of a Transmit Object for Remote Frames ............................................... 2363
22.10.3 Configuration of a Single Receive Object for Data Frames ........................................... 2363
22.10.4 Configuration of a Single Receive Object for Remote Frames ....................................... 2363
22.10.5 Configuration of a FIFO Buffer ............................................................................ 2364
22.11 Message Handling ..................................................................................................... 2364
22.11.1 Message Handler Overview ............................................................................... 2364
22.11.2 Receive/Transmit Priority .................................................................................. 2364
22.11.3 Transmission of Messages in Event Driven CAN Communication ................................... 2365
22.11.4 Updating a Transmit Object ............................................................................... 2365
22.11.5 Changing a Transmit Object ............................................................................... 2365
22.11.6 Acceptance Filtering of Received Messages ............................................................ 2366
22.11.7 Reception of Data Frames ................................................................................. 2366
22.11.8 Reception of Remote Frames ............................................................................. 2366
22.11.9 Reading Received Messages ............................................................................. 2367
22.11.10 Requesting New Data for a Receive Object ........................................................... 2367
22.11.11 Storing Received Messages in FIFO Buffers .......................................................... 2367
22.11.12 Reading from a FIFO Buffer ............................................................................. 2367
22.12 CAN Bit Timing ......................................................................................................... 2368
22.12.1 Bit Time and Bit Rate ....................................................................................... 2369
22.12.2 Configuration of the CAN Bit Timing ..................................................................... 2373
22.13 Message Interface Register Sets .................................................................................... 2376
22.13.1 Message Interface Register Sets 1 and 2 ............................................................... 2377
22.13.2 IF3 Register Set ............................................................................................. 2378
22.14 Message RAM .......................................................................................................... 2378
22.14.1 Structure of Message Objects ............................................................................. 2378
22.14.2 Addressing Message Objects in RAM ................................................................... 2380
22.14.3 Message RAM Representation in Debug Mode ........................................................ 2381
22.15 Registers ................................................................................................................. 2383
22.15.1 CAN Base Addresses ....................................................................................... 2383
22.15.2 CAN_REGS Registers ...................................................................................... 2384

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23 Universal Serial Bus (USB) Controller................................................................................ 2445

23.1 Introduction ............................................................................................................... 2446
23.2 Features .................................................................................................................. 2446
23.2.1 Block Diagram ................................................................................................. 2446
23.2.2 Signal Description ............................................................................................. 2447
23.2.3 VBus Recommendations ..................................................................................... 2447
23.3 Functional Description .................................................................................................. 2448
23.3.1 Operation as a Device ........................................................................................ 2448
23.3.2 Operation as a Host........................................................................................... 2452
23.3.3 DMA Operation ................................................................................................ 2455
23.3.4 Address/Data Bus Bridge .................................................................................... 2455
23.4 Initialization and Configuration......................................................................................... 2457
23.4.1 Pin Configuration .............................................................................................. 2457
23.4.2 Endpoint Configuration ....................................................................................... 2457
23.5 Register Map ............................................................................................................. 2458
23.6 Register Descriptions ................................................................................................... 2473
23.6.1 USB Device Functional Address Register (USBFADDR), offset 0x000................................ 2473
23.6.2 USB Power Management Register (USBPOWER), offset 0x001 ....................................... 2474
23.6.3 USB Transmit Interrupt Status Register (USBTXIS), offset 0x002 ..................................... 2476
23.6.4 USB Receive Interrupt Status Register (USBRXIS), offset 0x004 ...................................... 2478
23.6.5 USB Transmit Interrupt Enable Register (USBTXIE), offset 0x006 .................................... 2480
23.6.6 USB Receive Interrupt Enable Register (USBRXIE), offset 0x008 ..................................... 2482
23.6.7 USB General Interrupt Status Register (USBIS), offset 0x00A ......................................... 2484
23.6.8 USB Interrupt Enable Register (USBIE), offset 0x00B ................................................... 2486
23.6.9 USB Frame Value Register (USBFRAME), offset 0x00C ................................................ 2488
23.6.10 USB Endpoint Index Register (USBEPIDX), offset 0x00E ............................................. 2488
23.6.11 USB Test Mode Register (USBTEST), offset 0x00F .................................................... 2489
23.6.12 USB FIFO Endpoint n Register (USBFIFO[0]-USBFIFO[15]) .......................................... 2491
23.6.13 USB Device Control Register (USBDEVCTL), offset 0x060 ........................................... 2492
23.6.14 USB Transmit Dynamic FIFO Sizing Register (USBTXFIFOSZ), offset 0x062...................... 2494
23.6.15 USB Receive Dynamic FIFO Sizing Register (USBRXFIFOSZ), offset 0x063 ...................... 2495
23.6.16 USB Transmit FIFO Start Address Register (USBTXFIFOADD), offset 0x064...................... 2496
23.6.17 USB Receive FIFO Start Address Register (USBRXFIFOADD), offset 0x066 ...................... 2497
23.6.18 USB Connect Timing Register (USBCONTIM), offset 0x07A .......................................... 2498
23.6.19 USB Full-Speed Last Transaction to End of Frame Timing Register (USBFSEOF), offset
0x07D ............................................................................................................ 2499
23.6.20 USB Low-Speed Last Transaction to End of Frame Timing Register (USBLSEOF), offset
0x07E ............................................................................................................ 2499
23.6.21 USB Transmit Functional Address Endpoint n Registers (USBTXFUNCADDR[0]-
USBTXFUNCADDR[15]) ...................................................................................... 2500
23.6.22 USB Transmit Hub Address Endpoint n Registers (USBTXHUBADDR[0]-
USBTXHUBADDR[15]) ........................................................................................ 2501
23.6.23 USB Transmit Hub Port Endpoint n Registers (USBTXHUBPORT[0]-USBTXHUBPORT[15]) ... 2502
23.6.24 USB Receive Functional Address Endpoint n Registers (USBRXFUNCADDR[1]-
USBRXFUNCADDR[15]) ...................................................................................... 2503
23.6.25 USB Receive Hub Address Endpoint n Registers (USBRXHUBADDR[1]-
USBRXHUBADDR[15]) ........................................................................................ 2504
23.6.26 USB Receive Hub Port Endpoint n Registers (USBRXHUBPORT[1]-USBRXHUBPORT[15]) .... 2505
23.6.27 USB Maximum Transmit Data Endpoint n Registers (USBTXMAXP[1]-USBTXMAXP[15]) ....... 2506
23.6.28 USB Control and Status Endpoint 0 Low Register (USBCSRL0), offset 0x102 ..................... 2507
23.6.29 USB Control and Status Endpoint 0 High Register (USBCSRH0), offset 0x103 .................... 2509
23.6.30 USB Receive Byte Count Endpoint 0 Register (USBCOUNT0), offset 0x108 ....................... 2510
23.6.31 USB Type Endpoint 0 Register (USBTYPE0), offset 0x10A ........................................... 2510
23.6.32 USB NAK Limit Register (USBNAKLMT), offset 0x10B ................................................ 2511
23.6.33 USB Transmit Control and Status Endpoint n Low Register (USBTXCSRL[1]-
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USBTXCSRL[15]) .............................................................................................. 2512

23.6.34 USB Transmit Control and Status Endpoint n High Register (USBTXCSRH[1]-
USBTXCSRH[15]) .............................................................................................. 2515
23.6.35 USB Maximum Receive Data Endpoint n Registers (USBRXMAXP[1]-USBRXMAXP[15]) ....... 2517
23.6.36 USB Receive Control and Status Endpoint n Low Register (USBRXCSRL[1]-
USBRXCSRL[15)] .............................................................................................. 2518
23.6.37 USB Receive Control and Status Endpoint n High Register (USBRXCSRH[1]-
USBRXCSRH[15]) ............................................................................................. 2520
23.6.38 USB Receive Byte Count Endpoint n Registers (USBRXCOUNT[1]-USBRXCOUNT[15]) ........ 2522
23.6.39 USB Host Transmit Configure Type Endpoint n Register (USBTXTYPE[1]-USBTXTYPE[15]) ... 2523
23.6.40 USB Host Transmit Interval Endpoint n Register (USBTXINTERVAL[1]USBTXINTERVAL[15]) . 2524
23.6.41 USB Host Configure Receive Type Endpoint n Register (USBRXTYPE[1]-USBRXTYPE[15]) ... 2525
23.6.42 USB Host Receive Polling Interval Endpoint n Register (USBRXINTERVAL[1]-
USBRXINTERVAL[15]) ........................................................................................ 2526
23.6.43 USB Request Packet Count in Block Transfer Endpoint n Registers (USBRQPKTCOUNT[1]-
USBRQPKTCOUNT[15]) ...................................................................................... 2527
23.6.44 USB Receive Double Packet Buffer Disable Register (USBRXDPKTBUFDIS), offset 0x340 ..... 2528
23.6.45 USB Transmit Double Packet Buffer Disable Register (USBTXDPKTBUFDIS), offset 0x342 .... 2530
23.6.46 USB External Power Control Register (USBEPC), offset 0x400 ...................................... 2531
23.6.47 USB External Power Control Raw Interrupt Status Register (USBEPCRIS), offset 0x404 ........ 2533
23.6.48 USB External Power Control Interrupt Mask Register (USBEPCIM), offset 0x408 ................. 2534
23.6.49 USB External Power Control Interrupt Status and Clear Register (USBEPCISC), offset 0x40C . 2535
23.6.50 USB Device RESUME Raw Interrupt Status Register (USBDRRIS), offset 0x410 ................. 2536
23.6.51 USB Device RESUME Raw Interrupt Mask Register (USBDRIM), offset 0x414 .................... 2537
23.6.52 USB Device RESUME Interrupt Status and Clear Register (USBDRISC), offset 0x418 ........... 2538
23.6.53 USB General-Purpose Control and Status Register (USBGPCS), offset 0x41C .................... 2539
23.6.54 USB DMA Select Register (USBDMASEL), offset 0x450 .............................................. 2540
24 Universal Parallel Port (uPP) ............................................................................................ 2542
24.1 Introduction ............................................................................................................... 2543
24.1.1 Features Supported ........................................................................................... 2543
24.3 Functional Description .................................................................................................. 2544
24.3.1 Functional Block Diagram .................................................................................... 2544
24.3.2 Data Flow ...................................................................................................... 2544
24.3.3 Clock Generation and Control ............................................................................... 2545
24.4 IO Interface and System Requirements .............................................................................. 2547
24.4.1 Pin Multiplexing ................................................................................................ 2547
24.4.2 Internal DMA Controller Description ........................................................................ 2547
24.4.3 Protocol Description .......................................................................................... 2549
24.4.4 Data Format .................................................................................................... 2552
24.4.5 Reset Considerations ......................................................................................... 2552
24.4.6 Interrupt Support .............................................................................................. 2553
24.4.7 Emulation Considerations .................................................................................... 2554
24.4.8 Transmit and Receive FIFOs ................................................................................ 2554
24.4.9 Transmit and Receive Data (MSG) RAM .................................................................. 2554
24.4.10 Initialization and Operation ................................................................................. 2555
24.5 Registers ................................................................................................................. 2557
24.5.1 UPP Base Addresses ......................................................................................... 2557
24.5.2 UPP_REGS Registers ........................................................................................ 2558
25 External Memory Interface (EMIF) ..................................................................................... 2593
25.1 Introduction ............................................................................................................... 2594
25.1.1 Purpose of the Peripheral .................................................................................... 2595
25.1.2 Features ........................................................................................................ 2595
25.1.3 Functional Block Diagram .................................................................................... 2595

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25.3 EMIF Module Architecture ............................................................................................. 2596
25.3.1 EMIF Clock Control ........................................................................................... 2596
25.3.2 EMIF Requests ................................................................................................ 2596
25.3.3 EMIF Signal Descriptions .................................................................................... 2597
25.3.4 EMIF Signal Multiplexing Control ........................................................................... 2598
25.3.5 SDRAM Controller and Interface ............................................................................ 2598
25.3.6 Asynchronous Controller and Interface .................................................................... 2611
25.3.7 Data Bus Parking.............................................................................................. 2623
25.3.8 Reset and Initialization Considerations ..................................................................... 2623
25.3.9 Interrupt Support .............................................................................................. 2623
25.3.10 DMA Event Support ......................................................................................... 2624
25.3.11 EMIF Signal Multiplexing ................................................................................... 2624
25.3.12 Memory Map ................................................................................................. 2624
25.3.13 Priority and Arbitration ...................................................................................... 2625
25.3.14 System Considerations ..................................................................................... 2626
25.3.15 Power Management ......................................................................................... 2627
25.3.16 Emulation Considerations .................................................................................. 2627
25.4 Example Configuration ................................................................................................. 2628
25.4.1 Hardware Interface ............................................................................................ 2628
25.4.2 Software Configuration ....................................................................................... 2628
25.5 Registers ................................................................................................................. 2636
25.5.1 EMIF Base Addresses ........................................................................................ 2636
25.5.2 EMIF_REGS Registers ....................................................................................... 2637
25.5.3 EMIF1_CONFIG_REGS Registers ......................................................................... 2657
25.5.4 EMIF2_CONFIG_REGS Registers ......................................................................... 2662
Revision History ...................................................................................................................... 2666

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List of Figures
2-1. Device Interrupt Architecture ............................................................................................. 90
2-2. Interrupt Propagation Path ................................................................................................ 92
2-3. Missing Clock Detection Logic .......................................................................................... 105
2-4. ERRORSTS Pin Diagram ............................................................................................... 107
2-5. Clocking System .......................................................................................................... 108
2-6. Single-ended 3.3V External Clock ...................................................................................... 109
2-7. External Crystal ........................................................................................................... 110
2-8. External Resonator ....................................................................................................... 110
2-9. AUXCLKIN ................................................................................................................. 110
2-10. CPU-Timers ............................................................................................................... 117
2-11. CPU-Timer Interrupts Signals and Output Signal .................................................................... 118
2-12. CPU Watchdog Timer Module ......................................................................................... 119
2-13. Memory Architecture ..................................................................................................... 125
2-14. Arbitration Scheme on Global Shared Memories ..................................................................... 127
2-15. Arbitration Scheme on Local Shared Memories ...................................................................... 128
2-16. FMC Interface with Core, Bank and Pump ............................................................................ 135
2-17. Flash Prefetch Mode ..................................................................................................... 138
2-18. ECC Logic Inputs and Outputs.......................................................................................... 141
2-19. Flash Pump Semaphore (PUMPREQUEST) States and State Transitions ....................................... 145
2-20. Clock Configuration Semaphore (CLKSEM) State Transitions ..................................................... 145
2-21. Storage of Zone-Select Bits in OTP ................................................................................... 149
2-22. Location of Zone-Select Block Based on Link-Pointer ............................................................... 150
2-23. CSM Password Match Flow (PMF) ..................................................................................... 154
2-24. ECSL Password Match Flow (PMF) .................................................................................... 156
2-25. TIM Register ............................................................................................................... 161
2-26. PRD Register .............................................................................................................. 162
2-27. TCR Register .............................................................................................................. 163
2-28. TPR Register .............................................................................................................. 165
2-29. TPRH Register ............................................................................................................ 166
2-30. PIECTRL Register ........................................................................................................ 169
2-31. PIEACK Register.......................................................................................................... 170
2-32. PIEIER1 Register ......................................................................................................... 171
2-33. PIEIFR1 Register ......................................................................................................... 173
2-34. PIEIER2 Register ......................................................................................................... 175
2-35. PIEIFR2 Register ......................................................................................................... 177
2-36. PIEIER3 Register ......................................................................................................... 179
2-37. PIEIFR3 Register ......................................................................................................... 181
2-38. PIEIER4 Register ......................................................................................................... 183
2-39. PIEIFR4 Register ......................................................................................................... 185
2-40. PIEIER5 Register ......................................................................................................... 187
2-41. PIEIFR5 Register ......................................................................................................... 189
2-42. PIEIER6 Register ......................................................................................................... 191
2-43. PIEIFR6 Register ......................................................................................................... 193
2-44. PIEIER7 Register ......................................................................................................... 195
2-45. PIEIFR7 Register ......................................................................................................... 197
2-46. PIEIER8 Register ......................................................................................................... 199
2-47. PIEIFR8 Register ......................................................................................................... 201
18 List of Figures SPRUHM8G – December 2013 – Revised September 2017

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2-48. PIEIER9 Register ......................................................................................................... 203

2-49. PIEIFR9 Register ......................................................................................................... 205
2-50. PIEIER10 Register........................................................................................................ 207
2-51. PIEIFR10 Register ........................................................................................................ 209
2-52. PIEIER11 Register........................................................................................................ 211
2-53. PIEIFR11 Register ........................................................................................................ 213
2-54. PIEIER12 Register........................................................................................................ 215
2-55. PIEIFR12 Register ........................................................................................................ 217
2-56. SCSR Register ............................................................................................................ 220
2-57. WDCNTR Register ....................................................................................................... 221
2-58. WDKEY Register.......................................................................................................... 222
2-59. WDCR Register ........................................................................................................... 223
2-60. WDWCR Register ........................................................................................................ 224
2-61. NMICFG Register ......................................................................................................... 226
2-62. NMIFLG Register ......................................................................................................... 227
2-63. NMIFLGCLR Register .................................................................................................... 229
2-64. NMIFLGFRC Register .................................................................................................... 232
2-65. NMIWDCNT Register .................................................................................................... 234
2-66. NMIWDPRD Register .................................................................................................... 235
2-67. NMISHDFLG Register.................................................................................................... 236
2-68. XINT1CR Register ........................................................................................................ 239
2-69. XINT2CR Register ........................................................................................................ 240
2-70. XINT3CR Register ........................................................................................................ 241
2-71. XINT4CR Register ........................................................................................................ 242
2-72. XINT5CR Register ........................................................................................................ 243
2-73. XINT1CTR Register ...................................................................................................... 244
2-76. CLA1TASKSRCSELLOCK Register ................................................................................... 248
2-77. DMACHSRCSELLOCK Register ....................................................................................... 249
2-78. CLA1TASKSRCSEL1 Register ......................................................................................... 250
2-79. CLA1TASKSRCSEL2 Register ......................................................................................... 251
2-80. DMACHSRCSEL1 Register ............................................................................................. 252
2-81. DMACHSRCSEL2 Register ............................................................................................. 253
2-82. PUMPREQUEST Register............................................................................................... 255
2-83. DEVCFGLOCK1 Register ............................................................................................... 258
2-84. PARTIDL_1 Register ..................................................................................................... 260
2-85. PARTIDH_1 Register..................................................................................................... 262
2-86. REVID Register ........................................................................................................... 263
2-87. DC0_1 Register ........................................................................................................... 264
2-88. DC1_1 Register ........................................................................................................... 265
2-89. DC2_1 Register ........................................................................................................... 266
2-90. DC3_1 Register ........................................................................................................... 267
2-91. DC4_1 Register ........................................................................................................... 269
2-92. DC5_1 Register ........................................................................................................... 270
2-93. DC6_1 Register ........................................................................................................... 271
2-94. DC7_1 Register ........................................................................................................... 272
2-95. DC8_1 Register ........................................................................................................... 273
2-96. DC9_1 Register ........................................................................................................... 274
SPRUHM8G – December 2013 – Revised September 2017 List of Figures 19

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2-97. DC10_1 Register.......................................................................................................... 275

2-98. DC11_1 Register.......................................................................................................... 276
2-99. DC12_1 Register.......................................................................................................... 277
2-100. DC13_1 Register.......................................................................................................... 278
2-101. DC14_1 Register.......................................................................................................... 279
2-102. DC15_1 Register.......................................................................................................... 280
2-103. DC17_1 Register.......................................................................................................... 282
2-104. DC18_1 Register.......................................................................................................... 283
2-105. DC19_1 Register.......................................................................................................... 284
2-106. DC20_1 Register.......................................................................................................... 285
2-107. PERCNF1_1 Register .................................................................................................... 287
2-108. FUSEERR Register....................................................................................................... 288
2-109. SOFTPRES0 Register ................................................................................................... 289
2-118. SOFTPRES11 Register .................................................................................................. 299
2-122. CPUSEL0 Register ....................................................................................................... 303
2-123. CPUSEL1 Register ....................................................................................................... 305
2-124. CPUSEL2 Register ....................................................................................................... 306
2-125. CPUSEL3 Register ....................................................................................................... 307
2-126. CPUSEL4 Register ....................................................................................................... 308
2-127. CPUSEL5 Register ....................................................................................................... 309
2-128. CPUSEL6 Register ....................................................................................................... 310
2-129. CPUSEL7 Register ....................................................................................................... 311
2-130. CPUSEL8 Register ....................................................................................................... 312
2-131. CPUSEL9 Register ....................................................................................................... 313
2-132. CPUSEL11 Register ...................................................................................................... 314
2-133. CPUSEL12 Register ...................................................................................................... 316
2-134. CPUSEL14 Register ...................................................................................................... 318
2-135. CPU2RESCTL Register.................................................................................................. 319
2-136. RSTSTAT Register ....................................................................................................... 320
2-137. LPMSTAT Register ....................................................................................................... 321
2-138. SYSDBGCTL Register ................................................................................................... 322
2-139. CLKSEM Register ........................................................................................................ 325
2-140. CLKCFGLOCK1 Register ................................................................................................ 326
2-141. CLKSRCCTL1 Register .................................................................................................. 328
2-144. SYSPLLCTL1 Register ................................................................................................... 333
2-145. SYSPLLMULT Register .................................................................................................. 334

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2-146. SYSPLLSTS Register .................................................................................................... 335

2-147. AUXPLLCTL1 Register .................................................................................................. 336
2-148. AUXPLLMULT Register .................................................................................................. 337
2-149. AUXPLLSTS Register .................................................................................................... 338
2-150. SYSCLKDIVSEL Register ............................................................................................... 339
2-151. AUXCLKDIVSEL Register ............................................................................................... 340
2-152. PERCLKDIVSEL Register ............................................................................................... 341
2-153. XCLKOUTDIVSEL Register ............................................................................................. 342
2-154. LOSPCP Register ........................................................................................................ 343
2-155. MCDCR Register ......................................................................................................... 344
2-156. X1CNT Register........................................................................................................... 345
2-157. CPUSYSLOCK1 Register ............................................................................................... 348
2-158. HIBBOOTMODE Register ............................................................................................... 351
2-159. IORESTOREADDR Register ............................................................................................ 352
2-160. PIEVERRADDR Register ................................................................................................ 353
2-161. PCLKCR0 Register ....................................................................................................... 354
2-162. PCLKCR1 Register ....................................................................................................... 356
2-163. PCLKCR2 Register ....................................................................................................... 357
2-164. PCLKCR3 Register ....................................................................................................... 359
2-165. PCLKCR4 Register ....................................................................................................... 361
2-166. PCLKCR6 Register ....................................................................................................... 362
2-167. PCLKCR7 Register ....................................................................................................... 363
2-168. PCLKCR8 Register ....................................................................................................... 364
2-169. PCLKCR9 Register ....................................................................................................... 365
2-170. PCLKCR10 Register ..................................................................................................... 366
2-171. PCLKCR11 Register ..................................................................................................... 367
2-172. PCLKCR12 Register ..................................................................................................... 368
2-173. PCLKCR13 Register ..................................................................................................... 369
2-174. PCLKCR14 Register ..................................................................................................... 370
2-175. PCLKCR16 Register ..................................................................................................... 372
2-176. SECMSEL_1 Register.................................................................................................... 373
2-177. LPMCR Register .......................................................................................................... 374
2-178. GPIOLPMSEL0 Register................................................................................................. 376
2-179. GPIOLPMSEL1 Register................................................................................................. 379
2-180. TMR2CLKCTL Register .................................................................................................. 382
2-181. RESC Register ............................................................................................................ 384
2-182. ROMPREFETCH Register............................................................................................... 387
2-183. Z1OTP_LINKPOINTER1 Register ...................................................................................... 389
2-186. Z1OTP_PSWDLOCK Register .......................................................................................... 392
2-187. Z1OTP_CRCLOCK Register ............................................................................................ 393
2-188. Z1OTP_BOOTCTRL Register........................................................................................... 394
2-192. Z2OTP_PSWDLOCK Register .......................................................................................... 399
2-193. Z2OTP_CRCLOCK Register ............................................................................................ 400
2-194. Z2OTP_BOOTCTRL Register........................................................................................... 401

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2-195. Z1_LINKPOINTER Register ............................................................................................. 403

2-196. Z1_OTPSECLOCK Register ............................................................................................ 404
2-197. Z1_BOOTCTRL Register ................................................................................................ 405
2-198. Z1_LINKPOINTERERR Register ....................................................................................... 406
2-199. Z1_CSMKEY0 Register .................................................................................................. 407
2-203. Z1_CR Register ........................................................................................................... 411
2-204. Z1_GRABSECTR Register .............................................................................................. 412
2-205. Z1_GRABRAMR Register ............................................................................................... 415
2-206. Z1_EXEONLYSECTR Register ......................................................................................... 417
2-207. Z1_EXEONLYRAMR Register .......................................................................................... 420
2-208. Z2_LINKPOINTER Register ............................................................................................. 423
2-209. Z2_OTPSECLOCK Register ............................................................................................ 424
2-210. Z2_BOOTCTRL Register ................................................................................................ 425
2-211. Z2_LINKPOINTERERR Register ....................................................................................... 426
2-216. Z2_CR Register ........................................................................................................... 431
2-217. Z2_GRABSECTR Register .............................................................................................. 432
2-218. Z2_GRABRAMR Register ............................................................................................... 435
2-219. Z2_EXEONLYSECTR Register ......................................................................................... 437
2-220. Z2_EXEONLYRAMR Register .......................................................................................... 440
2-221. FLSEM Register .......................................................................................................... 443
2-222. SECTSTAT Register ..................................................................................................... 444
2-223. RAMSTAT Register....................................................................................................... 447
2-224. DxLOCK Register ......................................................................................................... 451
2-225. DxCOMMIT Register ..................................................................................................... 452
2-226. DxACCPROT0 Register ................................................................................................. 453
2-227. DxTEST Register ......................................................................................................... 454
2-228. DxINIT Register ........................................................................................................... 455
2-229. DxINITDONE Register ................................................................................................... 456
2-230. LSxLOCK Register ....................................................................................................... 457
2-231. LSxCOMMIT Register .................................................................................................... 459
2-232. LSxMSEL Register ....................................................................................................... 461
2-233. LSxCLAPGM Register ................................................................................................... 463
2-234. LSxACCPROT0 Register ................................................................................................ 464
2-235. LSxACCPROT1 Register ................................................................................................ 466
2-236. LSxTEST Register ........................................................................................................ 467
2-237. LSxINIT Register .......................................................................................................... 469
2-238. LSxINITDONE Register .................................................................................................. 470
2-239. GSxLOCK Register ....................................................................................................... 471
2-240. GSxCOMMIT Register ................................................................................................... 474
2-241. GSxMSEL Register ....................................................................................................... 477
2-242. GSxACCPROT0 Register ............................................................................................... 479

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2-246. GSxTEST Register ....................................................................................................... 487
2-247. GSxINIT Register ......................................................................................................... 490
2-248. GSxINITDONE Register ................................................................................................. 492
2-249. MSGxTEST Register ..................................................................................................... 494
2-250. MSGxINIT Register ....................................................................................................... 495
2-251. MSGxINITDONE Register ............................................................................................... 496
2-252. NMAVFLG Register ...................................................................................................... 499
2-253. NMAVSET Register ...................................................................................................... 501
2-254. NMAVCLR Register ...................................................................................................... 503
2-255. NMAVINTEN Register.................................................................................................... 505
2-256. NMCPURDAVADDR Register .......................................................................................... 506
2-257. NMCPUWRAVADDR Register .......................................................................................... 507
2-258. NMCPUFAVADDR Register ............................................................................................. 508
2-259. NMDMAWRAVADDR Register ......................................................................................... 509
2-260. NMCLA1RDAVADDR Register ......................................................................................... 510
2-261. NMCLA1WRAVADDR Register ......................................................................................... 511
2-262. NMCLA1FAVADDR Register............................................................................................ 512
2-263. MAVFLG Register ........................................................................................................ 513
2-264. MAVSET Register ........................................................................................................ 514
2-265. MAVCLR Register ........................................................................................................ 515
2-266. MAVINTEN Register ..................................................................................................... 516
2-267. MCPUFAVADDR Register............................................................................................... 517
2-268. MCPUWRAVADDR Register ............................................................................................ 518
2-269. MDMAWRAVADDR Register ........................................................................................... 519
2-270. UCERRFLG Register..................................................................................................... 521
2-271. UCERRSET Register..................................................................................................... 522
2-272. UCERRCLR Register .................................................................................................... 523
2-273. UCCPUREADDR Register .............................................................................................. 524
2-274. UCDMAREADDR Register .............................................................................................. 525
2-275. UCCLA1READDR Register ............................................................................................. 526
2-276. CERRFLG Register....................................................................................................... 527
2-277. CERRSET Register....................................................................................................... 528
2-278. CERRCLR Register ...................................................................................................... 529
2-279. CCPUREADDR Register ................................................................................................ 530
2-280. CERRCNT Register ...................................................................................................... 531
2-281. CERRTHRES Register ................................................................................................... 532
2-282. CEINTFLG Register ...................................................................................................... 533
2-283. CEINTCLR Register ...................................................................................................... 534
2-284. CEINTSET Register ...................................................................................................... 535
2-285. CEINTEN Register........................................................................................................ 536
2-286. ROMWAITSTATE Register .............................................................................................. 538
2-287. FRDCNTL Register ....................................................................................................... 540
2-288. FBAC Register ............................................................................................................ 541
2-289. FBFALLBACK Register .................................................................................................. 542
2-290. FBPRDY Register ........................................................................................................ 543
2-291. FPAC1 Register ........................................................................................................... 544
2-292. FMSTAT Register ......................................................................................................... 545

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2-293. FRD_INTF_CTRL Register .............................................................................................. 547

2-294. ECC_ENABLE Register.................................................................................................. 550
2-295. SINGLE_ERR_ADDR_LOW Register.................................................................................. 551
2-296. SINGLE_ERR_ADDR_HIGH Register ................................................................................. 552
2-297. UNC_ERR_ADDR_LOW Register...................................................................................... 553
2-298. UNC_ERR_ADDR_HIGH Register ..................................................................................... 554
2-299. ERR_STATUS Register.................................................................................................. 555
2-300. ERR_POS Register....................................................................................................... 557
2-301. ERR_STATUS_CLR Register ........................................................................................... 558
2-302. ERR_CNT Register ....................................................................................................... 559
2-303. ERR_THRESHOLD Register............................................................................................ 560
2-304. ERR_INTFLG Register ................................................................................................... 561
2-305. ERR_INTCLR Register .................................................................................................. 562
2-306. FDATAH_TEST Register ................................................................................................ 563
2-307. FDATAL_TEST Register ................................................................................................. 564
2-308. FADDR_TEST Register .................................................................................................. 565
2-309. FECC_TEST Register .................................................................................................... 566
2-310. FECC_CTRL Register.................................................................................................... 567
2-311. FOUTH_TEST Register .................................................................................................. 568
2-312. FOUTL_TEST Register .................................................................................................. 569
2-313. FECC_STATUS Register ................................................................................................ 570
2-314. CPUID_1 Register ........................................................................................................ 572
2-315. UID_PSRAND0 Register................................................................................................. 574
2-321. UID_UNIQUE Register ................................................................................................... 580
2-322. UID_CHECKSUM Register .............................................................................................. 581
3-1. Z1 and Z2 BOOTCTRL Selection ...................................................................................... 585
3-2. CPU1 Device Boot Flow ................................................................................................. 588
3-3. CPU2 Device Boot Flow ................................................................................................. 589
3-4. CPU1 Emulation Boot Flow ............................................................................................. 590
3-5. CPU2 Emulation Boot Flow ............................................................................................. 591
3-6. CPU1 Standalone and Hibernate Boot Flow .......................................................................... 592
3-7. CPU2 Standalone and Hibernate Boot Flow .......................................................................... 593
3-8. Overview of SCI Bootloader Operation ................................................................................ 599
3-9. Overview of SCI Boot Function ......................................................................................... 600
3-10. SPI Loader ................................................................................................................. 600
3-11. Data Transfer From EEPROM Flow .................................................................................... 602
3-12. EEPROM Device at Address 0x50 ..................................................................................... 602
3-13. Overview of I2C Boot Function ......................................................................................... 603
3-14. Random Read ............................................................................................................. 604
3-15. Sequential Read .......................................................................................................... 605
3-16. Overview of Parallel GPIO Bootloader Operation .................................................................... 605
3-17. Parallel GPIO Bootloader Handshake Protocol ....................................................................... 606
3-18. Parallel GPIO Mode Overview .......................................................................................... 606
3-19. Parallel GPIO Mode - Host Transfer Flow ............................................................................. 607

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3-20. 8-Bit Parallel GetWord Function ........................................................................................ 608

3-21. Overview of CAN-A Bootloader Operation ............................................................................ 609
3-22. USB Boot Flow ............................................................................................................ 610
4-1. DMA Block Diagram ...................................................................................................... 625
4-2. Common Peripheral Architecture ....................................................................................... 626
4-3. DMA Trigger Architecture ................................................................................................ 628
4-4. Peripheral Interrupt Trigger Input Diagram ........................................................................... 629
4-5. 4-Stage Pipeline DMA Transfer ......................................................................................... 633
4-6. 4-Stage Pipeline With One Read Stall (McBSP as source) ......................................................... 633
4-7. DMA State Diagram ...................................................................................................... 639
4-8. Overrun Detection Logic ................................................................................................. 641
4-9. DMA Control Register (DMACTRL) .................................................................................... 643
4-10. Debug Control Register (DEBUGCTRL) .............................................................................. 644
4-11. Revision Register (REVISION).......................................................................................... 644
4-12. Priority Control Register 1 (PRIORITYCTRL1) ....................................................................... 645
4-13. Priority Status Register (PRIORITYSTAT) ............................................................................ 646
4-14. Mode Register (MODE) ................................................................................................. 647
4-15. Control Register (CONTROL) .......................................................................................... 649
4-16. Burst Size Register (BURST_SIZE) .................................................................................... 651
4-17. Burst Size Register (BURST_COUNT) ................................................................................ 651
4-18. Source Burst Step Size Register (SRC_BURST_STEP) ............................................................ 652
4-19. Destination Burst Step Register Size (DST_BURST_STEP) ....................................................... 653
4-20. Transfer Size Register (TRANSFER_SIZE) ........................................................................... 653
4-21. Transfer Count Register (TRANSFER_COUNT) ..................................................................... 654
4-22. Source Transfer Step Size Register (SRC_TRANSFER_STEP) .................................................. 654
4-23. Destination Transfer Step Size Register (DST_TRANSFER_STEP) ............................................. 655
4-24. Source/Destination Wrap Size Register (SRC/DST_WRAP_SIZE) ............................................... 655
4-25. Source/Destination Wrap Count Register (SCR/DST_WRAP_COUNT) ......................................... 656
4-26. Source/Destination Wrap Step Size Registers (SRC/DST_WRAP_STEP) ...................................... 656
4-27. Shadow Source Begin and Current Address Pointer Registers
(SRC_BEG_ADDR_SHADOW/DST_BEG_ADDR_SHADOW) ..................................................... 657
4-28. Active Source Begin and Current Address Pointer Registers (SRC_BEG_ADDR/DST_BEG_ADDR) ....... 657
4-29. Shadow Destination Begin and Current Address Pointer Registers
(SRC_ADDR_SHADOW/DST_ADDR_SHADOW) ................................................................... 658
4-30. Active Destination Begin and Current Address Pointer Registers (SRC_ADDR/DST_ADDR) ................. 658
5-1. CLA Block Diagram ....................................................................................................... 661
5-2. MVECT1 Register ........................................................................................................ 795
5-3. MVECT2 Register ........................................................................................................ 796
5-4. MVECT3 Register ........................................................................................................ 797
5-5. MVECT4 Register ........................................................................................................ 798
5-6. MVECT5 Register ........................................................................................................ 799
5-7. MVECT6 Register ........................................................................................................ 800
5-8. MVECT7 Register ........................................................................................................ 801
5-9. MVECT8 Register ........................................................................................................ 802
5-10. MCTL Register ............................................................................................................ 803
5-11. MIFR Register ............................................................................................................. 804
5-12. MIOVF Register ........................................................................................................... 806
5-13. MIFRC Register ........................................................................................................... 808
5-14. MICLR Register ........................................................................................................... 810

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5-15. MICLROVF Register ..................................................................................................... 812

5-16. MIER Register ............................................................................................................. 814
5-17. MIRUN Register........................................................................................................... 816
5-18. _MPC Register ............................................................................................................ 818
5-19. _MAR0 Register .......................................................................................................... 819
5-20. _MAR1 Register .......................................................................................................... 820
5-21. _MSTF Register........................................................................................................... 821
5-22. _MR0 Register ............................................................................................................ 824
5-23. _MR1 Register ............................................................................................................ 825
5-24. _MR2 Register ............................................................................................................ 826
5-25. _MR3 Register ............................................................................................................ 827
5-26. SOFTINTEN Register .................................................................................................... 829
5-27. SOFTINTFRC Register .................................................................................................. 831
6-1. IPC Module Architecture ................................................................................................. 834
6-2. Messaging with IPC Flags and Interrupts ............................................................................. 835
6-3. IPCACK Register ......................................................................................................... 840
6-4. IPCSTS Register .......................................................................................................... 843
6-5. IPCSET Register .......................................................................................................... 848
6-6. IPCCLR Register.......................................................................................................... 851
6-7. IPCFLG Register .......................................................................................................... 856
6-8. IPCCOUNTERL Register ................................................................................................ 860
6-9. IPCCOUNTERH Register ................................................................................................ 861
6-10. IPCSENDCOM Register ................................................................................................. 862
6-11. IPCSENDADDR Register ................................................................................................ 863
6-12. IPCSENDDATA Register ................................................................................................ 864
6-13. IPCREMOTEREPLY Register........................................................................................... 865
6-14. IPCRECVCOM Register ................................................................................................. 866
6-15. IPCRECVADDR Register ................................................................................................ 867
6-16. IPCRECVDATA Register ................................................................................................ 868
6-17. IPCLOCALREPLY Register ............................................................................................. 869
6-18. IPCBOOTSTS Register .................................................................................................. 870
6-19. IPCBOOTMODE Register ............................................................................................... 871
6-20. IPCACK Register ......................................................................................................... 873
6-21. IPCSTS Register .......................................................................................................... 876
6-22. IPCSET Register .......................................................................................................... 881
6-23. IPCCLR Register.......................................................................................................... 884
6-24. IPCFLG Register .......................................................................................................... 889
6-25. IPCCOUNTERL Register ................................................................................................ 893
6-26. IPCCOUNTERH Register ................................................................................................ 894
6-27. IPCRECVCOM Register ................................................................................................. 895
6-28. IPCRECVADDR Register ................................................................................................ 896
6-29. IPCRECVDATA Register ................................................................................................ 897
6-30. IPCLOCALREPLY Register ............................................................................................. 898
6-31. IPCSENDCOM Register ................................................................................................. 899
6-32. IPCSENDADDR Register ................................................................................................ 900
6-33. IPCSENDDATA Register ................................................................................................ 901
6-34. IPCREMOTEREPLY Register........................................................................................... 902
6-35. IPCBOOTSTS Register .................................................................................................. 903
6-36. IPCBOOTMODE Register ............................................................................................... 904

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7-1. GPIO Logic for a Single Pin ............................................................................................. 906

7-2. Input Qualification Using a Sampling Window ........................................................................ 909
7-3. Input Qualifier Clock Cycles ............................................................................................. 912
7-4. GPACTRL Register ....................................................................................................... 926
7-5. GPAQSEL1 Register ..................................................................................................... 927
7-6. GPAQSEL2 Register ..................................................................................................... 929
7-7. GPAMUX1 Register ...................................................................................................... 931
7-8. GPAMUX2 Register ...................................................................................................... 933
7-9. GPADIR Register ......................................................................................................... 935
7-10. GPAPUD Register ........................................................................................................ 937
7-11. GPAINV Register ......................................................................................................... 939
7-12. GPAODR Register ........................................................................................................ 941
7-13. GPAGMUX1 Register .................................................................................................... 943
7-14. GPAGMUX2 Register .................................................................................................... 944
7-15. GPACSEL1 Register ..................................................................................................... 945
7-19. GPALOCK Register ...................................................................................................... 949
7-20. GPACR Register .......................................................................................................... 951
7-21. GPBCTRL Register ....................................................................................................... 953
7-22. GPBQSEL1 Register ..................................................................................................... 954
7-23. GPBQSEL2 Register ..................................................................................................... 956
7-24. GPBMUX1 Register ...................................................................................................... 958
7-25. GPBMUX2 Register ...................................................................................................... 960
7-26. GPBDIR Register ......................................................................................................... 962
7-27. GPBPUD Register ........................................................................................................ 964
7-28. GPBINV Register ......................................................................................................... 966
7-29. GPBODR Register ........................................................................................................ 968
7-30. GPBAMSEL Register..................................................................................................... 970
7-31. GPBGMUX1 Register .................................................................................................... 972
7-32. GPBGMUX2 Register .................................................................................................... 973
7-33. GPBCSEL1 Register ..................................................................................................... 974
7-37. GPBLOCK Register ...................................................................................................... 978
7-38. GPBCR Register .......................................................................................................... 980
7-39. GPCCTRL Register....................................................................................................... 982
7-40. GPCQSEL1 Register ..................................................................................................... 983
7-41. GPCQSEL2 Register ..................................................................................................... 985
7-42. GPCMUX1 Register ...................................................................................................... 987
7-43. GPCMUX2 Register ...................................................................................................... 989
7-44. GPCDIR Register ......................................................................................................... 991
7-45. GPCPUD Register ........................................................................................................ 993
7-46. GPCINV Register ......................................................................................................... 995
7-47. GPCODR Register........................................................................................................ 997
7-48. GPCGMUX1 Register .................................................................................................... 999
7-49. GPCGMUX2 Register .................................................................................................. 1000

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7-50. GPCCSEL1 Register.................................................................................................... 1001

7-54. GPCLOCK Register ..................................................................................................... 1005
7-55. GPCCR Register ........................................................................................................ 1007
7-56. GPDCTRL Register ..................................................................................................... 1009
7-57. GPDQSEL1 Register ................................................................................................... 1010
7-58. GPDQSEL2 Register ................................................................................................... 1012
7-59. GPDMUX1 Register..................................................................................................... 1014
7-60. GPDMUX2 Register..................................................................................................... 1016
7-61. GPDDIR Register ....................................................................................................... 1018
7-62. GPDPUD Register ...................................................................................................... 1020
7-63. GPDINV Register........................................................................................................ 1022
7-64. GPDODR Register ...................................................................................................... 1024
7-65. GPDGMUX1 Register .................................................................................................. 1026
7-66. GPDGMUX2 Register .................................................................................................. 1028
7-67. GPDCSEL1 Register.................................................................................................... 1030
7-71. GPDLOCK Register ..................................................................................................... 1034
7-72. GPDCR Register ........................................................................................................ 1036
7-73. GPECTRL Register ..................................................................................................... 1038
7-74. GPEQSEL1 Register.................................................................................................... 1039
7-75. GPEQSEL2 Register.................................................................................................... 1041
7-76. GPEMUX1 Register ..................................................................................................... 1043
7-77. GPEMUX2 Register ..................................................................................................... 1045
7-78. GPEDIR Register........................................................................................................ 1047
7-79. GPEPUD Register....................................................................................................... 1049
7-80. GPEINV Register ........................................................................................................ 1051
7-81. GPEODR Register ...................................................................................................... 1053
7-82. GPEGMUX1 Register ................................................................................................... 1055
7-83. GPEGMUX2 Register ................................................................................................... 1057
7-84. GPECSEL1 Register .................................................................................................... 1059
7-88. GPELOCK Register ..................................................................................................... 1063
7-89. GPECR Register ........................................................................................................ 1065
7-90. GPFCTRL Register ..................................................................................................... 1067
7-91. GPFQSEL1 Register .................................................................................................... 1068
7-92. GPFMUX1 Register ..................................................................................................... 1070
7-93. GPFDIR Register ........................................................................................................ 1072
7-94. GPFPUD Register ....................................................................................................... 1074
7-95. GPFINV Register ........................................................................................................ 1076
7-96. GPFODR Register ...................................................................................................... 1078
7-97. GPFGMUX1 Register ................................................................................................... 1080
7-98. GPFCSEL1 Register .................................................................................................... 1081

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7-99. GPFCSEL2 Register .................................................................................................... 1082

7-100. GPFLOCK Register ..................................................................................................... 1083
7-101. GPFCR Register ........................................................................................................ 1085
7-102. GPADAT Register ....................................................................................................... 1089
7-103. GPASET Register ....................................................................................................... 1091
7-104. GPACLEAR Register ................................................................................................... 1093
7-105. GPATOGGLE Register ................................................................................................. 1095
7-106. GPBDAT Register ....................................................................................................... 1097
7-107. GPBSET Register ....................................................................................................... 1099
7-108. GPBCLEAR Register ................................................................................................... 1101
7-109. GPBTOGGLE Register ................................................................................................. 1103
7-110. GPCDAT Register ....................................................................................................... 1105
7-111. GPCSET Register ....................................................................................................... 1107
7-112. GPCCLEAR Register ................................................................................................... 1109
7-113. GPCTOGGLE Register ................................................................................................. 1111
7-114. GPDDAT Register ....................................................................................................... 1113
7-115. GPDSET Register ....................................................................................................... 1115
7-116. GPDCLEAR Register ................................................................................................... 1117
7-117. GPDTOGGLE Register ................................................................................................. 1119
7-118. GPEDAT Register ....................................................................................................... 1121
7-119. GPESET Register ....................................................................................................... 1123
7-120. GPECLEAR Register ................................................................................................... 1125
7-121. GPETOGGLE Register ................................................................................................. 1127
7-122. GPFDAT Register ....................................................................................................... 1129
7-123. GPFSET Register ....................................................................................................... 1131
7-124. GPFCLEAR Register ................................................................................................... 1133
7-125. GPFTOGGLE Register ................................................................................................. 1135
8-1. Input X-BAR .............................................................................................................. 1138
8-2. ePWM Architecture - Single Output................................................................................... 1140
8-3. GPIO Output X-BAR Architecture ..................................................................................... 1142
8-4. ePWM and Output X-BARs Architectures ........................................................................... 1144
8-5. INPUT1SELECT Register .............................................................................................. 1147
8-14. INPUT10SELECT Register ............................................................................................ 1156
8-19. INPUTSELECTLOCK Register ........................................................................................ 1161
8-20. XBARFLG1 Register .................................................................................................... 1166

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8-23. XBARCLR1 Register .................................................................................................... 1172

8-26. TRIP4MUX0TO15CFG Register ...................................................................................... 1180
8-27. TRIP4MUX16TO31CFG Register ..................................................................................... 1183
8-37. TRIP10MUX16TO31CFG Register ................................................................................... 1213
8-42. TRIP4MUXENABLE Register .......................................................................................... 1228
8-47. TRIP10MUXENABLE Register ........................................................................................ 1253
8-50. TRIPOUTINV Register.................................................................................................. 1268
8-51. TRIPLOCK Register .................................................................................................... 1270
8-52. OUTPUT1MUX0TO15CFG Register ................................................................................. 1273
8-53. OUTPUT1MUX16TO31CFG Register ................................................................................ 1276
8-68. OUTPUT1MUXENABLE Register ..................................................................................... 1321

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8-76. OUTPUTLATCH Register .............................................................................................. 1361
8-77. OUTPUTLATCHCLR Register......................................................................................... 1363
8-78. OUTPUTLATCHFRC Register ........................................................................................ 1365
8-79. OUTPUTLATCHENABLE Register ................................................................................... 1367
8-80. OUTPUTINV Register .................................................................................................. 1369
8-81. OUTPUTLOCK Register ............................................................................................... 1371
9-1. Analog Subsystem Block Diagram (337-Ball ZWT) ................................................................. 1374
9-2. Analog Subsystem Block Diagram (176-Pin PTP) .................................................................. 1375
9-3. Analog Subsystem Block Diagram (100-Pin PZP) .................................................................. 1376
9-4. INTOSC1TRIM Register ................................................................................................ 1379
9-5. INTOSC2TRIM Register ................................................................................................ 1380
9-6. TSNSCTL Register ...................................................................................................... 1381
9-7. LOCK Register........................................................................................................... 1382
9-8. ANAREFTRIMA Register............................................................................................... 1383
9-9. ANAREFTRIMB Register............................................................................................... 1384
9-10. ANAREFTRIMC Register .............................................................................................. 1385
9-11. ANAREFTRIMD Register .............................................................................................. 1386
10-1. ADC Module Block Diagram ........................................................................................... 1389
10-2. SOC Block Diagram..................................................................................................... 1393
10-3. Single-Ended Input Model .............................................................................................. 1394
10-4. Differential Input Model ................................................................................................. 1394
10-5. Round Robin Priority Example ........................................................................................ 1399
10-6. High Priority Example ................................................................................................... 1400
10-7. Burst Priority Example .................................................................................................. 1402
10-8. ADC EOC Interrupts .................................................................................................... 1403
10-9. ADC PPB Block Diagram .............................................................................................. 1404
10-10. ADC PPB Interrupt Event .............................................................................................. 1405
10-11. Opens/Shorts Detection Circuit ........................................................................................ 1406
10-12. ADC Timings for 12-bit Mode in Early Interrupt Mode ............................................................. 1409
10-13. ADC Timings for 12-bit Mode in Late Interrupt Mode .............................................................. 1410
10-14. ADC Timings for 16-bit Mode in Early Interrupt Mode ............................................................. 1411
10-15. ADC Timings for 16-bit Mode in Late Interrupt Mode (SYSCLK Cycles) ........................................ 1412
10-16. Example: Basic Synchronous Operation ............................................................................. 1414
10-17. Example: Synchronous Operation with Multiple Trigger Sources................................................. 1415
10-18. Example: Synchronous Operation with Uneven SOC Numbers .................................................. 1416
10-19. Example: Asynchronous Operation with Uneven SOC Numbers – Trigger Overflow .......................... 1416
10-20. Example: Asynchronous Operation with Different Resolutions ................................................... 1416
10-21. Example: Synchronous Operation with Different Resolutions ..................................................... 1417
10-22. Example: Synchronous Equivalent Operation with Non-Overlapping Conversions ............................ 1417
10-23. ADC Reference System ................................................................................................ 1419
10-24. ADC Shared Reference System....................................................................................... 1420
10-25. ADCCTL1 Register ...................................................................................................... 1425
10-26. ADCCTL2 Register ...................................................................................................... 1427
10-27. ADCBURSTCTL Register .............................................................................................. 1428
10-28. ADCINTFLG Register ................................................................................................... 1430

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10-29. ADCINTFLGCLR Register ............................................................................................. 1432

10-30. ADCINTOVF Register .................................................................................................. 1434
10-31. ADCINTOVFCLR Register ............................................................................................. 1436
10-32. ADCINTSEL1N2 Register .............................................................................................. 1437
10-33. ADCINTSEL3N4 Register .............................................................................................. 1439
10-34. ADCSOCPRICTL Register ............................................................................................. 1441
10-35. ADCINTSOCSEL1 Register ........................................................................................... 1444
10-36. ADCINTSOCSEL2 Register ........................................................................................... 1446
10-37. ADCSOCFLG1 Register ................................................................................................ 1448
10-38. ADCSOCFRC1 Register ............................................................................................... 1453
10-39. ADCSOCOVF1 Register ............................................................................................... 1458
10-40. ADCSOCOVFCLR1 Register .......................................................................................... 1462
10-41. ADCSOC0CTL Register ................................................................................................ 1466
10-51. ADCSOC10CTL Register .............................................................................................. 1496
10-57. ADCEVTSTAT Register ................................................................................................ 1514
10-58. ADCEVTCLR Register.................................................................................................. 1516
10-59. ADCEVTSEL Register .................................................................................................. 1518
10-60. ADCEVTINTSEL Register.............................................................................................. 1520
10-61. ADCCOUNTER Register ............................................................................................... 1522
10-62. ADCREV Register ....................................................................................................... 1523
10-63. ADCOFFTRIM Register ................................................................................................ 1524
10-64. ADCPPB1CONFIG Register ........................................................................................... 1525
10-65. ADCPPB1STAMP Register ............................................................................................ 1527
10-66. ADCPPB1OFFCAL Register ........................................................................................... 1528
10-67. ADCPPB1OFFREF Register........................................................................................... 1529
10-68. ADCPPB1TRIPHI Register ............................................................................................ 1530
10-69. ADCPPB1TRIPLO Register............................................................................................ 1531

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10-88. ADCINLTRIM1 Register ................................................................................................ 1553
10-94. ADCRESULT0 Register ................................................................................................ 1561
10-100. ADCRESULT6 Register ............................................................................................... 1567
10-104. ADCRESULT10 Register ............................................................................................. 1571
10-110. ADCPPB1RESULT Register ......................................................................................... 1577
11-1. DAC Module Block Diagram ........................................................................................... 1582
11-2. DACREV Register ....................................................................................................... 1585
11-3. DACCTL Register ....................................................................................................... 1586
11-4. DACVALA Register ..................................................................................................... 1587
11-5. DACVALS Register ..................................................................................................... 1588
11-6. DACOUTEN Register ................................................................................................... 1589
11-7. DACLOCK Register ..................................................................................................... 1590
11-8. DACTRIM Register ...................................................................................................... 1591
12-1. CMPSS Module Block Diagram ....................................................................................... 1593
12-2. Comparator Digital Output ............................................................................................. 1594
12-3. DAC Reference Select.................................................................................................. 1594
12-4. Output Voltage Calculation............................................................................................. 1594
12-5. Ramp Generator ......................................................................................................... 1595

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12-6. Ramp Generator Behavior ............................................................................................. 1596

12-7. Digital Filter Behavior ................................................................................................... 1596
12-8. COMPCTL Register ..................................................................................................... 1601
12-9. COMPHYSCTL Register ............................................................................................... 1603
12-10. COMPSTS Register..................................................................................................... 1604
12-11. COMPSTSCLR Register ............................................................................................... 1605
12-12. COMPDACCTL Register ............................................................................................... 1606
12-13. DACHVALS Register ................................................................................................... 1608
12-14. DACHVALA Register ................................................................................................... 1609
12-15. RAMPMAXREFA Register ............................................................................................. 1610
12-16. RAMPMAXREFS Register ............................................................................................. 1611
12-17. RAMPDECVALA Register.............................................................................................. 1612
12-18. RAMPDECVALS Register.............................................................................................. 1613
12-19. RAMPSTS Register ..................................................................................................... 1614
12-20. DACLVALS Register .................................................................................................... 1615
12-21. DACLVALA Register .................................................................................................... 1616
12-22. RAMPDLYA Register ................................................................................................... 1617
12-23. RAMPDLYS Register ................................................................................................... 1618
12-24. CTRIPLFILCTL Register ............................................................................................... 1619
12-25. CTRIPLFILCLKCTL Register .......................................................................................... 1620
12-26. CTRIPHFILCTL Register ............................................................................................... 1621
12-27. CTRIPHFILCLKCTL Register .......................................................................................... 1622
12-28. COMPLOCK Register .................................................................................................. 1623
13-1. Sigma Delta Filter Module (SDFM) CPU Interface ................................................................. 1625
13-2. Sigma Delta Filter Module (SDFM) Block Diagram ................................................................. 1626
13-3. Block Diagram of One Filter Module .................................................................................. 1627
13-4. Typical PWM Interface to Sigma Delta Filter Module .............................................................. 1627
13-5. Operation Diagrams..................................................................................................... 1629
13-6. Comparator Filter Resolution .......................................................................................... 1630
13-7. Frequency Response of Various Sinc Filters ........................................................................ 1631
13-8. Data Filter Resolution ................................................................................................... 1632
13-9. SDFM Interrupt Unit ..................................................................................................... 1635
13-10. SDIFLG Register ........................................................................................................ 1640
13-11. SDIFLGCLR Register ................................................................................................... 1642
13-12. SDCTL Register ......................................................................................................... 1644
13-13. SDMFILEN Register .................................................................................................... 1645
13-14. SDCTLPARM1 Register ................................................................................................ 1646
13-15. SDDFPARM1 Register ................................................................................................. 1647
13-16. SDDPARM1 Register ................................................................................................... 1648
13-17. SDCMPH1 Register ..................................................................................................... 1649
13-18. SDCMPL1 Register ..................................................................................................... 1650
13-19. SDCPARM1 Register ................................................................................................... 1651
13-20. SDDATA1 Register ..................................................................................................... 1652
13-24. SDCMPH2 Register ..................................................................................................... 1656
13-25. SDCMPL2 Register ..................................................................................................... 1657

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13-27. SDDATA2 Register ..................................................................................................... 1659

13-31. SDCMPH3 Register ..................................................................................................... 1663
13-32. SDCMPL3 Register ..................................................................................................... 1664
13-34. SDDATA3 Register ..................................................................................................... 1666
13-38. SDCMPH4 Register ..................................................................................................... 1670
13-39. SDCMPL4 Register ..................................................................................................... 1671
13-41. SDDATA4 Register ..................................................................................................... 1673
14-1. Multiple ePWM Modules................................................................................................ 1678
14-2. Submodules and Signal Connections for an ePWM Module ...................................................... 1679
14-3. ePWM Submodules and Critical Internal Signal Interconnects ................................................... 1681
14-4. Time-Base Submodule ................................................................................................. 1684
14-5. Time-Base Submodule Signals and Registers ...................................................................... 1685
14-6. Time-Base Frequency and Period .................................................................................... 1687
14-7. Time-Base Counter Synchronization Scheme ....................................................................... 1689
14-8. Time-Base Up-Count Mode Waveforms ............................................................................. 1691
14-9. Time-Base Down-Count Mode Waveforms .......................................................................... 1692
14-10. Time-Base Up-Down-Count Waveforms, TBCTL[PHSDIR = 0] Count Down On Synchronization Event ... 1692
14-11. Time-Base Up-Down Count Waveforms, TBCTL[PHSDIR = 1] Count Up On Synchronization Event ...... 1693
14-12. Global Load: Signals and Registers .................................................................................. 1694
14-13. Counter-Compare Submodule ......................................................................................... 1695
14-14. Detailed View of the Counter-Compare Submodule ................................................................ 1696
14-15. Counter-Compare Event Waveforms in Up-Count Mode .......................................................... 1699
14-16. Counter-Compare Events in Down-Count Mode .................................................................... 1700
14-17. Counter-Compare Events In Up-Down-Count Mode, TBCTL[PHSDIR = 0] Count Down On
Synchronization Event ................................................................................................. 1701
14-18. Counter-Compare Events In Up-Down-Count Mode, TBCTL[PHSDIR = 1] Count Up On Synchronization
Event ..................................................................................................................... 1701
14-19. Action-Qualifier Submodule ............................................................................................ 1702
14-20. Action-Qualifier Submodule Inputs and Outputs .................................................................... 1703
14-21. Possible Action-Qualifier Actions for EPWMxA and EPWMxB Outputs ......................................... 1704
14-22. AQCTLR[SHDWAQAMODE] ......................................................................................... 1707
14-23. AQCTLR[SHDWAQBMODE] .......................................................................................... 1707
14-24. Up-Down-Count Mode Symmetrical Waveform ..................................................................... 1709
14-25. Up, Single Edge Asymmetric Waveform, With Independent Modulation on EPWMxA and
EPWMxB—Active High ................................................................................................. 1710
14-26. Up, Single Edge Asymmetric Waveform With Independent Modulation on EPWMxA and
EPWMxB—Active Low ................................................................................................. 1711
14-27. Up-Count, Pulse Placement Asymmetric Waveform With Independent Modulation on EPWMxA ........... 1712
14-28. Up-Down-Count, Dual Edge Symmetric Waveform, With Independent Modulation on EPWMxA and
EPWMxB — Active Low ................................................................................................ 1712
14-29. Up-Down-Count, Dual Edge Symmetric Waveform, With Independent Modulation on EPWMxA and
EPWMxB — Complementary .......................................................................................... 1713

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14-30. Up-Down-Count, Dual Edge Asymmetric Waveform, With Independent Modulation on EPWMxA—Active
Low ........................................................................................................................ 1713
14-31. Up-Down-Count, PWM Waveform Generation Utilizing T1 and T2 Events ..................................... 1714
14-32. Dead_Band Submodule ................................................................................................ 1714
14-33. Configuration Options for the Dead-Band Submodule ............................................................. 1717
14-34. Dead-Band Waveforms for Typical Cases (0% < Duty < 100%).................................................. 1719
14-35. PWM Chopper Submodule............................................................................................. 1721
14-36. PWM Chopper Submodule Operational Details ..................................................................... 1722
14-37. Simple PWM Chopper Submodule Waveforms Showing Chopping Action Only ............................... 1722
14-38. PWM Chopper Submodule Waveforms Showing the First Pulse and Subsequent Sustaining Pulses ...... 1723
14-39. PWM Chopper Submodule Waveforms Showing the Pulse Width (Duty Cycle) Control of Sustaining
Pulses ..................................................................................................................... 1724
14-40. Trip-Zone Submodule ................................................................................................... 1725
14-41. Trip-Zone Submodule Mode Control Logic .......................................................................... 1729
14-42. Trip-Zone Submodule Interrupt Logic................................................................................. 1730
14-43. Event-Trigger Submodule .............................................................................................. 1731
14-44. Event-Trigger Submodule Showing Event Inputs and Prescaled Outputs....................................... 1732
14-45. Event-Trigger Interrupt Generator ..................................................................................... 1734
14-46. Event-Trigger SOCA Pulse Generator ............................................................................... 1735
14-47. Event-Trigger SOCB Pulse Generator ............................................................................... 1735
14-48. Digital-Compare Submodule High-Level Block Diagram ........................................................... 1736
14-49. ePWM Trip Input Connectivity ......................................................................................... 1737
14-50. DCAEVT1 Event Triggering ............................................................................................ 1740
14-51. DCAEVT2 Event Triggering ............................................................................................ 1740
14-52. DCBEVT1 Event Triggering ............................................................................................ 1741
14-53. DCBEVT2 Event Triggering ............................................................................................ 1741
14-54. Event Filtering ........................................................................................................... 1742
14-55. Blanking Window Timing Diagram .................................................................................... 1742
14-56. Valley Switching ......................................................................................................... 1744
14-57. EPWM X-BAR ........................................................................................................... 1745
14-58. Simplified ePWM Module............................................................................................... 1746
14-59. EPWM1 Configured as a Typical Master, EPWM2 Configured as a Slave ..................................... 1747
14-60. Control of Four Buck Stages. Here FPWM1≠ FPWM2≠ FPWM3≠ FPWM4 .................................................. 1748
14-61. Buck Waveforms for (Note: Only three bucks shown here) ....................................................... 1749
14-62. Control of Four Buck Stages. (Note: FPWM2 = N x FPWM1) ............................................................ 1750
14-63. Buck Waveforms for (Note: FPWM2 = FPWM1))........................................................................... 1751
14-64. Control of Two Half-H Bridge Stages (FPWM2 = N x FPWM1) .......................................................... 1752
14-65. Half-H Bridge Waveforms for (Note: Here FPWM2 = FPWM1 ) .......................................................... 1753
14-66. 3-Phase Inverter Waveforms (Only One Inverter Shown) ......................................................... 1754
14-67. Configuring Two PWM Modules for Phase Control ................................................................. 1755
14-68. Timing Waveforms Associated With Phase Control Between Two Modules .................................... 1756
14-69. Control of a 3-Phase Interleaved DC/DC Converter ................................................................ 1757
14-70. 3-Phase Interleaved DC/DC Converter Waveforms for ........................................................... 1758
14-71. Controlling a Full-H Bridge Stage (FPWM2 = FPWM1) ................................................................... 1759
14-72. ZVS Full-H Bridge Waveforms ........................................................................................ 1760
14-73. Peak Current Mode Control of a Buck Converter ................................................................... 1760
14-74. Peak Current Mode Control Waveforms for ......................................................................... 1761
14-75. Control of Two Resonant Converter Stages ......................................................................... 1761
14-76. H-Bridge LLC Resonant Converter PWM Waveforms.............................................................. 1762

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14-77. TBCTL Register ......................................................................................................... 1767

14-78. TBCTL2 Register ........................................................................................................ 1770
14-79. EPWMSYNCINSEL Register .......................................................................................... 1771
14-80. TBCTR Register ......................................................................................................... 1772
14-81. TBSTS Register ......................................................................................................... 1773
14-82. EPWMSYNCOUTEN Register......................................................................................... 1774
14-83. CMPCTL Register ....................................................................................................... 1776
14-84. CMPCTL2 Register ..................................................................................................... 1778
14-85. DBCTL Register ......................................................................................................... 1780
14-86. DBCTL2 Register........................................................................................................ 1783
14-87. AQCTL Register ......................................................................................................... 1784
14-88. AQTSRCSEL Register.................................................................................................. 1786
14-89. PCCTL Register ......................................................................................................... 1787
14-90. VCAPCTL Register ..................................................................................................... 1789
14-91. VCNTCFG Register ..................................................................................................... 1791
14-92. HRCNFG Register ...................................................................................................... 1793
14-93. HRPWR Register ........................................................................................................ 1795
14-94. HRMSTEP Register ..................................................................................................... 1796
14-95. HRCNFG2 Register ..................................................................................................... 1797
14-96. HRPCTL Register ....................................................................................................... 1798
14-97. TRREM Register ........................................................................................................ 1800
14-98. GLDCTL Register ....................................................................................................... 1801
14-99. GLDCFG Register ....................................................................................................... 1803
14-100. EPWMXLINK Register ................................................................................................ 1805
14-101. EPWMREV Register ................................................................................................... 1809
14-102. AQCTLA Register ...................................................................................................... 1810
14-103. AQCTLA2 Register .................................................................................................... 1812
14-104. AQCTLB Register ...................................................................................................... 1814
14-105. AQCTLB2 Register .................................................................................................... 1816
14-106. AQSFRC Register ..................................................................................................... 1818
14-107. AQCSFRC Register ................................................................................................... 1820
14-108. DBREDHR Register ................................................................................................... 1821
14-109. DBRED Register ....................................................................................................... 1822
14-110. DBFEDHR Register ................................................................................................... 1823
14-111. DBFED Register ....................................................................................................... 1824
14-112. TBPHS Register........................................................................................................ 1825
14-113. TBPRDHR Register ................................................................................................... 1826
14-114. TBPRD Register ....................................................................................................... 1827
14-115. CMPA Register ......................................................................................................... 1828
14-116. CMPB Register ......................................................................................................... 1829
14-117. CMPC Register ......................................................................................................... 1830
14-118. CMPD Register ......................................................................................................... 1831
14-119. GLDCTL2 Register .................................................................................................... 1832
14-120. SWVDELVAL Register ................................................................................................ 1833
14-121. TZSEL Register ........................................................................................................ 1834
14-122. TZDCSEL Register .................................................................................................... 1836
14-123. TZCTL Register ........................................................................................................ 1838
14-124. TZCTL2 Register ....................................................................................................... 1840
14-125. TZCTLDCA Register .................................................................................................. 1842

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14-126. TZCTLDCB Register .................................................................................................. 1844

14-127. TZEINT Register ....................................................................................................... 1846
14-128. TZFLG Register ........................................................................................................ 1847
14-129. TZCBCFLG Register .................................................................................................. 1849
14-130. TZOSTFLG Register .................................................................................................. 1851
14-131. TZCLR Register ........................................................................................................ 1853
14-132. TZCBCCLR Register .................................................................................................. 1855
14-133. TZOSTCLR Register .................................................................................................. 1857
14-134. TZFRC Register ........................................................................................................ 1859
14-135. ETSEL Register ........................................................................................................ 1860
14-136. ETPS Register ......................................................................................................... 1863
14-137. ETFLG Register ........................................................................................................ 1866
14-138. ETCLR Register ........................................................................................................ 1867
14-139. ETFRC Register........................................................................................................ 1868
14-140. ETINTPS Register ..................................................................................................... 1869
14-141. ETSOCPS Register .................................................................................................... 1870
14-142. ETCNTINITCTL Register ............................................................................................. 1872
14-143. ETCNTINIT Register .................................................................................................. 1873
14-144. DCTRIPSEL Register ................................................................................................. 1874
14-145. DCACTL Register ...................................................................................................... 1876
14-146. DCBCTL Register ...................................................................................................... 1878
14-147. DCFCTL Register ...................................................................................................... 1880
14-148. DCCAPCTL Register .................................................................................................. 1881
14-149. DCFOFFSET Register ................................................................................................ 1883
14-150. DCFOFFSETCNT Register ........................................................................................... 1884
14-151. DCFWINDOW Register ............................................................................................... 1885
14-152. DCFWINDOWCNT Register .......................................................................................... 1886
14-153. DCCAP Register ....................................................................................................... 1887
14-154. DCAHTRIPSEL Register .............................................................................................. 1888
14-155. DCALTRIPSEL Register .............................................................................................. 1890
14-156. DCBHTRIPSEL Register .............................................................................................. 1892
14-157. DCBLTRIPSEL Register .............................................................................................. 1894
14-158. EPWMLOCK Register ................................................................................................. 1896
14-159. HWVDELVAL Register ................................................................................................ 1898
14-160. VCNTVAL Register .................................................................................................... 1899
14-172. TRIP10MUX16TO31CFG Register .................................................................................. 1935

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14-182. TRIP10MUXENABLE Register ....................................................................................... 1975
14-185. TRIPOUTINV Register ................................................................................................ 1990
14-186. TRIPLOCK Register ................................................................................................... 1992
14-187. SYNCSELECT Register............................................................................................... 1994
14-188. ADCSOCOUTSELECT Register ..................................................................................... 1997
14-189. SYNCSOCLOCK Register ............................................................................................ 2000
15-1. Resolution Calculations for Conventionally Generated PWM ..................................................... 2002
15-2. Operating Logic Using MEP ........................................................................................... 2004
15-3. HRPWM Extension Registers and Memory Configuration ......................................................... 2005
15-4. HRPWM System Interface ............................................................................................. 2006
15-5. HRPWM Block Diagram ................................................................................................ 2007
15-6. Required PWM Waveform for a Requested Duty = 40.5% ........................................................ 2009
15-7. Low % Duty Cycle Range Limitation Example (HRPCTL[HRPE] = 0) ........................................... 2012
15-8. High % Duty Cycle Range Limitation Example (HRPCTL[HRPE] = 0) .......................................... 2014
15-9. Up-Count Duty Cycle Range Limitation Example (HRPCTL[HRPE]=1) ......................................... 2014
15-10. Up-Down Count Duty Cycle Range Limitation Example (HRPCTL[HRPE]=1) .................................. 2015
15-11. Simple Buck Controlled Converter Using a Single PWM .......................................................... 2020
15-12. PWM Waveform Generated for Simple Buck Controlled Converter .............................................. 2020
15-13. Simple Reconstruction Filter for a PWM-based DAC .............................................................. 2022
15-14. PWM Waveform Generated for the PWM DAC Function .......................................................... 2022
16-1. Capture and APWM Modes of Operation ............................................................................ 2030
16-2. Counter Compare and PRD Effects on the eCAP Output in APWM Mode ...................................... 2031
16-3. Capture Function Diagram ............................................................................................. 2032
16-4. Event Prescale Control ................................................................................................. 2033
16-5. Prescale Function Waveforms ......................................................................................... 2033
16-6. Details of the Continuous/One-shot Block ........................................................................... 2034
16-7. Details of the Counter and Synchronization Block .................................................................. 2035
16-8. Time-Base Counter Synchronization Scheme 4 .................................................................... 2036
16-9. Interrupts in eCAP Module ............................................................................................. 2037
16-10. PWM Waveform Details Of APWM Mode Operation ............................................................... 2038
16-11. Time-Base Frequency and Period Calculation ...................................................................... 2039
16-12. Capture Sequence for Absolute Time-stamp and Rising Edge Detect........................................... 2040
16-13. Capture Sequence for Absolute Time-stamp With Rising and Falling Edge Detect ............................ 2042
16-14. Capture Sequence for Delta Mode Time-stamp and Rising Edge Detect ....................................... 2044
16-15. Capture Sequence for Delta Mode Time-stamp With Rising and Falling Edge Detect ........................ 2046
16-16. PWM Waveform Details of APWM Mode Operation................................................................ 2048
16-17. TSCTR Register ......................................................................................................... 2052
16-18. CTRPHS Register ....................................................................................................... 2053
16-19. CAP1 Register ........................................................................................................... 2054
16-20. CAP2 Register ........................................................................................................... 2055

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16-21. CAP3 Register ........................................................................................................... 2056

16-22. CAP4 Register ........................................................................................................... 2057
16-23. ECCTL1 Register........................................................................................................ 2058
16-24. ECCTL2 Register........................................................................................................ 2060
16-25. ECEINT Register ........................................................................................................ 2062
16-26. ECFLG Register ......................................................................................................... 2064
16-27. ECCLR Register ......................................................................................................... 2066
16-28. ECFRC Register ......................................................................................................... 2067
17-1. Optical Encoder Disk ................................................................................................... 2069
17-2. QEP Encoder Output Signal for Forward/Reverse Movement .................................................... 2069
17-3. Index Pulse Example ................................................................................................... 2070
17-4. Functional Block Diagram of the eQEP Peripheral ................................................................. 2072
17-5. Functional Block Diagram of Decoder Unit .......................................................................... 2074
17-6. Quadrature Decoder State Machine .................................................................................. 2075
17-7. Quadrature-clock and Direction Decoding ........................................................................... 2076
17-8. Position Counter Reset by Index Pulse for 1000 Line Encoder (QPOSMAX = 3999 or 0xF9F) .............. 2078
17-9. Position Counter Underflow/Overflow (QPOSMAX = 4) ........................................................... 2079
17-10. Software Index Marker for 1000-line Encoder (QEPCTL[IEL] = 1) ............................................... 2080
17-11. Strobe Event Latch (QEPCTL[SEL] = 1) ............................................................................. 2081
17-12. eQEP Position-compare Unit .......................................................................................... 2082
17-13. eQEP Position-compare Event Generation Points .................................................................. 2083
17-14. eQEP Position-compare Sync Output Pulse Stretcher ............................................................. 2083
17-15. eQEP Edge Capture Unit .............................................................................................. 2085
17-16. Unit Position Event for Low Speed Measurement (QCAPCTL[UPPS] = 0010) ................................. 2085
17-17. eQEP Edge Capture Unit - Timing Details ........................................................................... 2086
17-18. eQEP Watchdog Timer ................................................................................................. 2087
17-19. eQEP Unit Time Base .................................................................................................. 2088
17-20. EQEP Interrupt Generation ............................................................................................ 2088
17-21. QPOSCNT Register..................................................................................................... 2092
17-22. QPOSINIT Register ..................................................................................................... 2093
17-23. QPOSMAX Register .................................................................................................... 2094
17-24. QPOSCMP Register .................................................................................................... 2095
17-25. QPOSILAT Register .................................................................................................... 2096
17-26. QPOSSLAT Register ................................................................................................... 2097
17-27. QPOSLAT Register ..................................................................................................... 2098
17-28. QUTMR Register ........................................................................................................ 2099
17-29. QUPRD Register ........................................................................................................ 2100
17-30. QWDTMR Register ..................................................................................................... 2101
17-31. QWDPRD Register ...................................................................................................... 2102
17-32. QDECCTL Register ..................................................................................................... 2103
17-33. QEPCTL Register ....................................................................................................... 2105
17-34. QCAPCTL Register ..................................................................................................... 2108
17-35. QPOSCTL Register ..................................................................................................... 2109
17-36. QEINT Register .......................................................................................................... 2110
17-37. QFLG Register........................................................................................................... 2112
17-38. QCLR Register .......................................................................................................... 2114
17-39. QFRC Register .......................................................................................................... 2116
17-40. QEPSTS Register ....................................................................................................... 2118
17-41. QCTMR Register ........................................................................................................ 2120

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17-42. QCPRD Register ........................................................................................................ 2121

17-43. QCTMRLAT Register ................................................................................................... 2122
17-44. QCPRDLAT Register ................................................................................................... 2123
18-1. SPI CPU Interface ....................................................................................................... 2126
18-2. SPI Interrupt Flags and Enable Logic Generation .................................................................. 2129
18-3. SPI DMA Trigger Diagram ............................................................................................. 2130
18-4. SPI Master/Slave Connection ......................................................................................... 2131
18-5. SPI Module Master Configuration ..................................................................................... 2132
18-6. SPI Module Slave Configuration ...................................................................................... 2133
18-7. SPICLK Signal Options ................................................................................................. 2136
18-8. SPI: SPICLK-LSPCLK Characteristic When (BRR + 1) is Odd, BRR > 3, and CLKPOLARITY = 1 ......... 2136
18-9. SPI 3-wire Master Mode ................................................................................................ 2139
18-10. SPI 3-wire Slave Mode ................................................................................................. 2139
18-11. Five Bits per Character ................................................................................................. 2142
18-12. SPI Digital Audio Receiver Configuration Using 2 SPIs............................................................ 2143
18-13. Standard Right-Justified Digital Audio Data Format ................................................................ 2143
18-14. SPICCR Register ........................................................................................................ 2146
18-15. SPICTL Register ........................................................................................................ 2148
18-16. SPISTS Register ........................................................................................................ 2150
18-17. SPIBRR Register ........................................................................................................ 2152
18-18. SPIRXEMU Register .................................................................................................... 2153
18-19. SPIRXBUF Register .................................................................................................... 2154
18-20. SPITXBUF Register ..................................................................................................... 2155
18-21. SPIDAT Register ........................................................................................................ 2156
18-22. SPIFFTX Register ....................................................................................................... 2157
18-23. SPIFFRX Register....................................................................................................... 2159
18-24. SPIFFCT Register ....................................................................................................... 2161
18-25. SPIPRI Register ......................................................................................................... 2162
19-1. SCI CPU Interface ...................................................................................................... 2165
19-2. Serial Communications Interface (SCI) Module Block Diagram .................................................. 2166
19-3. Typical SCI Data Frame Formats ..................................................................................... 2168
19-4. Idle-Line Multiprocessor Communication Format ................................................................... 2170
19-5. Double-Buffered WUT and TXSHF ................................................................................... 2170
19-6. Address-Bit Multiprocessor Communication Format................................................................ 2172
19-7. SCI Asynchronous Communications Format ........................................................................ 2172
19-8. SCI RX Signals in Communication Modes ........................................................................... 2173
19-9. SCI TX Signals in Communications Mode ........................................................................... 2173
19-10. SCI FIFO Interrupt Flags and Enable Logic ......................................................................... 2176
19-11. SCICCR Register........................................................................................................ 2180
19-12. SCICTL1 Register ....................................................................................................... 2182
19-13. SCIHBAUD Register .................................................................................................... 2184
19-14. SCILBAUD Register .................................................................................................... 2185
19-15. SCICTL2 Register ....................................................................................................... 2186
19-16. SCIRXST Register ...................................................................................................... 2188
19-17. SCIRXEMU Register .................................................................................................... 2190
19-18. SCIRXBUF Register .................................................................................................... 2191
19-19. SCITXBUF Register..................................................................................................... 2192
19-20. SCIFFTX Register ....................................................................................................... 2193
19-21. SCIFFRX Register ...................................................................................................... 2195

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19-22. SCIFFCT Register....................................................................................................... 2197

19-23. SCIPRI Register ......................................................................................................... 2198
20-1. Multiple I2C Modules Connected ...................................................................................... 2200
20-2. I2C Module Conceptual Block Diagram .............................................................................. 2202
20-3. Clocking Diagram for the I2C Module ................................................................................ 2202
20-4. The Roles of the Clock Divide-Down Values (ICCL and ICCH) ................................................... 2203
20-5. Bit Transfer on the I2C-Bus ............................................................................................ 2204
20-6. I2C Module START and STOP Conditions .......................................................................... 2206
20-7. I2C Module Data Transfer (7-Bit Addressing with 8-bit Data Configuration Shown) ........................... 2206
20-8. I2C Module 7-Bit Addressing Format (FDF = 0, XA = 0 in I2CMDR) ............................................ 2206
20-9. I2C Module 10-Bit Addressing Format (FDF = 0, XA = 1 in I2CMDR) ........................................... 2207
20-10. I2C Module Free Data Format (FDF = 1 in I2CMDR) .............................................................. 2207
20-11. Repeated START Condition (in This Case, 7-Bit Addressing Format) ........................................... 2208
20-12. Synchronization of Two I2C Clock Generators During Arbitration ................................................ 2209
20-13. Arbitration Procedure Between Two Master-Transmitters ......................................................... 2210
20-14. Pin Diagram Showing the Effects of the Digital Loopback Mode (DLB) Bit ..................................... 2210
20-15. Enable Paths of the I2C Interrupt Requests ......................................................................... 2212
20-16. I2COAR Register ........................................................................................................ 2216
20-17. I2CIER Register ......................................................................................................... 2217
20-18. I2CSTR Register ........................................................................................................ 2218
20-19. I2CCLKL Register ....................................................................................................... 2223
20-20. I2CCLKH Register....................................................................................................... 2224
20-21. I2CCNT Register ........................................................................................................ 2225
20-22. I2CDRR Register ........................................................................................................ 2226
20-23. I2CSAR Register ........................................................................................................ 2227
20-24. I2CDXR Register ........................................................................................................ 2228
20-25. I2CMDR Register........................................................................................................ 2229
20-26. I2CISRC Register ....................................................................................................... 2233
20-27. I2CEMDR Register ...................................................................................................... 2234
20-28. I2CPSC Register ........................................................................................................ 2235
20-29. I2CFFTX Register ....................................................................................................... 2236
20-30. I2CFFRX Register ....................................................................................................... 2238
21-1. Conceptual Block Diagram of the McBSP ........................................................................... 2242
21-2. McBSP Data Transfer Paths ........................................................................................... 2243
21-3. Companding Processes ................................................................................................ 2244
21-4. μ-Law Transmit Data Companding Format .......................................................................... 2244
21-5. A-Law Transmit Data Companding Format .......................................................................... 2244
21-6. Two Methods by Which the McBSP Can Compand Internal Data ................................................ 2245
21-7. Example - Clock Signal Control of Bit Transfer Timing ............................................................ 2245
21-8. McBSP Operating at Maximum Packet Frequency ................................................................. 2247
21-9. Single-Phase Frame for a McBSP Data Transfer ................................................................... 2248
21-10. Dual-Phase Frame for a McBSP Data Transfer ..................................................................... 2249
21-11. Implementing the AC97 Standard With a Dual-Phase Frame ..................................................... 2249
21-12. Timing of an AC97-Standard Data Transfer Near Frame Synchronization ...................................... 2250
21-13. McBSP Reception Physical Data Path ............................................................................... 2250
21-14. McBSP Reception Signal Activity ..................................................................................... 2250
21-15. McBSP Transmission Physical Data Path ........................................................................... 2251
21-16. McBSP Transmission Signal Activity ................................................................................. 2251
21-17. Conceptual Block Diagram of the Sample Rate Generator ........................................................ 2253

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21-18. Possible Inputs to the Sample Rate Generator and the Polarity Bits ............................................ 2255
21-19. CLKG Synchronization and FSG Generation When GSYNC = 1 and CLKGDV = 1 ........................... 2257
21-20. CLKG Synchronization and FSG Generation When GSYNC = 1 and CLKGDV = 3 ........................... 2258
21-21. Overrun in the McBSP Receiver ...................................................................................... 2260
21-22. Overrun Prevented in the McBSP Receiver ......................................................................... 2261
21-23. Possible Responses to Receive Frame-Synchronization Pulses ................................................. 2261
21-24. An Unexpected Frame-Synchronization Pulse During a McBSP Reception .................................... 2262
21-25. Proper Positioning of Frame-Synchronization Pulses .............................................................. 2263
21-26. Data in the McBSP Transmitter Overwritten and Thus Not Transmitted......................................... 2263
21-27. Underflow During McBSP Transmission ............................................................................. 2264
21-28. Underflow Prevented in the McBSP Transmitter .................................................................... 2265
21-29. Possible Responses to Transmit Frame-Synchronization Pulses ................................................ 2265
21-30. An Unexpected Frame-Synchronization Pulse During a McBSP Transmission ................................ 2266
21-31. Proper Positioning of Frame-Synchronization Pulses .............................................................. 2267
21-32. Alternating Between the Channels of Partition A and the Channels of Partition B ............................. 2269
21-33. Reassigning Channel Blocks Throughout a McBSP Data Transfer .............................................. 2270
21-34. McBSP Data Transfer in the 8-Partition Mode ...................................................................... 2271
21-35. Activity on McBSP Pins for the Possible Values of XMCM ........................................................ 2274
21-36. Typical SPI Interface .................................................................................................... 2275
21-37. SPI Transfer With CLKSTP = 10b (No Clock Delay), CLKXP = 0, and CLKRP = 0 ........................... 2277
21-38. SPI Transfer With CLKSTP = 11b (Clock Delay), CLKXP = 0, CLKRP = 1 ..................................... 2277
21-39. SPI Transfer With CLKSTP = 10b (No Clock Delay), CLKXP = 1, and CLKRP = 0 ........................... 2277
21-40. SPI Transfer With CLKSTP = 11b (Clock Delay), CLKXP = 1, CLKRP = 1 ..................................... 2277
21-41. SPI Interface with McBSP Used as Master .......................................................................... 2279
21-42. SPI Interface With McBSP Used as Slave ........................................................................... 2280
21-43. Unexpected Frame-Synchronization Pulse With (R/X)FIG = 0 .................................................... 2287
21-44. Unexpected Frame-Synchronization Pulse With (R/X)FIG = 1 .................................................... 2287
21-45. Companding Processes for Reception and for Transmission .................................................... 2288
21-46. Range of Programmable Data Delay ................................................................................. 2289
21-47. 2-Bit Data Delay Used to Skip a Framing Bit ........................................................................ 2289
21-48. Data Clocked Externally Using a Rising Edge and Sampled by the McBSP Receiver on a Falling Edge .. 2294
21-49. Frame of Period 16 CLKG Periods and Active Width of 2 CLKG Periods ....................................... 2295
21-51. Unexpected Frame-Synchronization Pulse With (R/X) FIG = 0 ................................................... 2307
21-52. Unexpected Frame-Synchronization Pulse With (R/X) FIG = 1 ................................................... 2307
21-53. Companding Processes for Reception and for Transmission ..................................................... 2308
21-54. μ-Law Transmit Data Companding Format .......................................................................... 2308
21-55. A-Law Transmit Data Companding Format .......................................................................... 2309
21-56. Range of Programmable Data Delay ................................................................................. 2310
21-57. 2-Bit Data Delay Used to Skip a Framing Bit ........................................................................ 2310
21-59. Frame of Period 16 CLKG Periods and Active Width of 2 CLKG Periods ....................................... 2314
21-61. Four 8-Bit Data Words Transferred To/From the McBSP .......................................................... 2320
21-62. One 32-Bit Data Word Transferred To/From the McBSP .......................................................... 2320
21-63. 8-Bit Data Words Transferred at Maximum Packet Frequency ................................................... 2321
21-64. Configuring the Data Stream of as a Continuous 32-Bit Word .................................................... 2321
21-65. Receive Interrupt Generation .......................................................................................... 2322
21-66. Transmit Interrupt Generation ......................................................................................... 2322

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21-67. Data Receive Registers (DRR2 and DRR1) ......................................................................... 2326

21-68. Data Transmit Registers (DXR2 and DXR1) ........................................................................ 2326
21-69. Serial Port Control 1 Register (SPCR1) ............................................................................. 2327
21-70. Serial Port Control 2 Register (SPCR2) ............................................................................. 2330
21-71. Receive Control Register 1 (RCR1) .................................................................................. 2332
21-72. Receive Control Register 2 (RCR2) .................................................................................. 2333
21-73. Transmit Control 1 Register (XCR1) .................................................................................. 2335
21-74. Transmit Control 2 Register (XCR2) ................................................................................. 2336
21-75. Sample Rate Generator 1 Register (SRGR1) ....................................................................... 2338
21-76. Sample Rate Generator 2 Register (SRGR2) ....................................................................... 2338
21-77. Multichannel Control 1 Register (MCR1) ............................................................................ 2340
21-78. Multichannel Control 2 Register (MCR2) ............................................................................. 2342
21-79. Pin Control Register (PCR) ........................................................................................... 2344
21-80. Receive Channel Enable Registers (RCERA...RCERH) ........................................................... 2346
21-81. Transmit Channel Enable Registers (XCERA...XCERH) .......................................................... 2348
21-82. McBSP Interrupt Enable Register (MFFINT) ........................................................................ 2350
22-1. CAN Block Diagram ..................................................................................................... 2353
22-2. CAN Core in Silent Mode .............................................................................................. 2357
22-3. CAN Core in Loopback Mode ......................................................................................... 2358
22-4. CAN Core in External Loopback Mode ............................................................................... 2359
22-5. CAN Core in Loopback Combined with Silent Mode ............................................................... 2359
22-6. Initialization of a Transmit Object ..................................................................................... 2362
22-7. Initialization of a single Receive Object for Data Frames .......................................................... 2363
22-8. Initialization of a single Receive Object for Remote Frames ...................................................... 2363
22-9. CPU Handling of a FIFO Buffer (Interrupt Driven) .................................................................. 2368
22-10. Bit Timing ................................................................................................................. 2369
22-11. The Propagation Time Segment ...................................................................................... 2370
22-12. Synchronization on Late and Early Edges ........................................................................... 2372
22-13. Filtering of Short Dominant Spikes .................................................................................... 2373
22-14. Structure of the CAN Core's CAN Protocol Controller ............................................................. 2374
22-15. Data Transfer Between IF1 / IF2 Registers and Message RAM .................................................. 2377
22-16. Structure of a Message Object ........................................................................................ 2378
22-17. Message RAM Representation in Debug Mode ..................................................................... 2382
22-18. CAN_CTL Register ...................................................................................................... 2386
22-19. CAN_ES Register ....................................................................................................... 2389
22-20. CAN_ERRC Register ................................................................................................... 2391
22-21. CAN_BTR Register ..................................................................................................... 2392
22-22. CAN_INT Register ...................................................................................................... 2394
22-23. CAN_TEST Register .................................................................................................... 2395
22-24. CAN_PERR Register ................................................................................................... 2397
22-25. CAN_RAM_INIT Register .............................................................................................. 2398
22-26. CAN_GLB_INT_EN Register .......................................................................................... 2399
22-27. CAN_GLB_INT_FLG Register ......................................................................................... 2400
22-28. CAN_GLB_INT_CLR Register......................................................................................... 2401
22-29. CAN_ABOTR Register ................................................................................................. 2402
22-30. CAN_TXRQ_X Register ................................................................................................ 2403
22-31. CAN_TXRQ_21 Register ............................................................................................... 2404
22-32. CAN_NDAT_X Register ................................................................................................ 2405
22-33. CAN_NDAT_21 Register ............................................................................................... 2406

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22-34. CAN_IPEN_X Register ................................................................................................. 2407

22-35. CAN_IPEN_21 Register ................................................................................................ 2408
22-36. CAN_MVAL_X Register ................................................................................................ 2409
22-37. CAN_MVAL_21 Register ............................................................................................... 2410
22-38. CAN_IP_MUX21 Register .............................................................................................. 2411
22-39. CAN_IF1CMD Register ................................................................................................. 2412
22-40. CAN_IF1MSK Register ................................................................................................. 2416
22-41. CAN_IF1ARB Register ................................................................................................. 2417
22-42. CAN_IF1MCTL Register ............................................................................................... 2419
22-43. CAN_IF1DATA Register ................................................................................................ 2422
22-44. CAN_IF1DATB Register ................................................................................................ 2423
22-45. CAN_IF2CMD Register ................................................................................................. 2424
22-51. CAN_IF3OBS Register ................................................................................................. 2436
22-57. CAN_IF3UPD Register ................................................................................................. 2444
23-1. USB Block Diagram ..................................................................................................... 2446
23-2. USB Scheme............................................................................................................. 2447
23-3. Function Address Register (USBFADDR) ........................................................................... 2473
23-4. Power Management Register (USBPOWER) in Host Mode....................................................... 2474
23-5. Power Management Register (USBPOWER) in Device Mode .................................................... 2474
23-6. USB Transmit Interrupt Status Register (USBTXIS) ................................................................ 2476
23-7. USB Transmit Interrupt Status Register (USBRXIS) ............................................................... 2478
23-8. USB Transmit Interrupt Status Enable Register (USBTXIE) ...................................................... 2480
23-9. USB Transmit Interrupt Status Enable Register (USBRXIE) ...................................................... 2482
23-10. USB General Interrupt Status Register (USBIS) in Host Mode ................................................... 2484
23-11. USB General Interrupt Status Register (USBIS) in Device Mode ................................................ 2485
23-12. USB Interrupt Enable Register (USBIE) in Host Mode ............................................................. 2486
23-13. USB Interrupt Enable Register (USBIE) in Device Mode .......................................................... 2487
23-14. Frame Number Register (FRAME) .................................................................................... 2488
23-15. USB Endpoint Index Register (USBEPIDX) ......................................................................... 2488
23-16. USB Test Mode Register (USBTEST) in Host Mode ............................................................... 2489
23-17. USB Test Mode Register (USBTEST) in Device Mode ............................................................ 2489
23-18. USB FIFO Endpoint n Register (USBFIFO[n]) ...................................................................... 2491
23-19. USB Device Control Register (USBDEVCTL) ....................................................................... 2492
23-20. USB Transmit Dynamic FIFO Sizing Register (USBTXFIFOSZ) ................................................. 2494
23-21. USB Receive Dynamic FIFO Sizing Register (USBRXFIFOSZ) .................................................. 2495
23-22. USB Transmit FIFO Start Address Register (USBTXFIFOADDR]) ............................................... 2496
23-23. USB Receive FIFO Start Address Register (USBRXFIFOADDR) ................................................ 2497
23-24. USB Connect Timing Register (USBCONTIM) ...................................................................... 2498
23-25. USB Full-Speed Last Transaction to End of Frame Timing Register (USBFSEOF) ........................... 2499

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23-26. USB Low-Speed Last Transaction to End of Frame Timing Register (USBLSEOF) ........................... 2499
23-27. USB Transmit Functional Address Endpoint n Registers (USBTXFUNCADDR[n]) ............................ 2500
23-28. USB Transmit Hub Address Endpoint n Registers (USBTXHUBADDR[n])...................................... 2501
23-29. USB Transmit Hub Port Endpoint n Registers (USBTXHUBPORT[n]) ........................................... 2502
23-30. USB Receive Functional Address Endpoint n Registers (USBFIFO[n]) ......................................... 2503
23-31. USB Receive Hub Address Endpoint n Registers (USBRXHUBADDR[n]) ...................................... 2504
23-32. USB Transmit Hub Port Endpoint n Registers (USBRXHUBPORT[n]) .......................................... 2505
23-33. USB Maximum Transmit Data Endpoint n Registers (USBTXMAXP[n]) ......................................... 2506
23-34. USB Control and Status Endpoint 0 Low Register (USBCSRL0) in Host Mode ................................ 2507
23-35. USB Control and Status Endpoint 0 Low Register (USBCSRL0) in Device Mode ............................. 2508
23-36. USB Control and Status Endpoint 0 High Register (USBCSRH0) in Host Mode ............................... 2509
23-37. USB Control and Status Endpoint 0 High Register (USBCSRH0) in Device Mode ............................ 2509
23-38. USB Receive Byte Count Endpoint 0 Register (USBCOUNT0)................................................... 2510
23-39. USB Type Endpoint 0 Register (USBTYPE0) ....................................................................... 2510
23-40. USB NAK Limit Register (USBNAKLMT) ............................................................................ 2511
23-41. USB Transmit Control and Status Endpoint n Low Register (USBTXCSRL[n]) in Host Mode ................ 2512
23-42. USB Transmit Control and Status Endpoint n Low Register (USBTXCSRL[n]) in Device Mode ............. 2513
23-43. USB Transmit Control and Status Endpoint n High Register (USBTXCSRH[n]) in Host Mode ............... 2515
23-44. USB Transmit Control and Status Endpoint n High Register (USBTXCSRH[n]) in Device Mode ............ 2516
23-45. USB Maximum Receive Data Endpoint n Registers (USBRXMAXP[n]) ......................................... 2517
23-46. USB Receive Control and Status Endpoint n Low Register (USBCSRL[n]) in Host Mode .................... 2518
23-47. USB Control and Status Endpoint n Low Register (USBCSRL[n]) in Device Mode ............................ 2519
23-48. USB Receive Control and Status Endpoint n High Register (USBCSRH[n]) in Host Mode ................... 2520
23-49. USB Control and Status Endpoint n High Register (USBCSRH[n]) in Device Mode ........................... 2521
23-50. USB Maximum Receive Data Endpoint n Registers (USBRXCOUNT[n]) ....................................... 2522
23-51. USB Host Transmit Configure Type Endpoint n Register (USBTXTYPE[n]) .................................... 2523
23-52. USB Host Transmit Interval Endpoint n Register (USBTXINTERVAL[n]) ....................................... 2524
23-53. USB Host Configure Receive Type Endpoint n Register (USBRXTYPE[n]) .................................... 2525
23-54. USB Host Receive Polling Interval Endpoint n Register (USBRXINTERVAL[n]) ............................... 2526
23-55. USB Request Packet Count in Block Transfer Endpoint n Registers (USBRQPKTCOUNT[n]) .............. 2527
23-56. USB Receive Double Packet Buffer Disable Register (USBRXDPKTBUFDIS) ................................. 2528
23-57. USB Transmit Double Packet Buffer Disable Register (USBTXDPKTBUFDIS) ................................ 2530
23-58. USB External Power Control Register (USBEPC) .................................................................. 2531
23-59. USB External Power Control Raw Interrupt Status Register (USBEPCRIS) .................................... 2533
23-60. USB External Power Control Interrupt Mask Register (USBEPCIM) ............................................. 2534
23-61. USB External Power Control Interrupt Status and Clear Register (USBEPCISC) .............................. 2535
23-62. USB Device RESUME Raw Interrupt Status Register (USBDRRIS) ............................................. 2536
23-63. USB Device RESUME Raw Interrupt Status Register (USBDRRIS) ............................................. 2537
23-64. USB Device RESUME Interrupt Status and Clear Register (USBDRISC)....................................... 2538
23-65. USB General-Purpose Control and Status Register (USBGPCS) ................................................ 2539
23-66. USB DMA Select Register (USBDMASEL) .......................................................................... 2540
24-1. uPP Integration .......................................................................................................... 2543
24-2. Functional Block Diagram .............................................................................................. 2544
24-3. RX in SDR or DDR (non-demux) Mode .............................................................................. 2545
24-4. RX in DDR (demux) Mode ............................................................................................. 2545
24-5. TX in SDR (non-interleave) or DDR (non-demux) Mode ........................................................... 2545
24-6. TX in SDR (interleave) or DDR (demux) Mode ..................................................................... 2545
24-7. IO Output Clock Generation for TX Mode............................................................................ 2546
24-8. IO Input clock for RX Mode ............................................................................................ 2546

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24-9. Structure of DMA Window and Lines in Memory.................................................................... 2548

24-10. uPP Receive in SDR Mode ............................................................................................ 2550
24-11. uPP Transmit in SDR Mode ........................................................................................... 2551
24-12. uPP Transmit in SDR Mode – Interleaving .......................................................................... 2551
24-13. uPP Receive DDR Case ............................................................................................... 2551
24-14. uPP Transmit DDR Case ............................................................................................... 2551
24-15. uPP Tx Data Pattern in Non-Interleaved Mode ..................................................................... 2552
24-16. uPP Rx Data Pattern in Non-Interleaved Mode ..................................................................... 2552
24-17. PID Register ............................................................................................................. 2560
24-18. PERCTL Register ....................................................................................................... 2561
24-19. CHCTL Register ......................................................................................................... 2563
24-20. IFCFG Register .......................................................................................................... 2564
24-21. IFIVAL Register .......................................................................................................... 2566
24-22. THCFG Register ......................................................................................................... 2567
24-23. RAWINTST Register .................................................................................................... 2569
24-24. ENINTST Register ...................................................................................................... 2571
24-25. INTENSET Register..................................................................................................... 2573
24-26. INTENCLR Register .................................................................................................... 2575
24-27. CHIDESC0 Register .................................................................................................... 2577
24-30. CHIST0 Register ........................................................................................................ 2580
24-31. CHIST1 Register ........................................................................................................ 2581
24-32. CHIST2 Register ........................................................................................................ 2582
24-33. CHQDESC0 Register ................................................................................................... 2583
24-36. CHQST0 Register ....................................................................................................... 2586
24-37. CHQST1 Register ....................................................................................................... 2587
24-38. CHQST2 Register ....................................................................................................... 2588
24-39. GINTEN Register ........................................................................................................ 2589
24-40. GINTFLG Register ...................................................................................................... 2590
24-41. GINTCLR Register ...................................................................................................... 2591
24-42. DLYCTL Register........................................................................................................ 2592
25-1. EMIF Module Overview ................................................................................................. 2594
25-2. EMIF Functional Block Diagram ....................................................................................... 2596
25-3. Timing Waveform of SDRAM PRE Command ...................................................................... 2599
25-4. EMIF to 2M × 16 × 4 bank SDRAM Interface ....................................................................... 2600
25-5. EMIF to 512K × 16 × 2 bank SDRAM Interface ..................................................................... 2600
25-6. Timing Waveform for Basic SDRAM Read Operation .............................................................. 2608
25-7. Timing Waveform for Basic SDRAM Write Operation .............................................................. 2609
25-8. EMIF Asynchronous Interface ......................................................................................... 2611
25-9. EMIF to 8-bit/16-bit Memory Interface ................................................................................ 2612
25-10. Common Asynchronous Interface ..................................................................................... 2612
25-11. Timing Waveform of an Asynchronous Read Cycle in Normal Mode ............................................ 2616
25-12. Timing Waveform of an Asynchronous Write Cycle in Normal Mode ............................................ 2618
25-13. Timing Waveform of an Asynchronous Read Cycle in Select Strobe Mode .................................... 2620
25-14. Timing Waveform of an Asynchronous Write Cycle in Select Strobe Mode ..................................... 2622
25-15. Example Configuration Interface ...................................................................................... 2629

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25-16. SDRAM Timing Register (SDRAM_TR) .............................................................................. 2630

25-17. SDRAM Self Refresh Exit Timing Register (SDR_EXT_TMNG) .................................................. 2631
25-18. SDRAM Refresh Control Register (SDRAM_RCR) ................................................................. 2632
25-19. SDRAM Configuration Register (SDRAM_CR)...................................................................... 2632
25-20. LH28F800BJE-PTTL90 to EMIF Read Timing Waveforms ........................................................ 2633
25-21. LH28F800BJE-PTTL90 to EMIF Write Timing Waveforms ........................................................ 2634
25-22. Asynchronous m Configuration Register (m = 1, 2) (ASYNC_CSn_CR(n = 2, 3)) ............................. 2635
25-23. RCSR Register .......................................................................................................... 2638
25-24. ASYNC_WCCR Register ............................................................................................... 2639
25-25. SDRAM_CR Register ................................................................................................... 2640
25-26. SDRAM_RCR Register ................................................................................................. 2642
25-27. ASYNC_CS2_CR Register ............................................................................................ 2643
25-30. SDRAM_TR Register ................................................................................................... 2649
25-31. TOTAL_SDRAM_AR Register ......................................................................................... 2650
25-32. TOTAL_SDRAM_ACTR Register ..................................................................................... 2651
25-33. SDR_EXT_TMNG Register ............................................................................................ 2652
25-34. INT_RAW Register ...................................................................................................... 2653
25-35. INT_MSK Register ...................................................................................................... 2654
25-36. INT_MSK_SET Register ............................................................................................... 2655
25-37. INT_MSK_CLR Register ............................................................................................... 2656
25-38. EMIF1LOCK Register ................................................................................................... 2658
25-39. EMIF1COMMIT Register ............................................................................................... 2659
25-40. EMIF1MSEL Register ................................................................................................... 2660
25-41. EMIF1ACCPROT0 Register ........................................................................................... 2661
25-42. EMIF2LOCK Register ................................................................................................... 2663
25-43. EMIF2COMMIT Register ............................................................................................... 2664
25-44. EMIF2ACCPROT0 Register ........................................................................................... 2665

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List of Tables
1-1. TMU Supported Instructions .............................................................................................. 83
1-2. Viterbi Decode Performance .............................................................................................. 84
1-3. Complex Math Performance .............................................................................................. 84
2-1. Reset Signals ............................................................................................................... 87
2-2. PIE Channel Mapping ..................................................................................................... 95
2-3. CPU Interrupt Vectors ..................................................................................................... 96
2-4. PIE Interrupt Vectors ....................................................................................................... 97
2-5. Access to EALLOW-Protected Registers .............................................................................. 104
2-6. Clock Connections Sorted by Clock Domain .......................................................................... 113
2-7. Clock Connections Sorted by Module Name .......................................................................... 114
2-8. Example Watchdog Key Sequences ................................................................................... 119
2-9. Local Shared RAM........................................................................................................ 126
2-10. Global Shared RAM ...................................................................................................... 126
2-11. Error Handling in Different Scenarios .................................................................................. 131
2-12. Mapping of ECC Bits in Read Data from ECC/Parity Address Map ............................................... 132
2-13. Mapping of Parity Bits in Read Data from ECC/Parity Address Map .............................................. 132
2-14. RAM Status ................................................................................................................ 146
2-15. Security Levels ............................................................................................................ 147
2-16. System Control Base Address Table................................................................................... 159
2-17. CPUTIMER_REGS Registers ........................................................................................... 160
2-18. CPUTIMER_REGS Access Type Codes .............................................................................. 160
2-19. TIM Register Field Descriptions ........................................................................................ 161
2-20. PRD Register Field Descriptions ....................................................................................... 162
2-21. TCR Register Field Descriptions........................................................................................ 163
2-22. TPR Register Field Descriptions ........................................................................................ 165
2-23. TPRH Register Field Descriptions ...................................................................................... 166
2-24. PIE_CTRL_REGS Registers ............................................................................................ 167
2-25. PIE_CTRL_REGS Access Type Codes ............................................................................... 167
2-26. PIECTRL Register Field Descriptions .................................................................................. 169
2-27. PIEACK Register Field Descriptions ................................................................................... 170
2-28. PIEIER1 Register Field Descriptions ................................................................................... 171
2-29. PIEIFR1 Register Field Descriptions ................................................................................... 173
SPRUHM8G – December 2013 – Revised September 2017 List of Tables 49

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2-46. PIEIER10 Register Field Descriptions ................................................................................. 207
2-47. PIEIFR10 Register Field Descriptions ................................................................................. 209
2-52. WD_REGS Registers .................................................................................................... 219
2-53. WD_REGS Access Type Codes ........................................................................................ 219
2-54. SCSR Register Field Descriptions ...................................................................................... 220
2-55. WDCNTR Register Field Descriptions ................................................................................. 221
2-56. WDKEY Register Field Descriptions ................................................................................... 222
2-57. WDCR Register Field Descriptions ..................................................................................... 223
2-58. WDWCR Register Field Descriptions .................................................................................. 224
2-59. NMI_INTRUPT_REGS Registers ....................................................................................... 225
2-60. NMI_INTRUPT_REGS Access Type Codes .......................................................................... 225
2-61. NMICFG Register Field Descriptions .................................................................................. 226
2-62. NMIFLG Register Field Descriptions ................................................................................... 227
2-63. NMIFLGCLR Register Field Descriptions.............................................................................. 229
2-64. NMIFLGFRC Register Field Descriptions ............................................................................. 232
2-65. NMIWDCNT Register Field Descriptions .............................................................................. 234
2-66. NMIWDPRD Register Field Descriptions .............................................................................. 235
2-67. NMISHDFLG Register Field Descriptions ............................................................................. 236
2-68. XINT_REGS Registers ................................................................................................... 238
2-69. XINT_REGS Access Type Codes ...................................................................................... 238
2-70. XINT1CR Register Field Descriptions.................................................................................. 239
2-75. XINT1CTR Register Field Descriptions ................................................................................ 244
2-78. DMA_CLA_SRC_SEL_REGS Registers .............................................................................. 247
2-79. DMA_CLA_SRC_SEL_REGS Access Type Codes .................................................................. 247
2-80. CLA1TASKSRCSELLOCK Register Field Descriptions ............................................................. 248
2-81. DMACHSRCSELLOCK Register Field Descriptions ................................................................. 249
2-82. CLA1TASKSRCSEL1 Register Field Descriptions ................................................................... 250
2-83. CLA1TASKSRCSEL2 Register Field Descriptions ................................................................... 251
2-84. DMACHSRCSEL1 Register Field Descriptions ....................................................................... 252
2-85. DMACHSRCSEL2 Register Field Descriptions ....................................................................... 253
2-86. FLASH_PUMP_SEMAPHORE_REGS Registers .................................................................... 254
2-87. FLASH_PUMP_SEMAPHORE_REGS Access Type Codes ....................................................... 254
2-88. PUMPREQUEST Register Field Descriptions ........................................................................ 255
2-89. DEV_CFG_REGS Registers ............................................................................................ 256
2-90. DEV_CFG_REGS Access Type Codes ............................................................................... 257
2-91. DEVCFGLOCK1 Register Field Descriptions ......................................................................... 258
2-92. PARTIDL_1 Register Field Descriptions ............................................................................... 260
2-93. PARTIDH_1 Register Field Descriptions .............................................................................. 262
50 List of Tables SPRUHM8G – December 2013 – Revised September 2017

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2-94. REVID Register Field Descriptions ..................................................................................... 263

2-95. DC0_1 Register Field Descriptions ..................................................................................... 264
2-105. DC10_1 Register Field Descriptions ................................................................................... 275
2-115. PERCNF1_1 Register Field Descriptions.............................................................................. 287
2-116. FUSEERR Register Field Descriptions ................................................................................ 288
2-117. SOFTPRES0 Register Field Descriptions ............................................................................. 289
2-126. SOFTPRES11 Register Field Descriptions............................................................................ 299
2-130. CPUSEL0 Register Field Descriptions ................................................................................. 303
2-140. CPUSEL11 Register Field Descriptions ............................................................................... 314

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2-143. CPU2RESCTL Register Field Descriptions ........................................................................... 319

2-144. RSTSTAT Register Field Descriptions ................................................................................. 320
2-145. LPMSTAT Register Field Descriptions ................................................................................. 321
2-146. SYSDBGCTL Register Field Descriptions ............................................................................. 322
2-147. CLK_CFG_REGS Registers ............................................................................................ 323
2-148. CLK_CFG_REGS Access Type Codes ................................................................................ 323
2-149. CLKSEM Register Field Descriptions .................................................................................. 325
2-150. CLKCFGLOCK1 Register Field Descriptions ......................................................................... 326
2-151. CLKSRCCTL1 Register Field Descriptions............................................................................ 328
2-154. SYSPLLCTL1 Register Field Descriptions ............................................................................ 333
2-155. SYSPLLMULT Register Field Descriptions............................................................................ 334
2-156. SYSPLLSTS Register Field Descriptions .............................................................................. 335
2-157. AUXPLLCTL1 Register Field Descriptions ............................................................................ 336
2-158. AUXPLLMULT Register Field Descriptions ........................................................................... 337
2-159. AUXPLLSTS Register Field Descriptions.............................................................................. 338
2-160. SYSCLKDIVSEL Register Field Descriptions ......................................................................... 339
2-161. AUXCLKDIVSEL Register Field Descriptions ......................................................................... 340
2-162. PERCLKDIVSEL Register Field Descriptions ......................................................................... 341
2-163. XCLKOUTDIVSEL Register Field Descriptions ....................................................................... 342
2-164. LOSPCP Register Field Descriptions .................................................................................. 343
2-165. MCDCR Register Field Descriptions ................................................................................... 344
2-166. X1CNT Register Field Descriptions .................................................................................... 345
2-167. CPU_SYS_REGS Registers ............................................................................................ 346
2-168. CPU_SYS_REGS Access Type Codes ................................................................................ 346
2-169. CPUSYSLOCK1 Register Field Descriptions ......................................................................... 348
2-170. HIBBOOTMODE Register Field Descriptions ......................................................................... 351
2-171. IORESTOREADDR Register Field Descriptions...................................................................... 352
2-172. PIEVERRADDR Register Field Descriptions .......................................................................... 353
2-173. PCLKCR0 Register Field Descriptions ................................................................................. 354
2-182. PCLKCR10 Register Field Descriptions ............................................................................... 366
2-188. SECMSEL_1 Register Field Descriptions ............................................................................. 373
2-189. LPMCR Register Field Descriptions .................................................................................... 374
2-190. GPIOLPMSEL0 Register Field Descriptions .......................................................................... 376
2-191. GPIOLPMSEL1 Register Field Descriptions .......................................................................... 379

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2-192. TMR2CLKCTL Register Field Descriptions ........................................................................... 382

2-193. RESC Register Field Descriptions ...................................................................................... 384
2-194. ROM_PREFETCH_REGS Registers................................................................................... 386
2-195. ROM_PREFETCH_REGS Access Type Codes ...................................................................... 386
2-196. ROMPREFETCH Register Field Descriptions ........................................................................ 387
2-197. DCSM_Z1_OTP Registers .............................................................................................. 388
2-198. DCSM_Z1_OTP Access Type Codes .................................................................................. 388
2-199. Z1OTP_LINKPOINTER1 Register Field Descriptions ............................................................... 389
2-202. Z1OTP_PSWDLOCK Register Field Descriptions ................................................................... 392
2-203. Z1OTP_CRCLOCK Register Field Descriptions ...................................................................... 393
2-204. Z1OTP_BOOTCTRL Register Field Descriptions .................................................................... 394
2-205. DCSM_Z2_OTP Registers .............................................................................................. 395
2-206. DCSM_Z2_OTP Access Type Codes .................................................................................. 395
2-210. Z2OTP_PSWDLOCK Register Field Descriptions ................................................................... 399
2-211. Z2OTP_CRCLOCK Register Field Descriptions ...................................................................... 400
2-212. Z2OTP_BOOTCTRL Register Field Descriptions .................................................................... 401
2-213. DCSM_Z1_REGS Registers ............................................................................................ 402
2-214. DCSM_Z1_REGS Access Type Codes ................................................................................ 402
2-215. Z1_LINKPOINTER Register Field Descriptions ...................................................................... 403
2-216. Z1_OTPSECLOCK Register Field Descriptions ...................................................................... 404
2-217. Z1_BOOTCTRL Register Field Descriptions .......................................................................... 405
2-218. Z1_LINKPOINTERERR Register Field Descriptions ................................................................. 406
2-219. Z1_CSMKEY0 Register Field Descriptions............................................................................ 407
2-223. Z1_CR Register Field Descriptions..................................................................................... 411
2-224. Z1_GRABSECTR Register Field Descriptions ........................................................................ 412
2-225. Z1_GRABRAMR Register Field Descriptions ......................................................................... 415
2-226. Z1_EXEONLYSECTR Register Field Descriptions................................................................... 417
2-227. Z1_EXEONLYRAMR Register Field Descriptions .................................................................... 420
2-228. DCSM_Z2_REGS Registers ............................................................................................ 422
2-229. DCSM_Z2_REGS Access Type Codes ................................................................................ 422
2-230. Z2_LINKPOINTER Register Field Descriptions ...................................................................... 423
2-231. Z2_OTPSECLOCK Register Field Descriptions ...................................................................... 424
2-232. Z2_BOOTCTRL Register Field Descriptions .......................................................................... 425
2-233. Z2_LINKPOINTERERR Register Field Descriptions ................................................................. 426
2-238. Z2_CR Register Field Descriptions..................................................................................... 431
2-239. Z2_GRABSECTR Register Field Descriptions ........................................................................ 432
2-240. Z2_GRABRAMR Register Field Descriptions ......................................................................... 435

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2-241. Z2_EXEONLYSECTR Register Field Descriptions................................................................... 437

2-242. Z2_EXEONLYRAMR Register Field Descriptions .................................................................... 440
2-243. DCSM_COMMON_REGS Registers ................................................................................... 442
2-244. DCSM_COMMON_REGS Access Type Codes ...................................................................... 442
2-245. FLSEM Register Field Descriptions .................................................................................... 443
2-246. SECTSTAT Register Field Descriptions ............................................................................... 444
2-247. RAMSTAT Register Field Descriptions ................................................................................ 447
2-248. MEM_CFG_REGS Registers ........................................................................................... 449
2-249. MEM_CFG_REGS Access Type Codes ............................................................................... 449
2-250. DxLOCK Register Field Descriptions .................................................................................. 451
2-251. DxCOMMIT Register Field Descriptions ............................................................................... 452
2-252. DxACCPROT0 Register Field Descriptions ........................................................................... 453
2-253. DxTEST Register Field Descriptions ................................................................................... 454
2-254. DxINIT Register Field Descriptions ..................................................................................... 455
2-255. DxINITDONE Register Field Descriptions ............................................................................. 456
2-256. LSxLOCK Register Field Descriptions ................................................................................. 457
2-257. LSxCOMMIT Register Field Descriptions.............................................................................. 459
2-258. LSxMSEL Register Field Descriptions ................................................................................. 461
2-259. LSxCLAPGM Register Field Descriptions ............................................................................. 463
2-260. LSxACCPROT0 Register Field Descriptions .......................................................................... 464
2-261. LSxACCPROT1 Register Field Descriptions .......................................................................... 466
2-262. LSxTEST Register Field Descriptions.................................................................................. 467
2-263. LSxINIT Register Field Descriptions ................................................................................... 469
2-264. LSxINITDONE Register Field Descriptions............................................................................ 470
2-265. GSxLOCK Register Field Descriptions................................................................................. 471
2-266. GSxCOMMIT Register Field Descriptions ............................................................................. 474
2-267. GSxMSEL Register Field Descriptions................................................................................. 477
2-268. GSxACCPROT0 Register Field Descriptions ......................................................................... 479
2-272. GSxTEST Register Field Descriptions ................................................................................. 487
2-273. GSxINIT Register Field Descriptions ................................................................................... 490
2-274. GSxINITDONE Register Field Descriptions ........................................................................... 492
2-275. MSGxTEST Register Field Descriptions ............................................................................... 494
2-276. MSGxINIT Register Field Descriptions................................................................................. 495
2-277. MSGxINITDONE Register Field Descriptions ......................................................................... 496
2-278. ACCESS_PROTECTION_REGS Registers ........................................................................... 497
2-279. ACCESS_PROTECTION_REGS Access Type Codes .............................................................. 497
2-280. NMAVFLG Register Field Descriptions ................................................................................ 499
2-281. NMAVSET Register Field Descriptions ................................................................................ 501
2-282. NMAVCLR Register Field Descriptions ................................................................................ 503
2-283. NMAVINTEN Register Field Descriptions ............................................................................. 505
2-284. NMCPURDAVADDR Register Field Descriptions .................................................................... 506
2-285. NMCPUWRAVADDR Register Field Descriptions ................................................................... 507
2-286. NMCPUFAVADDR Register Field Descriptions ...................................................................... 508
2-287. NMDMAWRAVADDR Register Field Descriptions ................................................................... 509
2-288. NMCLA1RDAVADDR Register Field Descriptions ................................................................... 510
2-289. NMCLA1WRAVADDR Register Field Descriptions .................................................................. 511

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2-290. NMCLA1FAVADDR Register Field Descriptions ..................................................................... 512

2-291. MAVFLG Register Field Descriptions .................................................................................. 513
2-292. MAVSET Register Field Descriptions .................................................................................. 514
2-293. MAVCLR Register Field Descriptions .................................................................................. 515
2-294. MAVINTEN Register Field Descriptions ............................................................................... 516
2-295. MCPUFAVADDR Register Field Descriptions ........................................................................ 517
2-296. MCPUWRAVADDR Register Field Descriptions ..................................................................... 518
2-297. MDMAWRAVADDR Register Field Descriptions ..................................................................... 519
2-298. MEMORY_ERROR_REGS Registers.................................................................................. 520
2-299. MEMORY_ERROR_REGS Access Type Codes ..................................................................... 520
2-300. UCERRFLG Register Field Descriptions .............................................................................. 521
2-301. UCERRSET Register Field Descriptions .............................................................................. 522
2-302. UCERRCLR Register Field Descriptions .............................................................................. 523
2-303. UCCPUREADDR Register Field Descriptions ........................................................................ 524
2-304. UCDMAREADDR Register Field Descriptions ........................................................................ 525
2-305. UCCLA1READDR Register Field Descriptions ....................................................................... 526
2-306. CERRFLG Register Field Descriptions ................................................................................ 527
2-307. CERRSET Register Field Descriptions ................................................................................ 528
2-308. CERRCLR Register Field Descriptions ................................................................................ 529
2-309. CCPUREADDR Register Field Descriptions .......................................................................... 530
2-310. CERRCNT Register Field Descriptions ................................................................................ 531
2-311. CERRTHRES Register Field Descriptions ............................................................................ 532
2-312. CEINTFLG Register Field Descriptions ................................................................................ 533
2-313. CEINTCLR Register Field Descriptions ................................................................................ 534
2-314. CEINTSET Register Field Descriptions ................................................................................ 535
2-315. CEINTEN Register Field Descriptions ................................................................................. 536
2-316. ROM_WAIT_STATE_REGS Registers ................................................................................ 537
2-317. ROM_WAIT_STATE_REGS Access Type Codes ................................................................... 537
2-318. ROMWAITSTATE Register Field Descriptions ....................................................................... 538
2-319. FLASH_CTRL_REGS Registers ........................................................................................ 539
2-320. FLASH_CTRL_REGS Access Type Codes ........................................................................... 539
2-321. FRDCNTL Register Field Descriptions................................................................................. 540
2-322. FBAC Register Field Descriptions ...................................................................................... 541
2-323. FBFALLBACK Register Field Descriptions ............................................................................ 542
2-324. FBPRDY Register Field Descriptions .................................................................................. 543
2-325. FPAC1 Register Field Descriptions .................................................................................... 544
2-326. FMSTAT Register Field Descriptions .................................................................................. 545
2-327. FRD_INTF_CTRL Register Field Descriptions........................................................................ 547
2-328. FLASH_ECC_REGS Registers ......................................................................................... 548
2-329. FLASH_ECC_REGS Access Type Codes ............................................................................ 548
2-330. ECC_ENABLE Register Field Descriptions ........................................................................... 550
2-331. SINGLE_ERR_ADDR_LOW Register Field Descriptions ........................................................... 551
2-332. SINGLE_ERR_ADDR_HIGH Register Field Descriptions ........................................................... 552
2-333. UNC_ERR_ADDR_LOW Register Field Descriptions ............................................................... 553
2-334. UNC_ERR_ADDR_HIGH Register Field Descriptions ............................................................... 554
2-335. ERR_STATUS Register Field Descriptions ........................................................................... 555
2-336. ERR_POS Register Field Descriptions ................................................................................ 557
2-337. ERR_STATUS_CLR Register Field Descriptions .................................................................... 558
2-338. ERR_CNT Register Field Descriptions ................................................................................ 559

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2-339. ERR_THRESHOLD Register Field Descriptions ..................................................................... 560

2-340. ERR_INTFLG Register Field Descriptions ............................................................................ 561
2-341. ERR_INTCLR Register Field Descriptions ............................................................................ 562
2-342. FDATAH_TEST Register Field Descriptions .......................................................................... 563
2-343. FDATAL_TEST Register Field Descriptions .......................................................................... 564
2-344. FADDR_TEST Register Field Descriptions ........................................................................... 565
2-345. FECC_TEST Register Field Descriptions ............................................................................. 566
2-346. FECC_CTRL Register Field Descriptions ............................................................................. 567
2-347. FOUTH_TEST Register Field Descriptions ........................................................................... 568
2-348. FOUTL_TEST Register Field Descriptions ............................................................................ 569
2-349. FECC_STATUS Register Field Descriptions .......................................................................... 570
2-350. CPU_ID_REGS Registers ............................................................................................... 571
2-351. CPU_ID_REGS Access Type Codes .................................................................................. 571
2-352. CPUID_1 Register Field Descriptions .................................................................................. 572
2-353. UID_REGS Registers .................................................................................................... 573
2-354. UID_REGS Access Type Codes........................................................................................ 573
2-355. UID_PSRAND0 Register Field Descriptions .......................................................................... 574
2-361. UID_UNIQUE Register Field Descriptions ............................................................................ 580
2-362. UID_CHECKSUM Register Field Descriptions........................................................................ 581
3-1. ROM Memory ............................................................................................................. 583
3-2. Boot ROM Philosophy .................................................................................................... 583
3-3. Device Default Boot Modes for CPU1 ................................................................................. 584
3-4. All Available Boot Modes ................................................................................................ 584
3-5. BOOTCTRL Register Bit Fields for CPU1 ............................................................................. 584
3-6. BOOTCTRL Register Bit Fields for CPU2 ............................................................................. 585
3-7. Get Mode Decoding on CPU1 .......................................................................................... 586
3-8. Get Mode Decoding on CPU2 .......................................................................................... 586
3-9. Emulation Boot Options .................................................................................................. 586
3-10. Boot ROM Reset Causes and Actions ................................................................................. 593
3-11. Boot ROM Exceptions and Actions ..................................................................................... 594
3-12. Entry Point Addresses for CPU1 and CPU2 .......................................................................... 595
3-13. Wait Point Addresses for CPU1 ........................................................................................ 595
3-14. Wait Point Addresses for CPU2 ........................................................................................ 595
3-15. CPU1 Boot ROM Memory Map ......................................................................................... 595
3-16. CPU2 Boot ROM Memory Map ......................................................................................... 596
3-17. CLA Data ROM Memory Map ........................................................................................... 596
3-18. Reserved RAM and Flash Memory Map for CPU1 ................................................................... 597
3-19. Reserved RAM and Flash Memory Map for CPU2 ................................................................... 597
3-20. CLA Data ROM Tables................................................................................................... 597
3-21. SPI 8-Bit Data Stream ................................................................................................... 601
3-22. I2C 8-Bit Data Stream ................................................................................................... 604
3-23. Parallel GPIO Boot 8-Bit Data Stream ................................................................................. 605
3-24. Bit-Rate Value for Internal Oscillators .................................................................................. 609
3-25. CAN 8-Bit Data Stream .................................................................................................. 609

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3-26. USB 8-Bit Data Stream .................................................................................................. 610

3-27. LSB/MSB Loading Sequence in 8-Bit Data Stream .................................................................. 612
3-28. SCI Boot Options ......................................................................................................... 614
3-29. CAN Boot Options ........................................................................................................ 614
3-30. I2C Boot Options .......................................................................................................... 614
3-31. USB Boot Options ........................................................................................................ 614
3-32. RAM Boot Options ........................................................................................................ 614
3-33. Flash Boot Options ....................................................................................................... 614
3-34. Wait Boot Options ........................................................................................................ 614
3-35. SPI Boot Options ......................................................................................................... 614
3-36. Parallel Boot Options ..................................................................................................... 615
3-37. C2TOC1IPC Commands Table ........................................................................................ 615
3-38. C1TOC2IPC Commands Table ......................................................................................... 616
3-39. CPU2 Error Command Values .......................................................................................... 618
3-40. Boot Clock Sources ...................................................................................................... 618
3-41. Clock State After Boot ROM ............................................................................................ 619
3-42. ROM Wait States ......................................................................................................... 619
3-43. CPU1 Boot Status Address.............................................................................................. 619
3-44. CPU1 Boot Status Bit Fields ............................................................................................ 619
3-45. CPU2 Boot ROM Status Address ...................................................................................... 620
3-46. CPU Booting Status ...................................................................................................... 620
3-47. CPU1 IPC NAK Status Bit Fields ....................................................................................... 621
3-48. CPU2 IPC NAK Status Bit Fields ....................................................................................... 621
3-49. Boot ROM Version Information for CPU1 and CPU2 ................................................................ 622
4-1. Peripheral Interrupt Trigger Source Options .......................................................................... 629
4-2. DMA Register Summary ................................................................................................ 642
4-3. DMA Control Register (DMACTRL) Field Descriptions .............................................................. 643
4-4. Debug Control Register (DEBUGCTRL) Field Descriptions ........................................................ 644
4-5. Revision Register (REVISION) Field Descriptions ................................................................... 644
4-6. Priority Control Register 1 (PRIORITYCTRL1) Field Descriptions ................................................. 645
4-7. Priority Status Register (PRIORITYSTAT) Field Descriptions ...................................................... 646
4-8. Mode Register (MODE) Field Descriptions ............................................................................ 647
4-9. Control Register (CONTROL) Field Descriptions ..................................................................... 649
4-10. Burst Size Register (BURST_SIZE) Field Descriptions.............................................................. 651
4-11. Burst Count Register (BURST_COUNT) Field Descriptions ........................................................ 651
4-12. Source Burst Step Size Register (SRC_BURST_STEP) Field Descriptions...................................... 652
4-13. Destination Burst Step Register Size (DST_BURST_STEP) Field Descriptions ................................. 653
4-14. Transfer Size Register (TRANSFER_SIZE) Field Descriptions .................................................... 653
4-15. Transfer Count Register (TRANSFER_COUNT) Field Descriptions ............................................... 654
4-16. Source Transfer Step Size Register (SRC_TRANSFER_STEP) Field Descriptions ............................ 654
4-17. Destination Transfer Step Size Register (DST_TRANSFER_STEP) Field Descriptions ........................ 655
4-18. Source/Destination Wrap Size Register (SRC/DST_WRAP_SIZE) Field Descriptions ......................... 655
4-19. Source/Destination Wrap Count Register (SCR/DST_WRAP_COUNT) Field Descriptions .................... 656
4-20. Source/Destination Wrap Step Size Registers (SRC/DST_WRAP_STEP) Field Descriptions ................. 656
4-21. Shadow Source Begin and Current Address Pointer Registers
(SRC_BEG_ADDR_SHADOW/DST_BEG_ADDR_SHADOW) Field Descriptions .............................. 657
4-22. Active Source Begin and Current Address Pointer Registers (SRC_BEG_ADDR/DST_BEG_ADDR) Field
Descriptions ............................................................................................................... 657
4-23. Shadow Destination Begin and Current Address Pointer Registers
(SRC_ADDR_SHADOW/DST_ADDR_SHADOW) Field Descriptions ............................................. 658

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4-24. Active Destination Begin and Current Address Pointer Registers (SRC_ADDR/DST_ADDR) Field
Descriptions ............................................................................................................... 658
5-1. Configuration Options .................................................................................................... 664
5-2. Write Followed by Read - Read Occurs First ........................................................................ 673
5-3. Write Followed by Read - Write Occurs First ........................................................................ 673
5-4. ADC to CLA Early Interrupt Response ................................................................................ 675
5-5. Operand Nomenclature .................................................................................................. 677
5-6. INSTRUCTION dest, source1, source2 Short Description .......................................................... 678
5-7. Addressing Modes ........................................................................................................ 679
5-8. Shift Field Encoding ...................................................................................................... 680
5-9. Operand Encoding ........................................................................................................ 680
5-10. Condition Field Encoding ................................................................................................ 680
5-11. General Instructions ...................................................................................................... 681
5-12. Pipeline Activity For MBCNDD, Branch Not Taken .................................................................. 696
5-13. Pipeline Activity For MBCNDD, Branch Taken ....................................................................... 696
5-14. Pipeline Activity For MCCNDD, Call Not Taken ..................................................................... 702
5-15. Pipeline Activity For MCCNDD, Call Taken .......................................................................... 702
5-16. Pipeline Activity For MMOV16 MARx, MRa , #16I ................................................................... 734
5-17. Pipeline Activity For MMOV16 MAR0/MAR1, mem16 ............................................................... 737
5-18. Pipeline Activity For MMOVI16 MAR0/MAR1, #16I .................................................................. 751
5-19. Pipeline Activity For MRCNDD, Return Not Taken .................................................................. 773
5-20. Pipeline Activity For MRCNDD, Return Taken ....................................................................... 773
5-21. Pipeline Activity For MSTOP ............................................................................................ 777
5-22. CLA Base Address Table ................................................................................................ 792
5-23. CLA_REGS Registers .................................................................................................... 793
5-24. CLA_REGS Access Type Codes ....................................................................................... 793
5-25. MVECT1 Register Field Descriptions .................................................................................. 795
5-33. MCTL Register Field Descriptions ...................................................................................... 803
5-34. MIFR Register Field Descriptions....................................................................................... 804
5-35. MIOVF Register Field Descriptions..................................................................................... 806
5-36. MIFRC Register Field Descriptions..................................................................................... 808
5-37. MICLR Register Field Descriptions ..................................................................................... 810
5-38. MICLROVF Register Field Descriptions ............................................................................... 812
5-39. MIER Register Field Descriptions ...................................................................................... 814
5-40. MIRUN Register Field Descriptions .................................................................................... 816
5-41. _MPC Register Field Descriptions ...................................................................................... 818
5-42. _MAR0 Register Field Descriptions .................................................................................... 819
5-43. _MAR1 Register Field Descriptions .................................................................................... 820
5-44. _MSTF Register Field Descriptions .................................................................................... 821
5-45. _MR0 Register Field Descriptions ...................................................................................... 824

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5-49. CLA_SOFTINT_REGS Registers ....................................................................................... 828
5-50. CLA_SOFTINT_REGS Access Type Codes .......................................................................... 828
5-51. SOFTINTEN Register Field Descriptions .............................................................................. 829
5-52. SOFTINTFRC Register Field Descriptions ............................................................................ 831
6-1. IPC Message RAM Read/Write Access ............................................................................... 835
6-2. IPC Command Registers ................................................................................................ 836
6-3. IPC Base Addresses ..................................................................................................... 838
6-4. IPC_REGS_CPU1 Registers ............................................................................................ 839
6-5. IPC_REGS_CPU1 Access Type Codes ............................................................................... 839
6-6. IPCACK Register Field Descriptions ................................................................................... 840
6-7. IPCSTS Register Field Descriptions ................................................................................... 843
6-8. IPCSET Register Field Descriptions ................................................................................... 848
6-9. IPCCLR Register Field Descriptions ................................................................................... 851
6-10. IPCFLG Register Field Descriptions ................................................................................... 856
6-11. IPCCOUNTERL Register Field Descriptions .......................................................................... 860
6-12. IPCCOUNTERH Register Field Descriptions ......................................................................... 861
6-13. IPCSENDCOM Register Field Descriptions ........................................................................... 862
6-14. IPCSENDADDR Register Field Descriptions ......................................................................... 863
6-15. IPCSENDDATA Register Field Descriptions .......................................................................... 864
6-16. IPCREMOTEREPLY Register Field Descriptions .................................................................... 865
6-17. IPCRECVCOM Register Field Descriptions ........................................................................... 866
6-18. IPCRECVADDR Register Field Descriptions ......................................................................... 867
6-19. IPCRECVDATA Register Field Descriptions .......................................................................... 868
6-20. IPCLOCALREPLY Register Field Descriptions ....................................................................... 869
6-21. IPCBOOTSTS Register Field Descriptions ............................................................................ 870
6-22. IPCBOOTMODE Register Field Descriptions ......................................................................... 871
6-23. IPC_REGS_CPU2 Registers ............................................................................................ 872
6-24. IPC_REGS_CPU2 Access Type Codes ............................................................................... 872
6-25. IPCACK Register Field Descriptions ................................................................................... 873
6-26. IPCSTS Register Field Descriptions ................................................................................... 876
6-27. IPCSET Register Field Descriptions ................................................................................... 881
6-28. IPCCLR Register Field Descriptions ................................................................................... 884
6-29. IPCFLG Register Field Descriptions ................................................................................... 889
6-30. IPCCOUNTERL Register Field Descriptions .......................................................................... 893
6-31. IPCCOUNTERH Register Field Descriptions ......................................................................... 894
6-32. IPCRECVCOM Register Field Descriptions ........................................................................... 895
6-33. IPCRECVADDR Register Field Descriptions ......................................................................... 896
6-34. IPCRECVDATA Register Field Descriptions .......................................................................... 897
6-35. IPCLOCALREPLY Register Field Descriptions ....................................................................... 898
6-36. IPCSENDCOM Register Field Descriptions ........................................................................... 899
6-37. IPCSENDADDR Register Field Descriptions ......................................................................... 900
6-38. IPCSENDDATA Register Field Descriptions .......................................................................... 901
6-39. IPCREMOTEREPLY Register Field Descriptions .................................................................... 902
6-40. IPCBOOTSTS Register Field Descriptions ............................................................................ 903
6-41. IPCBOOTMODE Register Field Descriptions ......................................................................... 904
7-1. Sampling Period .......................................................................................................... 910
7-2. Sampling Frequency ..................................................................................................... 910
7-3. Case 1: Three-Sample Sampling Window Width ..................................................................... 911

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7-4. Case 2: Six-Sample Sampling Window Width ........................................................................ 911

7-5. USB I/O Signal Muxing .................................................................................................. 912
7-6. High-Speed SPI-Enabled GPIOs ....................................................................................... 912
7-7. GPIO Configuration for High-Speed SPI .............................................................................. 913
7-8. GPIO Muxed Pins......................................................................................................... 914
7-9. GPIO and Peripheral Muxing ............................................................................................ 917
7-10. Peripheral Muxing (multiple pins assigned) ........................................................................... 919
7-11. Pullup Resistors for 176-pin Packages ............................................................................... 919
7-12. Pullup Resistors for 100-pin Packages ................................................................................ 920
7-13. GPIO Base Address Table .............................................................................................. 921
7-14. Specific vs Generic Termilogy for Registers .......................................................................... 921
7-15. GPIO_CTRL_REGS Registers .......................................................................................... 922
7-16. GPIO_CTRL_REGS Access Type Codes ............................................................................. 924
7-17. GPACTRL Register Field Descriptions ................................................................................ 926
7-18. GPAQSEL1 Register Field Descriptions ............................................................................... 927
7-19. GPAQSEL2 Register Field Descriptions ............................................................................... 929
7-20. GPAMUX1 Register Field Descriptions ................................................................................ 931
7-21. GPAMUX2 Register Field Descriptions ................................................................................ 933
7-22. GPADIR Register Field Descriptions ................................................................................... 935
7-23. GPAPUD Register Field Descriptions .................................................................................. 937
7-24. GPAINV Register Field Descriptions ................................................................................... 939
7-25. GPAODR Register Field Descriptions ................................................................................. 941
7-26. GPAGMUX1 Register Field Descriptions .............................................................................. 943
7-27. GPAGMUX2 Register Field Descriptions .............................................................................. 944
7-28. GPACSEL1 Register Field Descriptions ............................................................................... 945
7-32. GPALOCK Register Field Descriptions ................................................................................ 949
7-33. GPACR Register Field Descriptions.................................................................................... 951
7-34. GPBCTRL Register Field Descriptions ................................................................................ 953
7-35. GPBQSEL1 Register Field Descriptions ............................................................................... 954
7-36. GPBQSEL2 Register Field Descriptions ............................................................................... 956
7-37. GPBMUX1 Register Field Descriptions ................................................................................ 958
7-38. GPBMUX2 Register Field Descriptions ................................................................................ 960
7-39. GPBDIR Register Field Descriptions ................................................................................... 962
7-40. GPBPUD Register Field Descriptions .................................................................................. 964
7-41. GPBINV Register Field Descriptions ................................................................................... 966
7-42. GPBODR Register Field Descriptions ................................................................................. 968
7-43. GPBAMSEL Register Field Descriptions .............................................................................. 970
7-44. GPBGMUX1 Register Field Descriptions .............................................................................. 972
7-45. GPBGMUX2 Register Field Descriptions .............................................................................. 973
7-46. GPBCSEL1 Register Field Descriptions ............................................................................... 974
7-50. GPBLOCK Register Field Descriptions ................................................................................ 978
7-51. GPBCR Register Field Descriptions.................................................................................... 980
7-52. GPCCTRL Register Field Descriptions ................................................................................ 982

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7-53. GPCQSEL1 Register Field Descriptions............................................................................... 983

7-54. GPCQSEL2 Register Field Descriptions............................................................................... 985
7-55. GPCMUX1 Register Field Descriptions ................................................................................ 987
7-56. GPCMUX2 Register Field Descriptions ................................................................................ 989
7-57. GPCDIR Register Field Descriptions ................................................................................... 991
7-58. GPCPUD Register Field Descriptions.................................................................................. 993
7-59. GPCINV Register Field Descriptions ................................................................................... 995
7-60. GPCODR Register Field Descriptions ................................................................................. 997
7-61. GPCGMUX1 Register Field Descriptions .............................................................................. 999
7-62. GPCGMUX2 Register Field Descriptions ............................................................................ 1000
7-63. GPCCSEL1 Register Field Descriptions ............................................................................. 1001
7-67. GPCLOCK Register Field Descriptions .............................................................................. 1005
7-68. GPCCR Register Field Descriptions .................................................................................. 1007
7-69. GPDCTRL Register Field Descriptions ............................................................................... 1009
7-70. GPDQSEL1 Register Field Descriptions ............................................................................. 1010
7-71. GPDQSEL2 Register Field Descriptions ............................................................................. 1012
7-72. GPDMUX1 Register Field Descriptions .............................................................................. 1014
7-73. GPDMUX2 Register Field Descriptions .............................................................................. 1016
7-74. GPDDIR Register Field Descriptions ................................................................................. 1018
7-75. GPDPUD Register Field Descriptions ................................................................................ 1020
7-76. GPDINV Register Field Descriptions ................................................................................. 1022
7-77. GPDODR Register Field Descriptions ................................................................................ 1024
7-78. GPDGMUX1 Register Field Descriptions ............................................................................ 1026
7-79. GPDGMUX2 Register Field Descriptions ............................................................................ 1028
7-80. GPDCSEL1 Register Field Descriptions ............................................................................. 1030
7-84. GPDLOCK Register Field Descriptions .............................................................................. 1034
7-85. GPDCR Register Field Descriptions .................................................................................. 1036
7-86. GPECTRL Register Field Descriptions ............................................................................... 1038
7-87. GPEQSEL1 Register Field Descriptions ............................................................................. 1039
7-88. GPEQSEL2 Register Field Descriptions ............................................................................. 1041
7-89. GPEMUX1 Register Field Descriptions .............................................................................. 1043
7-90. GPEMUX2 Register Field Descriptions .............................................................................. 1045
7-91. GPEDIR Register Field Descriptions ................................................................................. 1047
7-92. GPEPUD Register Field Descriptions ................................................................................ 1049
7-93. GPEINV Register Field Descriptions ................................................................................. 1051
7-94. GPEODR Register Field Descriptions ................................................................................ 1053
7-95. GPEGMUX1 Register Field Descriptions ............................................................................ 1055
7-96. GPEGMUX2 Register Field Descriptions ............................................................................ 1057
7-97. GPECSEL1 Register Field Descriptions ............................................................................. 1059
7-101. GPELOCK Register Field Descriptions............................................................................... 1063

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7-102. GPECR Register Field Descriptions .................................................................................. 1065

7-103. GPFCTRL Register Field Descriptions ............................................................................... 1067
7-104. GPFQSEL1 Register Field Descriptions ............................................................................. 1068
7-105. GPFMUX1 Register Field Descriptions............................................................................... 1070
7-106. GPFDIR Register Field Descriptions ................................................................................. 1072
7-107. GPFPUD Register Field Descriptions ................................................................................ 1074
7-108. GPFINV Register Field Descriptions.................................................................................. 1076
7-109. GPFODR Register Field Descriptions ................................................................................ 1078
7-110. GPFGMUX1 Register Field Descriptions ............................................................................ 1080
7-111. GPFCSEL1 Register Field Descriptions.............................................................................. 1081
7-112. GPFCSEL2 Register Field Descriptions.............................................................................. 1082
7-113. GPFLOCK Register Field Descriptions ............................................................................... 1083
7-114. GPFCR Register Field Descriptions .................................................................................. 1085
7-115. GPIO_DATA_REGS Registers ........................................................................................ 1087
7-116. GPIO_DATA_REGS Access Type Codes ........................................................................... 1087
7-117. GPADAT Register Field Descriptions................................................................................. 1089
7-118. GPASET Register Field Descriptions ................................................................................. 1091
7-119. GPACLEAR Register Field Descriptions ............................................................................. 1093
7-120. GPATOGGLE Register Field Descriptions ........................................................................... 1095
7-121. GPBDAT Register Field Descriptions................................................................................. 1097
7-122. GPBSET Register Field Descriptions ................................................................................. 1099
7-123. GPBCLEAR Register Field Descriptions ............................................................................. 1101
7-124. GPBTOGGLE Register Field Descriptions ........................................................................... 1103
7-125. GPCDAT Register Field Descriptions ................................................................................ 1105
7-126. GPCSET Register Field Descriptions................................................................................. 1107
7-127. GPCCLEAR Register Field Descriptions ............................................................................. 1109
7-128. GPCTOGGLE Register Field Descriptions........................................................................... 1111
7-129. GPDDAT Register Field Descriptions ................................................................................ 1113
7-130. GPDSET Register Field Descriptions................................................................................. 1115
7-131. GPDCLEAR Register Field Descriptions ............................................................................. 1117
7-132. GPDTOGGLE Register Field Descriptions........................................................................... 1119
7-133. GPEDAT Register Field Descriptions................................................................................. 1121
7-134. GPESET Register Field Descriptions ................................................................................. 1123
7-135. GPECLEAR Register Field Descriptions ............................................................................. 1125
7-136. GPETOGGLE Register Field Descriptions ........................................................................... 1127
7-137. GPFDAT Register Field Descriptions ................................................................................. 1129
7-138. GPFSET Register Field Descriptions ................................................................................. 1131
7-139. GPFCLEAR Register Field Descriptions ............................................................................. 1133
7-140. GPFTOGGLE Register Field Descriptions ........................................................................... 1135
8-1. Input X-BAR Destinations .............................................................................................. 1139
8-2. ePWM X-BAR Mux Configuration Table ............................................................................ 1141
8-3. Output X-Bar Mux Configuration Table ............................................................................... 1143
8-4. X-BAR Base Address Table ........................................................................................... 1145
8-5. INPUT_XBAR_REGS Registers ...................................................................................... 1146
8-6. INPUT_XBAR_REGS Access Type Codes .......................................................................... 1146
8-7. INPUT1SELECT Register Field Descriptions........................................................................ 1147

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8-16. INPUT10SELECT Register Field Descriptions ...................................................................... 1156
8-21. INPUTSELECTLOCK Register Field Descriptions .................................................................. 1161
8-22. XBAR_REGS Registers ................................................................................................ 1165
8-23. XBAR_REGS Access Type Codes ................................................................................... 1165
8-24. XBARFLG1 Register Field Descriptions.............................................................................. 1166
8-27. XBARCLR1 Register Field Descriptions ............................................................................. 1172
8-30. EPWM_XBAR_REGS Registers ...................................................................................... 1178
8-31. EPWM_XBAR_REGS Access Type Codes ......................................................................... 1178
8-32. TRIP4MUX0TO15CFG Register Field Descriptions ................................................................ 1180
8-33. TRIP4MUX16TO31CFG Register Field Descriptions............................................................... 1183
8-43. TRIP10MUX16TO31CFG Register Field Descriptions ............................................................. 1213
8-48. TRIP4MUXENABLE Register Field Descriptions ................................................................... 1228
8-53. TRIP10MUXENABLE Register Field Descriptions .................................................................. 1253
8-56. TRIPOUTINV Register Field Descriptions ........................................................................... 1268
8-57. TRIPLOCK Register Field Descriptions .............................................................................. 1270
8-58. OUTPUT_XBAR_REGS Registers ................................................................................... 1271
8-59. OUTPUT_XBAR_REGS Access Type Codes ....................................................................... 1271

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8-60. OUTPUT1MUX0TO15CFG Register Field Descriptions ........................................................... 1273

8-61. OUTPUT1MUX16TO31CFG Register Field Descriptions.......................................................... 1276
8-76. OUTPUT1MUXENABLE Register Field Descriptions .............................................................. 1321
8-84. OUTPUTLATCH Register Field Descriptions ........................................................................ 1361
8-85. OUTPUTLATCHCLR Register Field Descriptions .................................................................. 1363
8-86. OUTPUTLATCHFRC Register Field Descriptions .................................................................. 1365
8-87. OUTPUTLATCHENABLE Register Field Descriptions ............................................................. 1367
8-88. OUTPUTINV Register Field Descriptions ............................................................................ 1369
8-89. OUTPUTLOCK Register Field Descriptions ......................................................................... 1371
9-1. Analog Subsystem Base Address Table ............................................................................. 1377
9-2. ANALOG_SUBSYS_REGS Registers ................................................................................ 1378
9-3. ANALOG_SUBSYS_REGS Access Type Codes ................................................................... 1378
9-4. INTOSC1TRIM Register Field Descriptions ......................................................................... 1379
9-5. INTOSC2TRIM Register Field Descriptions ......................................................................... 1380
9-6. TSNSCTL Register Field Descriptions ............................................................................... 1381
9-7. LOCK Register Field Descriptions .................................................................................... 1382
9-8. ANAREFTRIMA Register Field Descriptions ........................................................................ 1383
9-9. ANAREFTRIMB Register Field Descriptions ........................................................................ 1384
9-10. ANAREFTRIMC Register Field Descriptions ........................................................................ 1385
9-11. ANAREFTRIMD Register Field Descriptions ........................................................................ 1386
10-1. ADC Options and Configuration Levels .............................................................................. 1389
10-2. Analog to 12-bit Digital Formulas ..................................................................................... 1392
10-3. Analog to 16-bit Digital Formulas ..................................................................................... 1392
10-4. 12-Bit Digital-to-Analog Formulas .................................................................................... 1392
10-5. 16-Bit Digital-to-Analog Formulas .................................................................................... 1392
10-6. Channel Selection of Input Pins ....................................................................................... 1395
10-7. Example Requirements for Multiple Signal Sampling .............................................................. 1397
10-8. Example Connections for Multiple Signal Sampling ................................................................ 1397

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10-9. DETECTCFG Settings .................................................................................................. 1407

10-10. ADC Timings in 12-bit Mode (SYSCLK Cycles) ..................................................................... 1412
10-11. ADC Timings in 16-bit Mode ........................................................................................... 1413
10-12. ADC Base Address Table .............................................................................................. 1421
10-13. ADC_REGS Registers .................................................................................................. 1422
10-14. ADC_REGS Access Type Codes ..................................................................................... 1423
10-15. ADCCTL1 Register Field Descriptions ............................................................................... 1425
10-16. ADCCTL2 Register Field Descriptions ............................................................................... 1427
10-17. ADCBURSTCTL Register Field Descriptions ........................................................................ 1428
10-18. ADCINTFLG Register Field Descriptions ............................................................................ 1430
10-19. ADCINTFLGCLR Register Field Descriptions ....................................................................... 1432
10-20. ADCINTOVF Register Field Descriptions ............................................................................ 1434
10-21. ADCINTOVFCLR Register Field Descriptions ....................................................................... 1436
10-22. ADCINTSEL1N2 Register Field Descriptions........................................................................ 1437
10-23. ADCINTSEL3N4 Register Field Descriptions........................................................................ 1439
10-24. ADCSOCPRICTL Register Field Descriptions ...................................................................... 1441
10-25. ADCINTSOCSEL1 Register Field Descriptions ..................................................................... 1444
10-26. ADCINTSOCSEL2 Register Field Descriptions ..................................................................... 1446
10-27. ADCSOCFLG1 Register Field Descriptions ......................................................................... 1448
10-28. ADCSOCFRC1 Register Field Descriptions ......................................................................... 1453
10-29. ADCSOCOVF1 Register Field Descriptions ......................................................................... 1458
10-30. ADCSOCOVFCLR1 Register Field Descriptions .................................................................... 1462
10-31. ADCSOC0CTL Register Field Descriptions ......................................................................... 1466
10-41. ADCSOC10CTL Register Field Descriptions ........................................................................ 1496
10-47. ADCEVTSTAT Register Field Descriptions .......................................................................... 1514
10-48. ADCEVTCLR Register Field Descriptions ........................................................................... 1516
10-49. ADCEVTSEL Register Field Descriptions............................................................................ 1518
10-50. ADCEVTINTSEL Register Field Descriptions ....................................................................... 1520
10-51. ADCCOUNTER Register Field Descriptions......................................................................... 1522
10-52. ADCREV Register Field Descriptions ................................................................................ 1523
10-53. ADCOFFTRIM Register Field Descriptions .......................................................................... 1524
10-54. ADCPPB1CONFIG Register Field Descriptions..................................................................... 1525
10-55. ADCPPB1STAMP Register Field Descriptions ...................................................................... 1527
10-56. ADCPPB1OFFCAL Register Field Descriptions .................................................................... 1528
10-57. ADCPPB1OFFREF Register Field Descriptions .................................................................... 1529

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10-58. ADCPPB1TRIPHI Register Field Descriptions ...................................................................... 1530

10-59. ADCPPB1TRIPLO Register Field Descriptions ..................................................................... 1531
10-78. ADCINLTRIM1 Register Field Descriptions .......................................................................... 1553
10-84. ADC_RESULT_REGS Registers...................................................................................... 1560
10-85. ADC_RESULT_REGS Access Type Codes ......................................................................... 1560
10-86. ADCRESULT0 Register Field Descriptions .......................................................................... 1561
10-96. ADCRESULT10 Register Field Descriptions ........................................................................ 1571
10-100. ADCRESULT14 Register Field Descriptions ....................................................................... 1575
10-101. ADCRESULT15 Register Field Descriptions ....................................................................... 1576
10-102. ADCPPB1RESULT Register Field Descriptions ................................................................... 1577
11-1. DAC Base Address Table .............................................................................................. 1583

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11-2. DAC_REGS Registers .................................................................................................. 1584

11-3. DAC_REGS Access Type Codes ..................................................................................... 1584
11-4. DACREV Register Field Descriptions ................................................................................ 1585
11-5. DACCTL Register Field Descriptions ................................................................................. 1586
11-6. DACVALA Register Field Descriptions ............................................................................... 1587
11-7. DACVALS Register Field Descriptions ............................................................................... 1588
11-8. DACOUTEN Register Field Descriptions ............................................................................ 1589
11-9. DACLOCK Register Field Descriptions............................................................................... 1590
11-10. DACTRIM Register Field Descriptions ............................................................................... 1591
12-1. CMPSS Base Address Table .......................................................................................... 1598
12-2. CMPSS_REGS Registers .............................................................................................. 1599
12-3. CMPSS_REGS Access Type Codes ................................................................................. 1599
12-4. COMPCTL Register Field Descriptions .............................................................................. 1601
12-5. COMPHYSCTL Register Field Descriptions ......................................................................... 1603
12-6. COMPSTS Register Field Descriptions .............................................................................. 1604
12-7. COMPSTSCLR Register Field Descriptions ......................................................................... 1605
12-8. COMPDACCTL Register Field Descriptions ......................................................................... 1606
12-9. DACHVALS Register Field Descriptions ............................................................................. 1608
12-10. DACHVALA Register Field Descriptions ............................................................................. 1609
12-11. RAMPMAXREFA Register Field Descriptions ....................................................................... 1610
12-12. RAMPMAXREFS Register Field Descriptions ....................................................................... 1611
12-13. RAMPDECVALA Register Field Descriptions ....................................................................... 1612
12-14. RAMPDECVALS Register Field Descriptions ....................................................................... 1613
12-15. RAMPSTS Register Field Descriptions............................................................................... 1614
12-16. DACLVALS Register Field Descriptions.............................................................................. 1615
12-17. DACLVALA Register Field Descriptions.............................................................................. 1616
12-18. RAMPDLYA Register Field Descriptions ............................................................................. 1617
12-19. RAMPDLYS Register Field Descriptions ............................................................................. 1618
12-20. CTRIPLFILCTL Register Field Descriptions ......................................................................... 1619
12-21. CTRIPLFILCLKCTL Register Field Descriptions .................................................................... 1620
12-22. CTRIPHFILCTL Register Field Descriptions......................................................................... 1621
12-23. CTRIPHFILCLKCTL Register Field Descriptions ................................................................... 1622
12-24. COMPLOCK Register Field Descriptions ............................................................................ 1623
13-1. Modulator Clock Modes ................................................................................................ 1628
13-2. Peak Data Values for Different OSR/Filter Combinations ......................................................... 1630
13-3. Peak Data Values for Different DOSR/Filter Combinations ....................................................... 1631
13-4. Number of Incorrect Samples Tabulated ............................................................................. 1632
13-5. Shift Control Bit Configuration Settings .............................................................................. 1633
13-6. General Registers ....................................................................................................... 1636
13-7. Filter 1 Registers ........................................................................................................ 1636
13-11. SDFM Base Address Table ............................................................................................ 1637
13-12. SDFM_REGS Registers ................................................................................................ 1638
13-13. SDFM_REGS Access Type Codes ................................................................................... 1638
13-14. SDIFLG Register Field Descriptions .................................................................................. 1640
13-15. SDIFLGCLR Register Field Descriptions ............................................................................ 1642
13-16. SDCTL Register Field Descriptions ................................................................................... 1644

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13-17. SDMFILEN Register Field Descriptions .............................................................................. 1645

13-18. SDCTLPARM1 Register Field Descriptions ......................................................................... 1646
13-19. SDDFPARM1 Register Field Descriptions ........................................................................... 1647
13-20. SDDPARM1 Register Field Descriptions ............................................................................. 1648
13-21. SDCMPH1 Register Field Descriptions .............................................................................. 1649
13-22. SDCMPL1 Register Field Descriptions ............................................................................... 1650
13-23. SDCPARM1 Register Field Descriptions ............................................................................. 1651
13-24. SDDATA1 Register Field Descriptions ............................................................................... 1652
14-1. Submodule Configuration Parameters................................................................................ 1682
14-2. Key Time-Base Signals ................................................................................................. 1685
14-3. Action-Qualifier Submodule Possible Input Events ................................................................. 1703
14-4. Action-Qualifier Event Priority for Up-Down-Count Mode .......................................................... 1705
14-5. Action-Qualifier Event Priority for Up-Count Mode.................................................................. 1705
14-6. Action-Qualifier Event Priority for Down-Count Mode .............................................................. 1705
14-7. Behavior if CMPA/CMPB is Greater than the Period ............................................................... 1706
14-8. Classical Dead-Band Operating Modes ............................................................................. 1718
14-9. Additional Dead-Band Operating Modes ............................................................................. 1718
14-10. Dead-Band Delay Values in μS as a Function of DBFED and DBRED ......................................... 1720
14-11. Possible Pulse Width Values for EPWMCLK = 80 MHz ........................................................... 1723
14-12. Possible Actions On a Trip Event ..................................................................................... 1727
14-13. EPWM Base Address Table ........................................................................................... 1763
14-14. EPWM_REGS Registers ............................................................................................... 1764
14-15. EPWM_REGS Access Type Codes .................................................................................. 1766
14-16. TBCTL Register Field Descriptions ................................................................................... 1767
14-17. TBCTL2 Register Field Descriptions.................................................................................. 1770
14-18. EPWMSYNCINSEL Register Field Descriptions .................................................................... 1771
14-19. TBCTR Register Field Descriptions ................................................................................... 1772
14-20. TBSTS Register Field Descriptions ................................................................................... 1773

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14-21. EPWMSYNCOUTEN Register Field Descriptions .................................................................. 1774

14-22. CMPCTL Register Field Descriptions................................................................................. 1776
14-23. CMPCTL2 Register Field Descriptions ............................................................................... 1778
14-24. DBCTL Register Field Descriptions ................................................................................... 1780
14-25. DBCTL2 Register Field Descriptions ................................................................................. 1783
14-26. AQCTL Register Field Descriptions ................................................................................... 1784
14-27. AQTSRCSEL Register Field Descriptions ........................................................................... 1786
14-28. PCCTL Register Field Descriptions ................................................................................... 1787
14-29. VCAPCTL Register Field Descriptions ............................................................................... 1789
14-30. VCNTCFG Register Field Descriptions............................................................................... 1791
14-31. HRCNFG Register Field Descriptions ................................................................................ 1793
14-32. HRPWR Register Field Descriptions ................................................................................. 1795
14-33. HRMSTEP Register Field Descriptions .............................................................................. 1796
14-34. HRCNFG2 Register Field Descriptions............................................................................... 1797
14-35. HRPCTL Register Field Descriptions ................................................................................. 1798
14-36. TRREM Register Field Descriptions .................................................................................. 1800
14-37. GLDCTL Register Field Descriptions ................................................................................. 1801
14-38. GLDCFG Register Field Descriptions ................................................................................ 1803
14-39. EPWMXLINK Register Field Descriptions ........................................................................... 1805
14-40. EPWMREV Register Field Descriptions .............................................................................. 1809
14-41. AQCTLA Register Field Descriptions ................................................................................. 1810
14-42. AQCTLA2 Register Field Descriptions ............................................................................... 1812
14-43. AQCTLB Register Field Descriptions ................................................................................. 1814
14-44. AQCTLB2 Register Field Descriptions ............................................................................... 1816
14-45. AQSFRC Register Field Descriptions ................................................................................ 1818
14-46. AQCSFRC Register Field Descriptions .............................................................................. 1820
14-47. DBREDHR Register Field Descriptions .............................................................................. 1821
14-48. DBRED Register Field Descriptions .................................................................................. 1822
14-49. DBFEDHR Register Field Descriptions............................................................................... 1823
14-50. DBFED Register Field Descriptions .................................................................................. 1824
14-51. TBPHS Register Field Descriptions ................................................................................... 1825
14-52. TBPRDHR Register Field Descriptions............................................................................... 1826
14-53. TBPRD Register Field Descriptions .................................................................................. 1827
14-54. CMPA Register Field Descriptions .................................................................................... 1828
14-55. CMPB Register Field Descriptions .................................................................................... 1829
14-56. CMPC Register Field Descriptions .................................................................................... 1830
14-57. CMPD Register Field Descriptions .................................................................................... 1831
14-58. GLDCTL2 Register Field Descriptions ............................................................................... 1832
14-59. SWVDELVAL Register Field Descriptions ........................................................................... 1833
14-60. TZSEL Register Field Descriptions ................................................................................... 1834
14-61. TZDCSEL Register Field Descriptions ............................................................................... 1836
14-62. TZCTL Register Field Descriptions ................................................................................... 1838
14-63. TZCTL2 Register Field Descriptions .................................................................................. 1840
14-64. TZCTLDCA Register Field Descriptions.............................................................................. 1842
14-65. TZCTLDCB Register Field Descriptions.............................................................................. 1844
14-66. TZEINT Register Field Descriptions .................................................................................. 1846
14-67. TZFLG Register Field Descriptions ................................................................................... 1847
14-68. TZCBCFLG Register Field Descriptions ............................................................................. 1849
14-69. TZOSTFLG Register Field Descriptions.............................................................................. 1851

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14-70. TZCLR Register Field Descriptions ................................................................................... 1853

14-71. TZCBCCLR Register Field Descriptions ............................................................................. 1855
14-72. TZOSTCLR Register Field Descriptions ............................................................................. 1857
14-73. TZFRC Register Field Descriptions ................................................................................... 1859
14-74. ETSEL Register Field Descriptions ................................................................................... 1860
14-75. ETPS Register Field Descriptions..................................................................................... 1863
14-76. ETFLG Register Field Descriptions ................................................................................... 1866
14-77. ETCLR Register Field Descriptions ................................................................................... 1867
14-78. ETFRC Register Field Descriptions ................................................................................... 1868
14-79. ETINTPS Register Field Descriptions ................................................................................ 1869
14-80. ETSOCPS Register Field Descriptions ............................................................................... 1870
14-81. ETCNTINITCTL Register Field Descriptions ........................................................................ 1872
14-82. ETCNTINIT Register Field Descriptions.............................................................................. 1873
14-83. DCTRIPSEL Register Field Descriptions ............................................................................ 1874
14-84. DCACTL Register Field Descriptions ................................................................................. 1876
14-85. DCBCTL Register Field Descriptions ................................................................................. 1878
14-86. DCFCTL Register Field Descriptions ................................................................................. 1880
14-87. DCCAPCTL Register Field Descriptions ............................................................................. 1881
14-88. DCFOFFSET Register Field Descriptions ........................................................................... 1883
14-89. DCFOFFSETCNT Register Field Descriptions ...................................................................... 1884
14-90. DCFWINDOW Register Field Descriptions .......................................................................... 1885
14-91. DCFWINDOWCNT Register Field Descriptions ..................................................................... 1886
14-92. DCCAP Register Field Descriptions .................................................................................. 1887
14-93. DCAHTRIPSEL Register Field Descriptions ......................................................................... 1888
14-94. DCALTRIPSEL Register Field Descriptions ......................................................................... 1890
14-95. DCBHTRIPSEL Register Field Descriptions ......................................................................... 1892
14-96. DCBLTRIPSEL Register Field Descriptions ......................................................................... 1894
14-97. EPWMLOCK Register Field Descriptions ............................................................................ 1896
14-98. HWVDELVAL Register Field Descriptions ........................................................................... 1898
14-99. VCNTVAL Register Field Descriptions ............................................................................... 1899
14-100. EPWM_XBAR_REGS Registers ..................................................................................... 1900
14-101. EPWM_XBAR_REGS Access Type Codes ........................................................................ 1900
14-102. TRIP4MUX0TO15CFG Register Field Descriptions ............................................................... 1902
14-113. TRIP10MUX16TO31CFG Register Field Descriptions ............................................................ 1935

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14-123. TRIP10MUXENABLE Register Field Descriptions ................................................................ 1975
14-126. TRIPOUTINV Register Field Descriptions .......................................................................... 1990
14-127. TRIPLOCK Register Field Descriptions ............................................................................. 1992
14-128. SYNC_SOC_REGS Registers ....................................................................................... 1993
14-129. SYNC_SOC_REGS Access Type Codes .......................................................................... 1993
14-130. SYNCSELECT Register Field Descriptions ........................................................................ 1994
14-131. ADCSOCOUTSELECT Register Field Descriptions .............................................................. 1997
14-132. SYNCSOCLOCK Register Field Descriptions...................................................................... 2000
15-1. Resolution for PWM and HRPWM .................................................................................... 2003
15-2. Relationship Between MEP Steps, PWM Frequency and Resolution ............................................ 2009
15-3. CMPA vs Duty (left), and [CMPA:CMPAHR] vs Duty (right)....................................................... 2010
15-4. Duty Cycle Range Limitation for Three EPWMCLK/TBCLK Cycles .............................................. 2013
15-5. SFO Library Features ................................................................................................... 2025
15-6. Factor Values ............................................................................................................ 2026
16-1. eCAP Base Address Table ............................................................................................ 2050
16-2. ECAP_REGS Registers ................................................................................................ 2051
16-3. ECAP_REGS Access Type Codes ................................................................................... 2051
16-4. TSCTR Register Field Descriptions ................................................................................... 2052
16-5. CTRPHS Register Field Descriptions................................................................................. 2053
16-6. CAP1 Register Field Descriptions..................................................................................... 2054
16-10. ECCTL1 Register Field Descriptions ................................................................................. 2058
16-11. ECCTL2 Register Field Descriptions ................................................................................. 2060
16-12. ECEINT Register Field Descriptions .................................................................................. 2062
16-13. ECFLG Register Field Descriptions ................................................................................... 2064
16-14. ECCLR Register Field Descriptions .................................................................................. 2066
16-15. ECFRC Register Field Descriptions .................................................................................. 2067
17-1. EQEP Memory Map .................................................................................................... 2073
17-2. Quadrature Decoder Truth Table ..................................................................................... 2075
17-3. eQEP Base Address Table ............................................................................................ 2089
17-4. EQEP_REGS Registers ................................................................................................ 2090
17-5. EQEP_REGS Access Type Codes ................................................................................... 2090
17-6. QPOSCNT Register Field Descriptions .............................................................................. 2092
17-7. QPOSINIT Register Field Descriptions ............................................................................... 2093
17-8. QPOSMAX Register Field Descriptions .............................................................................. 2094
17-9. QPOSCMP Register Field Descriptions .............................................................................. 2095
17-10. QPOSILAT Register Field Descriptions .............................................................................. 2096
17-11. QPOSSLAT Register Field Descriptions ............................................................................. 2097
17-12. QPOSLAT Register Field Descriptions ............................................................................... 2098
17-13. QUTMR Register Field Descriptions .................................................................................. 2099
17-14. QUPRD Register Field Descriptions .................................................................................. 2100

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17-15. QWDTMR Register Field Descriptions ............................................................................... 2101

17-16. QWDPRD Register Field Descriptions ............................................................................... 2102
17-17. QDECCTL Register Field Descriptions ............................................................................... 2103
17-18. QEPCTL Register Field Descriptions ................................................................................. 2105
17-19. QCAPCTL Register Field Descriptions ............................................................................... 2108
17-20. QPOSCTL Register Field Descriptions ............................................................................... 2109
17-21. QEINT Register Field Descriptions ................................................................................... 2110
17-22. QFLG Register Field Descriptions .................................................................................... 2112
17-23. QCLR Register Field Descriptions .................................................................................... 2114
17-24. QFRC Register Field Descriptions .................................................................................... 2116
17-25. QEPSTS Register Field Descriptions ................................................................................. 2118
17-26. QCTMR Register Field Descriptions .................................................................................. 2120
17-27. QCPRD Register Field Descriptions .................................................................................. 2121
17-28. QCTMRLAT Register Field Descriptions ............................................................................. 2122
17-29. QCPRDLAT Register Field Descriptions ............................................................................. 2123
18-1. SPI Module Signal Summary .......................................................................................... 2126
18-2. High-Speed SPI Capable GPIOs ...................................................................................... 2127
18-3. SPI Interrupt Flag Modes ............................................................................................... 2129
18-4. SPI Clocking Scheme Selection Guide ............................................................................... 2135
18-5. 4-wire vs. 3-wire SPI Pin Functions ................................................................................... 2138
18-6. 3-Wire SPI Pin Configuration .......................................................................................... 2139
18-7. SPI Base Address Table ............................................................................................... 2144
18-8. SPI_REGS Registers ................................................................................................... 2145
18-9. SPI_REGS Access Type Codes ...................................................................................... 2145
18-10. SPICCR Register Field Descriptions ................................................................................. 2146
18-11. SPICTL Register Field Descriptions .................................................................................. 2148
18-12. SPISTS Register Field Descriptions .................................................................................. 2150
18-13. SPIBRR Register Field Descriptions.................................................................................. 2152
18-14. SPIRXEMU Register Field Descriptions.............................................................................. 2153
18-15. SPIRXBUF Register Field Descriptions .............................................................................. 2154
18-16. SPITXBUF Register Field Descriptions .............................................................................. 2155
18-17. SPIDAT Register Field Descriptions .................................................................................. 2156
18-18. SPIFFTX Register Field Descriptions................................................................................. 2157
18-19. SPIFFRX Register Field Descriptions ................................................................................ 2159
18-20. SPIFFCT Register Field Descriptions ................................................................................ 2161
18-21. SPIPRI Register Field Descriptions ................................................................................... 2162
19-1. SCI Module Signal Summary .......................................................................................... 2167
19-2. Programming the Data Format Using SCICCR ..................................................................... 2168
19-3. Asynchronous Baud Register Values for Common SCI Bit Rates ................................................ 2174
19-4. SCI Interrupt Flags ...................................................................................................... 2176
19-5. SCI Base Address Table ............................................................................................... 2178
19-6. SCI_REGS Registers ................................................................................................... 2179
19-7. SCI_REGS Access Type Codes ...................................................................................... 2179
19-8. SCICCR Register Field Descriptions ................................................................................. 2180
19-9. SCICTL1 Register Field Descriptions................................................................................. 2182
19-10. SCIHBAUD Register Field Descriptions .............................................................................. 2184
19-11. SCILBAUD Register Field Descriptions .............................................................................. 2185
19-12. SCICTL2 Register Field Descriptions................................................................................. 2186
19-13. SCIRXST Register Field Descriptions ................................................................................ 2188

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19-14. SCIRXEMU Register Field Descriptions ............................................................................. 2190

19-15. SCIRXBUF Register Field Descriptions .............................................................................. 2191
19-16. SCITXBUF Register Field Descriptions .............................................................................. 2192
19-17. SCIFFTX Register Field Descriptions ................................................................................ 2193
19-18. SCIFFRX Register Field Descriptions ................................................................................ 2195
19-19. SCIFFCT Register Field Descriptions ................................................................................ 2197
19-20. SCIPRI Register Field Descriptions ................................................................................... 2198
20-1. Dependency of Delay d on the Divide-Down Value IPSC ......................................................... 2203
20-2. Operating Modes of the I2C Module .................................................................................. 2205
20-3. Master-Transmitter/Receiver Bus Activity Defined by the RM, STT, and STP Bits of I2CMDR .............. 2205
20-4. How the MST and FDF Bits of I2CMDR Affect the Role of the TRX Bit of I2CMDR ........................... 2207
20-5. Ways to Generate a NACK Bit ........................................................................................ 2208
20-6. Descriptions of the Basic I2C Interrupt Requests ................................................................... 2211
20-7. I2C Base Address Table ............................................................................................... 2214
20-8. I2C_REGS Registers ................................................................................................... 2215
20-9. I2C_REGS Access Type Codes....................................................................................... 2215
20-10. I2COAR Register Field Descriptions.................................................................................. 2216
20-11. I2CIER Register Field Descriptions ................................................................................... 2217
20-12. I2CSTR Register Field Descriptions .................................................................................. 2218
20-13. I2CCLKL Register Field Descriptions ................................................................................. 2223
20-14. I2CCLKH Register Field Descriptions ................................................................................ 2224
20-15. I2CCNT Register Field Descriptions .................................................................................. 2225
20-16. I2CDRR Register Field Descriptions.................................................................................. 2226
20-17. I2CSAR Register Field Descriptions .................................................................................. 2227
20-18. I2CDXR Register Field Descriptions .................................................................................. 2228
20-19. I2CMDR Register Field Descriptions ................................................................................. 2229
20-20. I2CISRC Register Field Descriptions ................................................................................. 2233
20-21. I2CEMDR Register Field Descriptions ............................................................................... 2234
20-22. I2CPSC Register Field Descriptions .................................................................................. 2235
20-23. I2CFFTX Register Field Descriptions ................................................................................. 2236
20-24. I2CFFRX Register Field Descriptions ................................................................................ 2238
21-1. McBSP Interface Pins/Signals ......................................................................................... 2241
21-2. Register Bits That Determine the Number of Phases, Words, and Bits ......................................... 2248
21-3. Interrupts and DMA Events Generated by a McBSP ............................................................... 2252
21-4. Effects of DLB and CLKSTP on Clock Modes....................................................................... 2254
21-5. Choosing an Input Clock for the Sample Rate Generator with the SCLKME and CLKSM Bits .............. 2254
21-6. Polarity Options for the Input to the Sample Rate Generator .................................................... 2255
21-7. Input Clock Selection for Sample Rate Generator .................................................................. 2258
21-8. Block - Channel Assignment ........................................................................................... 2267
21-9. 2-Partition Mode ......................................................................................................... 2268
21-10. 8-Partition mode ......................................................................................................... 2268
21-11. Receive Channel Assignment and Control With Eight Receive Partitions ....................................... 2270
21-12. Transmit Channel Assignment and Control When Eight Transmit Partitions Are Used ....................... 2271
21-13. Selecting a Transmit Multichannel Selection Mode With the XMCM Bits........................................ 2272
21-14. Bits Used to Enable and Configure the Clock Stop Mode ......................................................... 2275
21-15. Effects of CLKSTP, CLKXP, and CLKRP on the Clock Scheme ................................................. 2276
21-16. Bit Values Required to Configure the McBSP as an SPI Master ................................................ 2279
21-17. Bit Values Required to Configure the McBSP as an SPI Slave ................................................... 2280
21-18. Register Bits Used to Reset or Enable the McBSP Receiver Field Descriptions ............................... 2282

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21-19. Reset State of Each McBSP Pin ...................................................................................... 2282

21-20. Register Bit Used to Enable/Disable the Digital Loopback Mode ................................................. 2283
21-21. Receive Signals Connected to Transmit Signals in Digital Loopback Mode .................................... 2283
21-22. Register Bits Used to Enable/Disable the Clock Stop Mode ...................................................... 2283
21-24. Register Bit Used to Enable/Disable the Receive Multichannel Selection Mode ............................... 2284
21-25. Register Bit Used to Choose One or Two Phases for the Receive Frame ...................................... 2284
21-26. Register Bits Used to Set the Receive Word Length(s) ............................................................ 2285
21-27. Register Bits Used to Set the Receive Frame Length .............................................................. 2285
21-28. How to Calculate the Length of the Receive Frame ................................................................ 2286
21-29. Register Bit Used to Enable/Disable the Receive Frame-Synchronization Ignore Function .................. 2286
21-30. Register Bits Used to Set the Receive Companding Mode ........................................................ 2287
21-31. Register Bits Used to Set the Receive Data Delay ................................................................. 2288
21-32. Register Bits Used to Set the Receive Sign-Extension and Justification Mode................................. 2290
21-33. Example: Use of RJUST Field With 12-Bit Data Value ABCh..................................................... 2290
21-34. Example: Use of RJUST Field With 20-Bit Data Value ABCDEh ................................................. 2290
21-35. Register Bits Used to Set the Receive Interrupt Mode ............................................................. 2291
21-36. Register Bits Used to Set the Receive Frame Synchronization Mode .......................................... 2291
21-37. Select Sources to Provide the Receive Frame-Synchronization Signal and the Effect on the FSR Pin..... 2292
21-38. Register Bit Used to Set Receive Frame-Synchronization Polarity ............................................... 2293
21-39. Register Bits Used to Set the SRG Frame-Synchronization Period and Pulse Width ......................... 2294
21-40. Register Bits Used to Set the Receive Clock Mode ............................................................... 2295
21-41. Receive Clock Signal Source Selection .............................................................................. 2296
21-42. Register Bit Used to Set Receive Clock Polarity .................................................................... 2296
21-43. Register Bits Used to Set the Sample Rate Generator (SRG) Clock Divide-Down Value ..................... 2298
21-44. Register Bit Used to Set the SRG Clock Synchronization Mode ................................................. 2298
21-45. Register Bits Used to Set the SRG Clock Mode (Choose an Input Clock) ...................................... 2299
21-46. Register Bits Used to Set the SRG Input Clock Polarity ........................................................... 2300
21-47. Register Bits Used to Place Transmitter in Reset Field Descriptions ............................................ 2301
21-48. Register Bit Used to Enable/Disable the Digital Loopback Mode ................................................. 2302
21-49. Receive Signals Connected to Transmit Signals in Digital Loopback Mode .................................... 2302
21-50. Register Bits Used to Enable/Disable the Clock Stop Mode ...................................................... 2302
21-52. Register Bits Used to Enable/Disable Transmit Multichannel Selection ......................................... 2304
21-53. Register Bit Used to Choose 1 or 2 Phases for the Transmit Frame ............................................ 2305
21-54. Register Bits Used to Set the Transmit Word Length(s) ........................................................... 2305
21-55. Register Bits Used to Set the Transmit Frame Length ............................................................. 2306
21-56. How to Calculate Frame Length ....................................................................................... 2306
21-57. Register Bit Used to Enable/Disable the Transmit Frame-Synchronization Ignore Function ................. 2307
21-58. Register Bits Used to Set the Transmit Companding Mode ....................................................... 2308
21-59. Register Bits Used to Set the Transmit Data Delay ................................................................ 2309
21-60. Register Bit Used to Set the Transmit DXENA (DX Delay Enabler) Mode ...................................... 2311
21-61. Register Bits Used to Set the Transmit Interrupt Mode ............................................................ 2311
21-62. Register Bits Used to Set the Transmit Frame-Synchronization Mode .......................................... 2312
21-63. How FSXM and FSGM Select the Source of Transmit Frame-Synchronization Pulses ....................... 2312
21-64. Register Bit Used to Set Transmit Frame-Synchronization Polarity .............................................. 2313
21-65. Register Bits Used to Set SRG Frame-Synchronization Period and Pulse Width .............................. 2314
21-66. Register Bit Used to Set the Transmit Clock Mode ................................................................. 2315
21-67. How the CLKXM Bit Selects the Transmit Clock and the Corresponding Status of the MCLKX pin ......... 2315

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21-68. Register Bit Used to Set Transmit Clock Polarity ................................................................... 2315
21-69. McBSP Emulation Modes Selectable with FREE and SOFT Bits of SPCR2.................................... 2317
21-70. Reset State of Each McBSP Pin ...................................................................................... 2317
21-71. Receive Interrupt Sources and Signals .............................................................................. 2322
21-72. Transmit Interrupt Sources and Signals .............................................................................. 2322
21-73. Error Flags ............................................................................................................... 2323
21-74. McBSP Mode Selection ................................................................................................ 2323
21-75. McBSP Base Address Table........................................................................................... 2325
21-76. McBSP Register Summary............................................................................................. 2325
21-77. Serial Port Control 1 Register (SPCR1) Field Descriptions ....................................................... 2327
21-78. Serial Port Control 2 Register (SPCR2) Field Descriptions........................................................ 2330
21-79. Receive Control Register 1 (RCR1) Field Descriptions ............................................................ 2332
21-80. Frame Length Formula for Receive Control 1 Register (RCR1) .................................................. 2333
21-81. Receive Control Register 2 (RCR2) Field Descriptions ............................................................ 2333
21-82. Frame Length Formula for Receive Control 2 Register (RCR2) .................................................. 2334
21-83. Transmit Control 1 Register (XCR1) Field Descriptions ........................................................... 2335
21-84. Frame Length Formula for Transmit Control 1 Register (XCR1) ................................................. 2335
21-85. Transmit Control 2 Register (XCR2) Field Descriptions ........................................................... 2336
21-86. Frame Length Formula for Transmit Control 2 Register (XCR2) ................................................. 2337
21-87. Sample Rate Generator 1 Register (SRGR1) Field Descriptions ................................................. 2338
21-88. Sample Rate Generator 2 Register (SRGR2) Field Descriptions ................................................. 2339
21-89. Multichannel Control 1 Register (MCR1) Field Descriptions ...................................................... 2340
21-90. Multichannel Control 2 Register (MCR2) Field Descriptions ...................................................... 2342
21-91. Pin Control Register (PCR) Field Descriptions ...................................................................... 2344
21-92. Pin Configuration ....................................................................................................... 2346
21-93. Receive Channel Enable Registers (RCERA...RCERH) Field Descriptions..................................... 2346
21-94. Use of the Receive Channel Enable Registers ..................................................................... 2347
21-95. Transmit Channel Enable Registers (XCERA...XCERH) Field Descriptions .................................... 2348
21-96. Use of the Transmit Channel Enable Registers .................................................................... 2349
21-97. McBSP Interrupt Enable Register (MFFINT) Field Descriptions .................................................. 2350
22-1. CAN Register Access From Software ................................................................................ 2354
22-2. CAN Register Access From CCS ..................................................................................... 2355
22-3. PIE Nomenclature for Interrupts ....................................................................................... 2361
22-4. Programmable Ranges Required by CAN Protocol ................................................................ 2369
22-5. Message Object Field Descriptions ................................................................................... 2378
22-6. Message RAM Addressing in Debug Mode ......................................................................... 2381
22-7. CAN Base Addresses Table ........................................................................................... 2383
22-8. CAN_REGS Registers .................................................................................................. 2384
22-9. CAN_REGS Access Type Codes ..................................................................................... 2385
22-10. CAN_CTL Register Field Descriptions ............................................................................... 2386
22-11. CAN_ES Register Field Descriptions ................................................................................. 2389
22-12. CAN_ERRC Register Field Descriptions ............................................................................. 2391
22-13. CAN_BTR Register Field Descriptions ............................................................................... 2392
22-14. CAN_INT Register Field Descriptions ................................................................................ 2394
22-15. CAN_TEST Register Field Descriptions.............................................................................. 2395
22-16. CAN_PERR Register Field Descriptions ............................................................................. 2397
22-17. CAN_RAM_INIT Register Field Descriptions ........................................................................ 2398
22-18. CAN_GLB_INT_EN Register Field Descriptions .................................................................... 2399
22-19. CAN_GLB_INT_FLG Register Field Descriptions .................................................................. 2400

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22-20. CAN_GLB_INT_CLR Register Field Descriptions .................................................................. 2401

22-21. CAN_ABOTR Register Field Descriptions ........................................................................... 2402
22-22. CAN_TXRQ_X Register Field Descriptions .......................................................................... 2403
22-23. CAN_TXRQ_21 Register Field Descriptions ........................................................................ 2404
22-24. CAN_NDAT_X Register Field Descriptions .......................................................................... 2405
22-25. CAN_NDAT_21 Register Field Descriptions......................................................................... 2406
22-26. CAN_IPEN_X Register Field Descriptions ........................................................................... 2407
22-27. CAN_IPEN_21 Register Field Descriptions .......................................................................... 2408
22-28. CAN_MVAL_X Register Field Descriptions .......................................................................... 2409
22-29. CAN_MVAL_21 Register Field Descriptions......................................................................... 2410
22-30. CAN_IP_MUX21 Register Field Descriptions ....................................................................... 2411
22-31. CAN_IF1CMD Register Field Descriptions .......................................................................... 2412
22-32. CAN_IF1MSK Register Field Descriptions ........................................................................... 2416
22-33. CAN_IF1ARB Register Field Descriptions ........................................................................... 2417
22-34. CAN_IF1MCTL Register Field Descriptions ......................................................................... 2419
22-35. CAN_IF1DATA Register Field Descriptions ......................................................................... 2422
22-36. CAN_IF1DATB Register Field Descriptions ......................................................................... 2423
22-37. CAN_IF2CMD Register Field Descriptions .......................................................................... 2424
22-43. CAN_IF3OBS Register Field Descriptions ........................................................................... 2436
22-49. CAN_IF3UPD Register Field Descriptions ........................................................................... 2444
23-1. USB Memory Access From Software ................................................................................. 2455
23-2. USB Memory Access From CCS...................................................................................... 2456
23-3. Universal Serial Bus (USB) Controller Register Map .............................................................. 2458
23-4. Function Address Register (USBFADDR) Field Descriptions ..................................................... 2473
23-5. Power Management Register (USBPOWER) in Host Mode Field Descriptions ................................ 2474
23-6. Power Management Register (USBPOWER) in Device Mode Field Descriptions.............................. 2474
23-7. USB Transmit Interrupt Status Register (USBTXIS) Field Descriptions ......................................... 2476
23-8. USB Transmit Interrupt Status Register (USBRXIS) Field Descriptions ......................................... 2478
23-9. USB Transmit Interrupt Status Register (USBTXIE) Field Descriptions ......................................... 2480
23-10. USB Transmit Interrupt Status Register (USBRXIE) Field Descriptions ......................................... 2482
23-11. USB General Interrupt Status Register (USBIS) in Host Mode Field Descriptions ............................. 2484
23-12. USB General Interrupt Status Register (USBIS) in Device Mode Field Descriptions .......................... 2485
23-13. USB Interrupt Enable Register (USBIE) in Host Mode Field Descriptions ...................................... 2486
23-14. USB Interrupt Enable Register (USBIE) in Device Mode Field Descriptions .................................... 2487
23-15. Frame Number Register (FRAME) Field Descriptions ............................................................. 2488
23-16. USB Endpoint Index Register (USBEPIDX) Field Descriptions ................................................... 2488
23-17. USB Test Mode Register (USBTEST) in Host Mode Field Descriptions......................................... 2489
23-18. USB Test Mode Register (USBTEST) in Device Mode Field Descriptions ...................................... 2489
23-19. USB FIFO Endpoint n Register (USBFIFO[n]) Field Descriptions ................................................ 2491

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23-20. USB Device Control Register (USBDEVCTL) Field Descriptions ................................................. 2492
23-21. USB Transmit Dynamic FIFO Sizing Register (USBTXFIFOSZ) Field Descriptions ........................... 2494
23-22. USB Receive Dynamic FIFO Sizing Register (USBRXFIFOSZ) Field Descriptions ............................ 2495
23-23. USB Transmit FIFO Start Address Register (USBTXFIFOADDR) Field Descriptions ......................... 2496
23-24. USB Receive FIFO Start Address Register (USBRXFIFOADDR) Field Descriptions .......................... 2497
23-25. USB Connect Timing Register (USBCONTIM) Field Descriptions................................................ 2498
23-26. USB Full-Speed Last Transaction to End of Frame Timing Register (USBFSEOF) Field Descriptions ..... 2499
23-27. USB Low-Speed Last Transaction to End of Frame Timing Register (USBLSEOF) Field Descriptions..... 2499
23-28. USB Transmit Functional Address Endpoint n Registers (USBTXFUNCADDR[n]) Field Descriptions ...... 2500
23-29. USB Transmit Hub Address Endpoint n Registers(USBTXHUBADDR[n]) Field Descriptions ................ 2501
23-30. USB Transmit Hub Port Endpoint n Registers(USBTXHUBPORT[n]) Field Descriptions ..................... 2502
23-31. USB Recieve Functional Address Endpoint n Registers(USBFIFO[n]) Field Descriptions .................... 2503
23-32. USB Receive Hub Address Endpoint n Registers(USBRXHUBADDR[n]) Field Descriptions ................ 2504
23-33. USB Transmit Hub Port Endpoint n Registers(USBRXHUBPORT[n]) Field Descriptions ..................... 2505
23-34. USB Maximum Transmit Data Endpoint n Registers(USBTXMAXP[n]) Field Descriptions ................... 2506
23-35. USB Control and Status Endpoint 0 Low Register(USBCSRL0) in Host Mode Field Descriptions .......... 2507
23-36. USB Control and Status Endpoint 0 Low Register (USBCSRL0) in Device Mode Field Descriptions ....... 2508
23-37. USB Control and Status Endpoint 0 High Register (USBCSRH0) in Host Mode Field Descriptions......... 2509
23-38. USB Control and Status Endpoint 0 High Register (USBCSRH0) in Device Mode Field Descriptions ...... 2509
23-39. USB Receive Byte Count Endpoint 0 Register (USBCOUNT0) Field Descriptions ............................ 2510
23-40. USB Type Endpoint 0 Register (USBTYPE0) Field Descriptions ................................................. 2510
23-41. USB NAK Limit Register (USBNAKLMT) Field Descriptions ...................................................... 2511
23-42. USB Transmit Control and Status Endpoint n Low Register (USBTXCSRL[n]) in Host Mode Field
Descriptions .............................................................................................................. 2512
23-43. USB Transmit Control and Status Endpoint n Low Register (USBTXCSRL[n]) in Device Mode Field
Descriptions .............................................................................................................. 2513
23-44. USB Transmit Control and Status Endpoint n High Register (USBTXCSRH[n]) in Host Mode Field
Descriptions .............................................................................................................. 2515
23-45. USB Transmit Control and Status Endpoint n High Register (USBTXCSRH[n]) in Device Mode Field
Descriptions .............................................................................................................. 2516
23-46. USB Maximum Receive Data Endpoint n Registers (USBTXMAXP[n]) Field Descriptions ................... 2517
23-47. USB Control and Status Endpoint n Low Register(USBCSRL[n]) in Host Mode Field Descriptions ......... 2518
23-48. USB Control and Status Endpoint 0 Low Register(USBCSRL[n]) in Device Mode Field Descriptions ...... 2519
23-49. USB Control and Status Endpoint n High Register (USBCSRH[n]) in Host Mode Field Descriptions ....... 2520
23-50. USB Control and Status Endpoint 0 High Register(USBCSRH[n]) in Device Mode Field Descriptions ..... 2521
23-51. USB Maximum Receive Data Endpoint n Registers (USBRXCOUNT[n]) Field Descriptions ................. 2522
23-52. USB Host Transmit Configure Type Endpoint n Register(USBTXTYPE[n]) Field Descriptions .............. 2523
23-53. USBTXINTERVAL[n] Frame Numbers ............................................................................... 2524
23-54. USB Host Transmit Interval Endpoint n Register(USBTXINTERVAL[n]) Field Descriptions .................. 2524
23-55. USB Host Configure Receive Type Endpoint n Register(USBRXTYPE[n]) Field Descriptions ............... 2525
23-56. USBRXINTERVAL[n] Frame Numbers ............................................................................... 2526
23-57. USB Host Receive Polling Interval Endpoint n Register(USBRXINTERVAL[n]) Field Descriptions.......... 2526
23-58. USB Request Packet Count in Block Transfer Endpoint n Registers (USBRQPKTCOUNT[n]) Field
Descriptions .............................................................................................................. 2527
23-59. USB Receive Double Packet Buffer Disable Register (USBRXDPKTBUFDIS) Field Descriptions .......... 2528
23-60. USB Transmit Double Packet Buffer Disable Register (USBTXDPKTBUFDIS) Field Descriptions .......... 2530
23-61. USB External Power Control Register (USBEPC) Field Descriptions ............................................ 2531
23-62. USB External Power Control Raw Interrupt Status Register (USBEPCRIS) Field Descriptions .............. 2533
23-63. USB External Power Control Interrupt Mask Register (USBEPCIM) Field Descriptions....................... 2534
23-64. USB External Power Control Interrupt Status and Clear Register (USBEPCISC) Field Descriptions ....... 2535

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23-65. USB Device RESUME Raw Interrupt Status Register (USBDRRIS) Field Descriptions....................... 2536
23-66. USB Device RESUME Raw Interrupt Status Register (USBDRRIS) Field Descriptions....................... 2537
23-67. USB Device RESUME Interrupt Status and Clear Register (USBDRISC) Field Descriptions ................ 2538
23-68. USB General-Purpose Control and Status Register (USBGPCS) Field Descriptions .......................... 2539
23-69. USB DMA Select Register (USBDMASEL) Field Descriptions .................................................... 2540
24-1. uPP Signal Description ................................................................................................. 2547
24-2. CPU/CLA/uPP-DMA Address Map.................................................................................... 2554
24-3. CPU/CLA/uPP-DMA Address Map.................................................................................... 2555
24-4. uPP Parameters Useful for System Tuning .......................................................................... 2556
24-5. UPP Base Address Table .............................................................................................. 2557
24-6. UPP_REGS Registers .................................................................................................. 2558
24-7. UPP_REGS Access Type Codes ..................................................................................... 2558
24-8. PID Register Field Descriptions ....................................................................................... 2560
24-9. PERCTL Register Field Descriptions ................................................................................. 2561
24-10. CHCTL Register Field Descriptions ................................................................................... 2563
24-11. IFCFG Register Field Descriptions.................................................................................... 2564
24-12. IFIVAL Register Field Descriptions ................................................................................... 2566
24-13. THCFG Register Field Descriptions .................................................................................. 2567
24-14. RAWINTST Register Field Descriptions.............................................................................. 2569
24-15. ENINTST Register Field Descriptions ................................................................................ 2571
24-16. INTENSET Register Field Descriptions .............................................................................. 2573
24-17. INTENCLR Register Field Descriptions .............................................................................. 2575
24-18. CHIDESC0 Register Field Descriptions .............................................................................. 2577
24-21. CHIST0 Register Field Descriptions .................................................................................. 2580
24-24. CHQDESC0 Register Field Descriptions ............................................................................. 2583
24-27. CHQST0 Register Field Descriptions ................................................................................. 2586
24-30. GINTEN Register Field Descriptions ................................................................................. 2589
24-31. GINTFLG Register Field Descriptions ................................................................................ 2590
24-32. GINTCLR Register Field Descriptions ................................................................................ 2591
24-33. DLYCTL Register Field Descriptions ................................................................................. 2592
25-1. Configuration for EMIF1 and EMIF2 Modules ....................................................................... 2594
25-2. EMIF Pins Used to Access Both SDRAM and Asynchronous Memories ........................................ 2597
25-3. EMIF Pins Specific to SDRAM ........................................................................................ 2597
25-4. EMIF Pins Specific to Asynchronous Memory ...................................................................... 2598
25-5. EMIF SDRAM Commands ............................................................................................. 2598
25-6. Truth Table for SDRAM Commands .................................................................................. 2599
25-7. 16-bit EMIF Address Pin Connections................................................................................ 2600
25-8. Description of the SDRAM Configuration Register (SDRAM_CR) ................................................ 2602
25-9. Description of the SDRAM Refresh Control Register (SDRAM_RCR) ........................................... 2602
25-10. Description of the SDRAM Timing Register (SDRAM_TR) ........................................................ 2603
25-11. Description of the SDRAM Self Refresh Exit Timing Register (SDR_EXT_TMNG) ............................ 2603

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25-12. SDRAM LOAD MODE REGISTER Command ...................................................................... 2604

25-13. Refresh Urgency Levels ................................................................................................ 2605
25-14. Mapping from Logical Address to EMIF Pins for 32-bit SDRAM .................................................. 2610
25-15. Mapping from Logical Address to EMIF Pins for 16-bit SDRAM .................................................. 2610
25-16. Normal Mode vs. Select Strobe Mode ................................................................................ 2611
25-17. Description of the Asynchronous m Configuration Register (ASYNC_CSn_CR) ............................... 2613
25-18. Description of the Asynchronous Wait Cycle Configuration Register (ASYNC_WCCR) ...................... 2614
25-19. Description of EMIF Interrupt Mask Set Register (INT_MSK_SET) .............................................. 2614
25-20. Description of EMIF Interrupt Mast Clear Register (INT_MSK_CLR) ............................................ 2614
25-21. Asynchronous Read Operation in Normal Mode .................................................................... 2615
25-22. Asynchronous Write Operation in Normal Mode .................................................................... 2617
25-23. Asynchronous Read Operation in Select Strobe Mode ............................................................ 2619
25-24. Asynchronous Write Operation in Select Strobe Mode ............................................................ 2621
25-25. Interrupt Monitor and Control Bit Fields .............................................................................. 2624
25-26. SR Field Value For EMIF to K4S641632H-TC(L)70 Interface..................................................... 2628
25-27. SDRAM_TR Field Calculations for EMIF to K4S641632H-TC(L)70 Interface................................... 2630
25-28. RR Calculation for EMIF to K4S641632H-TC(L)70 Interface ..................................................... 2631
25-29. RR Calculation for EMIF to K4S641632H-TC(L)70 Interface ..................................................... 2631
25-30. SDRAM_CR Field Values For EMIF to K4S641632H-TC(L)70 Interface ........................................ 2632
25-31. AC Characteristics for a Read Access ............................................................................... 2633
25-32. AC Characteristics for a Write Access ............................................................................... 2633
25-33. EMIF Base Address Table ............................................................................................. 2636
25-34. EMIF_REGS Registers ................................................................................................. 2637
25-35. EMIF_REGS Access Type Codes .................................................................................... 2637
25-36. RCSR Register Field Descriptions .................................................................................... 2638
25-37. ASYNC_WCCR Register Field Descriptions ........................................................................ 2639
25-38. SDRAM_CR Register Field Descriptions ............................................................................ 2640
25-39. SDRAM_RCR Register Field Descriptions........................................................................... 2642
25-40. ASYNC_CS2_CR Register Field Descriptions ...................................................................... 2643
25-43. SDRAM_TR Register Field Descriptions ............................................................................. 2649
25-44. TOTAL_SDRAM_AR Register Field Descriptions .................................................................. 2650
25-45. TOTAL_SDRAM_ACTR Register Field Descriptions ............................................................... 2651
25-46. SDR_EXT_TMNG Register Field Descriptions ...................................................................... 2652
25-47. INT_RAW Register Field Descriptions ............................................................................... 2653
25-48. INT_MSK Register Field Descriptions ................................................................................ 2654
25-49. INT_MSK_SET Register Field Descriptions ......................................................................... 2655
25-50. INT_MSK_CLR Register Field Descriptions ......................................................................... 2656
25-51. EMIF1_CONFIG_REGS Registers ................................................................................... 2657
25-52. EMIF1_CONFIG_REGS Access Type Codes ....................................................................... 2657
25-53. EMIF1LOCK Register Field Descriptions ............................................................................ 2658
25-54. EMIF1COMMIT Register Field Descriptions ......................................................................... 2659
25-55. EMIF1MSEL Register Field Descriptions ............................................................................ 2660
25-56. EMIF1ACCPROT0 Register Field Descriptions ..................................................................... 2661
25-57. EMIF2_CONFIG_REGS Registers ................................................................................... 2662
25-58. EMIF2_CONFIG_REGS Access Type Codes ....................................................................... 2662
25-59. EMIF2LOCK Register Field Descriptions ............................................................................ 2663
25-60. EMIF2COMMIT Register Field Descriptions ......................................................................... 2664

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25-61. EMIF2ACCPROT0 Register Field Descriptions ..................................................................... 2665

Preface
SPRUHM8G – December 2013 – Revised September 2017
Read This First
About This Manual

This Technical Reference Manual (TRM) details the integration, the environment, the functional
description, and the programming models for each peripheral and subsystem in the device.
The TRM should not be considered a substitute for the data manual, rather a companion guide that should
be used alongside the device-specific data manual to understand the details to program the device. The
primary purpose of the TRM is to abstract the programming details of the device from the data manual.
This allows the data manual to outline the high-level features of the device without unnecessary
information about register descriptions or programming models.
Notational Conventions
This document uses the following conventions.
• Hexadecimal numbers may be shown with the suffix h or the prefix 0x. For example, the following
number is 40 hexadecimal (decimal 64): 40h or 0x40.
• Registers in this document are shown in figures and described in tables.
– Each register figure shows a rectangle divided into fields that represent the fields of the register.
Each field is labeled with its bit name, its beginning and ending bit numbers above, and its
read/write properties with default reset value below. A legend explains the notation used for the
properties.
– Reserved bits in a register figure can have one of multiple meanings:
• Not implemented on the device
• Reserved for future device expansion
• Reserved for TI testing
• Reserved configurations of the device that are not supported
– Writing nondefault values to the Reserved bits could cause unexpected behavior and should be
avoided.
Glossary
TI Glossary — This glossary lists and explains terms, acronyms, and definitions.
Related Documentation From Texas Instruments

For a complete listing of related documentation and development-support tools for these devices, visit the
Texas Instruments website at http://www.ti.com. Additionally, the TMS320C28x CPU and Instruction Set
Reference Guide (SPRU430) and TMS320C28x Floating Point Unit and Instruction Set Reference Guide
(SPRUEO2) must be used in conjunction with this TRM.
Trademarks
controlSUITE, Code Composer Studio are trademarks of Texas Instruments.
USB Specification Revision 2.0 is a trademark of Compaq Computer Corp.
SPRUHM8G – December 2013 – Revised September 2017 Read This First 81

Chapter 1
C28x Processor
This chapter contains a modified description of the C28x Processor and provides links to access their
respective references guides.
Topic ........................................................................................................................... Page
1.1 Overview ........................................................................................................... 83
82 C28x Processor SPRUHM8G – December 2013 – Revised September 2017

www.ti.com Overview
1.1 Overview
The CPU is a 32-bit fixed-point processor. This device draws from the best features of digital signal
processing; reduced instruction set computing (RISC); and microcontroller architectures, firmware, and
tool sets.
The CPU features include a modified Harvard architecture and circular addressing. The RISC features are
single-cycle instruction execution, register-to-register operations, and modified Harvard architecture. The
microcontroller features include ease of use through an intuitive instruction set, byte packing and
unpacking, and bit manipulation. The modified Harvard architecture of the CPU enables instruction and
data fetches to be performed in parallel. The CPU can read instructions and data while it writes data
simultaneously to maintain the single-cycle instruction operation across the pipeline. The CPU does this
over six separate address/data buses.
For more information on CPU architecture and instruction set, see the TMS320C28x CPU and Instruction
Set Reference Guide (literature number SPRU430). For more information on the C28x Floating Point Unit
(FPU), Trigonometric Math Unit, and Viterbi, Complex Math, and CRC Unit II (VCU-II) instruction sets, see
the TMS320C28x Extended Instruction Sets Technical Reference Guide (literature number SPRUHS1). A
brief overview of the FPU, TMU, and VCU-II are provided here.
1.1.1 Floating-Point Unit

The C28x plus floating-point (C28x+FPU) processor extends the capabilities of the C28x fixed-point CPU
by adding registers and instructions to support IEEE single-precision floating point operations.
Devices with the C28x+FPU include the standard C28x register set plus an additional set of floating-point
unit registers. The additional floating-point unit registers are the following:
• Eight floating-point result registers, RnH (where n = 0–7)
• Floating-point Status Register (STF)
• Repeat Block Register (RB)
All of the floating-point registers, except the repeat block register, are shadowed. This shadowing can be
used in high-priority interrupts for fast context save and restore of the floating-point registers.
1.1.2 Trigonometric Math Unit

The TMU extends the capabilities of a C28x+FPU by adding instructions and leveraging existing FPU
instructions to speed up the execution of common trigonometric and arithmetic operations listed in
Table 1-1.
Table 1-1. TMU Supported Instructions

INSTRUCTIONS C EQUIVALENT OPERATION PIPELINE CYCLES
MPY2PIF32 RaH,RbH a = b * 2pi 2/3
DIV2PIF32 RaH,RbH a = b / 2pi 2/3
DIVF32 RaH,RbH,RcH a = b/c 5
SQRTF32 RaH,RbH a = sqrt(b) 5
SINPUF32 RaH,RbH a = sin(b*2pi) 4
COSPUF32 RaH,RbH a = cos(b*2pi) 4
ATANPUF32 RaH,RbH a = atan(b)/2pi 4
QUADF32 RaH,RbH,RcH,RdH Operation to assist in calculating ATANPU2 5
No changes have been made to existing instructions, pipeline or memory bus architecture. All TMU
instructions use the existing FPU register set (R0H to R7H) to carry out their operations.
SPRUHM8G – December 2013 – Revised September 2017 C28x Processor 83

Overview www.ti.com
1.1.3 Viterbi, Complex Math, and CRC Unit II (VCU-II)

The VCU-II is the second-generation Viterbi, Complex Math, and CRC extension to the C28x CPU. The
VCU-II extends the capabilities of the C28x CPU by adding registers and instructions to accelerate the
performance of FFTs and communications-based algorithms. The C28x+VCU-II supports the following
algorithm types:
• Viterbi Decoding
Viterbi decoding is commonly used in baseband communications applications. The Viterbi decode
algorithm consists of three main parts: branch metric calculations, compare-select (Viterbi butterfly),
and a traceback operation. Table 1-2 shows a summary of the VCU performance for each of these
operations.
Table 1-2. Viterbi Decode Performance

VITERBI OPERATION VCU CYCLES
Branch Metric Calculation (code rate = 1/2) 1
Branch Metric Calculation (code rate = 1/3) 2p
Viterbi Butterfly (add-compare-select) 2 (1)
Traceback per Stage 3 (2)
(1)
C28x CPU takes 15 cycles per butterfly.
(2)
C28x CPU takes 22 cycles per stage.
• Cyclic Redundancy Check

Cyclic redundancy check (CRC) algorithms provide a straightforward method for verifying data integrity
over large data blocks, communication packets, or code sections. The C28x+VCU can perform 8-bit,
16-bit, 24-bit, and 32-bit CRCs. For example, the VCU can compute the CRC for a block length of 10
bytes in 10 cycles. A CRC result register contains the current CRC, which is updated whenever a CRC
instruction is executed.
• Complex Math
Complex math is used in many applications, a few of which are:
– Fast Fourier Transform (FFT)
The complex FFT is used in spread spectrum communications, as well as in many signal
processing algorithms.
– Complex filters
Complex filters improve data reliability, transmission distance, and power efficiency. The
C28x+VCU can perform a complex I and Q multiply with coefficients (four multiplies) in a single
cycle. In addition, the C28x+VCU can read/write the real and imaginary parts of 16-bit complex data
to memory in a single cycle.
Table 1-3. Complex Math Performance

COMPLEX MATH OPERATION VCU CYCLES NOTES
Add or Subtract 1 32 +/- 32 = 32-bit (Useful for filters)
Add or Subtract 1 16 +/- 32 = 15-bit (Useful for FFT)
Multiply 2p 16 x 16 = 32-bit
Multiply and Accumulate (MAC) 2p 32 + 32 = 32-bit, 16 x 16 = 32-bit
RPT MAC 2p+N Repeat MAC. Single cycle after the first operation.
NOTE: Only the CRC-related VCU instructions will be supported in future devices. FFT algorithms
are available for the C28x+FPU.
84 C28x Processor SPRUHM8G – December 2013 – Revised September 2017

Chapter 2
System Control
This chapter explains system control and interrupts found on this MCU. The system control module
configures and manages the overall operation of the device and provides information about the device
status. Configurable features in system control include reset control, NMI operation, power control, clock
control, and low-power modes.
Topic ........................................................................................................................... Page
2.1 Introduction ....................................................................................................... 86

2.2 System Control Functional Description................................................................. 86
2.3 Resets .............................................................................................................. 87
2.4 Peripheral Interrupts ........................................................................................... 89
2.5 Exceptions and Non-Maskable Interrupts ............................................................ 102
2.6 Safety Features ................................................................................................ 103
2.7 Clocking ......................................................................................................... 107
2.8 32-Bit CPU Timers 0/1/2 ..................................................................................... 117
2.9 Watchdog Timers ............................................................................................. 119
2.10 Low Power Modes ............................................................................................ 122
2.11 Memory Controller Module ................................................................................ 125
2.12 Flash and OTP Memory ..................................................................................... 133
2.13 Dual Code Security Module (DCSM) .................................................................... 146
2.14 JTAG............................................................................................................... 157
2.15 Registers ......................................................................................................... 159
SPRUHM8G – December 2013 – Revised September 2017 System Control 85

Introduction www.ti.com
2.1 Introduction
On this device, the CPU1 subsystem acts as a master, and by default (upon reset), it owns all the
configuration and control. Through software running on CPU1, peripherals and I/Os can be configured to
be accessible by the CPU2 subsystem and the configuration so chosen could be locked.
The PLL clock configuration is also owned by the CPU1 subsystem by default, but a clock control
semaphore is provided by which CPU2 can grab access to the clock configuration registers.
Each CPU has its own NMI module to handle different exceptions during run time. If the NMI was on
CPU1, any NMI exception that is unhandled before the NMI Watchdog (NMIWD) timer expiration will reset
the entire device. If the NMI was on the CPU2 subsystem, then the CPU2 subsystem alone will be reset,
in which case the CPU1 subsystem will be informed by another NMI that the CPU2 subsystem was reset
because of NMIWD timer expiration.
Each CPU subsystem has its own watchdog timer module for software to use. Watchdog timer expiration
on CPU2 will reset the CPU2 subsystem alone when configured to generate a reset, but watchdog timer
expiration on CPU1 will reset the entire device.
Except for a CPU2 standalone internal reset such as CPU2.NMIWD or CPU2.WD each time the device is
reset, the CPU2 subsystem will be held under reset until the CPU1 subsystem brings it out of reset. This
is done by the boot ROM software running on the CPU1 core.
The register space of the device system control module is divided into three categories and will be
explained further in this chapter. They are:
1. System Control Device Configuration Registers (DEV_CFG_REGS). These registers are mapped to
CPU1 only. The base address of these registers on the CPU1 address space begins at 0x5D000.
2. System Control Clock Configuration Registers (CLK_CFG_REGS). These registers are mapped to
both CPU1 and CPU2 address space but access control is based on a Clock Control Semaphore
register. The base address of these registers on both the CPU subsystems begins at 0x5D200.
3. System control CPU Subsystem Registers (CPU_SYS_REGS). These registers are mapped to both
the CPU subsystems. The base address of these registers on both the CPU subsystems begins at
0x5D300.
This chapter explains the system control module on both the CPU subsystems.
2.2 System Control Functional Description

The system control module provides the following capabilities:
• Device identification and configuration registers
• Reset control
• Exceptions and Interrupt control
• Safety and error handling features of the device
• Power control
• Clock control
• Low Power modes
• Security module
• Inter-Processor Communication (IPC)
2.2.1 Device Identification

Device identification registers provide information on device class, device family, revision, part number, pin
count, operating temperature range, package type, pin count, and device qualification status.
All of the device information is part of the DEV_CFG_REGS space and is accessible only by the software
running on the CPU1 subsystem.
The control subsystem device identification registers are: PARTIDL, PARTIDH, and REVID.
A 256-bit Unique ID (UID) is available in UID_REGS. The 256 bits are separated into these registers:
86 System Control SPRUHM8G – December 2013 – Revised September 2017

www.ti.com System Control Functional Description
• UID_PSRAND0-5: 192 bits of pseudo-random data

• UID_UNIQUE: 32-bit unique data, the value in this register will be unique across all devices with the
same PARTIDH
• UID_CHECKSUM: 32-bit fletcher checksum of UID_PSRAND0-5 and UID_UNIQUE
• CPU ID: 16-bit location in OTP. The value at this location provides the information about CPU (CPU1
or CPU20. Please refer to the device datasheet, for more detail.
2.2.2 Device Configuration Registers

Several registers provide users with configuration information for debug and identification purposes on this
MCU. This information includes the features of the peripheral and how much RAM and FLASH memory is
available on this part.
These registers are part of DEV_CFG_REGS space and are accessible only by the software running on
the CPU1 subsystem.
• DC0 – DC20: Device Configuration or Capabilities registers.
If a particular bit in these registers is set to ‘1’ then the associated/feature or module is available in the
device.
• PERCNF: Peripheral configuration register.
This register configures ADC capabilities, and enables or disables the USB internal PHY.
• CPUID: CPU identification register
This register is available for software to identify on which CPU it is executing.
2.3 Resets
This section explains the types and effects of the different resets on this device.
2.3.1 Reset Sources

Table 2-1 summarizes the various reset signals and their effect on the device.
Table 2-1. Reset Signals

Reset Source CPU1 CPU1 CPU2 CPU2 CPU2 Held JTAG / IOs XRS
Core Peripheral Core Peripheral In Reset Debug Output
Reset s Reset Reset s Reset Logic
(C28x, (C28x, Reset
TMU, FPU, TMU, FPU,
VCU) VCU)
POR Yes Yes Yes Yes Yes Yes Hi-Z Yes
XRS Pin Yes Yes Yes Yes Yes No Hi-Z -
CPU1.WDRS Yes Yes Yes Yes Yes No Hi-Z Yes
CPU1.NMIWDRS Yes Yes Yes Yes Yes No Hi-Z Yes
CPU1.SYSRS Yes Yes Yes Yes Yes No Hi-Z No
(Debugger Reset)
CPU1.SCCRESET Yes Yes Yes Yes Yes No Hi-Z No
CPU2.SYSRS No No Yes Yes No No - No
(Debugger Reset)
CPU2.WDRS No No Yes Yes No No - No
CPU2.NMIWDRS No No Yes Yes No No - No
CPU2.SCCRESET No No Yes Yes No No - No
HIBRESET Yes Yes Yes Yes Yes Yes Isolated No
CPU1.HWBISTRS Yes No No No No No - No
CPU2.HWBISTRS No No Yes No No No - No
TRST No No No No No Yes - No

Resets www.ti.com
The resets can be divided into a few groups:

• Chip-level resets (XRS, POR, CPU1.WDRS, and CPU1.NMIWDRS), which reset all or almost all of the
device.
• System resets (CPU1.SYSRS and CPU1.SCCRESET), which reset a large subset of the device but
maintain some system-level configuration.
• CPU2 subsystem resets (CPU2.SYSRS, CPU2.WDRS, CPU2.NMIWDRS, and CPU2.SCCRESET),
which reset only CPU2 and its peripherals.
• Special resets (HIBRESET, CPU1.HWBISTRS, CPU2.HWBISTRS, and TRST), which enable specific
device functions.
Whenever the CPU1 subsystem is reset, CPU2 and its peripherals are also reset, and CPU2 is held in
reset. CPU1 brings it out of reset by writing to the CPU2RESCTL register. This is normally done by the
boot ROM. For more details on the boot process, refer to the ROM Code and Peripheral Booting chapter.
After a reset, the reset cause register (RESC) is updated with the reset cause. The bits in this register
maintain their state across multiple resets. They can only be cleared by a power-on reset (POR) or by
writing ones to the register. Each CPU has its own RESC register, referred to as CPU1.RESC and
CPU2.RESC.
Many peripheral modules have individual resets accessible through the system control registers. For
information about a module's reset state, refer to the appropriate chapter for that module.
After a POR, XRS, CPU1.WDRS, CPU1.NMIWDRS, or HIBRESET, the boot ROMs will clear all of the
system and message RAMs on both CPUs. After a CPU2.WDRS or CPU2.NMIWDRS, CPU2's boot ROM
will clear all of the CPU2 system and message RAMs.
2.3.2 External Reset (XRS)

The external reset (XRS) is the main chip-level reset for the device. It resets both CPUs , all peripherals
and I/O pin configurations, and most of the system control registers. It also holds CPU2 in reset. There is
a dedicated open-drain pin for XRS. This pin may be used to drive reset pins for other ICs in the
application, and may itself be driven by an external source. The XRS is driven internally during watchdog,
NMI, and power-on resets. In hibernate mode, toggling XRS will produce a HIBRESET.
The XRSn bit in the RESC register will be set whenever XRS is driven low for any reason. This bit is then
cleared by the boot ROM.
2.3.3 Power-On Reset (POR)

The power-on reset (POR) circuit creates a clean reset throughout the device during power-up,
suppressing glitches on the GPIOs. The XRS pin is held low for the duration of the POR. In most
applications, XRS is held low long enough to reset other system ICs, but some applications may require a
longer pulse. In these cases, XRS can be driven low externally to provide the correct reset duration. A
POR resets everything that XRS does, along with a few other registers – the reset cause register (RESC),
the NMI shadow flag register (NMISHDFLG), the X1 clock counter register (X1CNT), and the hibernate
configuration registers (HIBBOOTMODE, IORESTOREADDR, and LPMCR.M0M1MODE).
After a POR, the POR and XRSn bits in RESC are set. These bits are then cleared by the boot ROM.
2.3.4 Debugger Reset (SYSRS)

During development, it is sometimes necessary to reset the CPU and its peripherals without disconnecting
the debugger or disrupting the system-level configuration. To facilitate this, each CPU has its own
subsystem reset, which can be triggered by a debugger using Code Composer Studio. CPU2's subsystem
reset (CPU2.SYSRS) resets only CPU2, its peripherals, and its clock gating and LPM configuration. It
does not hold CPU2 in reset. CPU1's subsystem reset (CPU1.SYSRS) resets CPU1, its peripherals, many
system control registers (including its clock gating and LPM configuration and the peripherals' CPU
ownership), and all I/O pin configurations. It also produces a CPU2.SYSRS and holds CPU2 in reset.
Neither SYSRS resets the ICEPick debug module, the device capability registers, the clock source and
PLL configurations, the missing clock detection state, the PIE vector fetch error handler address, the NMI
flags, the analog trims, or anything reset only by a POR (see Section 2.3.3).

www.ti.com Resets
2.3.5 Watchdog Reset (WDRS)

Each CPU has a watchdog timer that can optionally trigger a reset that lasts for 512 INTOSC1 cycles.
CPU1's watchdog reset (CPU1.WDRS) produces an XRS. CPU2's watchdog reset (CPU2.WDRS)
produces a CPU2.SYSRS and triggers an NMI on CPU1.
After a watchdog reset, the WDRSn bit in RESC is set.
2.3.6 NMI Watchdog Reset (NMIWDRS)

Each CPU has a non-maskable interrupt (NMI) module that detects hardware errors in the system. Each
NMI module has a watchdog timer that triggers a reset if the CPU does not respond to an error within a
user-specified amount of time. CPU1's NMI watchdog reset (CPU1.NMIWDRS) produces an XRS. CPU2's
NMI watchdog reset (CPU2.NMIWDRS) produces a CPU2.SYSRS and triggers an NMI on CPU1.
After an NMI watchdog reset, the NMIWDRSn bit in RESC is set.
2.3.7 DCSM Safe Code Copy Reset (SCCRESET)

Each CPU has a dual-zone code security module (DCSM) that blocks read access to certain areas of the
flash memory. To facilitate CRC checks and copying of CLA code, TI provides ROM functions to securely
access those memory areas. To prevent security breaches, interrupts must be disabled before calling
these functions. If a vector fetch occurs in a safe copy or CRC function, the DCSM triggers a reset.
CPU1's security reset (CPU1.SCCRESET) is similar to a CPU1.SYSRS, and CPU2's security reset
(CPU2.SCCRESET) is similar to a CPU2.SYSRS. However, the security reset also resets the debug logic
to deny access to a potential attacker.
After a security reset, the SCCRESETn bit in RESC is set.
2.3.8 Hibernate Reset (HIBRESET)

Hibernate is a chip-level low-power mode that gates power to large portions of the device. Waking up from
hibernate involves a special reset (HIBRESET). This reset is similar to a POR except that the I/O pins
remain isolated and the XRS pin is not toggled. (An external XRS toggle during hibernate will trigger a
HIBRESET). I/O isolation is disabled in software as part of a special boot ROM flow. For more information
on hibernate, refer to Section 2.10.
After a hibernate reset, the HIBRESETn bit in RESC is set. This bit is then cleared by the boot ROM.
2.3.9 Hardware BIST Reset (HWBISTRS)

Each CPU has a Hardware Built-In Self Test (HWBIST) module that tests the functionality of the CPU. At
the end of the test, it resets the CPU to return it to a working state. This reset (HWBISTRS) only affects
the CPU itself. The peripherals and system control remain as previously configured. The CPU state is
restored in software as part of a special boot ROM flow. For more information on the HWBIST flow,
contact your local TI representative.
After a HWBIST reset, the HWBISTn bit in RESC is set. This bit is then cleared by the boot ROM.
2.3.10 Test Reset (TRST)

The ICEPick debug module and associated JTAG logic has its own reset (TRST) which is controlled by a
dedicated pin. This reset is normally active unless the user connects a debugger to the device. For more
information on the debug module, see the TI Processors Wiki page on ICEPick:
http://processors.wiki.ti.com/index.php/ICEPICK.
The TRST does not have a normal RESC bit, but the TRSTn_pin_status bit indicates the state of the pin.
2.4 Peripheral Interrupts

This section explains the peripheral interrupt handling on the device. Non-maskable interrupts are covered
in Section 2.5. Software interrupts and emulation interrupts are not covered in this document. For
information on those, see the TMS320C28x CPU and Instruction Set Reference Guide (SPRU430).

Peripheral Interrupts www.ti.com
2.4.1 Interrupt Concepts

An interrupt is a signal that causes the CPU to pause its current execution and branch to a different piece
of code known as an interrupt service routine (ISR). This is a useful mechanism for handling peripheral
events, and involves less CPU overhead or program complexity than register polling. However, because
interrupts are asynchronous to the program flow, care must be taken to avoid conflicts over resources that
are accessed both in interrupts and in the main program code.
Interrupts propagate to the CPU through a series of flag and enable registers. The flag registers store the
interrupt until it is processed. The enable registers block the propagation of the interrupt. When an
interrupt signal reaches the CPU, the CPU fetches the appropriate ISR address from a list called the
vector table.
2.4.2 Interrupt Architecture

The C28x CPU has fourteen peripheral interrupt lines. Two of them (INT13 and INT14) are connected
directly to CPU timers 1 and 2, respectively. The remaining twelve are connected to peripheral interrupt
signals through the enhanced Peripheral Interrupt Expansion module (ePIE, or PIE as a shortened
version). The PIE multiplexes up to sixteen peripheral interrupts into each CPU interrupt line. It also
expands the vector table to allow each interrupt to have its own ISR. This allows the CPU to support a
large number of peripherals.
An interrupt path is divided into three stages – the peripheral, the PIE, and the CPU. Each stage has its
own enable and flag registers. This system allows the CPU to handle one interrupt while others are
pending, implement and prioritize nested interrupts in software, and disable interrupts during certain
critical tasks.
Figure 2-1 shows the interrupt architecture for this device.
Figure 2-1. Device Interrupt Architecture

CPU1.TINT0
CPU1.TIMER0
LPM Logic CPU1.LPMINT

CPU1.W AKEINT
CPU1.WD CPU1.NMIWD NMI
CPU1.W DINT
CPU1
INPUTXBAR4 CPU1.XINT1 Control
GPIO0 CPU1. INT1
GPIO1 INPUTXBAR5 CPU1.XINT2 Control to
Input ePIE
... INPUTXBAR6 CPU1.XINT3 Control INT12
... X-BAR CPU1.XINT4 Control
INPUTXBAR13
GPIOx
INPUTXBAR14 CPU1.XINT5 Control
CPU1.TINT1
CPU1.TIMER1 INT13
CPU1.TINT2
CPU1.TIMER2 INT14
IPC
4 Interrupts
Peripherals
CPU1.NMIWD NMI
CPU2
CPU2.XINT1 Control
CPU2.XINT2 Control INT1
CPU2.XINT3 Control CPU2 to
ePIE INT12
CPU2.XINT4 Control
CPU2.XINT5 Control
CPU2.TINT1
CPU2 .LPMINT CPU2.TIMER1 INT13
LPM Logic CPU2.W AKEINT
CPU2.TINT2
CPU2.WD CPU2.TIMER2 INT14
CPU2.W DINT
CPU2.TINT0
CPU2.TIMER0

www.ti.com Peripheral Interrupts
2.4.2.1 Peripheral Stage

Each peripheral has its own unique interrupt configuration, which is described in that peripheral's chapter.
Some peripherals allow multiple events to trigger the same interrupt signal. For example, a
communications peripheral might use the same interrupt to indicate that data has been received or that
there has been a transmission error. The cause of the interrupt can be determined by reading the
peripheral's status register. Often, the bits in the status register must be cleared manually before another
interrupt will be generated.
2.4.2.2 PIE Stage

The PIE provides individual flag and enable register bits for each of the peripheral interrupt signals, which
are sometimes called PIE channels. These channels are grouped according to their associated CPU
interrupt. Each PIE group has one 16-bit enable register (PIEIERx), one 16-bit flag register (PIEIFRx), and
one bit in the PIE acknowledge register (PIEACK). The PIEACK register bit acts as a common interrupt
mask for the entire PIE group.
When the CPU receives an interrupt, it fetches the address of the ISR from the PIE. The PIE returns the
vector for the lowest-numbered channel in the group that is both flagged and enabled. This gives lower-
numbered interrupts a higher priority when multiple interrupts are pending.
If no interrupt is both flagged and enabled, the PIE returns the vector for channel 1. This condition will not
happen unless software changes the state of the PIE while an interrupt is propagating. Section 2.4.4
contains procedures for safely modifying the PIE configuration once interrupts have been enabled.
2.4.2.3 CPU Stage

Like the PIE, the CPU provides flag and enable register bits for each of its interrupts. There is one enable
register (IER) and one flag register (IFR), both of which are internal CPU registers. There is also a global
interrupt mask, which is controlled by the INTM bit in the ST1 register. This mask can be set and cleared
using the CPU's SETC instruction. In C code, controlSUITE's DINT and EINT macros can be used for this
purpose.
Writes to IER and INTM are atomic operations. In particular, if INTM is cleared, the next instruction in the
pipeline will run with interrupts disabled. No software delays are needed.
2.4.2.4 Dual-CPU Interrupt Handling

Each CPU has its own PIE. Both PIEs must be configured independently.
Some interrupts come from shared peripherals that can be owned by either CPU, such as the ADCs and
SPIs. These interrupts are sent to both PIEs regardless of the peripheral's ownership. Thus, a peripheral
owned by one CPU can cause an interrupt on the other CPU if that interrupt is enabled in the other CPU's
PIE.
2.4.3 Interrupt Entry Sequence

Figure 2-2 shows how peripheral interrupts propagate to the CPU.

Figure 2-2. Interrupt Propagation Path

PIEIERx.1
0
Peripheral
PIEIFRx.1 1
Interrupt
Latch
A
PIEIERx.2
Peripheral 0 Set
PIEIFRx.2 1 PIEACK.x IER.x ST1.INTM
Interrupt
Latch 1 0 1
CPU
B 0 IFR.x 1 0
Interrupt
Latch
Logic
PIEIERx.16
0
Peripheral
PIEIFRx.16 1
Interrupt
Latch
P
When a peripheral generates an interrupt (on PIE group x, channel y), it triggers the following sequence of
events:
1. The interrupt is latched in PIEIFRx.y.
2. If PIEIERx.y is set, the interrupt propagates.
3. If PIEACK.x is clear, the interrupt propagates and PIEACK.x is set.
4. The interrupt is latched in IFR.x.
5. If IER.x is set, the interrupt propagates.
6. If INTM is clear, the CPU receives the interrupt.
7. Any instructions in the D2 or later stage of the pipeline are run to completion. Instructions in earlier
stages are flushed.
8. The CPU saves its context on the stack.
9. IFR.x and IER.x are cleared. INTM is set. EALLOW is cleared.
10. The CPU fetches the ISR vector from the PIE. PIEIFRx.y is cleared.
11. The CPU branches to the ISR.
The interrupt latency is the time between PIEIFRx.y latching the interrupt and the first ISR instruction
entering the execution stage of the CPU pipeline. The minimum interrupt latency is 14 SYSCLK cycles.
Wait states on the ISR or stack memories will add to the latency. External interrupts add a minimum of two
SYSCLK cycles for GPIO synchronization plus extra time for input qualification (if used). Loops created
using the C28x RPT instruction cannot be interrupted.
2.4.4 Configuring and Using Interrupts

At power-up, no interrupts are enabled by default. The PIEIER and IER registers are cleared and INTM is
set. The application code is responsible for configuring and enabling all peripheral interrupts.
2.4.4.1 Enabling Interrupts

To enable a peripheral interrupt, perform the following steps:
1. Disable interrupts globally (DINT or SETC INTM).
2. Enable the PIE by setting the ENPIE bit of the PIECTRL register.
3. Write the ISR vector for each interrupt to the appropriate location in the PIE vector table, which can be
found in Table 2-2.
4. Set the appropriate PIEIERx bit for each interrupt. The PIE group and channel assignments can be

found in Table 2-2.

5. Set the CPU IER bit for any PIE group containing enabled interrupts.
6. Enable the interrupt in the peripheral.
7. Enable interrupts globally (EINT or CLRC INTM).
Step 4 does not apply to the Timer1 and Timer2 interrupts, which connect directly to the CPU.
2.4.4.2 Handling Interrupts

ISRs are similar to normal functions, but must do the following:
1. Save and restore the state of certain CPU registers (if used).
2. Clear the PIEACK bit for the interrupt group.
3. Return using the IRET instruction.
Requirements 1 and 3 are handled automatically by the TMS320C28x C compiler if the function is defined
using the __interrupt keyword. For information on this keyword, see the Keywords section of the
TMS320C28x Optimizing C/C++ Compiler v6.2.4 User's Guide (SPRU514). For information on writing
assembly code to handle interrupts, see the Standard Operation for Maskable Interrupts section of the
TMS320C28x CPU and Instruction Set Reference Guide (SPRU430).
The PIEACK bit for the interrupt group must be cleared manually in user code. This is normally done at
the end of the ISR. If the PIEACK bit is not cleared, the CPU will not receive any further interrupts from
that group. This does not apply to the Timer1 and Timer2 interrupts, which do not go through the PIE.
2.4.4.3 Disabling Interrupts

To disable all interrupts, set the CPU's global interrupt mask via DINT or SETC INTM. It is not necessary
to add NOPs after setting INTM or modifying IER – the next instruction will execute with interrupts
disabled.
Individual interrupts can be disabled using the PIEIERx registers, but care must be taken to avoid race
conditions. If an interrupt signal is already propagating when the PIEIER write completes, it may reach the
CPU and trigger a spurious interrupt condition. To avoid this, use the following procedure:
2. Clear the PIEIER bit for the interrupt.
3. Wait 5 cycles to make sure that any propagating interrupt has reached the CPU IFR register.
4. Clear the CPU IFR bit for the interrupt's PIE group.
5. Clear the PIEACK bit for the interrupt's PIE group.
Interrupt groups can be disabled using the CPU IER register. This cannot cause a race condition, so no
special procedure is needed.
PIEIFR bits must never be cleared in software since the read/modify/write operation may cause incoming
interrupts to be lost. The only safe way to clear a PIEIFR bit is to have the CPU take the interrupt. The
following procedure can be used to bypass the normal ISR:
2. Modify the PIE vector table to map the PIEIFR bit's interrupt vector to an empty ISR. This ISR will only
contain a return from interrupt instruction (IRET).
3. Disable the interrupt in the peripheral registers.
5. Wait for the pending interrupt to be serviced by the empty ISR.
6. Disable interrupts globally.
7. Modify the PIE vector table to map the interrupt vector back to its original ISR.
8. Clear the PIEACK bit for the interrupt's PIE group.
9. Enable interrupts globally.

2.4.4.4 Nesting Interrupts

By default, interrupts do not nest. It is possible to nest and prioritize interrupts via software control of the
IER and PIEIERx registers. Documentation and example code can be found in controlSUITE and on the TI
Processors wiki:
http://processors.wiki.ti.com/index.php/Interrupt_Nesting_on_C28x

2.4.5 PIE Channel Mapping

Table 2-2 shows the PIE group and channel assignments for each peripheral interrupt. Each row is a group, and each column is a channel within
that group. When multiple interrupts are pending, the lowest-numbered channel is the lowest-numbered group is serviced first. Thus, the interrupts
at the top of the table have the highest priority, and the interrupts at the bottom have the lowest priority.
Table 2-2. PIE Channel Mapping

INTx.1 INTx.2 INTx.3 INTx.4 INTx.5 INTx.6 INTx.7 INTx.8 INTx.9 INTx.10 INTx.11 INTx.12 INTx.13 INTx.14 INTx.15 INTx.16
INT1.y ADCA1 ADCB1 ADCC1 XINT1 XINT2 ADCD1 TIMER0 WAKE - - - - IPC0 IPC1 IPC2 IPC3
INT2.y EPWM1_ EPWM2_ EPWM3_ EPWM4_ EPWM5_ EPWM6_ EPWM7_ EPWM8_ EPWM9_ EPWM10_ EPWM11_ EPWM12_ - - - -
TZ TZ TZ TZ TZ TZ TZ TZ TZ TZ TZ TZ
INT3.y EPWM1 EPWM2 EPWM3 EPWM4 EPWM5 EPWM6 EPWM7 EPWM8 EPWM9 EPWM10 EPWM11 EPWM12 - - - -
INT4.y ECAP1 ECAP2 ECAP3 ECAP4 ECAP5 ECAP6 - - - - - - - - - -
INT5.y EQEP1 EQEP2 EQEP3 - - - - - SD1 SD2 - - - - - -
INT6.y SPIA_RX SPIA_TX SPIB_RX SPIB_TX MCBSPA_ MCBSPA_ MCBSPB_ MCBSPB_ SPIC_RX SPIC_TX - - - - - -
RX TX RX TX
INT7.y DMA_CH1 DMA_CH2 DMA_CH3 DMA_CH4 DMA_CH5 DMA_CH6 - - - - - - - - - -
INT8.y I2CA I2CA_ I2CB I2CB_ SCIC_RX SCIC_TX SCID_RX SCID_TX - - - - - - UPPA -
FIFO FIFO (CPU1 only)
INT9.y SCIA_RX SCIA_TX SCIB_RX SCIB_TX CANA_0 CANA_1 CANB_0 CANB_1 - - - - - - USBA -
(CPU1 only)
INT10.y ADCA_ ADCA2 ADCA3 ADCA4 ADCB_EVT ADCB2 ADCB3 ADCB4 ADCC_EVT ADCC2 ADCC3 ADCC4 ADCD_EVT ADCD2 ADCD3 ADCD4
EVT
INT11.y CLA1_1 CLA1_2 CLA1_3 CLA1_4 CLA1_5 CLA1_6 CLA1_7 CLA1_8 - - - - - - - -
INT12.y XINT3 XINT4 XINT5 - - VCU FPU_OVER FPU_ EMIF_ RAM_COR FLASH_CO RAM_ACCE SYS_PLL_ AUX_PLL_ CLA OVER CLA
FLOW UNDER ERROR RECTABLE RRECTABL SS_VIOLAT SLIP SLIP FLOW UNDER
FLOW _ERROR E_ERROR ION FLOW
Note: Cells marked "-" are Reserved

2.4.6 Vector Tables

Table 2-3 shows the CPU interrupt vector table. The vectors for INT1 – INT12 are not used in this device.
The reset vector is fetched from the boot ROM instead of from this table.
Table 2-3. CPU Interrupt Vectors

Name Vector ID Address Size (x16) Description Core priority ePIE group
Priority
Reset 0 0x0000 0D00 2 Reset is always fetched from 1 (Highest) -
location 0x003F_FFC0 in Boot
ROM
INT1 1 0x0000 0D02 2 Not used. See PIE Group 1 5 -
INT5 5 0x0000 0D0A 2 Not used. See PIE Group 5 9 -
INT6 6 0x0000 0D0C 2 Not used. See PIE Group 6 10 -
INT7 7 0x0000 0D0E 2 Not used. See PIE Group 7 11 -
INT13 13 0x0000 0D1A 2 CPU TIMER1 Interrupt 17 -
INT14 14 0x0000 0D1C 2 CPU TIMER2 Interrupt (for 18 -
TI/RTOS use)
DATALOG 15 0x0000 0D1E 2 CPU Data Logging Interrupt 19 (lowest) -
RTOSINT 16 0x0000 0D20 2 CPU Real-Time OS Interrupt 4 -
EMUINT 17 0x0000 0D22 2 CPU Emulation Interrupt 2 -
NMI 18 0x0000 0D24 2 Non-Maskable Interrupt 3 -
ILLEGAL 19 0x0000 0D26 2 Illegal Instruction (ITRAP) - -
USER 1 20 0x0000 0D28 2 User-Defined Trap - -
USER 2 21 0x0000 0D2A 2 User-Defined Trap - -
USER 3 22 0x0000 0D2C 2 User-Defined Trap - -
USER 4 23 0x0000 0D2E 2 User-Defined Trap - -
USER 10 29 0x0000 0D3A 2 User-Defined Trap - -
USER 11 30 0x0000 0D3C 2 User-Defined Trap - -
USER 12 31 0x0000 0D3E 2 User-Defined Trap - -

Table 2-4 shows the Pie vector table.
Table 2-4. PIE Interrupt Vectors

Priority
PIE Group 1 Vectors - Muxed into CPU INT1
INT1.1 32 0x0000 0D40 2 ADCA1 interrupt 5 1 (Highest)
INT1.2 33 0x0000 0D42 2 ADCB1 interrupt 5 2
INT1.3 34 0x0000 0D44 2 ADCC1 interrupt 5 3
INT1.4 35 0x0000 0D46 2 XINT1 interrupt 5 4
INT1.5 36 0x0000 0D48 2 XINT2 interrupt 5 5
INT1.6 37 0x0000 0D4A 2 ADCD1 interrupt 5 6
INT1.7 38 0x0000 0D4C 2 TIMER0 interrupt 5 7
INT1.8 39 0x0000 0D4E 2 WAKE interrupt 5 8
INT1.9 128 0x0000 0E00 2 Reserved 5 9
INT1.10 129 0x0000 0E02 2 Reserved 5 10
INT1.11 130 0x0000 0E04 2 Reserved 5 11
INT1.12 131 0x0000 0E06 2 Reserved 5 12
INT1.13 132 0x0000 0E08 2 IPC1 interrupt 5 13
INT1.14 133 0x0000 0E0A 2 IPC2 interrupt 5 14
INT1.15 134 0x0000 0E0C 2 IPC3 interrupt 5 15
INT1.16 135 0x0000 0E0E 2 IPC4 interrupt 5 16 (Lowest)
INT2.1 40 0x0000 0D50 2 EPWM1_TZ 6 1 (Highest)
interrupt
INT2.2 41 0x0000 0D52 2 EPWM2_TZ 6 2
interrupt
INT2.3 42 0x0000 0D54 2 EPWM3_TZ 6 3
interrupt
INT2.4 43 0x0000 0D56 2 EPWM4_TZ 6 4
interrupt
INT2.5 44 0x0000 0D58 2 EPWM5_TZ 6 5
interrupt
INT2.6 45 0x0000 0D5A 2 EPWM6_TZ 6 6
interrupt
INT2.7 46 0x0000 0D5C 2 EPWM7_TZ 6 7
interrupt
INT2.8 47 0x0000 0D5E 2 EPWM8_TZ 6 8
interrupt
INT2.9 136 0x0000 0E10 2 EPWM9_TZ 6 9
interrupt
INT2.10 137 0x0000 0E12 2 EPWM10_TZ 6 10
interrupt
INT2.11 138 0x0000 0E14 2 EPWM11_TZ 6 11
interrupt
INT2.12 139 0x0000 0E16 2 EPWM12_TZ 6 12
interrupt
INT2.13 140 0x0000 0E18 2 Reserved 6 13
INT2.14 141 0x0000 0E1A 2 Reserved 6 14
INT2.15 142 0x0000 0E1C 2 Reserved 6 15
INT2.16 143 0x0000 0E1E 2 Reserved 6 16 (Lowest)
INT3.1 48 0x0000 0D60 2 EPWM1 interrupt 7 1 (Highest)
INT3.2 49 0x0000 0D62 2 EPWM2 interrupt 7 2

Table 2-4. PIE Interrupt Vectors (continued)

Priority
INT3.6 53 0x0000 0D6A 2 EPWM6 interrupt 7 6
INT3.7 54 0x0000 0D6C 2 EPWM7 interrupt 7 7
INT3.8 55 0x0000 0D6E 2 EPWM8 interrupt 7 8
INT3.9 144 0x0000 0E20 2 EPWM9 interrupt 7 9
INT3.10 145 0x0000 0E22 2 EPWM10 7 10
interrupt
INT3.11 146 0x0000 0E24 2 EPWM11 7 11
interrupt
INT3.12 147 0x0000 0E26 2 EPWM12 7 12
interrupt
INT3.13 148 0x0000 0E28 2 Reserved 7 13
INT3.14 149 0x0000 0E2A 2 Reserved 7 14
INT3.15 150 0x0000 0E2C 2 Reserved 7 15
INT4.1 56 0x0000 0D70 2 ECAP1 interrupt 8 1 (Highest)
INT4.2 57 0x0000 0D72 2 ECAP2 interrupt 8 2
INT4.6 61 0x0000 0D7A 2 ECAP6 interrupt 8 6
INT4.7 62 0x0000 0D7C 2 Reserved 8 7
INT4.8 63 0x0000 0D7E 2 Reserved 8 8
INT4.9 152 0x0000 0E30 2 Reserved 8 9
INT4.10 153 0x0000 0E32 2 Reserved 8 10
INT4.11 154 0x0000 0E34 2 Reserved 8 11
INT4.12 155 0x0000 0E36 2 Reserved 8 12
INT4.13 156 0x0000 0E38 2 Reserved 8 13
INT4.14 157 0x0000 0E3A 2 Reserved 8 14
INT4.15 158 0x0000 0E3C 2 Reserved 8 15
INT5.1 64 0x0000 0D80 2 EQEP1 interrupt 9 1 (Highest)
INT5.2 65 0x0000 0D82 2 EQEP2 interrupt 9 2
INT5.3 66 0x0000 0D84 2 EQEP3 interrupt 9 3
INT5.4 67 0x0000 0D86 2 Reserved 9 4
INT5.5 68 0x0000 0D88 2 Reserved 9 5
INT5.6 69 0x0000 0D8A 2 Reserved 9 6
INT5.7 70 0x0000 0D8C 2 Reserved 9 7
INT5.8 71 0x0000 0D8E 2 Reserved 9 8
INT5.9 160 0x0000 0E40 2 SD1 interrupt 9 9
INT5.10 161 0x0000 0E42 2 SD2 interrupt 9 10
INT5.11 162 0x0000 0E44 2 Reserved 9 11
INT5.12 163 0x0000 0E46 2 Reserved 9 12
INT5.13 164 0x0000 0E48 2 Reserved 9 13


Priority
INT5.14 165 0x0000 0E4A 2 Reserved 9 14
INT5.15 166 0x0000 0E4C 2 Reserved 9 15
INT6.1 72 0x0000 0D90 2 SPIA_RX 10 1 (Highest)
interrupt
INT6.2 73 0x0000 0D92 2 SPIA_TX 10 2
interrupt
INT6.3 74 0x0000 0D94 2 SPIB_RX 10 3
interrupt
INT6.4 75 0x0000 0D96 2 SPIB_TX 10 4
interrupt
INT6.5 76 0x0000 0D98 2 MCBSPA_RX 10 5
interrupt
INT6.6 77 0x0000 0D9A 2 MCBSPA_TX 10 6
interrupt
INT6.7 78 0x0000 0D9C 2 MCBSPB_RX 10 7
interrupt
INT6.8 79 0x0000 0D9E 2 MCBSPB_TX 10 8
interrupt
INT6.9 168 0x0000 0E50 2 SPIC_RX 10 9
interrupt
INT6.10 169 0x0000 0E52 2 SPIC_TX 10 10
interrupt
INT6.11 170 0x0000 0E54 2 Reserved 10 11
INT6.12 171 0x0000 0E56 2 Reserved 10 12
INT6.13 172 0x0000 0E58 2 Reserved 10 13
INT6.14 173 0x0000 0E5A 2 Reserved 10 14
INT6.15 174 0x0000 0E5C 2 Reserved 10 15
INT7.1 80 0x0000 0DA0 2 DMA_CH1 11 1 (Highest)
interrupt
INT7.2 81 0x0000 0DA2 2 DMA_CH2 11 2
interrupt
INT7.3 82 0x0000 0DA4 2 DMA_CH3 11 3
interrupt
INT7.4 83 0x0000 0DA6 2 DMA_CH4 11 4
interrupt
INT7.5 84 0x0000 0DA8 2 DMA_CH5 11 5
interrupt
INT7.6 85 0x0000 0DAA 2 DMA_CH6 11 6
interrupt
INT7.7 86 0x0000 0DAC 2 Reserved 11 7
INT7.8 87 0x0000 0DAE 2 Reserved 11 8
INT7.9 176 0x0000 0E60 2 Reserved 11 9
INT7.10 177 0x0000 0E62 2 Reserved 11 10
INT7.11 178 0x0000 0E64 2 Reserved 11 11
INT7.12 179 0x0000 0E66 2 Reserved 11 12
INT7.13 180 0x0000 0E68 2 Reserved 11 13
INT7.14 181 0x0000 0E6A 2 Reserved 11 14
INT7.15 182 0x0000 0E6C 2 Reserved 11 15


Priority
INT8.1 88 0x0000 0DB0 2 I2CA interrupt 12 1 (Highest)
INT8.2 89 0x0000 0DB2 2 I2CA_FIFO 12 2
interrupt
INT8.3 90 0x0000 0DB4 2 I2CB interrupt 12 3
INT8.4 91 0x0000 0DB6 2 I2CB_FIFO 12 4
interrupt
INT8.5 92 0x0000 0DB8 2 SCIC_RX 12 5
interrupt
INT8.6 93 0x0000 0DBA 2 SCIC_TX 12 6
interrupt
INT8.7 94 0x0000 0DBC 2 SCID_RX 12 7
interrupt
INT8.8 95 0x0000 0DBE 2 SCID_TX 12 8
interrupt
INT8.9 184 0x0000 0E70 2 Reserved 12 9
INT8.10 185 0x0000 0E72 2 Reserved 12 10
INT8.11 186 0x0000 0E74 2 Reserved 12 11
INT8.12 187 0x0000 0E76 2 Reserved 12 12
INT8.13 188 0x0000 0E78 2 Reserved 12 13
INT8.14 189 0x0000 0E7A 2 Reserved 12 14
INT8.15 190 0x0000 0E7C 2 UPPA interrupt 12 15
(CPU1 only)
INT9.1 96 0x0000 0DC0 2 SCIA_RX 13 1 (Highest)
interrupt
INT9.2 97 0x0000 0DC2 2 SCIA_TX 13 2
interrupt
INT9.3 98 0x0000 0DC4 2 SCIB_RX 13 3
interrupt
INT9.4 99 0x0000 0DC6 2 SCIB_TX 13 4
interrupt
INT9.5 100 0x0000 0DC8 2 CANA interrupt 0 13 5
INT9.6 101 0x0000 0DCA 2 CANA interrupt 1 13 6
INT9.7 102 0x0000 0DCC 2 CANB interrupt 0 13 7
INT9.8 103 0x0000 0DCE 2 CANB interrupt 1 13 8
INT9.9 192 0x0000 0E80 2 Reserved 13 9
INT9.10 193 0x0000 0E82 2 Reserved 13 10
INT9.11 194 0x0000 0E84 2 Reserved 13 11
INT9.12 195 0x0000 0E86 2 Reserved 13 12
INT9.13 196 0x0000 0E88 2 Reserved 13 13
INT9.14 197 0x0000 0E8A 2 Reserved 13 14
INT9.15 198 0x0000 0E8C 2 USBA interrupt 13 15
(CPU1 only)
INT10.1 104 0x0000 0DD0 2 ADCA_EVT 14 1 (Highest)
interrupt
INT10.2 105 0x0000 0DD2 2 ADCA2 interrupt 14 2


Priority
INT10.5 108 0x0000 0DD8 2 ADCB_EVT 14 5
interrupt
INT10.6 109 0x0000 0DDA 2 ADCB2 interrupt 14 6
INT10.7 110 0x0000 0DDC 2 ADCB3 interrupt 14 7
INT10.8 111 0x0000 0DDE 2 ADCB4 interrupt 14 8
INT10.9 200 0x0000 0E90 2 ADCC_EVT 14 9
interrupt
INT10.10 201 0x0000 0E92 2 ADCC2 interrupt 14 10
INT10.13 204 0x0000 0E98 2 ADCD_EVT 14 13
interrupt
INT10.14 205 0x0000 0E9A 2 ADCD2 interrupt 14 14
INT10.15 206 0x0000 0E9C 2 ADCD3 interrupt 14 15
INT10.16 207 0x0000 0E9E 2 ADCD4 interrupt 14 16 (Lowest)
INT11.1 112 0x0000 0DE0 2 CLA1_1 interrupt 15 1 (Highest)
INT11.2 113 0x0000 0DE2 2 CLA1_2 interrupt 15 2
INT11.6 117 0x0000 0DEA 2 CLA1_6 interrupt 15 6
INT11.7 118 0x0000 0DEC 2 CLA1_7 interrupt 15 7
INT11.8 119 0x0000 0DEE 2 CLA1_8 interrupt 15 8
INT11.9 208 0x0000 0EA0 2 Reserved 15 9
INT11.10 209 0x0000 0EA2 2 Reserved 15 10
INT11.11 210 0x0000 0EA4 2 Reserved 15 11
INT11.12 211 0x0000 0EA6 2 Reserved 15 12
INT11.13 212 0x0000 0EA8 2 Reserved 15 13
INT11.14 213 0x0000 0EAA 2 Reserved 15 14
INT11.15 214 0x0000 0EAC 2 Reserved 15 15
INT11.16 215 0x0000 0EAE 2 Reserved 15 16 (Lowest)
INT12.1 120 0x0000 0DF0 2 XINT3 interrupt 16 1 (Highest)
INT12.2 121 0x0000 0DF2 2 XINT4 interrupt 16 2
INT12.3 122 0x0000 0DF4 2 XINT5 interrupt 16 3
INT12.4 123 0x0000 0DF6 2 Reserved 16 4
INT12.5 124 0x0000 0DF8 2 Reserved 16 5
INT12.6 125 0x0000 0DFA 2 VCU interrupt 16 6
INT12.7 126 0x0000 0DFC 2 FPU_OVERFLO 16 7
W interrupt
INT12.8 127 0x0000 0DFE 2 FPU_UNDERFL 16 8
OW interrupt
INT12.9 216 0x0000 0EB0 2 EMIF_ERROR 16 9
interrupt

Exceptions and Non-Maskable Interrupts www.ti.com

Priority
INT12.10 217 0x0000 0EB2 2 RAM_CORREC 16 10
TABLE_ERROR
interrupt
INT12.11 218 0x0000 0EB4 2 FLASH_CORRE 16 11
CTABLE_ERRO
R interrupt
INT12.12 219 0x0000 0EB6 2 RAM_ACCESS_ 16 12
VIOLATION
interrupt
INT12.13 220 0x0000 0EB8 2 SYS_PLL_SLIP 16 13
interrupt
INT12.14 221 0x0000 0EBA 2 AUX_PLL_SLIP 16 14
interrupt
INT12.15 222 0x0000 0EBC 2 CLA_OVERFLO 16 15
W interrupt
INT12.16 223 0x0000 0EBE 2 CLA_UNDERFL 16 16 (Lowest)
OW interrupt
2.5 Exceptions and Non-Maskable Interrupts

This section describes system-level error conditions that can trigger a non-maskable interrupt (NMI). The
interrupt allows the application to respond to the error.
2.5.1 Configuring and Using NMIs

Each CPU has its own NMI module. An incoming NMI sets a status bit in the NMIFLG register and starts
the NMI watchdog counter. This counter is clocked by the SYSCLK, and if it reaches the value in the
NMIWDPRD register, it triggers an NMI watchdog reset (NMIWDRS). To prevent this, the NMI handler
must clear the flag bit using the NMIFLGCLR register. Once all flag bits are clear, the NMIINT bit in the
NMIFLG register may also be cleared to allow future NMIs to be taken.
The NMI module is enabled by the boot ROM during the startup process. To respond to NMIs, an NMI
handler vector must be written to the PIE vector table.
2.5.2 Emulation Considerations

The NMI watchdog counter behaves as follows under debug conditions:
CPU Suspended When the CPU is suspended, the NMI watchdog counter will
be suspended.
Run-Free Mode When the CPU is placed in run-free mode, the NMI watchdog
counter will resume operation as normal.
Real-Time Single-Step Mode When the CPU is in real-time single-step mode, the NMI
watchdog counter will be suspended. The counter remains
suspended even within real-time interrupts.
Real-Time Run-Free Mode When the CPU is in real-time run-free mode, the NMI
watchdog counter operates as normal.

www.ti.com Exceptions and Non-Maskable Interrupts
2.5.3 NMI Sources

There are several types of hardware errors that can trigger an NMI. Additional information about the error
is usually available from the module that detects it.
2.5.3.1 Missing Clock Detection

The missing clock detection logic monitors OSCCLK for failure. If the OSCCLK source stops, the PLL is
bypassed, OSCCLK is connected to INTOSC1, and NMIs are fired to both CPUs. For more information on
missing clock detection, see Section 2.6.2.
2.5.3.2 RAM Uncorrectable ECC Error

A single-bit parity error, double-bit ECC data error, or single-bit ECC address error in a RAM read will
trigger an NMI. This applies to CPU, CLA, and DMA reads. Single-bit ECC data errors do not trigger an
NMI, but can optionally trigger a normal peripheral interrupt. For more information on RAM error detection,
see Section 2.11.1.8.
2.5.3.3 Flash Uncorrectable ECC Error

A double-bit ECC data error or single-bit ECC address error in a flash read will trigger an NMI. Single-bit
ECC data errors do not trigger an NMI, but can optionally trigger a normal peripheral interrupt. For more
information on flash error detection, see Section 2.12.10.
2.5.3.4 NMI Vector Fetch Mismatch

Each CPU's Peripheral Interrupt Expansion module (PIE) has redundant vector tables. If a mismatch in
these tables is detected during a vector fetch, a user-specified error handler is run instead of the ISR. If
the vector fetch was caused by an NMI, a second NMI is fired to the other CPU. Mismatches for other
interrupts do not trigger an NMI. For more information about the vector address check, see Section 2.6.4.
2.5.3.5 CPU2 Watchdog or NMI Watchdog Reset

A watchdog reset or NMI watchdog reset on CPU2 will trigger an NMI on CPU1. Since a CPU1 reset also
resets CPU2, this NMI source is not available on CPU2.
Watchdog interrupts do not trigger an NMI.
2.5.4 Illegal Instruction Trap (ITRAP)

If the CPU tries to execute an illegal instruction, it generates a special interrupt called an illegal instruction
trap (ITRAP). This interrupt is non-maskable and has its own vector in the PIE vector table. For more
information about ITRAPs, see the Illegal-Instruction Trap section of the TMS320C28x DSP CPU and
Instruction Set Reference Guide (SPRU430).
NOTE: A RAM fetch access violation will trigger an ITRAP in addition to the normal peripheral
interrupt for RAM access violations. The CPU will handle the ITRAP first.
2.6 Safety Features

This section gives details on features that monitor device operation during run-time to detect any error in
operation.
2.6.1 Write Protection on Registers
2.6.1.1 LOCK Protection on System Configuration Registers

Several system configuration registers are protected from spurious CPU writes by “LOCK” registers. Once
these associated LOCK register bits are set the respective locked registers can no longer be modified by
software. See specific register descriptions for details.

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2.6.1.2 EALLOW Protection

Several control registers are protected from spurious CPU writes by the EALLOW protection mechanism.
The EALLOW bit in status register 1 (ST1) indicates the state of protection as shown in Table 2-5.
Table 2-5. Access to EALLOW-Protected Registers

EALLOW Bit CPU Writes CPU Reads JTAG Writes JTAG Reads
0 Ignored Allowed Allowed (1) Allowed
1 Allowed Allowed Allowed Allowed
(1)
The EALLOW bit is overridden via the JTAG port, allowing full access of protected registers during debug from the Code
Composer Studio interface.
At reset, the EALLOW bit is cleared, enabling EALLOW protection. While protected, all writes to protected
registers by the CPU are ignored and only CPU reads, JTAG reads, and JTAG writes are allowed. If this
bit is set, by executing the EALLOW instruction, the CPU is allowed to write freely to protected registers.
After modifying registers, they can once again be protected by executing the EDIS instruction to clear the
EALLOW bit.
2.6.2 Missing Clock Detection Logic

The missing clock detect (MCD) logic detects OSCCLK failure, using INTOSC1 as the reference clock
source. This circuit only detects complete loss of OSCCLK and doesn’t do any detection of frequency drift
on the OSCCLK.
This circuit monitors the OSCLK (primary clock) using the 10 MHz clock provided by the INTOSC1
(secondary clock) as a backup clock. This circuit functions as below:
1. The primary clock (OSCCLK) clock keeps ticking a 7-bit counter (named as MCDPCNT). This counter
is asynchronously reset with XRS.
2. The secondary clock (INTOSC1) clock keeps ticking a 13-bit counter (named as MCDSCNT). This
counter is asynchronously reset with XRS.
3. Each time MCDPCNT overflows, the MCDSCNT counter is reset. Thus, if OSCCLK is present or not
slower than INTOSC1 by a factor of 64, MCDSCNT will never overflow.
4. If OSCCLK stops for some reason, or is slower than INTOSC1 by at least a factor of 64, the
MCDSCNT will overflow and a missing clock condition will be detected on OSCCLK.
5. The above check is continuously active, unless the MCD is disabled using MCDCR register (by making
the MCLKOFF bit 1)
6. If the circuit ever detects a missing OSCCLK, the following occurs:
• The MCDSTS flag is set
• The MCDSCNT counter is frozen to prevent further missing clock detection
• The CLOCKFAIL signal goes high, which generates TRIP events to PWM modules and fires NMIs
to CPU1.NMIWD and CPU2.NMIWD.
• PLL is forcefully bypassed and OSCCLK is switched to INTOSC1 (after the PLLSYSCLK divider).
PLLMULT is zeroed out automatically in this case.
• While the MCDSTS bit is set, the OSCCLKSRCSEL bits have no effect and OSCCLK is forcefully
connected to INTOSC1.
• PLLRAWCLK going to the system is switched to INTOSC1 automatically
7. If the MCLKCLR bit is written (this is a W=1 bit), MCDSTS bit will be cleared and OSCCLK source will
be decided by the OSCCLKSRCSEL bits. Writing to MCLKCLR will also clear the MCDPCNT and
MCDSCNT counters to allow the circuit re-evaluate missing clock detection. If user wants to lock the
PLL after missing clock detection, he needs to first switch the clock source to INTOSC1 (using
OSCCLKSRCSEL register), do a MCLKCLR and re-lock the PLL.
8. The MCD is enabled at power up. There is no support for missing clock detection if INTOSC2 is failed
from the device power-up.
Figure 2-3 shows the missing clock logic functional flow.

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Figure 2-3. Missing Clock Detection Logic
Secondary Clock CLOCKFAIL

INTOSC1 Missing
Clock INTOSC1
Detect
Primary Clock (MCD)
Logic
Low
OSCCLK Power
INTOSC2 Source Mode
Select OSCCLK Ckt
Ckt
X1/X2
CLKSRCCTL1.OSCCLRSRCSEL /1,
Switch
SYSPLL /2,
Ckt
/4
Mux
PLLRAWCLK ..
(glitch- PLLSYSCLK
/124
PLL Locking free)
/126
Registers Control
Ckt
Clock Dividers
Clock Sources SYSPLLCTL1/2/3,

SYSPLLMULT,
SYSPLLSTS
2.6.3 PLLSLIP Detection

The PLL SLIP detection on this device can detect if the PLL reference clock goes too high or too slow
while PLL is locked. An interrupt to both the CPUs is triggered as shown in the ePIE table in Section 2.4.
Apart from the interrupt to both the CPUs, the PLLSTS.SLIP bit is set for user software to check the error.
The SLIP detection is available on both SYSPLL and AUXPLL.
2.6.4 CPU1 and CPU2 PIE Vector Address Validity Check

The ePIE vector table on each CPU is duplicated into these two parts:
• Main ePIE Vector Table mapped from 0xD00 to 0xEFF in the C28x memory space
• Redundant ePIE Vector Table mapped from 0x1000D00 to 0x1000EFF in the C28x memory space
Following is the behavior of accesses to the ePIE memories:
• Data Writes to Main Vector Table: Writes to both memories
• Data Writes to Redundant Vector Table: Writes only to the Redundant Vector Table
• Vector Fetch: Data from both the vector tables are compared
• Data Read: Can read the Main and Redundant vector table separately
On every vector fetch from the ePIE, a hardware comparison (no cycle penalty is incurred to do the
comparison) of both the vector table outputs is performed and if there is a mismatch between the two
vector table outputs, the following occurs:
1. If the PIEVERRADDR register (default value 0x3F FFFF) is not initialized, the default error handler at
address 0x3FFFBE gets executed.
But, when the PIEVERRADDR register is initialized to the address of the user-defined routine, the
user-defined routine is executed instead of the default error handler.
Note: Each CPU has its own copy of the PIE Vector Fetch Error Handler register
(CPU1.PIEVERRADDR and CPU2.PIEVERRADDR).

Safety Features www.ti.com
2. Hardware also generates EPWM Trip signals which will trip the PWM outputs using TRIPIN15.
3. An NMI to the other CPU is sent if the current mismatch is during a vector fetch. For example, on an
NMI vector fetch error for CPU2, an NMI is also fired to CPU1.NMIWD.
If there is no mismatch, the correct vector is jammed onto the C28 program control.
2.6.5 NMIWDs
Each CPU has user-programmable NMIWD period registers, in which users can set a limit on how much
time they want to allocate for the device to acknowledge the NMI. If the NMI is not acknowledged, it will
cause a device reset.
2.6.6 ECC and Parity Enabled RAMs, Shared RAMs Protection

Each CPU subsystem has different RAM blocks. Few RAM blocks are ECC-enabled and others are parity-
enabled. All single-bit errors in ECC RAM are auto-corrected and an error counter is incremented every
time a single bit error is detected. If the error counter reaches a predefined user configured limit, an
interrupt is generated to the corresponding CPU. Refer to Section 2.11 for more details on RAM errors.
All uncorrectable double-bit errors end up triggering an NMI to corresponding CPUs.
2.6.7 ECC Enabled Flash Memory

When ECC is programmed and enabled, flash single-bit errors are corrected automatically by ECC logic
before giving data to the CPU, but they are not corrected in flash memory. Flash memory will still contain
wrong data until another erase/program operation happens to correct the flash contents. Irrespective of
whether the error interrupt is enabled or disabled, single-bit errors are always corrected before giving data
to the CPU. When the interrupt is disabled, users can check the single-bit error counter register for any
single-bit error occurrences. The error counter stops incrementing once its value is equal to the
threshold+1. It is always suggested to set the threshold register to a non-zero value so that the error
counter can increment. It is up to the user to decide the threshold value at which they have to reprogram
the flash with the correct data.
When ECC is programmed and enabled, flash uncorrectable errors end up triggering an NMI to the
respective CPU. Please refer to Section 2.11 for more details on flash error correction and error catching
mechanisms.
2.6.8 ERRORSTS Pin

The ERRORSTS pin is an ‘always output’ pin and remains low until an error is detected inside the chip.
On an error, the ERRORSTS pin goes high until the corresponding internal error status flag for that error
source is cleared. Figure 2-4 shows the functionality of the ERRORSTS pin.
The ERRORSTS pin will be tri-stated until the chip power rails ramp up to the lower operational limit. As
the ERRORSTS pin is an active-high pin, users who care about the state of this pin during power-up
should connect an external pull-down on this pin.

www.ti.com Clocking
Figure 2-4. ERRORSTS Pin Diagram

CPU1's NMIWD Shadow flags
CPU1.NMIWD.NMISHDFLG.Bit-0
CPU2's NMIWD Shadow flags

ERROR
2.7 Clocking
This section explains the clock sources and clock domains on this device, and how to configure them for
application use. Figure 2-5 provides an overview of the device's clocking system.

Clocking www.ti.com
Figure 2-5. Clocking System

INTOSC1 WDCLK To watchdog timers
CLKSRCCTL1 SYSPLLCTL1 SYSCLKDIVSEL

INTOSC2
SYSCLK To GS RAMs, GPIOs,

OSCCLK PLLSYSCLK
Divider NMIWDs, and IPC
X1 (XTAL) System PLL PLLRAWCLK
CPU1.SYSCLK CPU1 CPU1.CPUCLK To local memories
CPU2.SYSCLK CPU2 CPU2.CPUCLK To local memories
CPU1.SYSCLK To ePIEs, LS RAMs,

CLA message RAMs,
CPU2.SYSCLK and DCSMs
One per SYSCLK peripheral
CPU1.PCLKCRx CPUSELx
PERx.SYSCLK To peripherals
CPU2.PCLKCRx
One per LSPCLK peripheral

LOSPCP
CPU1.PCLKCRx CPUSELx
LSP To SCIs, SPIs, and

PERx.LSPCLK
Divider McBSPs
CPU2.PCLKCRx
One per ePWM
EPWMCLKDIV CPU1.PCLKCRx CPUSELx
PLLSYSCLK /1
EPWMCLK To ePWMs
/2
CPU2.PCLKCRx
HRPWM
CPU1.PCLKCRx
HRPWMCLK To HRPWM Registers
One per CAN module
CPUSELx
CLKSRCCTL2
CAN Bit Clock To CANs

AUXCLKIN
CLKSRCCTL2 AUXPLLCTL1 AUXCLKDIVSEL
AUXCLK
AUXOSCCLK AUXPLLCLK To USB bit clock
Divider
Auxiliary PLL AUXPLLRAWCLK

www.ti.com Clocking
Note: The default/2 divider for ePWMs and EMIFs is not shown.
2.7.1 Clock Sources

All of the clocks in the device are derived from one of four clock sources.
2.7.1.1 Primary Internal Oscillator (INTOSC2)

At power-up, the device is clocked from an on-chip 10 MHz oscillator (INTOSC2). INTOSC2 is the primary
internal clock source, and is the default system clock at reset. It is used to run the boot ROM and can be
used as the system clock source for the application. Note that INTOSC2's frequency tolerance is too loose
to meet the timing requirements for CAN and USB, so an external clock must be used to support those
features.
2.7.1.2 Backup Internal Oscillator (INTOSC1)

The device also includes a redundant on-chip 10 MHz oscillator (INTOSC1). INTOSC1 is a backup clock
source that normally only clocks the watchdog timers and missing clock detection circuit (MCD). If MCD is
enabled and a missing system clock is detected, the system PLL is bypassed and all system clocks are
connected to INTOSC1 automatically. INTOSC1 may also be manually selected as the system and
auxiliary clock source for debug purposes.
2.7.1.3 External Oscillator (XTAL)

The dedicated X1 and X2 pins support an external clock source (XTAL), which can be used as the main
system and auxiliary clock source. Frequency limits and timing requirements can be found in the device
datasheet. Three types of external clock sources are supported:
• A single-ended 3.3V external clock. The clock signal should be connected to X1 while X2 is left
unconnected, as shown in Figure 2-6.
Figure 2-6. Single-ended 3.3V External Clock
VDDOSC X1 VSSOSC X2
3.3V NC
3.3V
Clk
VDD OUT
GND
3.3V Oscillator
• An external crystal. The crystal should be connected across X1 and X2 with its load capacitors
connected to VSSOSC as shown in Figure 2-7.

Clocking www.ti.com
Figure 2-7. External Crystal
VDDOSC X1 VSSOSC X2
3.3V
Crystal
RD CL2 CL1
• An external resonator. The resonator should be connected across X1 and X2 with its ground
connected to VSSOSC as shown in Figure 2-8.
Figure 2-8. External Resonator
VDDOSC X1 VSSOSC X2
3.3V
Resonator
2.7.1.4 Auxiliary Clock Input (AUXCLKIN)

An additional external clock source is supported on GPIO133 (AUXCLKIN). This must be a single-ended
3.3V external clock. It can be used as the source for the USB and CAN bit clocks. Frequency limits and
timing requirements can be found in the device datasheet. The external clock should be connected directly
to the GPIO133 pin, as shown in Figure 2-9.
Figure 2-9. AUXCLKIN

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2.7.2 Derived Clocks

The clock sources discussed in the previous section can be multiplied (via PLL) and divided down to
produce the desired clock frequencies for the application. This process produces a set of derived clocks,
which are described in this section.
2.7.2.1 Oscillator Clock (OSCCLK)

One of INTOSC2, XTAL, or INTOSC1 must be chosen to be the master reference clock (OSCCLK) for the
CPU and most of the peripherals. OSCCLK may be used directly or fed through the system PLL to reach
a higher frequency. At reset, OSCCLK is the default system clock, and is connected to INTOSC2.
2.7.2.2 System PLL Output Clock (PLLRAWCLK)

The system PLL allows the device to run at its maximum rated operating frequency, and in most
applications will generate the main system clock. This PLL uses OSCCLK as a reference, and features a
fractional multiplier and slip detection. For configuration instructions, see Section 2.7.6.
2.7.2.3 Auxiliary Oscillator Clock (AUXOSCCLK)

One of INTOSC2, XTAL, or AUXCLKIN may be chosen to be the auxiliary reference clock (AUXOSCCLK)
for the USB module. (This selection does not affect the CAN bit clock, which uses AUXCLKIN directly).
AUXOSCCLK may be used directly or fed through the auxiliary PLL to reach a higher frequency. At reset,
AUXOSCCLK is connected to INTOSC2, but only an external oscillator can meet the USB timing
requirements.
2.7.2.4 Auxiliary PLL Output Clock (AUXPLLRAWCLK)

The auxiliary PLL is used to generate a 60 MHz clock for the USB module. This PLL uses AUXOSCCLK
as a reference, and features a fractional multiplier and slip detection. For configuration instructions, see
Section 2.7.6.
2.7.3 Device Clock Domains

The device clock domains feed the clock inputs of the various modules in the device. They are connected
to the derived clocks, either directly or through an additional divider.
2.7.3.1 System Clock (PLLSYSCLK)

The system control registers, GS RAMs, IPC module, GPIO qualification, and NMI watchdog timers have
their own clock domain (PLLSYSCLK). Despite the name, PLLSYSCLK may be connected to the system
PLL (PLLRAWCLK) or to OSCCLK. The chosen clock source is run through a frequency divider, which is
configured via the SYSCLKDIVSEL register. PLLSYSCLK is gated in HALT mode.
2.7.3.2 CPU Clock (CPUCLK)

Each CPU has its own clock (CPU1.CPUCLK and CPU2.CPUCLK) which is used to clock the CPU, its
coprocessors, its private RAMs (M0, M1, D0, and D1), and its boot ROM and flash wrapper. This clock is
identical to PLLSYSCLK, but is gated when the CPU enters IDLE, STANDBY, or HALT mode.
2.7.3.3 CPU Subsystem Clock (SYSCLK and PERx.SYSCLK)

Each CPU provides a clock (CPU1.SYSCLK and CPU2.SYSCLK) to its CLA, DMA, and most owned
peripherals. This clock is identical to PLLSYSCLK, but is gated when the CPU enters STANDBY or HALT
mode.
Each peripheral clock can be connected to either CPU1.SYSCLK or CPU2.SYSCLK. This selection is
made by CPU1 via the CPUSELx registers. Each peripheral clock also has its own independent clock
gating which is controlled by the CPU's PCLKCRx registers. By default, the ePWM, EMIF1, and EMIF2
clocks each have an additional /2 divider, which is required to support CPU frequencies over 100 MHz. At
slower CPU frequencies, these dividers can be disabled via the PERCLKDIVSEL register.

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2.7.3.4 Low-Speed Peripheral Clock (LSPCLK and PERx.LSPCLK)

The SCI, SPI, and McBSP modules can communicate at bit rates that are much slower than the CPU
frequency. These modules are connected to a shared clock divider, which generates a low-speed
peripheral clock (LSPCLK) derived from SYSCLK. LSPCLK uses a /4 divider by default, but the ratio can
be changed via the LOSPCP register. Each SCI, SPI, and McBSP module's clock (PERx.LSPCLK) can be
gated independently via the PCLKCRx registers.
2.7.3.5 USB Auxiliary Clock (AUXPLLCLK)

The USB module requires a fixed 60 MHz clock for bit sampling. Since the main system clock is usually
not a multiple of 60 MHz, the correct frequency cannot be achieved with a simple divider. Instead, the
USB clock is provided through an auxiliary clock path (AUXPLLCLK), which can use an independent clock
source and PLL to generate the correct frequency.
USB clock tolerances are very tight. As stated in section 7.1.11 of the USB 2.0 specification, low-speed
devices (1.50 Mb/s) have a tolerance of +/- 1.5% , while high-speed devices (12.000 Mb/s) have a
tolerance of +/- 0.25%. Typically these tolerances are achieved by using an external crystal or resonator
as the source for AUXOSCCLK.
2.7.3.6 CAN Bit Clock

The required frequency tolerance for the CAN bit clock depends on the bit timing setup and network
configuration, and can be as tight as 0.1%. Since the main system clock (in the form of PERx.SYSCLK)
may not be precise enough, the bit clock can also be connected to XTAL or AUXCLKIN via the
CLKSRCCTL2 register. There is an independent selection for each CAN module.
2.7.3.7 CPU Timer2 Clock (TIMER2CLK)

CPU timers 0 and 1 are connected to PERx.SYSCLK. Timer 2 is connected to PERx.SYSCLK by default,
but may also be connected to INTOSC1, INTOSC2, XTAL, or AUXPLLCLK via the TMR2CLKCTL register.
This register also provides a separate prescale divider for timer 2. If a source other than SYSCLK is used,
the SYSCLK frequency must be at least twice the source frequency to ensure correct sampling. Each
CPU has its own independent CPU timers and TMR2CLKCTL register.
The main reason to use a non-SYSCLK source would be for internal frequency measurement. In most
applications, timer 2 will run off of the SYSCLK.
2.7.4 XCLKOUT
It is sometimes necessary to observe a clock directly for debug and testing purposes. The external clock
output (XCLKOUT) feature supports this by connecting a clock to an external pin, GPIO73. The available
clock sources are PLLSYSCLK, PLLRAWCLK, CPU1.SYSCLK, CPU2.SYSCLK, AUXPLLRAWCLK,
INTOSC1, and INTOSC2.
To use XCLKOUT, first select the clock source via the CLKSRCCTL3 register. Next, select the desired
output divider via the XCLKOUTDIVSEL register. Finally, connect GPIO73 to mux channel 3 using the
GPIO configuration registers.

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2.7.5 Clock Connectivity

The tables below provide details on the clock connections of every module present in the device.
Table 2-6. Clock Connections Sorted by Clock Domain

Clock Domain CPU1 Subsystem CPU2 Subsystem Shared Modules
CPUx.CPUCLK CPU1 CPU2
CPU1.VCU CPU2.VCU
CPU1.FPU CPU2.FPU
CPU1.TMU CPU2.TMU
CPU1.M0 - M1 RAMs CPU2.M0 - M1 RAMs
CPU1.D0 - D1 RAMs CPU2.D0 - D1 RAMs
CPU1.BootROM CPU2.BootROM
CPU1.Flash CPU2.Flash
CPUx.SYSCLK CPU1.ePIE CPU2.ePIE
CPU1.LS0 - LS5 RAMs CPU2.LS0 - LS5 RAMs
CPU1.CLA1 Message RAMs CPU2.CLA1 Message RAMs
CPU1.DCSM CPU2.DCSM
PLLSYSCLK CPU1.NMIWD CPU2.NMIWD GS0 - GS15 RAMs
EMIF1 GPIO Input Sync and Qual
IPC
PERx.SYSCLK CPU1.CLA1 CPU2.CLA1 ADCA - D
CPU1.DMA CPU2.DMA CMPSS1 - 8
CPU1.Timer0 - 2 CPU2.Timer0 - 2 DACA - C
EMIF2 ePWM1 - 12
uPP A eCAP1 - 6
eQEP1 - 3
I2CA - B
McBSPA - B
SDFM1 - 8
PERx.LSPCLK McBSPA - B
SCIA - D
SPIA - C
CAN Bit Clock CANA - B
AUXPLLCLK USB
WDCLK (INTOSC1) CPU1.Watchdog CPU2.Watchdog

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Table 2-7. Clock Connections Sorted by Module Name

Module Name Clock Domain
ADCA - D PERx.SYSCLK
Boot ROM CPUx.CPUCLK
CANA - B CAN Bit Clock
CLA PERx.SYSCLK
CLA Message RAMs CPUx.SYSCLK
CMPSS1 - 8 PERx.SYSCLK
CPU CPUx.CPUCLK
CPU Timers PERx.SYSCLK
D0 - D1 RAMs CPUx.CPUCLK
DACA - C PERx.SYSCLK
DCSM CPUx.SYSCLK
DMA PERx.SYSCLK
eCAP1 - 6 PERx.SYSCLK
EMIF1 PLLSYSCLK
EMIF2 PERx.SYSCLK
ePIE CPUx.SYSCLK
ePWM PERx.SYSCLK
eQEP1 - 3 PERx.SYSCLK
Flash CPUx.CPUCLK
FPU CPUx.CPUCLK
GS0 - GS15 RAMs PLLSYSCLK
I2CA - B PERx.SYSCLK
IPC PLLSYSCLK
LS0 - LS5 RAMs CPUx.SYSCLK
M0 - M1 RAMs CPUx.CPUCLK
McBSPA - B PERx.LSPCLK
NMIWD PLLSYSCLK
SCIA - D PERx.LSPCLK
SDFM1 - 8 PERx.SYSCLK
SPIA - C PERx.LSPCLK
TMU CPUx.CPUCLK
uPP PERx.SYSCLK
USB AUXPLLCLK
VCU CPUx.CPUCLK
Watchdog Timer WDCLK (INTOSC1)
2.7.6 Clock Source and PLL Setup

The needs of the application are what ultimately determine the clock configuration. Specific concerns such
as application performance, power consumption, total system cost, and EMC are beyond the scope of this
document, but they should provide answers to the following questions:
1. What is the desired CPU frequency?
2. Is CAN required?
3. Is USB required?
4. What types of external oscillators or clock sources are available?

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If CAN or USB is required, an external clock source with a precise frequency must be used as a reference
clock. Otherwise, it may be possible to use only INTOSC2 and avoid the need for more external
components.
2.7.6.1 Choosing PLL Settings

There are two settings to configure for each PLL – a multiplier and a divider. They obey the formulas:
fPLLSYSCLK = fOSCCLK * (SYSPLLMULT.IMULT + SYSPLLMULT.FMULT) / SYSCLKDIVSEL.PLLSYSCLKDIV
fAUXPLLCLK = fAUXOSCCLK * (AUXPLLMULT.IMULT + AUXPLLMULT.FMULT) / AUXCLKDIVSEL.AUXPLLDIV
where fOSCCLK is the system oscillator clock frequency, fAUXOSCCLK is the auxiliary oscillator clock frequency,
IMULT and FMULT are the integral and fractional parts of the multipliers, PLLSYSCLKDIV is the system
clock divider, and AUXPLLDIV is the auxiliary clock divider. For the permissible values of the multipliers
and dividers, see the documentation for their respective registers.
Many combinations of multiplier and divider can produce the same output frequency. However, the
product of the reference clock frequency and the multiplier (known as the VCO frequency) must be in the
range specified in the data manual.
NOTE: The system clock frequency (PLLSYSCLK) may not exceed the limit specified in the
datasheet. This limit does not allow for oscillator tolerance.
The clock source and PLL configuration registers are shared between the two CPUs. Register access is
controlled via a semaphore, which is described in the Inter-Processor Communication chapter.
2.7.6.2 System Clock Setup

Once the application requirements are understood, a specific clock configuration can be determined. The
default configuration is for INTOSC2 to be used as the system clock (PLLSYSCLK) with a divider of 1.
The following procedure should be used to set up the desired application configuration:
1. Select the reference clock source (OSCCLK) by writing to CLKSRCCTL1.OSCCLKSRCSEL.
2. Set up the system PLL: (see the InitSysPll() function in your devices controlSUITE installation for an
example):
a. Bypass the PLL by clearing SYSPLLCTL1[PLLCLKEN].
b. Set the system clock divider to /1 to ensure the fastest PLL configuration by clearing
SYSCLKDIVSEL[ PLLSYSCLKDIV].
c. Set the integral and fractional multipliers by simultaneously writing them both to SYSPLLMULT.
This will automatically enable the PLL. Be sure that the product of OSCCLK and the multiplier is in
the range specified in the data manual.
d. Lock the PLL five times (see your device errata for details). This number can be increased
depending on application requirements. A higher number of lock attempts helps to ensure a
successful PLL start
e. Set the system clock divider one setting higher than the final desired value. For example
ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV = divsel + 1. This limits the current increase
when switching to the PLL.
f. Set up the watchdog to reset the device. Note that the SCRS[WDOVERRIDE] bit should not be
cleared prior to locking the PLL.
g. Set the SYSDBGCTL[BIT_0] bit. This bit is only reset by a POR reset. If the watchdog has to reset
the device due to an issue with switching to the PLL, this bit can be checked in the reset handler to
determine the reset was caused by a PLL error.
h. Switch to the PLL as the system clock by setting SYSPLLCTL1[PLLCLKEN].
i. Clear the SYSDBGCTL[BIT_0] bit.
j. Change the divider to the appropriate value.
k. Reconfigure the watchdog as needed for the application.

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NOTE: If the CPU2 changes the OSCCLK source, it will not automatically bypass the PLL. The
CPU2 must manually bypass the PLL first by writing a 0 to SYSPLLCTL1.PLLCLKEN.
2.7.6.3 USB Auxiliary Clock Setup

See the InitAuxPll() function in your device’s controlSUITE installation for an example.
If USB functionality is needed, the auxiliary clock (AUXPLLCLK) must be configured to produce 60 MHz.
The procedure is similar to the system clock setup:
1. Select the reference clock source (AUXOSCCLK) by writing to CLKSRCCTL2.AUXOSCCLKSRCSEL.
2. Wait two AUXOSCCLK cycles.
3. Set up the auxiliary PLL. If the PLL is not needed, bypass it and power it down by writing a 0 to
AUXPLLCTL1.PLLEN. To use the PLL:
a. Set the desired auxiliary clock divider by writing to AUXCLKDIVSEL.AUXPLLDIV.
b. ) Configure CPU Timer 2 to be clocked from AUXPLL. Keep the counter frozen.
c. ) Power down the AUXPLL by clearing AUXPLLCTL1[PLLEN].
d. Set the integral and fractional multipliers simultaneously. This will automatically enable the PLL. Be
sure that the product of AUXOSCCLK and the multiplier is in the range specified in the data
manual..
e. Wait for the PLL to lock by polling the AUXPLLSTS.LOCKS bit. This will take 16 µs plus 1024
AUXOSCCLK cycles.
f. Connect the auxiliary PLL output clock (AUXPLLRAWCLK) to AUXPLLCLK by writing a 1 to
AUXPLLCTL1.PLLCLKEN.
g. Start CPU Timer 2. In a large for() loop, continue polling the TCR[TIF] overflow flag. If it sets, the
AUXPLL started correctly. If not, repeat steps (c) through (g). The auxiliary clock configuration can
be changed at run time. Changing the AUXOSCCLK source will automatically bypass the PLL and
set the multiplier to zero. Changing the multiplier from one non-zero value to another will
temporarily bypass the PLL until it re-locks.
The auxiliary clock configuration can be changed at run time. Changing the AUXOSCCLK source will
automatically bypass the PLL and set the multiplier to zero. Changing the multiplier from one non-zero
value to another will temporarily bypass the PLL until it re-locks.
NOTE: If the AUXOSCCLK source is changed on the same AUXOSCCLK cycle as the multiplier, the
PLL will be disabled but the AUXPLLMULT register will show the written value. This can
happen when the system PLL is enabled before configuring the auxiliary PLL (CPUCLK >>
AUXOSCCLK). To avoid this issue, wait two AUXOSCCLK cycles between changing the
clock source and writing to AUXPLLMULT.
2.7.6.4 Clock Configuration Examples

Example 1: Using a crystal (15 MHz) as a reference, generate a CPU frequency of 100 MHz and a USB
clock of 60 MHz:
CLKSRCCTL1.OSCCLKSRCSEL = 0x1
SYSPLLMULT.IMULT = 26 (0x1A)
SYSPLLMULT.FMULT = .50 (0x2)
SYSCLKDIVSEL.PLLSYSCLKDIV = 4 (0x2)
SYSPLLCTL1.PLLCLKEN = 1
PERCLKDIVSEL.EPWMCLKDIV = 1 (0x0)
PERCLKDIVSEL.EMIF1CLKDIV = 1 (0x0)
PERCLKDIVSEL.EMIF2CLKDIV = 1 (0x0)
CLKSRCCTL2.AUXOSCCLKSRCSEL = 0x1

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AUXPLLMULT.IMULT = 8 (0x08)
AUXPLLMULT.FMULT = .00 (0x0)
AUXCLKDIVSEL.AUXPLLDIV = 2 (0x1)
AUXPLLCTL1.PLLCLKEN = 1
This gives a PLLRAWCLK of 397.5 MHz and an AUXPLLRAWCLK of 120 MHz, both of which are in the
acceptable range. The CPU frequency is 99.375 MHz. Crystals have tight frequency tolerances, which
should keep the system clock from exceeding 100 MHz. The USB frequency is exactly 60 MHz. Since the
CPU frequency is less than 100 MHz, the ePWM and EMIF clock dividers can be set to /1.
Example 2: Using INTOSC2 (10 MHz) as a reference, generate a CPU frequency of 200 MHz - 3%:
CLKSRCCTL1.OSCCLKSRCSEL = 0x0
SYSPLLMULT.IMULT = 38 (0x26)
SYSPLLMULT.FMULT = .75 (0x3)
SYSCLKDIVSEL.PLLSYSCLKDIV = 2 (0x1)
SYSPLLCTL1.PLLCLKEN = 1
2.8 32-Bit CPU Timers 0/1/2

This section describes the three 32-bit CPU-Timers (TIMER0/1/2) shown in Figure 2-10.
CPU-Timer0 and CPU-Timer1 can be used in user applications. CPU-Timer2 is reserved for real-time
operating system uses (for example, TI-RTOS). If the application is not using an operating system that
utilizes this timer, then CPU-Timer2 can be used in the application. CPU-Timer0 and CPU-Timer1 run off
of SYSCLK. CPU-Timer2 normally runs off of SYSCLK, but can also use INTOSC1, INTOSC2, XTAL, and
AUXPLLCLK. The CPU-Timer interrupt signals (TINT0, TINT1, TINT2) are connected as shown in
Figure 2-11.
Figure 2-10. CPU-Timers
Reset
Timer reload
16-bit timer divide-down

32-bit timer period
TDDRH:TDDR
PRDH:PRD
16-bit prescale counter

SYSCLKOUT
PSCH:PSC
TCR.4 32-bit counter
(Timer start status) Borrow TIMH:TIM
Borrow
TINT

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Figure 2-11. CPU-Timer Interrupts Signals and Output Signal
INT1 TINT0
to PIE TIMER0
INT12
28x
CPU
TINT1
INT13 TIMER1
TINT2
INT14 TIMER2
A The timer registers are connected to the memory bus of the C28x processor.
B The CPU Timers are synchronized to SYSCLKOUT.
The general operation of the CPU-Timer is as follows:

• The 32-bit counter register, TIMH:TIM, is loaded with the value in the period register PRDH:PRD
• The counter decrements once every (TPR[TDDRH:TDDR]+1) SYSCLKOUT cycles, where
TDDRH:TDDR is the timer divider.
• When the counter reaches 0, a timer interrupt output signal generates an interrupt pulse.
The registers listed in Section 2.15 are used to configure the timers.

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2.9 Watchdog Timers

The watchdog module generates an output pulse 512 watchdog clocks (WDCLKs) wide whenever the 8-
bit watchdog up counter has reached its maximum value. The watchdog clock source is INTOSC1.
Software must periodically write a 0x55 + 0xAA sequence into the watchdog key register to reset the
watchdog counter. The counter can also be disabled. Figure 2-12 shows the various functional blocks
within the watchdog module.
Figure 2-12. CPU Watchdog Timer Module
WDCR(WDPS(2:0)) WDCR(WDDIS)
WDCNTR(7:0)
WDCLK Watchdog 8-bit 1-count

(INTOSC1)
/512 Overflow
Prescaler Watchdog delay
Counter
SYSRSn
Clear
Count
WDWCR(MIN(7:0))
WDKEY(7:0) Watchdog
Watchdog Window
Good Key Out of Window
Key Detector Detector
Bad Key
55 + AA
WDRSTn
Generate
512-WDCLK
WDINTn Watchdog Timeout
Output Pulse
SCSR(WDENINT)
2.9.1 Servicing the Watchdog Timer

The watchdog counter (WDCNTR) is reset when the proper sequence is written to the WDKEY register
before the 8-bit watchdog counter overflows. The WDCNTR is reset-enabled when a value of 0x55 is
written to the WDKEY. When the next value written to the WDKEY register is 0xAA, then the WDCNTR is
reset. Any value written to the WDKEY other than 0x55 or 0xAA causes no action. Any sequence of 0x55
and 0xAA values can be written to the WDKEY without causing a system reset; only a write of 0x55
followed by a write of 0xAA to the WDKEY resets the WDCNTR.
Table 2-8. Example Watchdog Key Sequences

Step Value Written to WDKEY Result
1 0xAA No action
2 0xAA No action
3 0x55 WDCNTR is enabled to be reset if next value is 0xAA.
6 0xAA WDCNTR is reset.
7 0xAA No action

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Table 2-8. Example Watchdog Key Sequences (continued)

Step Value Written to WDKEY Result
11 0x32 Improper value written to WDKEY.
No action, WDCNTR no longer enabled to be reset by next 0xAA.
12 0xAA No action due to previous invalid value.
Step 3 in Table 2-8 is the first action that enables the WDCNTR to be reset. The WDCNTR is not actually
reset until step 6. Step 8 again re-enables the WDCNTR to be reset and step 9 resets the WDCNTR. Step
10 again re-enables the WDCNTR to be reset. Writing the wrong key value to the WDKEY in step 11
causes no action, however the WDCNTR is no longer enabled to be reset and the 0xAA in step 12 now
has no effect.
If the watchdog is configured to reset the device, then a WDCR overflow or writing the incorrect value to
the WDCR[WDCHK] bits will reset the device and set the watchdog flag (WDRSn) in the reset cause
register (RESC). After a reset, the program can read the state of this flag to determine whether the reset
was caused by the watchdog. After doing this, the program should clear WDRSn to allow subsequent
watchdog resets to be detected. Watchdog resets are not prevented when the flag is set.
2.9.2 Minimum Window Check

To complement the timeout mechanism, the watchdog also contains an optional "windowing" feature that
requires a minimum delay between counter resets. This can help protect against error conditions that
bypass large parts of the normal program flow but still include watchdog handling.
To set the window minimum, write the desired minimum watchdog count to the WDWCR register. This
value will take effect after the next WDKEY sequence. From then on, any attempt to service the watchdog
when WDCNTR is less than WDWCR will trigger a watchdog interrupt or reset. When WDCNTR is greater
than or equal to WDWCR, the watchdog can be serviced normally.
At reset, the window minimum is zero, which disables the windowing feature.
2.9.3 Watchdog Reset or Watchdog Interrupt Mode

The watchdog can be configured in the SCSR register to either reset the device (WDRST) or assert an
interrupt (WDINT) if the watchdog counter reaches its maximum value. The behavior of each condition is
described below:
• Reset mode:
If the watchdog is configured to reset the device, then the WDRST signal will pull the device reset
(XRS) pin low for 512 OSCCLK cycles when the watchdog counter reaches its maximum value.
Note: After a CPU1 watchdog reset, the boot ROMs will clear all of the system and message RAMs on
both CPUs. After a CPU2 watchdog reset, CPU2's boot ROM will clear all of the CPU2 system and
message RAMs.
• Interrupt mode:
When the watchdog counter expires, it will assert an interrupt by driving the WDINT signal low for 512
OSCCLK cycles. The falling edge of WDINT triggers a WAKEINT interrupt in the PIE if it is enabled.
Because the PIE is edge-triggered, re-enabling the WAKEINT while WDINT is active will not produce a
duplicate interrupt.
To avoid unexpected behavior, software should not change the configuration of the watchdog while
WDINT is active. For example, changing from interrupt mode to reset mode while WDINT is active will
immediately reset the device. Disabling the watchdog while WDINT is active will cause a duplicate
interrupt if the watchdog is later re-enabled. If a debug reset is issued while WDINT is active, the reset
cause register (RESC) will show a watchdog reset. The WDINTS bit in the SCSR register can be read
to determine the current state of WDINT.

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2.9.4 Watchdog Operation in Low Power Modes

In IDLE mode, the watchdog interrupt (WDINT) signal can generate an interrupt to the CPU to take the
CPU out of IDLE mode. As with any other peripheral, the watchdog interrupt will trigger a WAKEINT
interrupt in the PIE during IDLE mode. User software must determine which peripheral caused the
interrupt.
In STANDBY mode, all of the clocks to the peripherals are turned off within the CPU subsystem. The only
peripheral that remains functional is the watchdog since the watchdog module runs off the oscillator clock
(OSCCLK). The WDINT signal is fed to the Low Power Modes (LPM) block so that it can be used to wake
the CPU from STANDBY low power mode. This feature is enabled by setting LPMCR.WDINTE = 1. See
Section 2.10 for details.
Note: If the watchdog interrupt is used to wake-up from an IDLE or STANDBY low power mode condition,
software must make sure that the WDINT signal goes back high before attempting to reenter the IDLE or
STANDBY mode. The WDINT signal will be held low for 512 OSCCLK cycles when the watchdog interrupt
is generated. The current state of WDINT can be determined by reading the watchdog interrupt status bit
(WDINTS) bit in the SCSR register. WDINTS follows the state of WDINT by two SYSCLKOUT cycles.
In HALT mode, the internal oscillators and CPU1 watchdog are kept active if the user sets
CLKSRCCTL1.WDHALTI = 1. A watchdog reset can wake the system from HALT mode, but a watchdog
interrupt cannot.
2.9.5 Emulation Considerations

The watchdog module behaves as follows under various debug conditions:
CPU Suspended: When the CPU is suspended, the watchdog clock (WDCLK) is suspended
Run-Free Mode: When the CPU is placed in run-free mode, then the watchdog module
resumes operation as normal.
Real-Time Single-Step When the CPU is in real-time single-step mode, the watchdog clock
Mode: (WDCLK) is suspended. The watchdog remains suspended even within real-
time interrupts.
Real-Time Run-Free When the CPU is in real-time run-free mode, the watchdog operates as
Mode: normal.

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2.10 Low Power Modes

This device has three clock-gating, low-power modes and a special power-gating mode. All low-power
modes are entered by setting the LPMCR register and executing the IDLE instruction. More information
about this instruction can be found in the TMS320C28x CPU and Instruction Set Reference Guide
(SPRU430).
Low-power modes should not be entered into while a flash program or erase is ongoing.
The application should verify the following before entering STANDBY or HALT Mode:
1. Check the value of the GPIODAT register of the pin selected for STANDBY or HALT wake-up
(GPIOLPMSEL0/1) prior to entering the Low-Power mode to ensure that the wake event has not
already been asserted.
2. The LPMCR.QUALSTDBY register should be set to a value greater than the ratio of
INTOSC1/PLLSYSCLK to ensure proper wake up. This is applicable to STANDBY only.
2.10.1 IDLE
IDLE is a standard feature of the C28x CPU. In this mode, the CPU clock is gated while all peripheral
clocks are left running. IDLE can thus be used to conserve power while a CPU is waiting for peripheral
events. When one CPU is in IDLE, there is no effect on the other CPU subsystem.
Any enabled interrupt will wake the CPU up from IDLE mode.
To enter IDLE mode, set LPMCR.LPM to 0x0 and execute the IDLE instruction.
2.10.2 STANDBY
STANDBY is a more aggressive low-power mode that gates both the CPU clock and any peripheral clocks
derived from the CPU's SYSCLK. The watchdog however, is left active. Like IDLE, this mode affects only
one CPU subsystem. The other CPU subsystem and all of its peripherals are unaffected. STANDBY is
best suited for an application where the wake-up signal will come from an external system (or CPU
subsystem) rather than a peripheral input.
IPC interrupt 1 (flag 0), an NMI fired to the other CPU, or (optionally) a watchdog interrupt, will wake the
CPU subsystem up from STANDBY mode. Any of GPIO0-63 can also be configured to wake up the
subsystem when they are driven active low. Upon wakeup, the CPU receives a WAKEINT interrupt, even
if it was woken by an IPCINT1 signal.
To enter STANDBY mode:
1. Set LPMCR.LPM to 0x1.
2. Enable the WAKEINT interrupt in the PIE.
3. For watchdog interrupt wakeup, set LPMCR.WDINTE to 1 and configure the watchdog to generate
interrupts.
4. For GPIO wakeup, set GPIOLPMSEL0 and GPIOLPMSEL1 to connect the chosen GPIOs to the LPM
module, and set LPMCR.QUALSTDBY to select the number of OSCCLK cycles for input qualification.
5. Execute the IDLE instruction to enter STANDBY.
To wake up from Standby mode:
1. Configure the desired GPIO to trigger the wakeup.
2. Drive the selected GPIO signal low; it must remain low for the number of OSCCLK cycles specified in
the QUALSTDBY bits in the LPMCR register. If the signal is sampled high during this period, the count
restarts.
At the end of the qualification period, the PLL enables the CLKIN to the CPU and the WAKEINT interrupt
is latched in the PIE block. The WAKEINT interrupt can also triggered by IPCINT1 sent from the other
CPU and a watchdog interrupt.
The CPU is now out of STANDBY mode and can resume normal execution.

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If CPU2 is in STANDBY mode, writing a 1 to the RESET bit of the CPU2RESCTL register will have no
effect. CPU2 may be reset by any Chip-level reset (POR, XRSn, CPU1.WDRSn, or CPU1.NMIWDRSn) or
HIBRESETn. Alternately CPU2 may be woken up by any configured wake-up event.
If CPU2 is in STANDBY mode and the debugger is connected, executing a debug reset on CPU2 will
have no effect. In order to wake the CPU2 with the debugger, Click Run, Single Step, or Step over in the
Debug toolbar. CCS will prompt the user requesting to bring the CPU out of the low-power mode. Click
Yes. This will wake CPU2 from STANDBY and continue execution.
2.10.3 HALT
HALT is a global low-power mode that gates almost all system clocks and allows for power-down of
oscillators and analog blocks. This mode affects both CPU subsystems. HALT can be used for additional
power savings over putting both CPU subsystems in STANDBY, although the options for wakeup are
more limited.
Similar to STANDBY, any of GPIO0-63 can be configured to wake up the system from HALT. No other
wakeup option is available. However, CPU1's watchdog may still be clocked, and can be configured to
produce a watchdog reset if a timeout mechanism is needed. On wakeup, both CPUs receive a WAKEINT
interrupt.
To enter HALT mode:
1. Disable all interrupts with the exception of the WAKEINT interrupt on both CPUs. The other interrupts
can be reenabled after the device is brought out of HALT mode.
2. Put CPU2 into IDLE mode. (Using STANDBY will cause a duplicate WAKEINT on CPU2). CPU1
should verify this by checking the LPMSTAT register.
3. Set LPMCR.LPM to 0x2. Set GPIOLPMSEL0 and GPIOLPMSEL1 to connect the chosen GPIOs to the
LPM module.
4. Set CLKSRCCTL1.WDHALTI to 1 to keep the CPU1 watchdog active and INTOSC1 and INTOSC2
powered up in HALT.
5. Set CLKSRCCTL1.WDHALTI to 0 to disable the CPU1 watchdog and power down INTOSC1 and
INTOSC2 in HALT.
6. Execute the IDLE instruction on CPU1 to enter HALT.
If an interrupt or NMI is received while the IDLE instruction is in the pipeline, the system will begin
executing the WAKEINT ISR. After HALT wakeup, ISR execution will resume where it left off.
NOTE: Before entering HALT mode, if the system PLL is locked (SYSPLL.LOCKS = 1), it must also be
connected to the system clock (PLLCTL1.PLLCLKEN = 1). Otherwise, the device will never wake up.
To wake up from HALT mode:
1. Drive the selected GPIO low for a minimum 5us. This will activate the CPU1.WAKEINT and
CPU2.WAKEINT PIE interrupts.
2. Drive the wake-up GPIO high again to initiate the powering up of the SYSPLL and AUXPLL
3. Wait 16us plus 1024 OSCLK cycles to allow the PLLs to lock and the WAKEINT ISR to be latched.
4. Execute the WAKEINT ISR.
The device is now out of HALT mode and can resume normal execution.
2.10.4 HIB
Hibernate (HIB) is a global low-power mode that gates the supply voltages to most of the system. This
mode affects both CPU subsystems. HIB is essentially a controlled power-down with remote wakeup
capability, and can be used to save power during long periods of inactivity. Because gating the supply
voltage corrupts the state of the logic, a reset is required to exit HIB. To prevent external systems from
being affected by the reset, HIB provides isolation of the I/O pin states as well as low-power data retention
via the M0 and M1 memories.

Low Power Modes www.ti.com
Unlike the clock-gating modes, HIB does not have a true wakeup. Instead, GPIO41 becomes HIBWAKE,
an asynchronous reset signal. When the boot ROM detects a HIB wakeup, it will avoid clearing M0 and
M1 and call a user-specified I/O restore function. To prevent glitches on internal and external signals, XRS
will also generate a HIBWAKE signal during HIB. The I/O restore function should set up the GPIO control
registers to match their pre-HIB state, then write a 1 to LPMCR.IOISODIS to deactivate I/O isolation. If the
restore function does not disable isolation, the boot ROM will do it.
To enter HIB mode:
1. Save any necessary state to the M0 and M1 memories of both CPUs.
2. Put all I/Os in the desired state for isolation and deactivate any analog modules in use.
3. Write the address of the I/O restore function for each CPU to its IORESTOREADDR register.
4. Put CPU2 in reset, IDLE, or STANDBY.
5. Bypass the PLL by setting PLLCLKEN to 0.
6. Set CPU1's LPMCR.LPM to 0x3 and execute the IDLE instruction.
Any debugger connection will be lost on HIB entry since the JTAG logic is powered down.
Due to the loss of system state on HIB entry, it is possible for error information to be lost if an NMI is
triggered while the IDLE instruction is in the pipeline. The ERRORSTS pin will be set and remain set until
I/O isolation is disabled, but there will be no way to tell what caused the error.
To wake the device from HIB mode:
1. Assert the dedicated GPIOHIBWAKE pin (GPIO41) low to enable the power-up of the device clock
sources.
2. Assert GPIOHIBWAKE pin high again. This triggers the power-up of the rest of the device.
3. Boot ROM code will execute on HIB wake-up. Boot ROM will read CPU1.RESC.HIBRESTn bit to
determine this is a wakeup from HIB.
4. Boot ROM calls the I/O context restore routine. This I/O restore function should reconfigure the I/O
configuration and do any other necessary application setup.
Since waking up from HIB mode is a type of reset, the device will enter the main function. The device is
now out of HIB mode and can normal execution.
NOTE: The bootROM uses locations 0x02-0x122 on CPU1’s M0 RAM and locations 0x02-0x80 on
CPU2’s M0 RAM. To prevent losing any data during HIB wake-up, avoid saving any critical
data to these locations.
NOTE: The application must bypass the PLL before executing the IDLE instruction to enter HIB. If
the PLL is not bypassed when entering HIB, there will be a brief current spike on the Vdd
supply that may cause the device to reset.

www.ti.com Memory Controller Module
2.11 Memory Controller Module

For these devices, the RAMs have different characteristics. Some are:
• dedicated to each CPU (M0, M1, and Dx RAMs),
• shared between the CPU and its own CLA (LSx RAM),
• shared between the CPU and DMA of both subsystems (GSx RAM), and
• used to send and receive messages between processors (MSGRAM).
All these RAMs are highly configurable to achieve control for write access and fetch access from different
masters. There are also RAMs - called IPC MSGRAMs - that are used for interprocessor communication.
All dedicated RAMs are enabled with the ECC feature (both data and address) and shared RAMs, as well
as IPC MSGRAMs, are enabled with the PARITY (both data and address) feature. Some of the dedicated
memories are secure memory as well. Refer to Section 2.13 for more details. Each RAM has its own
controller which takes care of the access protection/security related checks and ECC/Parity features for
that RAM. Figure 2-13 shows the configuration of these RAMs.
Figure 2-13. Memory Architecture

CPU1.LSx RAM CPU2.LSx RAM
GSx RAM
CPU1 TO CPU2 TO CPU2.CLA1

CPU1.CLA1 CPU1.CLA1 CPU2.CLA1
MSGRAM MSGRAM
CPU1.CLA1 TO CPU2.CLA1 TO
CPU1 MSGRAM CPU2 MSGRAM
CPU1.DMA CPU2.DMA
CPU1 CPU2
CPU1.M0 RAM CPU2.M0 RAM
CPU2 TO CPU1
MSGRAM
CPU1.M1 RAM CPU2.M1 RAM
CPU1 TO CPU2
CPU1.Dx RAM MSGRAM CPU2.Dx RAM
NOTE: All RAMs on these devices are SRAMs.
2.11.1 Functional Description

This section further defines and discusses the dedicated RAMs, shared RAMs, and MSG RAMs on this
device.
2.11.1.1 Dedicated RAM (Dx RAM)

Each CPU subsystem has four dedicated RAM blocks: M0, M1, D0, and D1. M0/M1 memories are small
blocks of memory which are tightly coupled with the CPU. Only the CPU has access to these memories.
No other masters (including DMA) have any access to these memories.
All dedicated RAMs have the ECC feature. All dedicated memories (except for M0/M1) are secure
memory and also have the access protection (CPU write protection/CPU fetch protection) feature. Each
type of access protection for each RAM block can be enabled/disabled by configuring the specific bit in the
access protection register, allocated to each subsystem (DxACCPROT).

Memory Controller Module www.ti.com
2.11.1.2 Local Shared RAM (LSx RAM)

RAM blocks which are dedicated to each subsystem and are accessible to its CPU and CLA only, are
called local shared RAMs (LSx RAMs). All such memories are secure memory and have the parity feature.
By default, these memories are dedicated to the CPU only, and the user could choose to share these
memories with the CLA by appropriately configuring the MSEL_LSx bit field in the LSxMSEL register.
Further, when these memories are shared between the CPU and CLA, the user could choose to use these
memories as CLA program memory by configuring the CLAPGM_LSx bit field in the LSxCLAPGM
registers. CPU access to all memory blocks, which are programmed as CLA program memory, are
blocked.
All these RAMs have the access protection (CPU write/CPU fetch) feature. Each type of access protection
for each RAM block can be enabled or disabled by configuring the specific bit in the local shared RAM
access protection registers, mapped to each CPU subsystem. Table 2-9 shows the LSx RAM features.
Table 2-9. Local Shared RAM

MSEL_LSx CLAPGM_LSx CPUx Allowed CPUx.CLA1 Allowed Comment
Access Access
00 X All - LSx memory is configured as CPU
dedicated RAM
01 0 All Data Read LSx memory is shared between
Data Write CPU and CLA1
01 1 Emulation Read Fetch Only LSx memory is CLA1 program
Emulation Write memory
2.11.1.3 Global Shared RAM (GSx RAM)

RAM blocks which are accessible from both the CPU and their respective DMA are called global shared
RAMs (GSx RAMs). Each shared RAM can be owned by either CPU subsystem based on the
configuration of their respective bits (one bit for each GSx memory) in the GSxMSEL register. When a
particular GSx RAM block is owned by the CPU1 subsystem, CPU1 and CPU1.DMA have full access to
that RAM block, whereas CPU2 and CPU2.DMA have only read access to it (no fetch/write access).
Similarly, when a particular GSx RAM block is owned by the CPU2 subsystem, CPU1 and CPU1.DMA will
have only read access (no fetch/write access) to that RAM block, whereas CPU2 and CPU2.DMA will
have full access to it. Table 2-10 shows the features of the GSx RAM.
Table 2-10. Global Shared RAM

GSxMSEL CPU1 CPU1 CPU1 CPU1.DMA CPU1.DMA CPU2 CPU2 CPU2 CPU2.DMA CPU2.DMA
Fetch Read Write Read Write Fetch Read Write Read Write
0 Yes Yes Yes Yes Yes No Yes No Yes No
1 No Yes No Yes No Yes Yes Yes Yes Yes
Like other shared RAM, these RAMs also have a different levels of access protection which can be
enabled or disabled by configuring specific bits in the GSxACCPROT registersmapped in each subsystem.
Master select and access protection configuration for each GSx RAM block can be individually locked by
the user to prevent further update to these bit fields. The user can also choose to permanently lock the
configuration to individual bit fields by setting the specific bit fields in the GSxCOMMIT register (refer to
the register description for more details). Once configuration is committed for a particular GSx RAM block,
it can not be changed further until CPUx.SYSRS is issued. Only the CPU1 SW can change the master
select configuration by writing into the GSxMSEL register, mapped on the CPU1. The GSxMSEL register,
which is mapped to the CPU2 subsystem, is a status register which can only be used by CPU2 SW to
know the master ownership for each GSx RAM block.

2.11.1.4 CPU Message RAM (CPU MSG RAM)

These RAM blocks can be used to share data between CPU1 and CPU2. Since these RAMs are used for
interprocessor communication, they are also called IPC RAMs. The CPU MSGRAMs have CPU/DMA
read/write access from its own CPU subsystem, and CPU/DMA read only access from the other
subsystem.
This RAM has parity.
2.11.1.5 CLA Message RAM (CLA MSGRAM)

These RAM blocks are be used to share data between the CPU and CLA. The CLA has read and write
access to the "CLA to CPU MSGRAM." The CPU has read and write access to the "CPU to CLA
MSGRAM." The CPU and CLA both have read access to both MSGRAMs.
This RAM has parity.
2.11.1.6 Access Arbitration

For a shared RAM, multiple accesses can happen at a given time. The maximum number of accesses to
any shared RAM at any given time depends on the type of shared RAM. On this device, a combination of
a fixed and round robin scheme is followed to arbitrate multiple access at any given time. Accesses from
the same masters are arbitrated in a fixed priority manner, but the accesses from different masters are
arbitrated using the round robin scheme.
The following is the order of fixed priority for CPU accesses:
1. Data Write/Program Write
2. Data Read
3. Program Read/Program Fetch
The following is the order of fixed priority for CLA accesses:
1. Data Write
2. Data Read/Program Fetch
Figure 2-14 represents the arbitration scheme on global shared memories:
Figure 2-14. Arbitration Scheme on Global Shared Memories
Round Robin Arbitration

CPU1-DWRITE CPU1
Fixed Granted CPU1 Access
CPU1-DREAD Priority RR-CPU1
CPU1-PREAD/FETCH Arbiter
CPU1.DMA READ/WRITE
RR-CPU2.DMA RR-CPU1.DMA
CPU2-DWRITE
CPU2
CPU2-DREAD Fixed Granted CPU2 Access
Priority
CPU2-PREAD/FETCH Arbiter
RR-CPU2
CPU2.DMA READ/WRITE
Figure 2-15 represents the arbitration scheme on local shared memories.

Figure 2-15. Arbitration Scheme on Local Shared Memories
Round Robin Arbitration

CPU-DWRITE CPU
Fixed Granted CPU1 Access
CPU-DREAD
Priority
Arbiter RR-CPU
CPU-PREAD/FETCH
CLA-DWRITE CLA RR-CPU.CLA

Fixed
Priority Granted CLA Access
CLA-DREAD
Arbiter
2.11.1.7 Access Protection

All RAM blocks except for M0/M1 on both subsystems have different levels of protection. This feature
allows the user to enable or disable specific access to individual RAM blocks from individual masters.
There is no protection for read accesses, hence reads are always allowed from all the masters which have
access to that RAM block.
The following sections describe the different kinds of protection available for RAM blocks on this device.
Note: For debug accesses, all the protections are disabled.
2.11.1.7.1 CPU Fetch Protection

A CPU has execution permission from a memory, only if that memory is dedicated to that CPU or its
respective subsystem is master for that memory (in case of GSx memory). When fetch accesses are
allowed based on the mastership, it can be further protected by setting the FETCHPROTx bit of the
specific register to ‘1.’ If fetch access is done by the CPU to a memory where CPU fetch protection is
enabled, a fetch protection violation occurs.
There are two types of fetch protection violations:
• Non-master CPU fetch protection violation
• Master CPU fetch protection violation
If a fetch access is made to a memory by a non-master CPU, it is called a non-master fetch protection
violation. If a fetch access is made to a dedicated or shared memory by the master CPU, and
FETCHPROTx is set to ‘1’ for that memory, the violation is called a master CPU fetch protection violation.
If a fetch protection violation occurs, it results in an ITRAP for CPU. A flag gets set into the appropriate
access violation flag register, and the memory address for which the access violation occurred, get
latched into the appropriate CPU fetch access violation address register.
2.11.1.7.2 CPU Write Protection

A CPU has write permission to a memory only if that memory is dedicated to that CPU, or if its respective
subsystem is the master for that memory (in case of GSx memory). When write accesses are allowed
based on the mastership, it can be further protected by setting the CPUWRPROTx bit of the specific
register to ‘1.’ If write access is done by a CPU to memory where it is protected, a write protection
violation occurs.
There are two types of CPU write protection violations:
• Non-master CPU write protection violation
• Master CPU write protection violation
If a write access is made to a dedicated or shared memory by the master CPU and CPUWRPROTx is
set to ‘1’ for that memory, it’s called a master CPU write protection violation.

If a write protection violation occurs, write gets ignored, a flag gets set into the appropriate access
violation flag register, and the memory address for which the access violation occurred, gets latched into
the appropriate CPU write access violation address register. Also, an access violation interrupt is
generated if enabled in the interrupt enable register.
2.11.1.7.3 CPU Read Protection

For local shared RAM, if memory is shared between the CPU and its CLA, the CPU will only have access
if the memory is configured as data RAM for the CLA. If it is programmed as program RAM, all the access
from the CPU, including a read, will be blocked and the violation will be considered as a non-master
access violation.
If a read protection violation occurs, a flag gets set into the appropriate access violation flag register, and
the memory address for which the access violation occurred, gets latched into the appropriate CPU read
access violation address register. Also, an access violation interrupt is generated, if enabled in the
interrupt enable register.
2.11.1.7.4 CLA Fetch Protection

If local shared RAM is configured as dedicated RAM for the CPU, or if it is configured as data RAM for the
CLA, any fetch access from the CLA to that particular LSx RAM results in a CLA fetch protection violation,
which is a non-master access violation.
If a CLA fetch protection violation occurs, it results in a MSTOP, a flag gets set into the appropriate access
the appropriate CLA fetch access violation address register. Also, an access violation interrupt is
generated to the master CPU if enabled in the interrupt enable register.
2.11.1.7.5 CLA Write Protection

If local shared RAM is configured as dedicated RAM for the CPU, or if it is configured as program RAM for
the CLA, any data write access from the CLA to that particular LSx RAM results in a CLA write protection
violation, which is a non-master access violation.
If a CLA write protection violation occurs, write gets ignored, a flag gets set into the appropriate access
the appropriate CLA write access violation address register. Also, an access violation interrupt is
generated to the master CPU if enabled in the interrupt enable register.
2.11.1.7.6 CLA Read Protection

If local shared RAM is configured as dedicated RAM for the CPU, or if it is configured as program RAM for
the CLA, any data read access from the CLA to that particular LSx RAM results in a CLA read protection
violation, which is a non-master access violation.
If a CLA read protection violation occurs, a flag gets set into the appropriate access violation flag register,
and the memory address for which the access violation occurred, gets latched into the appropriate CLA
read access violation address register. Also, an access violation interrupt is generated to the master CPU
if enabled in the interrupt enable register.
2.11.1.7.7 DMA Write Protection

The CPU1 or CPU2 DMA has write permission to a GSx memory only if its respective subsystem is
master for that memory. When write accesses from a DMA are allowed based on the mastership, it can be
further protected by setting the DMAWRPROTx bit of a specific register to ‘1.’ If write access is done by
the DMA to protected memory, a write protection violation occurs.
There are two types of DMA write protection violations:
• Non-master DMA write protection violation (only applicable to Sx memories)
• Master DMA write protection violation

If a write access is made to GSx memory by a non-master DMA, it is called a non-master write protection
violation. If a write access is made to a dedicated or shared memory by a master DMA, and
DMAWRPROTx is set to ‘1’ for that memory, it is called a master DMA write protection violation.
If a write protection violation occurs on CPU1, write is ignored and a DMAERR interrupt gets generated,
whereas in the case of CPU2, a write is ignored and an access violation interrupt is generated if enabled
in the interrupt enable register. A flag gets set in the DMA access violation flag register, and the memory
address where the violation happened gets latched in the DMA fetch access violation address register.
These are dedicated registers for each subsystem.
Note 1: All access protections are ignored during debug accesses. Write access to a protected
memory will go through when it is done via the debugger, irrespective of the write protection
configuration for that memory.
Note 2: Access protection is not implemented for M0 and M1 memories.
Note 3: In the case of local shared RAM, if memory is shared between the CPU and its CLA, the
CPU will only have access if the memory is configured as data RAM for the CLA. If it is
programmed as program RAM, all the access from the CPU (including read) and data access
from the CLA will be blocked, and violation will be considered as a non-master access
violation. If the memory is configured as dedicated to the CPU, all access from the CLA will
be blocked and the violation will be considered a non-master access violation.
2.11.1.8 Memory Error Detection, Correction and Error Handling

These devices have memory error detection and correction features to satisfy safety standards
requirements. These requirements warrant the addition of detection mechanisms for finite dangerous
failures.
In this device, all dedicated RAMs support error correction code (ECC) protection and the shared RAMs
have parity protection. The ECC scheme used is Single Error Correction Double Error Detection
(SECDED). The parity scheme used is even parity. ECC/Parity will cover the data bits stored in memory
as well as address.
ECC/Parity calculation is done inside the memory controller module and then calculated. ECC/Parity is
written into the memory along with the data. ECC/Parity is computed for 16-bit data; hence, for each 32-bit
data, there will be three 7-bit ECC codes (or 3-bit parity), two of which are for data and a third one for the
address.
2.11.1.8.1 Error Detection and Correction

Error detection is done while reading the data from memory. The error detection is performed for data as
well as address. For parity memory, only a single-bit error gets detected, whereas in case of ECC
memory, along with a single-bit error, a double-bit error also gets detected. These errors are called
correctable error and uncorrectable errors. The following are characteristics of these errors:
• Parity errors are always uncorrectable errors
• Single-bit ECC errors are correctable errors
• Double-bit ECC errors are uncorrectable errors
• Address ECC errors are also uncorrectable errors
Correctable errors get corrected by the memory controller module and then correct data is given back as
read data to the master. It is also written back into the memory to prevent double-bit error due to another
single-bit error at the same memory address.

2.11.1.8.2 Error Handling

For each correctable error, the count in the correctable error count register will increment by one. When
the value in this count register becomes equal to the value configured into the correctable error threshold
register, an interrupt is generated to the respective CPU, that is, if the interrupt is enabled in the
correctable interrupt enable register. The user needs to configure the correctable error threshold register
based on the system requirements. Also, the address for which the error occurred, gets latched into the
master-specific status register and a flag gets set. Each of these registers are dedicated for each CPU
subsystem.
If there are uncorrectable errors, an NMI gets generated for the respective CPU. In this case, the address
for which the error occurred, also gets latched into the master-specific address status register, and a flag
gets set.
Table 2-11 summarizes different error situations that can arise. These need to be handled appropriately in
the software, using the status and interrupt indications provided.
Table 2-11. Error Handling in Different Scenarios

Access Error Found In Error Type Status Indication Error Notification
Type
Reads Data read from Uncorrectable Yes -CPUx/CPUx.DMA/CPUx.CLA1 NMI for CPUx access
memory Error CPU/DMA/CLA Read Error Address NMI for CPUx.DMA access
(Single-bit error Register Data returned to NMI to CPU for CPUx.CLA1 access
for Parity RAMs CPUx/CPUx.DMA/CPUx.CLA1 is
OR incorrect
Double bit Error
for ECC RAMs)
Reads Data read from Single-bit error for Yes - CPUx/CPUx.DMA CPU/DMA Interrupt when error counter reaches
memory ECC RAMs Read Error Address Register the user programmable threshold for
Increment single error counter single errors
Reads Address Address error Yes - CPUx/CPUx.DMA/CPUx.CLA1 NMI to CPU for CPUx access
CPU/DMA/CLA Read Address Error NMI to CPU for CPUx.DMA access
Register Data returned to NMI to CPU for CPUx.CLA1 access
CPUx/CPUx.DMA/CPUx.CLA1 is
incorrect
NOTE: In the case of an uncorrectable error during fetch on the CPU, there is the possibility of
getting an ITRAP before an NMI exception, since garbage instructions enter into the CPU
pipeline before the NMI gets generated.
During debug accesses, correctable as well as uncorrectable errors are masked.
2.11.1.9 Application Test Hooks for Error Detection and Correction

Since error detection and correction logic is part of safety critical logic, safety applications may need to
ensure that the logic is always working fine (during run time also). To enable this, a test mode is provided,
in which a user can modify the data bits (without modifying the ECC/Parity bits) or ECC/Parity bits directly.
Using this feature, an ECC/Parity error could be injected into data.
NOTE: The memory map for ECC/Parity bits and data bits are the same. The user must choose a
different test mode to access ECC/Parity bits.
The following table shows the bit mapping for the ECC/Parity bits when they are read in RAMTEST mode
using their respective addresses.

Table 2-12. Mapping of ECC Bits in Read Data from ECC/Parity Address Map
Data Bits Location in Read Data Content (ECC Memory)
6:0 ECC Code for lower 16 bits of data
7 Not Used
14:8 ECC Code for upper 16 bits of data
15 Not Used
22:16 ECC Code for address
31:23 Not Used
Table 2-13. Mapping of Parity Bits in Read Data from ECC/Parity Address Map
Data Bits Location in Read Data Content (Parity Memory)
0 Parity for lower 16 bits of data
7:1 Not Used
8 Parity for upper 16 bits of data
15:9 Not Used
16 Parity for address
31:17 Not Used
2.11.1.10 RAM Initialization

To ensure that read/fetch from uninitialized RAM locations do not cause ECC or parity errors, the
RAM_INIT feature is provided for each memory block. Using this feature, any RAM block can be initialized
with 0x0 data and respective ECC/Parity bits accordingly. This can be initiated by setting the INIT bit to ‘1’
for the specific RAM block in INIT registers. To check the status of RAM initialization, SW should poll for
the INITDONE bit for that RAM block in the INITDONE register to be set. Unless this bit gets set, no
access should be made to that RAM memory block.
In the case of GSx memory, only the CPU of the subsystem that is configured as the master for the
particular GSx RAM block can initiate the RAM initialization.
NOTE: None of the masters should access the memory while initialization is taking place. If memory
is accessed before RAMINITDONE is set, the memory read/write as well as initialization will
not happen correctly.

www.ti.com Flash and OTP Memory
2.12 Flash and OTP Memory

Flash is an electrically erasable/programmable nonvolatile memory that can be programmed and erased
many times to ease code development. Flash memory can be used primarily as a program memory for the
core, and secondarily as static data memory.
This section describes the proper sequence to configure the wait states and operating mode of flash. It
also includes information on flash and OTP power modes, how to improve flash performance by enabling
the flash prefetch/cache mode, and the SECDED safety feature.
2.12.1 Features
Features of flash memory include:
• Dedicated flash bank in the CPU1 subsystem (refer to the device data manual for the size of flash
bank)
• Dedicated flash bank in the CPU2 subsystem (refer to the device data manual for the size of flash
bank)
• Dedicated flash module controller (FMC) in the CPU1 and CPU2 subsystems for each bank
• 128 bits (bank width) can be programmed at a time along with ECC
• Multiple sectors providing the option of leaving some sectors programmed and only erasing specific
sectors
• User-programmable OTP locations for configuring security, OTP boot-mode and boot-mode select pins
(if the user is unable to use the factory-default boot-mode select pins)
• Single-flash pump shared by the CPU1 and CPU2 subsystems
• Hardware flash pump semaphore to control ownership of the pump between the two FMCs.
• Enhanced performance using the code-prefetch mechanism and data cache in CPU1-FMC and CPU2-
FMC
• Configurable wait states to give the best performance for a given execution speed
• Safety Features
– SECDED-single error correction and double error detection is supported in both FMCs
– Address bits are included in ECC
– Test mode to check the health of ECC logic
• Supports low-power modes for flash bank and pump for power savings
• Built-in power mode control logic
• Integrated flash program/erase state machine (FSM) in both FMCs
– Simple flash API algorithms
– Fast erase and program times (refer to the device data manual for details)
• Code Security Module (CSM) to prevent access to the flash by unauthorized persons (refer to
Section 2.13 for details)
2.12.2 Flash Tools

Texas Instruments provides the following tools for flash:
• Code Composer Studio (CCS) - the development environment with integrated flash plugin
• F021 Flash API Library - a set of software peripheral functions to erase/program flash
• UniFlash - standalone tool to erase/program/verify the flash content through JTAG. No CCS is
required.
• CCS On-Chip Flash Plugin and UniFlash tools developed for these devices support
AutoEccGeneration (see TMS320F2837xD Flash API Version 1.54 Reference Guide , SPNU629). But
they do not support the program of ECC generated by the linker -ecc options.
• Users must check and install available updates for CCS On-Chip Flash Plugin and UniFlash tools.

Flash and OTP Memory www.ti.com
2.12.3 Default Flash Configuration

The following are flash module configuration settings at power-up in both CPU1 and CPU2 subsystems:
• Dedicated flash banks are in sleep power mode
• Shared pump is in sleep mode
• ECC is enabled
• Wait-states are set to the maximum (0xF)
• Code-prefetch mechanism and data cache are disabled in both FMCs
During the boot process, the boot ROM performs a dummy read of the Code Security Module (CSM)
password locations in the OTP. This read is performed to unlock a new (or erased) device that has no
password stored in it, so that flash programming or loading of code into CSM-protected SARAM can be
performed. On devices with a password, this read has no effect and the device remains locked. One effect
of this read is that the flash will transition from the sleep (reset) state to the active state.
User application software must initialize wait-states using the FRDCNTL register, and configure
cache/prefetch features using the RD_INTF_CTRL register, to achieve optimum system performance.
Software that configures flash settings like wait-states, cache/prefetch features, and so on, must be
executed only from RAM memory, not from flash memory.
NOTE: Before initializing wait-states, turn off the pre-fetch and data caching in the FRD_INTF_CTRL
register.
2.12.4 Flash Bank, OTP and Pump

There is a dedicated flash bank in the CPU1 subsystem called the CPU1 flash bank and a dedicated flash
bank in the CPU2 subsystem called the CPU2 flash bank. Also, there is a one-time programmable (OTP)
memory on the CPU1 subsystem called USER OTP, which the user can program only once and cannot
erase. Flash and OTP are uniformly mapped in both program and data memory space.
Both the CPU1 subsystem and CPU2 subsystem have a TI-OTP which contains manufacturing
information like settings used by the flash state machine for erase and program operations, and so on.
Users may read TI-OTP but it cannot be programmed or erased. For memory map and size information of
the CPU1-Bank, CPU1 TI-OTP, CPU1 USER OTP, CPU2 flash bank, CPU2 TI-OTP, CPU2 USER-OTP
and corresponding ECC locations, please refer to the device data manual.
The CPU1 flash bank/USER OTP and CPU2 flash bank/USER OTP share a common flash pump. A
hardware semaphore, called the flash pump semaphore, is provided to control the access of the flash
pump between the CPU1 subsystem and CPU2 subsystem.
Figure 2-22 depicts the user-programmable OTP locations in CPU1 USER-OTP and CPU2 USER-OTP.
For more information on the functionality of these fields, please refer to Section 2.13 and the ROM Code
and Peripheral Booting chapter.
2.12.5 Flash Module Controller (FMC)

There is a dedicated flash module controller in both the CPU1 subsystem (CPU1-FMC) and the CPU2
subsystem (CPU2-FMC). The CPU1 in the CPU1 subsystem interfaces with the CPU1 flash module
controller (CPU1-FMC), which in turn, interfaces with the CPU1 flash bank and shared pump to perform
erase/program operations as well as to read data/execute code from the CPU1 flash bank.

Figure 2-16. FMC Interface with Core, Bank and Pump
CPU2-Bank
CPU2 System Clock
CPU2 Core
CPU2-FMC
Pump
CPU1-FMC
CPU1 Core
Pump Semaphore
CPU1 System Clock
CPU1-Bank
The CPU2 in the CPU2 subsystem interfaces with the CPU2 flash module controller (CPU2-FMC) which in
turn, interfaces with the CPU2 flash bank and shared pump to perform erase/program operations as well
as to read data/execute code from the CPU2 flash bank. Control signals to the flash pump will be
controlled by either CPU2-FMC or CPU1-FMC, depending on who gains the flash pump semaphore.
There is a state machine in both CPU1-FMC and CPU2-FMC which generates the erase/program
sequences in hardware. This simplifies the Flash API software which configures control registers in the
FMC to perform flash erase and program operations (see TMS320F2837xD Flash API Version 1.54
Reference Guide , SPNU629, for details on Flash API).
Section 2.12.6 through Section 2.12.10 describe FMC in detail.
2.12.6 Flash and OTP Power-Down Modes and Wakeup

The flash bank and pump consume a significant amount of power when active. The flash module provides
a mechanism to power-down flash banks and pump. Special timers automatically sequence the power-up
of the CPU1 flash bank and CPU2 flash bank independently of each other. The shared charge pump
module has its own independent power-up timer as well.
The flash bank and OTP operate in three power modes: Sleep (lowest power), Standby, and Active
(highest power)
• Sleep State
This is the state after a device reset. In this state, a CPU data read or opcode fetch will automatically
initiate a change in power mode to the standby state and then to the active state. During this transition
time to the active state, the CPU will automatically be stalled.
• Standby State
This state uses more power than the sleep state, but takes a shorter time to transition to the active or
read state. In this state, a CPU data read or opcode fetch will automatically initiate a change in power
mode to the active state. During this transition time to the active state, the CPU will automatically be
stalled. Once the flash/OTP has reached the active state, the CPU access will complete as normal.
• Active or Read State
In this state, the bank and pump are in active power mode state (highest power)
The charge pump operates in two power modes:
• Sleep (lowest power)
• Active (highest power)

Any access to any flash bank/OTP causes the charge pump to go into active mode, if it is in sleep mode.
An erase or program command causes the charge pump and bank to become active. If any bank is in
active or in standby mode, the charge pump will be in active mode, independent of the pump power mode
control configuration (PMPPWR bit field in the FPAC1 register).
To power down the Flash pump, both the CPU1 and CPU2 must each power down the Flash Pump
without any Flash accesses in between. The Flash Pump will not enter low-power mode if the below
sequence is not followed.
1. When the system is ready to power down the Flash completely, synchronize CPU1 and CPU2. CPU2
will enter its Flash power-down phase (steps 2, 3, 4, and 5) while the CPU1 will be waiting for it to
complete.
2. Acquire the Pump Semaphore with the CPU2.
3. Assign a value of 0x14 to CPU2 VREADST (refer to the FBAC register) to ensure the requisite delay
needed for the flash pump/bank to come out of low-power mode later: FBAC.VREADST = 0x14
4. Change the CPU2 Flash Bank Fall Back power mode to Sleep: FBFALLBACK.BNKPWR = 0.
5. Change the CPU2 Flash Charge Pump Fall Back power mode to Sleep: FPAC1.PMPPWR = 0. CPU2
should notify CPU1 that it has completed the above sequence. It should wait until CPU1 completes
steps 6, 7, 8, 9 and 10.
6. Acquire the Pump Semaphore with the CPU1.
7. Assign a value of 0x14 to CPU1 VREADST (refer to FBAC register) to ensure the requisite delay
needed for the flash pump/bank to come out of low-power mode later: FBAC.VREADST = 0x14
8. Change the CPU1 Flash Bank Fall Back power mode to Sleep: FBFALLBACK.BNKPWR = 0.
9. Change the CPU1 Flash Charge Pump Fall Back power mode to Sleep: FPAC1.PMPPWR = 0.
10. Release the Pump Semaphore from the CPU1. CPU1 should notify CPU2 that it has completed the
power-down sequence so that both subsystems may continue.
The above listed procedure should be executed from RAM and not from Flash. Note that exclusive control
of the Flash pump should be gained by a CPU (using Flash pump semaphore PUMPREQUEST) before
configuring the PMPPWR bit field of the FPAC1 register as shown in the above sequence. As the charge
pump is shared between CPU1-FMC and CPU2-FMC, the effective PMPPWR value used when powering
down the pump will be of the FMC (out of CPU1-FMC and CPU2-FMC) which owns the pump. The
application software can check the current power mode of the flash bank by reading the FBPRDY register.
The PUMPRDY bit in the FBPRDY register in CPU1-FMC and CPU2-FMC together reflect the power
mode of the charge pump. A value of 0 in the PUMPRDY bit in both CPU1-FMC and CPU2-FMC indicates
that the charge pump is in sleep mode. A value of 1 in the PUMPRDY bit in either CPU1-FMC or CPU2-
FMC or in both CPU1-FMC and CPU2-FMC indicates that the charge pump is in active mode. Refer to the
register descriptions, Section 2.15, for detailed information.
While the pump is in sleep state, a charge pump sleep down counter holds a user configurable value
(PSLEEP bit field in the FPAC1 register) and when the charge pump exits sleep power mode, the down
counter delays from 0 to PSLEEP prescaled SYSCLK clock cycles (prescaled clock is SYSCLK/2) before
putting the charge pump into active power mode. Note that the configured PSLEEP value should yield at
least a delay of 20us for the pump to go to active mode. Refer to the register descriptions, Section 2.15,
for detailed information.
Below are the number of cycles it will take for the Bank and pump to wake up from low power modes.
1. Pump sleep to active = PSLEEP * (SYSCLK/2) cycles
2. Bank sleep to standby = 425 Flash clock cycles
3. Bank standby to active = 90 Flash clock cycles
Where in Flash clock = SYSCLK/(RWAIT+1)

2.12.7 Flash and OTP Performance

Once the flash bank and pump are in the active power state, a read or fetch access can be classified as a
flash access (access to an address location in flash) or an OTP access (access to an address location in
OTP). Once the CPU throws an access to a flash memory address, data is returned after RWAIT+1
number of SYSCLK cycles. For a USER-OTP access, data is returned after 11 SYSCLK cycles.
RWAIT defines the number of random access wait-states and is configurable using the RWAIT bit-field in
the FRDCNTL register. At reset, the RWAIT bit-field defaults to a worst-case wait-state count (15), and
therefore needs to be initialized for the appropriate number of wait states to improve performance, based
on the CPU clock rate and the access time of the flash. The flash supports 0-wait accesses when the
RWAIT bits are set to zero. This assumes that the CPU speed is low enough to accommodate the access
time.
For a given system clock frequency, RWAIT has to be configured using below formula:
RWAIT = ceiling[(SYSCLK/FCLK)-1]
where SYSCLK is the system operating frequency

FCLK is flash clock frequency. FCLK should be ≤ FCLKmax, allowed maximum flash clock frequency at
RWAIT=0.
If RWAIT results in a fractional value when calculated using the above formula, RWAIT has to be rounded
up to the nearest integer.
2.12.8 Flash Read Interface

This section provides details about the data read modes to access flash bank/OTP and the configuration
registers which control the read interface. In addition to a standard read mode, the FMC has a built-in
prefetch and cache mechanism to allow increased clock speeds and CPU throughput wherever applicable.
2.12.8.1 FMC Flash Read Interface
2.12.8.1.1 Standard Read Mode

Standard read mode is defined as the read mode in effect when code prefetch-mechanism and data
cache are disabled. It is also the default read mode after reset. During this mode, each read access to
flash is decoded by the flash wrapper to fetch the data from the addressed location and the data is
returned after the RWAIT+1 number of cycles.
Prefetch buffers associated with prefetch mechanism and data cache are bypassed in standard read
mode; therefore, every access to the flash/OTP is used by the CPU immediately, and every access
creates a unique flash bank access.
Standard read mode is the recommended mode for lower system frequency operation in which RWAIT
can be set to zero to provide single-cycle access operation. The FMC can operate at higher frequencies
using standard read mode at the expense of adding wait states. At higher system frequencies, it is
recommended to enable cache and prefetch mechanisms to improve performance. Refer to the device
specific data manual to determine the maximum flash frequency allowed in standard read mode (that is,
maximum flash clock frequency with RWAIT=0, FCLKMAX).
2.12.8.1.2 Prefetch Mode

Flash memory is typically used to store application code. During code execution, instructions are fetched
from sequential memory addresses, except when a discontinuity occurs. Usually the portion of the code
that resides in sequential addresses makes up the majority of the application code and is referred to as
linear code. To improve the performance of linear code execution, a flash prefetch-mechanism has been
implemented in the FMC. Figure 2-17 illustrates how this mode functions.

Figure 2-17. Flash Prefetch Mode

Flash and OTP
16-bit
Flash prefetch
Instruction buffer
Flash or OTP Read (128-bit)
128-bit 128-bit
buffer buffer
Instruction fetch
128-bit
M Data cache
CPU 32-bit U
X
Data read from data memory
This prefetch mechanism does a look-ahead prefetch on linear address increments starting from the
address of the last instruction fetch. The flash prefetch mechanism is disabled by default. Setting the
PREFETCH_EN bit in the FRD_INTF_CTRL register enables this prefetch mode.
An instruction fetch from the flash or OTP reads out 128 bits per access. The starting address of the
access from flash is automatically aligned to a 128-bit boundary, such that the instruction location is within
the 128 bits to be fetched. With the flash prefetch mode enabled, the 128 bits read from the instruction
fetch are stored in a 128-bit wide by 2-level deep instruction prefetch buffer. The contents of this prefetch
buffer are then sent to the CPU for processing as required.
Up to four 32-bit or eight 16-bit instructions can reside within a single 128-bit access. The majority of C28x
instructions are 16 bits, so for every 128-bit instruction fetch from the flash bank, it is likely that there are
up to eight instructions in the prefetch buffer ready to process through the CPU. During the time it takes to
process these instructions, the flash prefetch mechanism automatically initiates another access to the
flash bank to prefetch the next 128 bits. In this manner, the flash prefetch mechanism works in the
background to keep the instruction prefetch buffers as full as possible. Using this technique, the overall
efficiency of sequential code execution from flash or OTP is improved significantly. If the prefetch
mechanism is enabled, then the last row of 128 bits in the bank should not be used, because the prefetch
logic which does a look-ahead prefetch, will try to fetch from outside the bank and would result in an ECC
error.
The flash prefetch is aborted only on a PC discontinuity caused by executing an instruction such as a
branch, BANZ, call, or loop. When this occurs, the prefetch mechanism is aborted and the contents of the
prefetch buffer are flushed. There are two possible scenarios when this occurs:
1. If the destination address is within the flash or OTP, the prefetch aborts and then resumes at the
destination address.
2. If the destination address is outside of the flash and OTP, the prefetch is aborted and begins again
only when a branch is made back into the flash or OTP. The flash prefetch mechanism only applies to
instruction fetches from program space. Data reads from data memory and from program memory do
not utilize the prefetch buffer capability and thus bypass the prefetch buffer. For example, instructions
such as MAC, DMAC, and PREAD read a data value from program memory. When this read happens,
the prefetch buffer is bypassed but the buffer is not flushed. If an instruction prefetch is already in
progress when a data read operation is initiated, then the data read will be stalled until the prefetch
completes.
Note that the prefetch mechanism gets bypassed when RWAIT is configured as zero.
2.12.8.1.2.1 Data Cache

Along with the prefetch mechanism, a data cache of 128 bits wide is also implemented to improve data-
space read performance. This data cache will not be filled by the prefetch mechanism. When any kind of
data-space read is made by the CPU from an address in the bank, and if the data corresponding to the
requested address is not in the data cache, then 128 bits of data will be read from the bank and loaded in
the data cache. This data is eventually sent to the CPU for processing. The starting address of the access
from flash is automatically aligned to a 128-bit boundary such that the requested address location is within
the 128 bits to be read from the bank. By default, this data cache is disabled and can be enabled by
setting DATA_CACHE_EN bit in the FRD_INTF_CTRL register. Note that the data cache gets bypassed
when RWAIT is configured as zero.
Some other points to keep in mind when working with flash/ OTP:
• Reads of the USER OTP locations are hardwired for 10 wait states. The RWAIT bits have no effect on
these locations.
• CPU writes to the flash or OTP memory map areas are ignored. They complete in a single cycle.
• If a security zone is in the locked state and the respective password lock bits are not all 1s, then,
– Data reads to Zx-CSMPSWD will return 0
– Program space reads to Zx-CSMPSWD will return 0
– Program fetches to Zx-CSMPSWD will return 0
.
• When the Code Security Module (CSM) is secured, reads to the flash/OTP memory map area from
outside the secure zone take the same number of cycles as a normal access. However, the read
operation returns a zero.
• The arbitration scheme in FMC prioritizes CPU accesses in the fixed priority order of data read
(highest priority), program space read and program fetches/program prefetches (lowest priority).
• When FSM interface is active for erase/program operations, data in the prefetch buffers and data
cache in FMC will be flushed.
• When data cache is enabled, the debugger memory window open to Flash/OTP space will invoke data
caching. Hence, debugger memory window should not be left open for Flash/OTP space when
benchmarking the code for performance.
2.12.9 Erase/Program Flash

Flash memory may be programmed either by using the CCS Flash plugin or by using Uniflash. If these
methods are not feasible in an application, the API may be used. The Flash memory should be
programmed, erased, and verified only by using the F021 Flash API library. These functions are written,
compiled and validated by Texas Instruments. The flash module contains a flash state machine (FSM) to
perform program and erase operations. This section only provides a high level description for these
operations, therefore, refer to the TMS320F2837xD Flash API Version 1.54 Reference Guide (SPNU629)
for more information. Note that Flash API execution is interruptible. However, there should not be any
read/fetch access from the Flash bank on which an erase/program operation is in progress. Flash API
must be executed from RAM.
A typical flow to program flash is:
Erase → Program → Verify
Always refer to the device-specific support folder in controlSUITE™ for the latest Flash API library.

2.12.9.1 Erase
When the target flash is erased, it reads as all 1's. This state is called 'blank.' The erase function must be
executed before programming. The user should NOT skip erase on sectors that read as 'blank' because
these sectors may require additional erasing due to marginally erased bits columns. The FSM provides an
“Erase Sector” command to erase the target sector. The erase function erases the data and the ECC
together. This command is implemented by the following Flash API function:
Fapi_issueAsyncCommandWithAddress();
The Flash API provides the following function to determine if the flash bank is 'blank':
Fapi_doBlankCheck();
2.12.9.2 Program
The FSM provides a command to program the USER OTP and Flash. This command is also used to
program ECC check bits.
This command is implemented by the following Flash API function:
Fapi_issueProgrammingCommand();
The Program function provides the options to program data without ECC, data along with user-provided
ECC data, data along with ECC calculated by API software , and to program ECC only.
2.12.9.3 Verify
After programming, the user must perform verify using API function Fapi_doVerify(). This function verifies
the flash contents against supplied data.
Application software typically perform a CRC check of the Flash memory contents during power-up and at
regular intervals during runtime (as needed). Apart from this, ECC logic, when enabled (enabled by
default), catches single-bit errors, double-bit errors, and address errors whenever the CPU reads/fetches
from a Flash address.
2.12.10 Error Correction Code (ECC) Protection

CPU1-FMC and CPU2-FMC contain an embedded single error correction and double error detection
(SECDED) module. SECDED, when enabled, provides the capability to screen out memory faults.
SECDED can detect and correct single-bit data errors and detect address errors/double-bit data errors.
For every 64 bits of flash/OTP data (aligned on a 64-bit memory boundary) that is programmed, eight ECC
check bits have to be calculated and programmed in ECC memory space. Refer to the device data
manual for the Flash/OTP ECC memory map. SECDED works with a total of eight user-calculated error
correction code (ECC) check bits associated with each 64-bit wide data word and its corresponding 128-
bit memory-aligned address. Users must program ECC check bits along with flash data. TI recommends
using the AutoEccGeneration option available in Plugin/API to program ECC. Users can use the F021
Flash API to calculate and program ECC data along with flash data. Flash API uses hardware ECC logic
in the device to generate the ECC data for the given Flash data. The Flash Plugin, the Flash programming
tool integrated with Code Composer Studio, uses Flash API to generate and program ECC data).
Figure 2-18 illustrates the ECC logic inputs and outputs.

Figure 2-18. ECC Logic Inputs and Outputs
Single-bit data error

Address/Double-bit data error
Single-bit Error position
Corrected data out
SECDED ECC[15:8]
Data[127:64]
128-bit aligned 19-bit CPU address

Flash
and
OTP
Single-bit data error

Address/Double-bit data error
Single-bit Error position
Corrected data out
SECDED Data[63:0]
ECC[7:0]
During an instruction fetch or a data read operation, the 19 most significant address bits (three least
significant bits of address are not considered), together with the 64-bit data/8-bit ECC read-out of flash
banks/ECC memory map area, pass through the SECDED logic and the eight checkbits are produced in
FMC. These eight calculated ECC check bits are then XORed with the stored check bits (user
programmed check bits) associated with the address and the read data. The 8-bit output is decoded inside
the SECDED module to determine one of three conditions:
• No error occurred
• A correctable error (single bit data error) occurred
• A non-correctable error (double bit data error or address error) occurred
If the SECDED logic finds a single-bit error in the address field, then it is considered to be a non-
correctable error.
NOTE: Since ECC is calculated for an entire 64-bit data, a non 64-bit read such as a byte read or a
half-word read will still force the entire 64-bit data to be read and calculated, but only the
byte or half-word will be actually used by the CPU.
This ECC (SECDED) feature is enabled at reset. The ECC_ENABLE register can be used to configure(
enable/disable) the ECC feature. The ECC for the application code must be programmed.. There are two
SECDED modules in each FMC. Out of the 128-bit data (aligned on a 128-bit memory boundary) read
from the bank/OTP address, the lower 64-bits of data and corresponding 8 ECC bits (read from user
programmable ECC memory area) are fed as inputs to one SECDED module along with 128-bit aligned
19-bit address from where data has been read. The upper 64- bits of data and corresponding 8 ECC bits
are fed as inputs to another SECDED module in parallel, along with 128-bit aligned 19-bit address. Each
of the SECDED modules evaluate their inputs and determine if there is any single-bit data error or double-
bit data error/address error.
ECC logic will be bypassed when the 64 data bits and the associated ECC bits fetched from the bank are
either all ones or zeros.

2.12.10.1 Single-Bit Data Error

This section provides information for both single-bit data errors and single-bit ECC check bit errors. If
there is a single bit flip (0 to 1 or 1 to 0) in flash data or in ECC data, then it is considered as a single-bit
data error. The SECDED module detects and corrects single-bit errors, if any, in the 64-bit flash data or
eight ECC check bits read from the flash/ECC memory map before the read data is provided to the CPU.
When SECDED finds and corrects single bit data errors, the following information is logged in the ECC
registers if the ECC feature is enabled:
• Address where the error occurred – if the single-bit error occurs in the lower 64-bits of a 128-bit
memory-aligned data, the lower 64-bit memory-aligned address will be captured in the
SINGLE_ERR_ADDR_LOW register. If the single-bit error occurs in the upper 64-bits of a 128-bit
memory-aligned data, the upper 64-bit memory-aligned address will be captured in the
SINGLE_ERR_ADDR_HIGH register.
• Whether the error occurred in data bits or ECC bits – the ERR_TYPE_L and ERR_TYPE_H bit fields in
the ERR_POS register indicate whether the error occurred in data bits or ECC bits of the lower 64-bits,
or the upper 64-bits respectively, of a 128-bit memory-aligned data.
• Bit position at which error occurred – the ERR_POS_L and ERR_POS_H bit fields in the ERR_POS
register indicate the bit position of the error in the lower 64-bits/lower 8-bit ECC, or the upper 64-
bits/upper 8-bit ECC respectively, of a 128-bit memory-aligned data.
• Whether the corrected value is 0 (FAIL_0_L, FAIL_0_H flags in ERR_STATUS register)
• Whether the corrected value is 1 (FAIL_1_L, FAIL_1_H flags in ERR_STATUS register)
• A single bit error counter that increments on every single bit error occurrence (ERR_CNT register) until
a user-configurable threshold (see ERR_THRESHOLD) is met
• A flag that gets set when one or more single-bit errors occurs after ERR_CNT equals
ERR_THRESHOLD (SINGLE_ERR_INT_FLG flag in the ERR_INTFLG register)
When the ERR_CNT value equals THRESHOLD+1 value and a single bit error occurs, the
SINGLE_ERR_INT flag is set, and an interrupt (FLASH_CORRECTABLE_ERR on C28x PIE has to be
enabled for interrupt, if needed) is fired. The SINGLE_ERR interrupt will not be fired again until the
SINGLE_ERR_INTFLG is cleared. If the single error interrupt flag is not cleared using the corresponding
error interrupt clear bit in the ERR_INTCLR register, the error interrupt will not come again, as this is an
edge-based interrupt.
When multiple single-bit errors get caught by ECC logic, Flash ECC registers will hold the information
related to the latest ECC error. When multiple single-bit errors get caught, both FAIL_0_L and FAIL_1_L
(and/or FAIL_0_H and FAIL_1_H) might get set, indicating that single-bit fail0/fail1 occurred in different 64-
bit aligned addresses.
Although ECC is calculated on 64-bit basis, a read of any address location within a 128-bit aligned Flash
memory will cause the single-bit error flag to get set when there is a single-bit error in both or in either one
of the lower 64 and upper 64 bits (or corresponding ECC check bits) of that 128-bit data.
2.12.10.2 Uncorrectable Error

Uncorrectable errors include address errors and double-bit errors in data/ECC. When SECDED finds
uncorrectable errors, the following information is logged in ECC registers if the ECC feature is enabled:
• Address where the error occurred – if the uncorrectable error occurs in the lower 64-bits of a 128-bit
memory-aligned data, the lower 64-bit memory-aligned address will be captured in the
UNC_ERR_ADDR_LOW register. If the uncorrectable error occurs in the upper 64-bits of a 128-bit
memory-aligned data, the upper 64-bit memory-aligned address will be captured in the
UNC_ERR_ADDR_HIGH register.
• A flag is set indicating that an uncorrectable error occurred – the UNC_ERR_L and UNC_ERR_H flags
in the ERR_STATUS register indicate the uncorrectable error occurrence in the lower 64-bits/lower 8-
bit ECC, or the upper 64-bits/upper 8-bit ECC, respectively, of a 128-bit memory-aligned data.
• A flag is set indicating that an uncorrectable error interrupt is fired (UNC_ERR_INTFLG in
ERR_INTFLG register)

When an uncorrectable error occurs, the UNC_ERR_INTFLG bit is set and an uncorrectable error interrupt
is fired. This uncorrectable error interrupt generates an NMI, if enabled. If an uncorrectable error interrupt
flag is not cleared using the corresponding error interrupt clear bit in the ERR_INTCLR register, an error
interrupt will not come again, as this is an edge based interrupt.
Although ECC is calculated on 64-bit basis, a read of any address location within a 128-bit aligned Flash
memory will cause the uncorrectable error flag to get set when there is a uncorrectable error in both or in
either one of the lower 64 and upper 64 bits (or corresponding ECC check bits) of that 128-bit data. NMI
will occur on the CPU for a read of any address location within a 128-bit aligned Flash memory, when
there is an uncorrectable error in both or in either one of the lower 64 and upper 64 bits (or corresponding
ECC check bits) of that 128-bit data.
2.12.10.3 SECDED Logic Correctness Check

Since error detection and correction logic are part of safety-critical logic, safety applications may need to
ensure that the SECDED logic is always working properly. For these safety concerns, in order to ensure
the correctness of the SECDED logic, an ECC test mode is provided to test the correctness of ECC logic
periodically. In this ECC test mode, data/ECC and address inputs to the ECC logic are controlled by the
ECC test mode registers FDATAH_TEST, FDATAL_TEST, FECC_TEST, and FADDR_TEST,
respectively. Using this test mode, users can introduce single-bit errors, double-bit errors, or address
errors and check whether or not SECDED logic is catching those errors. Users can also check if SECDED
logic is reporting any false errors when no errors are introduced.
This ECC test mode can be enabled by setting the ECC_TEST_EN bit in the FECC_CTRL register. When
ECC test mode is enabled, the CPU cannot read the data from flash and instead the CPU gets data from
the ECC test mode registers (FDATAH_TEST/FDATAL_TEST). This is because ECC test mode registers
(FDATAH_TEST, FDATAL_TEST, FECC_TEST) are multiplexed with data from the flash. Hence, the CPU
should not read/fetch from Flash when ECC test mode is enabled. For this reason, ECC test mode code
should be executed from RAM and not from flash.
Only one of the SECDED modules (out of the two SECDED modules that work on lower 64 bits and upper
64 bits of a read 128-bit data) at a time can be tested. The ECC_SELECT bit in the FECC_CTRL register
can be configured by users to select one of the SECDED modules for test.
To test the ECC logic using ECC test mode, users can follow the steps below:
1. Obtain the ECC for a given Flash address (128-bit aligned) and 64-bit data by using the Auto ECC
generation option provided in Flash API .
2. Develop an application to test ECC logic using the above data. In this application
• Write the 128-bit aligned 19-bit Flash address in FADDR_TEST
• Write 64-bit data in FDATAx_TEST (FDATAL_TEST or FDATAH_TEST depending on which ECC
logic the user wants to test) register
• Write the corresponding 8-bit ECC in the FECC_TEST register
• In any of the above three steps, users can insert errors (single-bit data error or double-bit data
error or address error or single-bit ECC error or double-bit ECC error) so that they can check
whether or not ECC logic is able to catch the errors
• Select the ECC logic block (lower 64-bits or upper 64-bits) which needs to be tested using the
ECC_SELECT bit in the FECC_CTRL register
• Enable ECC test mode usingthe ECC_TEST_EN bit in FECC_CTRL register
• Write a value of 1 in the DO_ECC_CALC bit in FECC_CTRL register to enable ECC test logic for a
single cycle to evaluate the address, data, ECC in FADDR_TEST, FDATAx_TEST and
FECC_TEST registers for ECC errors
Once the above ECC test mode registers are written by the user:
• The FECC_OUTH register holds the data output bits 63:32 from the SECDED block under test
• The FECC_OUTL register holds the data output bits 31:0 from the SECDED block under test
• The FECC_STATUS register holds the status of single-bit error occurrence, uncorrectable error
occurrence, and error position of single- bit error in data/check bits

2.12.10.4 Reading ECC Memory From a Higher Address Space

In these devices, ECC memory for Flash and OTP is allocated at a higher address space (address width
more than 22 bits). C2000 Codegen tools (6.2 and onwards) are updated to include the below intrinsics to
read ECC space.
For 16-bit read:
unsigned int variable = __addr32_read_uint16(unsigned long address);
For 32-bit read:
unsigned long variable = __addr32_read_uint32(unsigned long address);
2.12.11 Reserved Locations Within Flash and OTP

When allocating code and data to flash and OTP memory, keep the following reserved locations in mind:
• The entire OTP has reserved user-configurable locations for security and boot process. For more
details on the functionality of these fields, please refer to Section 2.13, and the ROM Code and
Peripheral Booting chapter.
• Refer to the ROM Code and Peripheral Booting chapter for reserved locations in flash for real-time
operating system usage and a boot-to-flash entry point. A boot-to-flash entry point is reserved for an
entry-into-flash branch instruction. When the boot-to-flash boot option is used, the boot ROM will jump
to this address in flash. If the user programs a branch instruction here, that will then redirect code
execution to the entry point of the application.
2.12.12 Procedure to Change the Flash Control Registers

During flash configuration, no accesses to the flash or OTP can be in progress. This includes instructions
still in the CPU pipeline, data reads, and instruction prefetch operations. To be sure that no access takes
place during the configuration change, you should follow the procedure shown below for any code that
modifies the flash control registers.
1. Start executing application code from RAM/Flash/OTP.
2. Branch to or call the flash configuration code (that writes to flash control registers) in RAM. This is
required to properly flush the CPU pipeline before the configuration change. The function that changes
the flash configuration cannot execute from the Flash or OTP. It must reside in RAM.
3. Execute the flash configuration code (should be located in RAM) that writes to flash control registers
like FRDCNTL, FRD_INTF_CTRL, and so on.
4. At the end of the flash configuration code execution, wait eight cycles to let the write instructions
propagate through the CPU pipeline. This must be done before the return-from-function call is made.
5. Return to the calling function which might reside in RAM or Flash/OTP and continue execution.
2.12.13 Flash Pump Ownership Semaphore

Each CPU subsystem has its own flash bank, which it can read, program, and erase. Both flash banks
share a single charge pump for program and erase operations. Hence, only one CPU can program or
erase its flash at any given time. A CPU can read data and execute code from its flash even when the
other CPU is programming or erasing. The flash pump ownership semaphore allows one CPU to take
control of the pump without being interrupted by the other CPU.
The pump ownership semaphore is implemented as a two-bit field in a PUMPREQUEST register with
special write protections. This register requires a key field to be written at the same time as the
semaphore bits. The possible semaphore states are:
00 or 11 Either CPU may write to the semaphore. CPU1 has control of the resource by
default. 00 is the reset state.
01 CPU2 has exclusive control of the resource and exclusive write access to the
semaphore.
10 CPU1 has exclusive control of the resource and exclusive write access to the
semaphore.

Each CPU is only allowed to take control of the pump for itself. Direct transfer between the 01 and 10
states is not allowed. However, CPU1 may force both semaphores into the default state (00) at any time
by putting CPU2 into reset. Figure 2-19 shows the allowed states and state transitions.
Figure 2-19. Flash Pump Semaphore (PUMPREQUEST) States and State Transitions
CPU1 should write 10 to gain pump CPU2 should write 01 to gain pump
control before erasing or programming Semaphore state 00 or 11 control before erasing or programming
its flash bank. its flash bank.
Pump controlled by CPU1
CPU1 should write 00 to relinquish Default at reset

CPU2 should write 00 to relinquish
pump control once the erase or
pump control once the erase or
program is complete.
program is complete.
Semaphore state 10 Semaphore state 01

Not allowed
Pump controlled by CPU1 Pump controlled by CPU2
Not allowed
CPU2 cannot take control of the pump in this CPU1 cannot take control of the pump in this
state. state.
2.12.13.1 Clock Configuration Semaphore

Both CPUs can access the PLL and peripheral clock configuration registers. The clock configuration
semaphore allows one CPU to access the registers without being interrupted by the other CPU.
The clock configuration semaphore is implemented as a two-bit field in a register with special write
protections. This register requires a key field to be written at the same time as the semaphore bits. The
possible semaphore states are:
00 or 11 Either CPU may write to the semaphore. CPU1 has control of the clock
configuration registers by default. 00 is the reset state.
01 CPU2 has exclusive control of the clock configuration registers and exclusive
write access to the semaphore.
10 CPU1 has exclusive control of the clock configuration registers and exclusive
write access to the semaphore.
Each CPU is only allowed to take control of the clock configuration registers for itself. However, CPU1
may force both semaphores into the default state (00) at any time by putting CPU2 into reset. Figure 2-20
shows the allowed states and state transitions.
Figure 2-20. Clock Configuration Semaphore (CLKSEM) State Transitions

CPU1 should write 10 to gain CPU2 should write 01 to gain
mastership of the clock configuration Semaphore state 00 or 11 mastership of the clock configuration
registers. registers.
Clock configuration registers
are controlled by CPU1
CPU1 should write 00 to relinquish
Default at reset CPU2 should write 00 to relinquish
mastership once configuration is
mastership once configuration is
complete.
complete.
Semaphore state 10 Semaphore state 01

Not allowed
Clock configuration registers Clock configuration registers
are controlled by CPU1 Not allowed are controlled by CPU2
CPU2 cannot take control of the pump in this CPU1 cannot take control of the pump in this
state state

Dual Code Security Module (DCSM) www.ti.com
2.13 Dual Code Security Module (DCSM)

The dual code security module (DCSM) is a security feature incorporated in this device. It prevents access
and visibility to on-chip secure memories (and other secure resources) to unauthorized persons. It also
prevents duplication and reverse engineering of proprietary code. The term “secure” implies access to on-
chip secure memories and resources are blocked. The term “unsecure” implies access is allowed (the
contents of the memory could be read by any means); for example, through a debugging tool such as
Code Composer Studio™.
There are two CPUs on this device and each CPU subsystem has its own CSM for code protection. Each
CPU subsystem’s CSM has dual-zone security, which means the CPU1 subsystem has two zones
(zone1/zone2) and CPU2 also has two zones (zone1/zone2).
2.13.1 Functional Description

The security module restricts the CPU access to on-chip secure memory and resources without
interrupting or stalling CPU execution. When a read occurs to a secure memory location, the read returns
a zero value and CPU execution continues with the next instruction. This, in effect, blocks read and write
access to secure memories through the JTAG port or external peripherals.
The code security mechanism offers protection for two zones, Zone 1 (Z1) and Zone 2 (Z2). The security
mechanism for both the zones is identical. Each zone has its own dedicated secure resource and
allocated secure resource. The following are different secure resources available on this device:
• OTP: Each zone has its own dedicated secure OTP (USER OTP). This contains the security
configurations for the individual zone. If a zone is secure, its USER OTP content (including CSM
passwords) can be read (execution not allowed) only if the zone is unlocked using the password match
flow (PMF).
• CLA: The CLA is a secure resource which can be allocated to either zone by configuring the
GRABRAM location in the USER OTP. CLA configuration can only be performed by code running from
the zone to which it has been allocated. The CLA message RAMs also belong to the same zone.
• RAM: All Dx and LSx RAMs can be secure RAM on this device. These RAMs can be allocated to
either zone by configuring the respective GRABRAM location in the USER OTP.
• Flash Sectors: Flash Sectors can be secure on this device. Each Flash sector can be allocated to
either zone by configuring the respective GRABSECT location in the USER OTP.
• Secure ROM: This device also has secure ROM which is EXEONLY-protected. This ROM contains
specific function for the user, provided by TI.
Table 2-14 shows the status of a RAM block based on the configuration in GRABRAM register.
Table 2-14. RAM Status

GRAM_RAMx Bits in Z1_GRABRAMR GRAM_RAMx Bits in Z2_GRABRAMR
Register Register Ownership
00 XX GRAM_RAMx is inaccessible
XX 00 GRAM_RAMx is inaccessible
Differential Value (01/10) Differential Value (01/10) GRAM_RAMx is inaccessible
Differential Value (01/10) 11 GRAM_RAMx belongs to Z1
11 Differential Value (01/10) GRAM_RAMx belongs to Z2
11 11 GRAM_RAMx is Non-Secure
The security of each zone is ensured by its own 128-bit (four 32-bit words) password (CSM password).
The password for each zone is stored in its dedicated OTP location based on a zone-specific link pointer.
A zone can be unsecured by executing the password match flow (PMF), described in Section 2.13.3.3.2.
There are three types of accesses: data/program reads, JTAG access, and instruction fetches (calls,
jumps, code executions, ISRs). Instruction fetches are never blocked. JTAG accesses are always blocked
when a memory is secure. Data reads to a secure memory are always blocked unless the program is
executing from a memory which belongs to the same zone. Data reads to unsecure memory are always
allowed. Table 2-15 shows the levels of security.

www.ti.com Dual Code Security Module (DCSM)
Table 2-15. Security Levels

PMF Executed With Correct
Password? Operating Mode of the Zone Program Fetch Location Security Description
No Secure Outside secure memory Only instruction fetches by the
CPU are allowed to secure
memory. In other words, code
can still be executed, but not
read.
No Secure Inside secure memory CPU has full access (except for
EXEONLY memories where
read is not allowed). JTAG port
cannot read the secured
memory contents.
Yes Non-Secure Anywhere Full access for CPU and JTAG
port to secure memory of that
zone.
If the password locations of a zone have all 128 bits as ones, the zone is considered unsecure. Since new
Flash devices have erased Flash (all ones), only a read of the password locations is required to bring any
zone into unsecure mode. If the password locations of a zone have all 128 bits as zeros, the zone is
secure, regardless of the contents of the CSMKEY registers. This means the zone can’t be unlocked using
PMF, the password match flow described in Section 2.13.3.3.2. Therefore, the user should never use all
zeros as a password. A password of all zeros will prevent debug of secure code or reprogramming the
Flash.
CSMKEY registers are user-accessible registers that are used to unsecure the zones.
2.13.1.1 Emulation Code Security Logic (ECSL)

In addition to the CSM, the emulation code security logic (ECSL) has been implemented using a 64-bit
password (part of existing CSM password) for each zone to prevent unauthorized users from stepping
through secure code. A halt in secure code while the emulator is connected will trip the ECSL and break
the emulation connection to the specific CPU subsystem for which the ECSL violation occurred. To allow
emulation of secure code, while maintaining the CSM protection against secure memory reads, the user
must write the correct 64-bit password into the CSMKEY (0/1) registers, which matches the password
value stored in the USER OTP of that zone. This will disable the ECSL for the specific zone.
When initially debugging a device with the password locations in OTP programmed (secured), the
emulator takes some time to take control of the CPU. During this time, the CPU will start running and may
execute an instruction that performs an access to a protected ECSL area and ifthe CPU is halted when
the program counter (PC) is pointing to a secure location, the ECSL will trip and cause the emulator
connection to be broken.
The solution to this problem is:
• Use the Wait Boot Mode boot option. In this mode, the CPU will be in a loop and hence will not jump to
the user application code. Using this BOOTMODE, the user can connect to CCS and debug the code.
2.13.1.2 CPU Secure Logic

The CPU Secure Logic (CPUSL) on this device prevents a hacker from reading the CPU registers in a
watch window while code is running in a secure zone. All accesses to CPU registers when the PC points
to a secure location are blocked by this logic. The only exception to this is read access to the PC. It is
highly recommended not to write into the CPU register in this case, because proper code execution may
get affected. If the CSM is unlocked using the CSM password match flow, the CPUSL logic also gets
disabled.

2.13.1.3 Execute-Only Protection

To achieve a higher level of security on secure Flash sectors and RAM blocks that store critical user code
(instruction opcodes), the Execute-Only protection feature is provided. When the Execute-Only protection
is turned on for any secure Flash sector or RAM block, data reads to that Flash sectors are disallowed
from any code (even from secure code). Execute-only protection for a Flash sector and RAM block can be
turned on by configuring the bit field associated for that particular sector/RAM block in the zone's (which
has ownership of that sector/RAM block) EXEONLYSECT and EXEONLYRAM register, respectively.
2.13.1.4 Password Lock

The password locations for each zone can be locked by programming the zone’s PSWDLOCK field with
any value other than “1111” (0xF) at the PSWDLOCK location in OTP. Until the passwords of a zone are
locked, password locations will not be secure and can be read from the debugger as well as code running
from non-secure memory. This feature can be used by the user to avoid accidental locking of the zone
while programming the Flash sectors during the software development phase. On a fresh device the value
for password lock fields for all zones at the PSWDLOCK location in OTP will be “1111” which means the
password for all zones will be unlocked.
NOTE: Password unlock only makes password locations non-secure. All other secure memories and
other locations of Flash sectors, which contain a password, remains secure as per security
settings. But since passwords are non-secure, anyone can read the password and make the
zone non-secure by running through PMF.
2.13.1.5 Link Pointer and Zone Select

For each of the two security zones of each CPU subsystem on this device, a dedicated OTP block exists
that holds the configuration related to zone’s security. The following are the available programmed
configurations:
• Zx-LINKPOINTER1
• Zx-LINKPOINTER2
• Zx-LINKPOINTER3
• Zx-PSWDLOCK
• Zx-CRCLOCK
• Zx-BOOTCTRL
• Zx-EXEONLYRAM
• Zx-EXEONLYSECT
• Zx-GRABRAM
• Zx-GRABSECT
• Zx-CSMPASSWORD
Since OTP can’t be erased, to provide flexibility of configuring some of the security settings like CSM
passwords, allocation of RAM/Flash sectors and their attributes, multiple times by the user, the following
configurations are placed in zone select regions of each zone’s OTP Flash.
• Zx-EXEONLYRAM
• Zx-EXEONLYSECT
• Zx-GRABRAM
• Zx-GRABSECT
• Zx-CSMPASSWORD
The location of the zone select region in OTP is decided based on the value of three 29-bit link pointers
(Zx-LINKPOINTERx) programmed in the OTP of each zone of both CPU subsystems. All OTP locations
except link pointer locations are protected with ECC. Since the link pointer locations are not protected with
ECC, three link pointers are provided that need to be programmed with the same value. The final value of
the link pointer is resolved in hardware when a dummy read is done to all the link pointers by comparing

all the three values (bit-wise voting logic). Since in OTP, a ‘1’ can be flipped by the user to ‘0’ but ‘0’ can’t
be flipped to ‘1’ (no erase operation for OTP), the most significant bit position in the resolved link pointer
which is ‘0’, defines the valid base address for the zone select region. While generating the final link
pointer value, if the bit patterns is not one of those listed in Figure 2-21, the final link pointer value
becomes All_1 (0xFFFF_FFFF) which selects the Zone-Select-Block1 (also known as the default zone
select block).
Figure 2-21. Storage of Zone-Select Bits in OTP

Addr Offset Of
Zx-LINKPOINTER Zone-Select
Block
32’bxxx11111111111111111111111111111 0x20
32’bxxx1111111111111111111111111111 0 0x30
32’bxxx111111111111111111111111111 0x 0x40
32’bxxx11111111111111111111111111 0xx 0x50
32’bxxx1111111111111111111111111 0xxx 0x60
32’bxxx111111111111111111111111 0xxxx 0x70 Zone Select Block
32’bxxx11111111111111111111111 0xxxxx 0x80
32’bxxx1111111111111111111111 0xxxxxx 0x90 Addr Offset 32-Bit Content
32’bxxx111111111111111111111 0xxxxxxx 0xa0
0x0 Zx-EXEONLYRAM
32’bxxx11111111111111111111 0xxxxxxxx 0xb0
32’bxxx1111111111111111111 0xxxxxxxxx 0xc0 0x2 Zx-EXEONLYSECT
32’bxxx111111111111111111 0xxxxxxxxxx 0xd0
32’bxxx11111111111111111 0xxxxxxxxxxx 0xe0 0x4 Zx-GRABRAM
32’bxxx1111111111111111 0xxxxxxxxxxxx 0xf0
32’bxxx111111111111111 0xxxxxxxxxxxxx 0x100 0x6 Zx-GRABSECT
32’bxxx11111111111111 0xxxxxxxxxxxxxx 0x110
0x8 Zx-CSMPSWD0
32’bxxx1111111111111 0xxxxxxxxxxxxxxx 0x120
32’bxxx111111111111 0xxxxxxxxxxxxxxxx 0x130 0xa Zx-CSMPSWD1
32’bxxx11111111111 0xxxxxxxxxxxxxxxxx 0x140
32’bxxx1111111111 0xxxxxxxxxxxxxxxxxx 0x150 0xc Zx-CSMPSWD2
32’bxxx111111111 0xxxxxxxxxxxxxxxxxxx 0x160
32’bxxx11111111 0xxxxxxxxxxxxxxxxxxxx 0x170 0xe Zx-CSMPSWD3
32’bxxx1111111 0xxxxxxxxxxxxxxxxxxxxx 0x180
32’bxxx111111 0xxxxxxxxxxxxxxxxxxxxxx 0x190
32’bxxx11111 0xxxxxxxxxxxxxxxxxxxxxxx 0x1a0
32’bxxx1111 0xxxxxxxxxxxxxxxxxxxxxxxx 0x1b0
32’bxxx111 0xxxxxxxxxxxxxxxxxxxxxxxxx 0x1c0
32’bxxx11 0xxxxxxxxxxxxxxxxxxxxxxxxxx 0x1d0
32’bxxx10xxxxxxxxxxxxxxxxxxxxxxxxxxx 0x1e0
32’bxxx0xxxxxxxxxxxxxxxxxxxxxxxxxxxx 0x1f0
NOTE: Address locations for other security settings (PSWDLOCK/CRCLOCK) that are not part of
Zone Select blocks) can be programmed only once; therefore, the user should program them
towards end of the development cycle.

Figure 2-22. Location of Zone-Select Block Based on Link-Pointer

Zone 1 OTP Flash Zone 2 OTP Flash
0x78000 Z1-LINKPOINTER 1 0x78200 Z2-LINKPOINTER 1
0x78002 Reserved 0x78202 Reserved
0x7800A Reserved 0x7820A Reserved
0x78010 Z1-PSWDLOCK 0x78210 Z2 PSWDLOCK
Zone Select Block
Addr 32-Bit Content
0x78014 Z1-CRCLOCK 0x78214 Z2-CRCLOCK
Offset
0x0 Zx-EXEONLYRAM
0x2 Zx-EXEONLYSECT
0x7801A Reserved 0x7821A Reserved
0x4 Zx-GRABRAM
0x7801E Z1-BOOTCTRL 0x7821E Z2-BOOTCTRL
0x78020 ZoneSelectBlock1 0x6 Zx-GRABSECT 0x78220 ZoneSelectBlock1
(16x16Bits) (16x16Bits)
0x8 Zx-CSMPSWD0
0x78030 ZoneSelectBlock2 0xa Zx-CSMPSWD1 0x78230 ZoneSelectBlock2
0xc Zx-CSMPSWD2
. .
. 0xe Zx-CSMPSWD3 .
0x781F0 ZoneSelectBlockn 0x783F0 ZoneSelectBlockn

2.13.1.5.1 C Code Example to get Zone Select Block Addr for Zone1
unsigned long LinkPointer;
unsigned long *Zone1SelBlockPtr;
int Bitpos = 28;
int ZeroFound = 0;
// Read Z1-Linkpointer register of DCSM module.

LinkPointer = *(unsigned long *)0x5F000;
// Bits 31 30 and 29 as most-sigificant 0 are reserved LinkPointer options
LinkPointer = LinkPointer << 2;
while ((ZeroFound == 0) && (bitpos > -1))

{
if ((LinkPointer & 0x80000000) == 0)
{
ZeroFound = 1;
Zone1SelBlockPtr = (unsigned long *)(0x78000 + ((bitpos + 3)*16));
} else
{
bitpos--;
LinkPointer = LinkPointer << 1;
}
}
if (ZeroFound == 0)
{

//Default in case there is no zero found.
Zone1SelBlockPtr = (unsigned long *)0x78020;
}
2.13.1.6 Flash and OTP Erase/Program

On this device, OTP as well as normal Flash, are secure resources. Each zone has its own dedicated
OTP, whereas normal Flash sectors can be allocated to any zone based on the value programmed in the
GRABSECT location in OTP. Each zone has its own CSM passwords; read and write accesses are not
allowed to resources owned by Z1 from code running from memory allocated to Z2 and vice versa. Before
programming any secure Flash sector, the user must either unlock the zone to which that particular sector
belongs, using PMF or execute the Flash programming code from secure memory which belongs to the
same zone. The same is the case for erasing any secure Flash sector. To program the security settings in
OTP Flash, the user must unlock the CSM of the respective zone. Unless the zone is unlocked, security
settings in OTP Flash cannot be updated. The OTP content cannot be erased.
This device has only one Flash pump used for erase/program operation of normal Flash and OTP Flash. A
semaphore mechanism is provided to avoid the conflict between Zone1 and Zone2. A zone needs to grab
this semaphore to successfully complete the erase/program operation on the Flash sectors allocated to
that zone. A semaphore can be grabbed by a zone by writing the appropriate value in the SEM field of the
FLSEM register. For further details of this field, see the register description.
NOTE: If there is a loss of power or a reset of any nature during the flash programming operation,
there is high probability of some (or possibly all) of the 128 bits in the corresponding 128-bit
aligned address getting corrupted. If this happens while programming the password locations
in USER OTP, the passwords may get corrupted.
2.13.1.7 Safe Copy Code

In some applications, the user may want to copy the code from secure Flash to secure RAM for better
performance. The user cannot do this for EXEONLY flash sectors because EXEONLY secure memories
cannot be read from anywhere. TI provides specific “Safe Copy Code” library functions for each zone to
enable the user to copy content from EXEONLY secure flash sectors to EXEONLY RAM blocks. These
functions do the copy-code operation in a highly secure environment and allow a copy to be performed
only when the following conditions are met:
• The secure RAM block and the secure flash sector belong to the same zone.
• Both the secure RAM block and the secure flash sector have EXEONLY protection enabled.
For further usage of these library functions, see the device-specific Boot ROM documentation.
2.13.1.8 SafeCRC
Since reads from EXEONLY memories are not allowed, the user cannot calculate the CRC for content in
EXEONLY memories using the VCU-II. But in some safety-critical applications, the user may have to
calculate the CRC on these memories as well. To enable this without compromising on security, TI
provides specific “SafeCRC” library functions for each zone. These functions do the CRC calculation in
highly secure environment and allow a CRC calculation to be performed only when the following
conditions are met:
• The source address should be modulo the number of words (based on length_id) for which the CRC
needs to be calculated.
• The destination address should belong to the same zone as the source address.
For further usage of these library functions, see the device-specific Boot ROM documentation.
NOTE: The user must disable all the interrupts before calling the safe copy code and the safeCRC
function. If there is a vector fetch during copy code operation, the CPU gets reset
immediately.

Disclaimer: Code Security Module Disclaimer The Code Security Module (CSM) included on this device
was designed to password protect the data stored in the associated memory and is warranted by Texas
Instruments (TI), in accordance with its standard terms and conditions, to conform to TI's published
specifications for the warranty period applicable for this device. TI DOES NOT, HOWEVER, WARRANT
OR REPRESENT THAT THE CSM CANNOT BE COMPROMISED OR BREACHED OR THAT THE
DATA STORED IN THE ASSOCIATED MEMORY CANNOT BE ACCESSED THROUGH OTHER
MEANS. MOREOVER, EXCEPT AS SET FORTH ABOVE, TI MAKES NO WARRANTIES OR
REPRESENTATIONS CONCERNING THE CSM OR OPERATION OF THIS DEVICE, INCLUDING ANY
IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. IN NO
EVENT SHALL TI BE LIABLE FOR ANY CONSEQUENTIAL, SPECIAL, INDIRECT, INCIDENTAL, OR
PUNITIVE DAMAGES, HOWEVER CAUSED, ARISING IN ANY WAY OUT OF YOUR USE OF THE CSM
OR THIS DEVICE, WHETHER OR NOT TI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH
DAMAGES. EXCLUDED DAMAGES INCLUDE, BUT ARE NOT LIMITED TO LOSS OF DATA, LOSS OF
GOODWILL, LOSS OF USE OR INTERRUPTION OF BUSINESS OR OTHER ECONOMIC LOSS.
2.13.2 CSM Impact on Other On-Chip Resources

On this device, M0/M1 and GSx memories are not secure. To avoid any potential hacking when the device
is in the default state (post reset), accesses (all types) to all memories (secure as well as non-secure,
except BOOT-ROM and OTP ) are disabled until proper security initialization is done. This means that
after reset none of the memory resources except BOOT_ROM and OTP is accessible to the user.
The following steps are required after reset (any type of reset) to initialize the security on each CPU
subsystem.
• Dummy Read to address location of SECDC (0x703F0, TI-reserved register) in TI OTP
• Dummy Read to address location of Z1_LINKPOINTER1 in Z1 OTP
• Dummy Read to address location of Z1_PSWDLOCK in Z1 OTP
• Dummy Read to address location of Z1_CRCLOCK in Z1 OTP
• Dummy Read to address location 0x78018 in Z1 OTP
• Dummy Read to address location of Z1_BOOTCTRL in Z1 OTP
• Read to memory map register of Z1_LINKPOINTER in DCSM module to calculate the address of zone
select block for Z1
• Dummy read to address location of Z1_EXEONLYRAM in Z1 OTP
• Dummy read to address location of Z1_EXEONLYSECT in Z1 OTP
• Dummy read to address location of Z1_GRABRAM in Z1 OTP
• Dummy read to address location of Z1_GRABSECT in Z1 OTP
• Dummy Read to address location of Z2_PSWDLOCK in Z2 OTP
• Dummy Read to address location of Z2_CRCLOCK in Z2 OTP
• Dummy Read to address location 0x78218 in Z2 OTP
• Dummy Read to address location of Z2_BOOTCTRL in Z2 OTP
• Read to memory map register of Z2_LINKPOINTER in DCSM module to calculate the address of zone
select block for Z2
• Dummy read to address location of Z2_EXEONLYRAM in Z2 OTP
• Dummy read to address location of Z2_EXEONLYSECT in Z2 OTP
• Dummy read to address location of Z2_GRABRAM in Z2 OTP
• Dummy read to address location of Z2_GRABSECT in Z2 OTP

2.13.3 Incorporating Code Security in User Applications

Code security is typically not required in the development phase of a project. However, security is needed
once a robust code is developed for a zone. Before such a code is programmed in the Flash memory, a
CSM password should be chosen to secure the zone. Once a CSM password is in place for a zone, the
zone is secured (programming a password at the appropriate locations and either performing a device
reset or setting the FORCESEC bit (Zx_CR.15) is the action that secures the device). From that time on,
access to debug the contents of secure memory by any means (via JTAG, code running off external/on-
chip memory, and so forth) requires a valid password. A password is not needed to run the code out of
secure memory (such as in a typical end-user usage); however, access to secure memory contents for
debug purposes, requires a password.
2.13.3.1 Environments That Require Security Unlocking

The following are the typical situations under which unsecuring can be required:
• Code development using debuggers (such as Code Composer Studio). This is the most common
environment during the design phase of a product.
• Flash programming using TI's Flash utilities such as Code Composer Studio On-Chip Flash
Programmer plug-in or the Uniflash tool. Flash programming is common during code development and
testing. Once the user supplies the necessary password, the flash utilities disable the security logic
before attempting to program the Flash. The flash utilities can disable the code security logic in new
devices without any authorization, since new devices come with an erased Flash. However,
reprogramming devices that already contain a custom password require the password to be supplied to
the flash utilities in order to unlock the device to enable programming. In custom programming
solutions that use the Flash API supplied by TI, unlocking the CSM can be avoided by executing the
Flash programming algorithms from secure memory.
• Custom environment defined by the application
In addition to the above, access to secure memory contents can be required in situations such as:
– Using the on-chip bootloader to load code or data into secure SARAM or to erase and program the
Flash.
– Executing code from on-chip unsecure memory and requiring access to secure memory for the
lookup table. This is not a suggested operating condition as supplying the password from external
code could compromise code security.
The unsecuring sequence is identical in all the above situations. This sequence is referred to as the
password match flow (PMF) for simplicity. Figure 2-23 explains the sequence of operation that is required
every time the user attempts to unsecure a particular zone. A code example is listed for clarity.
2.13.3.2 CSM Password Match Flow

Password match flow (PMF) is essentially a sequence of four dummy reads from password locations
(PWL) followed by four writes (32-bit writes) to CSMKEY(0/1/2/3) registers. Figure 2-23 shows how PMF
helps to initialize the security logic registers and disable security logic.

Figure 2-23. CSM Password Match Flow (PMF)
START
Zone secure after reset

or runtime
Dummy Read of CSM PWL

of the secure zone, which
needs to be unsecure
Are CSM YES

PWL = All
Fs?
NO
Write the CSM Password of

that zone into CSMKEYx
registers
NO Correct
Password?
YES
Zone Unsecure
2.13.3.3 Unsecuring Considerations for Zones With and Without Code Security
Case 1 and Case 2 provide unsecuring considerations for zones with and without code security.
• Case 1: Zone With Code Security
A zone with code security should have a predetermined password stored in the password locations of
that zone. The following are steps to unsecure any secure zone:

1. Perform a dummy read of the password locations of that zone.

2. Write the password into the CSMKEY registers.
3. If the password is correct, the zone becomes unsecure; otherwise, it stays secure.
• Case 2: Zone Without Code Security
A zone without code security should have 0x FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF (128
bits of all ones) stored in the password locations. The following are steps to use this zone:
1. At reset, the CSM will lock memory regions protected by the CSM.
2. Perform a dummy read of the password locations.
3. Since the password is all ones, this alone will unlock the zone and all the secure memories
dedicated to that zone are fully accessible immediately after this operation is completed.
NOTE: Even if a zone is not protected with a password (all password locations all ones), the CSM
will lock at reset. Thus, a dummy read operation must still be performed on these zones prior
to reading, writing, or programming secure memory if the code performing the access is
executing from outside of the CSM protected memory region. The Boot ROM code does this
dummy read for convenience.
2.13.3.3.1 C Code Example to Unsecure C28x Zone1

volatile long int *CSM = (volatile long int *)0x5F010; //CSM register file
volatile long int *CSMPWL = (volatile long int *)0x78028; //CSM Password location (assuming
default Zone sel block)
volatile int tmp;
int I;
// Read the 128-bits of the CSM password locations (PWL)
//
for (I=0;I<4; I++) tmp = *CSMPWL++;
// If the password locations (CSMPWL) are all = ones (0xFFFF),
// then the zone will now be unsecure. If the password
// is not all ones (0xFFFF), then the code below is required
// to unsecure the CSM.
// Write the 128-bit password to the CSMKEY registers
// If this password matches that stored in the
// CSLPWL then the CSM will become unsecure. If it does not
// match, then the zone will remain secure.
// An example password of:
// 0x11112222333344445555666677778888 is used.
*CSM++ = 0x22221111; // Register Z1_CSMKEY0 at 0x5F010
2.13.3.3.2 C Code Example to Resecure C28x Zone1

volatile int *Z1_CR = 0x5F019; //CSMSCR register
//Set FORCESEC bit
*Z1_CR = 0x8000;
2.13.3.4 Environments That Require ECSL Unlocking

The following are the typical situations under which unsecuring can be required:
• The user develops some main IP, and then outsources peripheral functions to a subcontractor who
must be able to run the user code during debug and may halt while main IP code is running. If ECSL is
not unlocked, then Code Composer Studio connections will get disconnected, which can be
inconvenient for the user. Note that unlocking ECSL doesn’t enable access to secure code but only
avoids disconnection of CCS (JTAG).

2.13.3.5 ECSL Password Match Flow

A password match flow (PMF) is essentially a sequence of eight dummy reads from password locations
(PWL) followed by two writes to KEY registers. Figure 2-24 shows how the PMF helps to initialize the
security logic registers and disable security logic.
Figure 2-24. ECSL Password Match Flow (PMF)
START
Zone’s ECSL LOCK after

reset or runtime
Dummy read of ECSL PWL

of the secure zone, which
ECSL needs to be unlocked
Are ECSL YES

PWL = All
Fs?
NO
Write the ECSL Password of

that zone into ECSLKEYx
registers
NO Correct
Password?
YES
Zone ECSL Unlock

www.ti.com JTAG
2.13.3.6 ECSL Disable Considerations for any Zone

A zone with ECSL enabled should have a predetermined ECSL password stored in the ECSL password
locations in Flash (same as lower 64 bits of CSM passwords). The following are steps to disable the ECSL
for any particular zone:
• Perform a dummy read of CAM password locations of that Zone
• Write the password into the CSMKEYx registers, corresponding to that Zone.
• If the password is correct, the ECSL gets disabled; otherwise, it stays enabled.
2.13.3.6.1 C Code Example to Disable ECSL for C28x-Zone1

volatile long int *ECSL = (volatile int *)0x5F010; //ECSL register file
volatile long int *ECSLPWL = (volatile int *)0x78028; //ECSL Password location (assuming default
Zone sel block)
volatile int tmp;
int I;
// Read the 64-bits of the password locations (PWL)
.
for (I=0;I<2; I++) tmp = *ECSLPWL++;
// If the ECSL password locations (ECSLPWL) are all = ones (0xFFFF),
// then the ECSL will now be disable. If the password
// is not all ones (0xFFFF), then the code below is required
// to disable the ECSL.
// Write the 64-bit password to the CSMKEYx registers
// If this password matches that stored in the
// CSMPWL then ECSL will get disable. If it does not
// match, then the zone will remain secure.
// An example password of:
// 0x1111222233334444 is used.
*ECSL++ = 0x22221111; // Register Z1_CSMKEY0 at 0x5F010
*ECSL++ = 0x44443333; // Register Z1_CSMKEY1 at 0x5F012
2.13.3.7 Device Unique ID

The CPU1 OTP contains a 256-bit value that is made up of both random and sequential parts. This value
can be used as a seed for code encryption. The starting address of the value is 0x703C0. The first 192
bits are random, the next 32 bits are sequential, and the last 32 bits are a checksum value.
2.14 JTAG
Gel files perform certain initialization tasks. This helps the users in a debug environment. However, when
executed standalone (without the emulator connected) the application may not work as expected, since
there is no gel file to perform those initializations. For example, gel file disables watchdog. If user code
does not service the watchdog in the application (or fails to disable it), there will be a difference in how the
application behaves with the debugger and without.
Common tasks performed by the gel files (but not boot-ROM)
On Reset:
• Disable Flash ECC on some devices.
– Disabling ECC only when using Flash API functions, see the Flash API User Guide for details.
Otherwise, TI suggests to always program ECC and enable ECC-check.
• Disable Watchdog
• Enable CLA clock
• Select real-time mode or C28x mode
On Restart:
• Clear IER and IFR
On Target Connect:

JTAG www.ti.com

www.ti.com Registers
2.15 Registers
2.15.1 Base Addresses
Table 2-16. System Control Base Address Table

Device Registers Register Name Start Address End Address
CpuTimer0Regs CPUTIMER_REGS 0x0000_0C00 0x0000_0C07
CpuTimer1Regs CPUTIMER_REGS 0x0000_0C08 0x0000_0C0F
CpuTimer2Regs CPUTIMER_REGS 0x0000_0C10 0x0000_0C17
PieCtrlRegs PIE_CTRL_REGS 0x0000_0CE0 0x0000_0CFF
WdRegs WD_REGS 0x0000_7000 0x0000_703F
NmiIntruptRegs NMI_INTRUPT_REGS 0x0000_7060 0x0000_706F
XintRegs XINT_REGS 0x0000_7070 0x0000_707F
DmaClaSrcSelRegs DMA_CLA_SRC_SEL_REGS 0x0000_7980 0x0000_79BF
FlashPumpSemaphoreRegs FLASH_PUMP_SEMAPHORE_RE 0x0005_0024 0x0005_0025
GS
DevCfgRegs (1) DEV_CFG_REGS 0x0005_D000 0x0005_D17F
ClkCfgRegs CLK_CFG_REGS 0x0005_D200 0x0005_D2FF
CpuSysRegs CPU_SYS_REGS 0x0005_D300 0x0005_D3FF
RomPrefetchRegs (1) ROM_PREFETCH_REGS 0x0005_E608 0x0005_E609
DcsmZ1Regs DCSM_Z1_REGS 0x0005_F000 0x0005_F02F
DcsmZ2Regs DCSM_Z2_REGS 0x0005_F040 0x0005_F05F
DcsmCommonRegs DCSM_COMMON_REGS 0x0005_F070 0x0005_F07F
MemCfgRegs MEM_CFG_REGS 0x0005_F400 0x0005_F47F
AccessProtectionRegs ACCESS_PROTECTION_REGS 0x0005_F4C0 0x0005_F4FF
MemoryErrorRegs MEMORY_ERROR_REGS 0x0005_F500 0x0005_F53F
RomWaitStateRegs (1) ROM_WAIT_STATE_REGS 0x0005_F540 0x0005_F541
Flash0CtrlRegs FLASH_CTRL_REGS 0x0005_F800 0x0005_FAFF
Flash0EccRegs FLASH_ECC_REGS 0x0005_FB00 0x0005_FB3F
(1)
Only available on CPU1.

Registers www.ti.com
2.15.2 CPUTIMER_REGS Registers

Table 2-17 lists the memory-mapped registers for the CPUTIMER_REGS. All register offset addresses not
listed in Table 2-17 should be considered as reserved locations and the register contents should not be
modified.
Table 2-17. CPUTIMER_REGS Registers

Offset Acronym Register Name Write Protection Section
0h TIM CPU-Timer, Counter Register Go
2h PRD CPU-Timer, Period Register Go
4h TCR CPU-Timer, Control Register Go
6h TPR CPU-Timer, Prescale Register Go
7h TPRH CPU-Timer, Prescale Register High Go
Complex bit access types are encoded to fit into small table cells. Table 2-18 shows the codes that are
used for access types in this section.
Table 2-18. CPUTIMER_REGS Access Type Codes

Access Type Code Description
Read Type
R R Read
Write Type
W W Write
W1C 1C 1 to clear
W Write
Reset or Default Value
-n Value after reset or the default
value
Register Array Variables
i,j,k,l,m,n When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups form
a hierarchical structure and the
array is represented with a
formula.
y When this variable is used in a
register name, an offset, or an
address it refers to the value of a
register array.

2.15.2.1 TIM Register (Offset = 0h) [reset = FFFFh]

TIM is shown in Figure 2-25 and described in Table 2-19.
Return to Summary Table.
CPU-Timer, Counter Register
Figure 2-25. TIM Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSW LSW
R/W-0h R/W-FFFFh
Table 2-19. TIM Register Field Descriptions

Bit Field Type Reset Description
31-16 MSW R/W 0h CPU-Timer Counter Registers
The TIMH register holds the high 16 bits of the current 32-bit count
of the timer. The TIMH:TIM decrements by one every
(TDDRH:TDDR+1) clock cycles, where TDDRH:TDDR is the timer
prescale dividedown value. When the TIMH:TIM decrements to zero,
the TIMH:TIM register is reloaded with the period value contained in
the PRDH:PRD registers. The timer interrupt (TINT) signal is
generated.
Reset type: SYSRSn
15-0 LSW R/W FFFFh CPU-Timer Counter Registers
The TIM register holds the low 16 bits of the current 32-bit count of
the timer. The TIMH:TIM decrements by one every
(TDDRH:TDDR+1) clock cycles, where TDDRH:TDDR is the timer
prescale dividedown value. When the TIMH:TIM decrements to zero,
the TIMH:TIM register is reloaded with the period value contained in
the PRDH:PRD registers. The timer interrupt (TINT) signal is
generated.
Reset type: SYSRSn

2.15.2.2 PRD Register (Offset = 2h) [reset = 0001FFFFh]

PRD is shown in Figure 2-26 and described in Table 2-20.
CPU-Timer, Period Register
Figure 2-26. PRD Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSW LSW
R/W-1h R/W-FFFFh
Table 2-20. PRD Register Field Descriptions

31-16 MSW R/W 1h CPU-Timer Period Registers
The PRDH register holds the high 16 bits of the 32-bit period. When
the TIMH:TIM decrements to zero, the TIMH:TIM register is reloaded
with the period value contained in the PRDH:PRD registers, at the
start of the next timer input clock cycle (the output of the prescaler).
The PRDH:PRD contents are also loaded into the TIMH:TIM when
you set the timer reload bit (TRB) in the Timer Control Register
(TCR).
Reset type: SYSRSn
15-0 LSW R/W FFFFh CPU-Timer Period Registers
The PRD register holds the low 16 bits of the 32-bit period. When
the TIMH:TIM decrements to zero, the TIMH:TIM register is reloaded
with the period value contained in the PRDH:PRD registers, at the
start of the next timer input clock cycle (the output of the prescaler).
The PRDH:PRD contents are also loaded into the TIMH:TIM when
you set the timer reload bit (TRB) in the Timer Control Register
(TCR).
Reset type: SYSRSn

2.15.2.3 TCR Register (Offset = 4h) [reset = 1h]

TCR is shown in Figure 2-27 and described in Table 2-21.
CPU-Timer, Control Register
Figure 2-27. TCR Register

15 14 13 12 11 10 9 8
TIF TIE RESERVED FREE SOFT RESERVED
R/W1C-0h R/W-0h R-0h R/W-0h R/W-0h R-0h
7 6 5 4 3 2 1 0
RESERVED TRB TSS RESERVED
R-0h R/W-0h R/W-0h R-1h
Table 2-21. TCR Register Field Descriptions

15 TIF R/W1C 0h CPU-Timer Overflow Flag.
TIF indicates whether a timer overflow has happened since TIF was
last cleared. TIF is not cleared automatically and does not need to
be cleared to enable the next timer interrupt.
Reset type: SYSRSn
0h (R/W) = The CPU-Timer has not decremented to zero.
Writes of 0 are ignored.
1h (R/W) = This flag gets set when the CPU-timer decrements to
zero.
Writing a 1 to this bit clears the flag.
14 TIE R/W 0h CPU-Timer Interrupt Enable.
Reset type: SYSRSn
0h (R/W) = The CPU-Timer interrupt is disabled.
1h (R/W) = The CPU-Timer interrupt is enabled. If the timer
decrements to zero, and TIE is set, the timer asserts its interrupt
request.
13-12 RESERVED R 0h Reserved
11 FREE R/W 0h If the FREE bit is set to 1, then, upon a software breakpoint, the
timer continues to run. If FREE is 0, then the SOFT bit controls the
emulation behavior.
Reset type: SYSRSn
0h (R/W) = Stop after the next decrement of the TIMH:TIM (hard
stop)
1h (R/W) = Stop after the TIMH:TIM decrements to 0 (soft stop)
In the SOFT STOP mode, the timer generates an interrupt before

shutting down (since reaching 0 is the interrupt causing condition).
2h (R/W) = Free run
3h (R/W) = Free run
10 SOFT R/W 0h If the FREE bit is set to 1, then, upon a software breakpoint, the
timer continues to run (that is, free runs). In this case, SOFT is a
don't care. But if FREE is 0, then SOFT takes effect. In this case, if
SOFT = 0, the timer halts the next time the TIMH:TIM decrements. If
the SOFT bit is 1, then the timer halts when the TIMH:TIM
has decremented to zero.
Reset type: SYSRSn

Table 2-21. TCR Register Field Descriptions (continued)

5 TRB R/W 0h Timer reload
Reset type: SYSRSn
0h (R/W) = The TRB bit is always read as zero. Writes of 0 are
ignored.
1h (R/W) = When you write a 1 to TRB, the TIMH:TIM is loaded with
the value in the PRDH:PRD,
and the prescaler counter (PSCH:PSC) is loaded with the value in
the timer dividedown
register (TDDRH:TDDR).
4 TSS R/W 0h CPU-Timer stop status bit.
TSS is a 1-bit flag that stops or starts the CPU-timer.
Reset type: SYSRSn
0h (R/W) = Reads of 0 indicate the CPU-timer is running.
To start or restart the CPU-timer, set TSS to 0. At reset, TSS is
cleared to 0 and the
CPU-timer immediately starts.
1h (R/W) = Reads of 1 indicate that the CPU-timer is stopped.
To stop the CPU-timer, set TSS to 1.

2.15.2.4 TPR Register (Offset = 6h) [reset = 0h]

TPR is shown in Figure 2-28 and described in Table 2-22.
CPU-Timer, Prescale Register
Figure 2-28. TPR Register

15 14 13 12 11 10 9 8
PSC
R-0h
7 6 5 4 3 2 1 0
TDDR
R/W-0h
Table 2-22. TPR Register Field Descriptions

15-8 PSC R 0h CPU-Timer Prescale Counter.
These bits hold the current prescale count for the timer. For every
timer clock source cycle that the PSCH:PSC value is greater than 0,
the PSCH:PSC decrements by one. One timer clock (output of the
timer prescaler) cycle after the PSCH:PSC reaches 0, the
PSCH:PSC is loaded with the contents of the TDDRH:TDDR, and
the timer counter register (TIMH:TIM) decrements by one. The
PSCH:PSC is also reloaded whenever the timer reload bit (TRB) is
set by software. The PSCH:PSC can be checked by reading the
register, but it cannot be set directly. It must get its value from the
timer divide-down register
(TDDRH:TDDR). At reset, the PSCH:PSC is set to 0.
Reset type: SYSRSn
7-0 TDDR R/W 0h CPU-Timer Divide-Down.
Every (TDDRH:TDDR + 1) timer clock source cycles, the timer
counter register (TIMH:TIM) decrements by one. At reset, the
TDDRH:TDDR bits are cleared to 0. To increase the overall timer
count by an integer factor, write this factor minus one to the
TDDRH:TDDR bits. When the prescaler counter (PSCH:PSC) value
is 0, one timer clock source cycle later, the contents of the
TDDRH:TDDR reload the PSCH:PSC, and the TIMH:TIM
decrements by one. TDDRH:TDDR also reloads the PSCH:PSC
whenever the timer reload bit (TRB) is set by software.
Reset type: SYSRSn

2.15.2.5 TPRH Register (Offset = 7h) [reset = 0h]

TPRH is shown in Figure 2-29 and described in Table 2-23.
CPU-Timer, Prescale Register High
Figure 2-29. TPRH Register

15 14 13 12 11 10 9 8
PSCH
R-0h
7 6 5 4 3 2 1 0
TDDRH
R/W-0h
Table 2-23. TPRH Register Field Descriptions

15-8 PSCH R 0h See description of TIMERxTPR.
Reset type: SYSRSn
7-0 TDDRH R/W 0h See description of TIMERxTPR.
Reset type: SYSRSn

2.15.3 PIE_CTRL_REGS Registers

Table 2-24 lists the memory-mapped registers for the PIE_CTRL_REGS. All register offset addresses not
modified.
Table 2-24. PIE_CTRL_REGS Registers

0h PIECTRL ePIE Control Register Go
1h PIEACK Interrupt Acknowledge Register Go
2h PIEIER1 Interrupt Group 1 Enable Register Go
3h PIEIFR1 Interrupt Group 1 Flag Register Go
Ah PIEIER5 Interrupt Group 5 Enable Register Go
Bh PIEIFR5 Interrupt Group 5 Flag Register Go
Ch PIEIER6 Interrupt Group 6 Enable Register Go
Dh PIEIFR6 Interrupt Group 6 Flag Register Go
Eh PIEIER7 Interrupt Group 7 Enable Register Go
Fh PIEIFR7 Interrupt Group 7 Flag Register Go
Table 2-25. PIE_CTRL_REGS Access Type Codes

Read Type
R R Read
R=0 R Read
Write Type
W W Write
W=1 W Write
value

Table 2-25. PIE_CTRL_REGS Access Type

Codes (continued)
formula.
register array.

2.15.3.1 PIECTRL Register (Offset = 0h) [reset = 0h]

PIECTRL is shown in Figure 2-30 and described in Table 2-26.
ePIE Control Register
Figure 2-30. PIECTRL Register

15 14 13 12 11 10 9 8
PIEVECT
R-0h
7 6 5 4 3 2 1 0
PIEVECT ENPIE
R-0h R/W-0h
Table 2-26. PIECTRL Register Field Descriptions

15-1 PIEVECT R 0h These bits indicate the vector address of the vector fetched from the
ePIE vector table. The least significant bit of the address is ignored
and only bits 1 to 15 of the address are shown. The vector value can
be read by the user to determine which interrupt generated the
vector fetch.
Note: When a NMI is serviced, the PIEVECT bit-field does not reflect
the vector as it does for other interrupts.
Reset type: SYSRSn
0 ENPIE R/W 0h Enable vector fetching from ePIE block. This bit must be set to 1 for
peripheral interrupts to work. All ePIE registers (PIEACK, PIEIFR,
PIEIER) can be accessed even when the ePIE block is disabled.
Reset type: SYSRSn

2.15.3.2 PIEACK Register (Offset = 1h) [reset = 0h]

PIEACK is shown in Figure 2-31 and described in Table 2-27.
Acknowledge Register
When an interrupt propagates from the ePIE to a CPU interrupt line, the interrupt group's PIEACK bit is
set. This prevents other interrupts in that group from propagating to the CPU while the first interrupt is
handled. Writing a 1 to a PIEACK bit clears it and allows another interrupt from the corresponding group to
propagate. ISRs for PIE interrupts should clear the group's PIEACK bit before returning from the interrupt.
Writes of 0 are ignored.
Figure 2-31. PIEACK Register

15 14 13 12 11 10 9 8
RESERVED ACK12 ACK11 ACK10 ACK9
R=0-0h R/W=1-0h R/W=1-0h R/W=1-0h R/W=1-0h
7 6 5 4 3 2 1 0
ACK8 ACK7 ACK6 ACK5 ACK4 ACK3 ACK2 ACK1
R/W=1-0h R/W=1-0h R/W=1-0h R/W=1-0h R/W=1-0h R/W=1-0h R/W=1-0h R/W=1-0h
Table 2-27. PIEACK Register Field Descriptions

15-12 RESERVED R=0 0h Reserved
11 ACK12 R/W=1 0h Acknowledge PIE Interrupt Group 12
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn

2.15.3.3 PIEIER1 Register (Offset = 2h) [reset = 0h]

PIEIER1 is shown in Figure 2-32 and described in Table 2-28.
Interrupt Group 1 Enable Register
These register bits individually enable an interrupt within a group. They behave very much like the bits in
the CPU interrupt enable register (IER).
Setting a bit to 1 allows the corresponding interrupt to propagate to the CPU.
Setting a bit to 0 prevents the corresponding interrupt from propagating. Note that a peripheral interrupt
signal can still set the PIEIFR bit for the disabled interrupt.
Figure 2-32. PIEIER1 Register

15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
Table 2-28. PIEIER1 Register Field Descriptions

15 INTx16 R/W 0h Enable for Interrupt 1.16
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn

Table 2-28. PIEIER1 Register Field Descriptions (continued)

Reset type: SYSRSn
Reset type: SYSRSn

2.15.3.4 PIEIFR1 Register (Offset = 3h) [reset = 0h]

PIEIFR1 is shown in Figure 2-33 and described in Table 2-29.
Interrupt Group 1 Flag Register
These register bits indicate whether each interrupt in the group is currently pending. They behave very
much like the bits in the CPU interrupt flag register (IFR).
When a peripheral sends an interrupt, the corresponding bit is set. This bit is cleared when the interrupt
propagates to the CPU, at which point PIEACK is set.
NOTE: PIE IFR flags can be written to create software interrupts.
The IFR flag will be cleared on a write of zero. Hence, when the intent is to fire an interrupt it may cause
inadvertent cancellation of other interrupts. It is recommended to use this only for testing or with extreme
caution in the application code. Reading the PIE IFR registers is safe.
Figure 2-33. PIEIFR1 Register

15 14 13 12 11 10 9 8
7 6 5 4 3 2 1 0
Table 2-29. PIEIFR1 Register Field Descriptions

15 INTx16 R/W 0h Flag for Interrupt 1.16
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn

Table 2-29. PIEIFR1 Register Field Descriptions (continued)

Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn



15 14 13 12 11 10 9 8
7 6 5 4 3 2 1 0

Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn


Reset type: SYSRSn
Reset type: SYSRSn



15 14 13 12 11 10 9 8
7 6 5 4 3 2 1 0

Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn


Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn



15 14 13 12 11 10 9 8
7 6 5 4 3 2 1 0

Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn


Reset type: SYSRSn
Reset type: SYSRSn



15 14 13 12 11 10 9 8
7 6 5 4 3 2 1 0

Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn


Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn



15 14 13 12 11 10 9 8
7 6 5 4 3 2 1 0

Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn


Reset type: SYSRSn
Reset type: SYSRSn



15 14 13 12 11 10 9 8
7 6 5 4 3 2 1 0

Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn


Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn

2.15.3.11 PIEIER5 Register (Offset = Ah) [reset = 0h]


15 14 13 12 11 10 9 8
7 6 5 4 3 2 1 0

Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn


Reset type: SYSRSn
Reset type: SYSRSn

2.15.3.12 PIEIFR5 Register (Offset = Bh) [reset = 0h]


15 14 13 12 11 10 9 8
7 6 5 4 3 2 1 0

Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn


Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn

2.15.3.13 PIEIER6 Register (Offset = Ch) [reset = 0h]


15 14 13 12 11 10 9 8
7 6 5 4 3 2 1 0

Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn


Reset type: SYSRSn
Reset type: SYSRSn

2.15.3.14 PIEIFR6 Register (Offset = Dh) [reset = 0h]


15 14 13 12 11 10 9 8
7 6 5 4 3 2 1 0

Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn


Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn

2.15.3.15 PIEIER7 Register (Offset = Eh) [reset = 0h]


15 14 13 12 11 10 9 8
7 6 5 4 3 2 1 0

Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn


Reset type: SYSRSn
Reset type: SYSRSn

2.15.3.16 PIEIFR7 Register (Offset = Fh) [reset = 0h]


15 14 13 12 11 10 9 8
7 6 5 4 3 2 1 0

Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn


Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn



15 14 13 12 11 10 9 8
7 6 5 4 3 2 1 0

Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn


Reset type: SYSRSn
Reset type: SYSRSn



15 14 13 12 11 10 9 8
7 6 5 4 3 2 1 0

Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn


Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn



15 14 13 12 11 10 9 8
7 6 5 4 3 2 1 0

Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn


Reset type: SYSRSn
Reset type: SYSRSn



15 14 13 12 11 10 9 8
7 6 5 4 3 2 1 0

Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn


Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn



15 14 13 12 11 10 9 8
7 6 5 4 3 2 1 0

Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn


Reset type: SYSRSn
Reset type: SYSRSn



15 14 13 12 11 10 9 8
7 6 5 4 3 2 1 0

Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn


Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn



15 14 13 12 11 10 9 8
7 6 5 4 3 2 1 0

Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn


Reset type: SYSRSn
Reset type: SYSRSn



15 14 13 12 11 10 9 8
7 6 5 4 3 2 1 0

Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn


Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn



15 14 13 12 11 10 9 8
7 6 5 4 3 2 1 0

Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn


Reset type: SYSRSn
Reset type: SYSRSn



15 14 13 12 11 10 9 8
7 6 5 4 3 2 1 0

Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn


Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn

2.15.4 WD_REGS Registers

Table 2-52 lists the memory-mapped registers for the WD_REGS. All register offset addresses not listed
in Table 2-52 should be considered as reserved locations and the register contents should not be
modified.
Table 2-52. WD_REGS Registers

22h SCSR System Control & Status Register EALLOW Go
23h WDCNTR Watchdog Counter Register EALLOW Go
25h WDKEY Watchdog Reset Key Register EALLOW Go
29h WDCR Watchdog Control Register EALLOW Go
2Ah WDWCR Watchdog Windowed Control Register EALLOW Go
Table 2-53. WD_REGS Access Type Codes

Read Type
R R Read
R=0 R Read
Write Type
W W Write
W1C 1C 1 to clear
W Write
W=1 W Write
value
formula.
register array.

2.15.4.1 SCSR Register (Offset = 22h) [reset = 5h]

SCSR is shown in Figure 2-56 and described in Table 2-54.
It is recommended to only use 16 bit accesses to write to this register. Use a read-modify-write instruction
may inadvertently clear other bits.
Figure 2-56. SCSR Register

15 14 13 12 11 10 9 8
RESERVED
R=0-0h
7 6 5 4 3 2 1 0
RESERVED WDINTS WDENINT WDOVERRIDE
R=0-0h R-1h R/W-0h R/W1C-1h
Table 2-54. SCSR Register Field Descriptions

2 WDINTS R 1h Watchdog interrupt (WDINTn) status signal. This is a read only bit
reflecting the current state of the WDINTn signal from the watchdog
block (after synchronization with SYSCLKOUT). If this bit is 1, the
watchdog interrupt is not active. If this bit is 0, then the watchdog
interrupt is active.
Note: ,If the WDINTn signal is used to wake up from IDLE or

STANDBY condition, then the user should make sure that the
WDINTn signal goes back high again before attempting to go back
into IDLE or STANDBY mode. Reading this bit will tell the user the
current state of this signal.
Reset type: SYSRSn
1 WDENINT R/W 0h If this bit is set to 1, the watchdog reset (WDRSTn) output signal is
disabled and the watchdog interrupt (WDINTn) output signal is
enabled. If this bit is zero, then the WDRSTn output signal is
enabled and the WDINTn output signal is disabled. This is the
default state on system reset (SYSRSn).
Reset type: SYSRSn
0 WDOVERRIDE R/W1C 1h If this bit is set to 1, the user is allowed to change the state of the
Watchdog disable (WDDIS) bit in the Watchdog Control (WDCR)
register. If the WDOVERRIDE bit is cleared, by writing a 1 the
WDDIS bit cannot be modified by the user. Writing a 0 will have no
effect. If this bit is cleared, then it will remain in this state until a reset
occurs. The current state of this bit is readable by the user.
Reset type: SYSRSn

2.15.4.2 WDCNTR Register (Offset = 23h) [reset = 0h]

WDCNTR is shown in Figure 2-57 and described in Table 2-55.
Watchdog Counter Register
Figure 2-57. WDCNTR Register

15 14 13 12 11 10 9 8
RESERVED
R=0-0h
7 6 5 4 3 2 1 0
WDCNTR
R-0h
Table 2-55. WDCNTR Register Field Descriptions

7-0 WDCNTR R 0h These bits contain the current value of the WD counter. The 8-bit
counter continually increments at the WDCLK rate. If the counter
overflows, then a watchdog output pulse (WDOUTn) is generated. If
the WDKEY register is written with a valid combination, then the
counter is reset to zero.
Reset type: IORSn

2.15.4.3 WDKEY Register (Offset = 25h) [reset = 0h]

WDKEY is shown in Figure 2-58 and described in Table 2-56.
Watchdog Reset Key Register
Figure 2-58. WDKEY Register

15 14 13 12 11 10 9 8
RESERVED
R=0-0h
7 6 5 4 3 2 1 0
WDKEY
R/W-0h
Table 2-56. WDKEY Register Field Descriptions

7-0 WDKEY R/W 0h Writing 0x55 followed by 0xAA will cause the WDCNTR bits to be
cleared.
Note:
[1] Reads from the WDKEY return the value of WDCR register.
Reset type: IORSn

2.15.4.4 WDCR Register (Offset = 29h) [reset = 0h]

WDCR is shown in Figure 2-59 and described in Table 2-57.
Watchdog Control Register
Figure 2-59. WDCR Register

15 14 13 12 11 10 9 8
RESERVED
R=0-0h
7 6 5 4 3 2 1 0
RESERVED WDDIS WDCHK WDPS
R-0h R/W-0h R=0/W-0h R/W-0h
Table 2-57. WDCR Register Field Descriptions

7 RESERVED R 0h Reserved
6 WDDIS R/W 0h Writing a 1 to this bit will disable the watchdog module. Writing a 0
will enable the module. This bit can only be modified if the
WDOVERRIDE bit in the SCSR2 register is set to 1. On reset, the
watchdog module is enabled.
Reset type: IORSn
5-3 WDCHK R=0/W 0h The user must ALWAYS write 1,0,1 to these bits whenever a write to
this register is performed. Writing any other value will cause an
immediate reset to the core (if WD enabled).
Reset type: IORSn
2-0 WDPS R/W 0h These bits configure the watchdog counter clock (WDCLK) rate
relative to INTOSC1/512:
000 WDCLK = INTOSC1/512/1
Reset type: IORSn

2.15.4.5 WDWCR Register (Offset = 2Ah) [reset = 0h]

WDWCR is shown in Figure 2-60 and described in Table 2-58.
Watchdog Windowed Control Register
Figure 2-60. WDWCR Register

15 14 13 12 11 10 9 8
RESERVED FIRSTKEY
R=0-0h R-0h
7 6 5 4 3 2 1 0
MIN
R/W-0h
Table 2-58. WDWCR Register Field Descriptions

8 FIRSTKEY R 0h This bit indicates if the 1st valid WDKEY (0x55 + 0xAA) got detected
after MIN was configured to a non-zero value
0: First Valid Key after non-zero MIN configuration has not happened
yet
1: First Valid key after non-zero MIN configuration got detected
Notes:
[1] If MIN = 0, this bit is never set
[2] If MIN is changed back to 0x0 from a non-zero value, this bit is
auto-cleared
[3] This bit is added for debug purposes only
Reset type: IORSn
7-0 MIN R/W 0h These bits define the lower limt of the Windowed functionality
Reset type: IORSn

2.15.5 NMI_INTRUPT_REGS Registers

Table 2-59 lists the memory-mapped registers for the NMI_INTRUPT_REGS. All register offset addresses
not listed in Table 2-59 should be considered as reserved locations and the register contents should not
be modified.
Table 2-59. NMI_INTRUPT_REGS Registers

0h NMICFG NMI Configuration Register EALLOW Go
1h NMIFLG NMI Flag Register (XRSn Clear) Go
2h NMIFLGCLR NMI Flag Clear Register EALLOW Go
3h NMIFLGFRC NMI Flag Force Register EALLOW Go
4h NMIWDCNT NMI Watchdog Counter Register Go
5h NMIWDPRD NMI Watchdog Period Register EALLOW Go
6h NMISHDFLG NMI Shadow Flag Register Go
Table 2-60. NMI_INTRUPT_REGS Access Type Codes

Read Type
R R Read
R=0 R Read
Write Type
W W Write
W=1 W Write
value
formula.
register array.

2.15.5.1 NMICFG Register (Offset = 0h) [reset = 0h]

NMICFG is shown in Figure 2-61 and described in Table 2-61.
NMI Configuration Register
Figure 2-61. NMICFG Register

15 14 13 12 11 10 9 8
RESERVED
R=0-0h
7 6 5 4 3 2 1 0
RESERVED NMIE
R=0-0h R/W=1-0h
Table 2-61. NMICFG Register Field Descriptions

0 NMIE R/W=1 0h When set to 1 any condition will generate an NMI interrupt to the
C28 CPU and kick off the NMI watchdog counter. As part of boot
sequence this bit should be set after the device security related
initialization is complete.
0 NMI disabled
1 NMI enabled
Reset type: SYSRSn

2.15.5.2 NMIFLG Register (Offset = 1h) [reset = 0h]

NMIFLG is shown in Figure 2-62 and described in Table 2-62.
NMI Flag Register (XRSn Clear)
Figure 2-62. NMIFLG Register

15 14 13 12 11 10 9 8
RESERVED RESERVED CPU2NMIWDR CPU2WDRSn RESERVED
Sn
R=0-0h R-0h R-0h R-0h R-0h
7 6 5 4 3 2 1 0
RESERVED PIEVECTERR CPU2HWBIST CPU1HWBIST FLUNCERR RAMUNCERR CLOCKFAIL NMIINT
ERR ERR
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h
Table 2-62. NMIFLG Register Field Descriptions

10 CPU2NMIWDRSn R 0h CPU2 NMIWDRSn Reset Indication Flag: This bits indicates if
CPU2s NMIWDRSn was fired or not.
0 No CPU2.NMIWDRsn was fired
1 CPU2.NMIWDRSn was fired to CPU2
Note:
[1] This bits is reserved for CPU2.NMIFLG register
Reset type: XRSn
9 CPU2WDRSn R 0h CPU2 WDRSn Reset Indication Flag: This bits indicates if CPU2s
WDRSn was fired or not.
0 No CPU2.WDRsn was fired
1 CPU2.WDRSn was fired to CPU2
Note:
[1] This bits is reserved for CPU2.NMIFLG register
Reset type: XRSn
6 PIEVECTERR R 0h PIE Vector Fetch Error Flag: This bit indicates if an error occurred on
an Vector Fect by the other CPU in the device. For example,
CPU1.NMIWD gets an NMI on an Vector fetch Error on CPU2. This
bit can only be cleared by the user writing to the corresponding clear
bit in the NMIFLGCLR register or by an XRSn reset:
0,No Vector Fetch Error condition (on the other CPU) pending
1,Vector Fetch error condition (on the other CPU) generated
Reset type: XRSn
5 CPU2HWBISTERR R 0h HW BIST Error NMI Flag: This bit indicates if the time out error or a
signature mismatch error condition during hardware BIST of C28
CPU2 occurred. This bit can only be cleared by the user writing to
the corresponding clear bit in the NMIFLGCLR register or by an
XRSn reset:
0,No C28 HWBIST error condition pending
1,C28 BIST error condition generated
Reset type: XRSn

Table 2-62. NMIFLG Register Field Descriptions (continued)

4 CPU1HWBISTERR R 0h HW BIST Error NMI Flag: This bit indicates if the time out error or a
signature mismatch error condition during hardware BIST of C28
CPU1 occurred. This bit can only be cleared by the user writing to
the corresponding clear bit in the NMIFLGCLR register or by an
XRSn reset:
0,No C28 HWBIST error condition pending
1,C28 BIST error condition generated
Reset type: XRSn
3 FLUNCERR R 0h Flash Uncorrectable Error NMI Flag: This bit indicates if an
uncorrectable error occurred on a C28 Flash access and that
condition is latched. This bit can only be cleared by the user writing
to the corresponding clear bit in the NMIFLGCLR register or by an
XRSn reset:
0,No C28 Flash uncorrectable error condition pending
1,C28 Flash uncorrectable error condition generated
Reset type: XRSn
2 RAMUNCERR R 0h RAM Uncorrectable Error NMI Flag: This bit indicates if an
uncorrectable error occurred on a RAM access (by any master) and
that condition is latched. This bit can only be cleared by the user
writing to the corresponding clear bit in the NMIFLGCLR register or
by an XRSn reset:
0,No RAM uncorrectable error condition pending
1,RAM uncorrectable error condition generated
Reset type: XRSn
1 CLOCKFAIL R 0h Clock Fail Interrupt Flag: These bits indicates if the CLOCKFAIL
condition is latched. These bits can only be cleared by the user
writing to the respective bit in the NMIFLGCLR register or by an
XRSn reset:
0,No CLOCKFAIL Condition Pending
1,CLOCKFAIL Condition Generated
Reset type: XRSn
0 NMIINT R 0h NMI Interrupt Flag: This bit indicates if an NMI interrupt was
generated. This bit can only be cleared by the user writing to the
respective bit in the NMIFLGCLR register or by an XRSn reset:
0 No NMI Interrupt Generated
1 NMI Interrupt Generated
No further NMI interrupts pulses are generated until this flag is
cleared by the user.
Reset type: XRSn

2.15.5.3 NMIFLGCLR Register (Offset = 2h) [reset = 0h]

NMIFLGCLR is shown in Figure 2-63 and described in Table 2-63.
NMI Flag Clear Register
Figure 2-63. NMIFLGCLR Register

15 14 13 12 11 10 9 8
RESERVED OVF CPU2NMIWDR CPU2WDRSn RESERVED
Sn
R=0-0h R=0/W=1-0h R=0/W=1-0h R=0/W=1-0h R-0h
7 6 5 4 3 2 1 0
RESERVED PIEVECTERR CPU2HWBIST CPU1HWBIST FLUNCERR RAMUNCERR CLOCKFAIL NMIINT
ERR ERR
R-0h R=0/W=1-0h R=0/W=1-0h R=0/W=1-0h R=0/W=1-0h R=0/W=1-0h R=0/W=1-0h R=0/W=1-0h
Table 2-63. NMIFLGCLR Register Field Descriptions

11 OVF R=0/W=1 0h Writing a 1 to the respective bit clears the corresponding flag bit in
the NMIFLG and NMISHDFLG registers. Writes of 0 are ignored.
Always reads back 0.
Notes:
[1] If hardware is trying to set a bit to 1 while software is trying to
clear a bit to 0 on the same cycle, hardware has priority.
[2] Users should clear the pending FAIL flag first and then clear the
NMIINT flag.
Reset type: SYSRSn
10 CPU2NMIWDRSn R=0/W=1 0h Writing a 1 to the respective bit clears the corresponding flag bit in
Notes:
NMIINT flag.
Reset type: SYSRSn
9 CPU2WDRSn R=0/W=1 0h Writing a 1 to the respective bit clears the corresponding flag bit in
Notes:
NMIINT flag.
[3] CPU2WDRSn and CPU2NMIWDRSn bits are reserved for
CPU2.NMIFLGCLR registers
Reset type: SYSRSn

Table 2-63. NMIFLGCLR Register Field Descriptions (continued)

6 PIEVECTERR R=0/W=1 0h Writing a 1 to the respective bit clears the corresponding flag bit in
Notes:
NMIINT flag.
Reset type: SYSRSn
5 CPU2HWBISTERR R=0/W=1 0h Writing a 1 to the respective bit clears the corresponding flag bit in
Notes:
NMIINT flag.
Reset type: SYSRSn
4 CPU1HWBISTERR R=0/W=1 0h Writing a 1 to the respective bit clears the corresponding flag bit in
Notes:
NMIINT flag.
Reset type: SYSRSn
3 FLUNCERR R=0/W=1 0h Writing a 1 to the respective bit clears the corresponding flag bit in
Notes:
NMIINT flag.
Reset type: SYSRSn
2 RAMUNCERR R=0/W=1 0h Writing a 1 to the respective bit clears the corresponding flag bit in
Notes:
NMIINT flag.
Reset type: SYSRSn
1 CLOCKFAIL R=0/W=1 0h Writing a 1 to the respective bit clears the corresponding flag bit in
Notes:
NMIINT flag.
Reset type: SYSRSn

Table 2-63. NMIFLGCLR Register Field Descriptions (continued)

0 NMIINT R=0/W=1 0h Writing a 1 to the respective bit clears the corresponding flag bit in
Notes:
NMIINT flag.
Reset type: SYSRSn

2.15.5.4 NMIFLGFRC Register (Offset = 3h) [reset = 0h]

NMIFLGFRC is shown in Figure 2-64 and described in Table 2-64.
NMI Flag Force Register
Figure 2-64. NMIFLGFRC Register

15 14 13 12 11 10 9 8
Sn
R=0-0h R=0/W=1-0h R=0/W=1-0h R=0/W=1-0h R-0h
7 6 5 4 3 2 1 0
RESERVED PIEVECTERR CPU2HWBIST CPU1HWBIST FLUNCERR RAMUNCERR CLOCKFAIL RESERVED
ERR ERR
R-0h R=0/W=1-0h R=0/W=1-0h R=0/W=1-0h R=0/W=1-0h R=0/W=1-0h R=0/W=1-0h R=0-0h
Table 2-64. NMIFLGFRC Register Field Descriptions

11 OVF R=0/W=1 0h Writing a 1 to these bits will set the respective FAIL flag in the
NMIFLG and NMISHDFLG registers. Writes of 0 are ignored. Always
reads back 0. This can be used as a means to test the NMI
mechanisms.
Reset type: SYSRSn
10 CPU2NMIWDRSn R=0/W=1 0h Writing a 1 to these bits will set the respective FAIL flag in the
mechanisms.
Note:
Reset type: SYSRSn
9 CPU2WDRSn R=0/W=1 0h Writing a 1 to these bits will set the respective FAIL flag in the
mechanisms.
Note:
Reset type: SYSRSn
6 PIEVECTERR R=0/W=1 0h Writing a 1 to these bits will set the respective FAIL flag in the
mechanisms.
Reset type: SYSRSn
5 CPU2HWBISTERR R=0/W=1 0h Writing a 1 to these bits will set the respective FAIL flag in the
mechanisms.
Reset type: SYSRSn

Table 2-64. NMIFLGFRC Register Field Descriptions (continued)

4 CPU1HWBISTERR R=0/W=1 0h Writing a 1 to these bits will set the respective FAIL flag in the
mechanisms.
Reset type: SYSRSn
3 FLUNCERR R=0/W=1 0h Writing a 1 to these bits will set the respective FAIL flag in the
mechanisms.
Reset type: SYSRSn
2 RAMUNCERR R=0/W=1 0h Writing a 1 to these bits will set the respective FAIL flag in the
mechanisms.
Reset type: SYSRSn
1 CLOCKFAIL R=0/W=1 0h Writing a 1 to these bits will set the respective FAIL flag in the
mechanisms.
Reset type: SYSRSn
0 RESERVED R=0 0h Reserved

2.15.5.5 NMIWDCNT Register (Offset = 4h) [reset = 0h]

NMIWDCNT is shown in Figure 2-65 and described in Table 2-65.
NMI Watchdog Counter Register
Figure 2-65. NMIWDCNT Register

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NMIWDCNT
R-0h
Table 2-65. NMIWDCNT Register Field Descriptions

15-0 NMIWDCNT R 0h NMI Watchdog Counter: This 16-bit incremental counter will start
incrementing whenever any one of the enabled FAIL flags are set. If
the counter reaches the period value, an NMIRSn signal is fired
which will then resets the system. The counter will reset to zero
when it reaches the period value and will then restart counting if any
of the enabled FAIL flags are set.
If no enabled FAIL flag is set, then the counter will reset to zero and
remain at zero until an enabled FAIL flag is set.
Normally, the software would respond to the NMI interrupt generated

and clear the offending FLAG(s) before the NMI watchdog triggers a
reset. In some situations, the software may decide to allow the
watchdog to reset the device anyway.
The counter is clocked at the SYSCLKOUT rate.

Reset type: SYSRSn

2.15.5.6 NMIWDPRD Register (Offset = 5h) [reset = FFFFh]

NMIWDPRD is shown in Figure 2-66 and described in Table 2-66.
NMI Watchdog Period Register
Figure 2-66. NMIWDPRD Register

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NMIWDPRD
R/W-FFFFh
Table 2-66. NMIWDPRD Register Field Descriptions

15-0 NMIWDPRD R/W FFFFh NMI Watchdog Period: This 16-bit value contains the period value at
which a reset is generated when the watchdog counter matches. At
reset this value is set at the maximum. The software can decrease
the period value at initialization time.
Writing a PERIOD value that is smaller then the current counter

value will automatically force an NMIRSn and hence reset the
watchdog counter.
Reset type: SYSRSn

2.15.5.7 NMISHDFLG Register (Offset = 6h) [reset = 0h]

NMISHDFLG is shown in Figure 2-67 and described in Table 2-67.
NMI Shadow Flag Register
Figure 2-67. NMISHDFLG Register

15 14 13 12 11 10 9 8
Sn
R=0-0h R-0h R-0h R-0h R-0h
7 6 5 4 3 2 1 0
RESERVED PIEVECTERR CPU2HWBIST CPU1HWBIST FLUNCERR RAMUNCERR CLOCKFAIL RESERVED
ERR ERR
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R=0-0h
Table 2-67. NMISHDFLG Register Field Descriptions

11 OVF R 0h Shadow NMI Flags: When an NMIFLG bit is set due to any of the
possible NMI source in the device, the corresponding bit in this
register is also set. Note that NMIFLGFRC and NMIFLGCLR register
also affects the bits of this register in the same way as they do for
the NMIFLG register. This register is resetted only by PORn.
Notes:
[1] This register is added to keep the definition of System Control
Reset Cause Register Clean.
Reset type: PORn
10 CPU2NMIWDRSn R 0h Shadow NMI Flags: When an NMIFLG bit is set due to any of the
Notes:
Reset type: PORn
9 CPU2WDRSn R 0h Shadow NMI Flags: When an NMIFLG bit is set due to any of the
Notes:
Reset type: PORn

Table 2-67. NMISHDFLG Register Field Descriptions (continued)

6 PIEVECTERR R 0h Shadow NMI Flags: When an NMIFLG bit is set due to any of the
Notes:
Reset type: PORn
5 CPU2HWBISTERR R 0h Shadow NMI Flags: When an NMIFLG bit is set due to any of the
Notes:
Reset type: PORn
4 CPU1HWBISTERR R 0h Shadow NMI Flags: When an NMIFLG bit is set due to any of the
Notes:
Reset type: PORn
3 FLUNCERR R 0h Shadow NMI Flags: When an NMIFLG bit is set due to any of the
Notes:
Reset type: PORn
2 RAMUNCERR R 0h Shadow NMI Flags: When an NMIFLG bit is set due to any of the
Notes:
Reset type: PORn
1 CLOCKFAIL R 0h Shadow NMI Flags: When an NMIFLG bit is set due to any of the
Notes:
Reset type: PORn

2.15.6 XINT_REGS Registers

Table 2-68 lists the memory-mapped registers for the XINT_REGS. All register offset addresses not listed
in Table 2-68 should be considered as reserved locations and the register contents should not be
modified.
Table 2-68. XINT_REGS Registers

0h XINT1CR XINT1 configuration register Go
8h XINT1CTR XINT1 counter register Go
9h XINT2CTR XINT2 counter register Go
Ah XINT3CTR XINT3 counter register Go
Table 2-69. XINT_REGS Access Type Codes

Read Type
R R Read
R=0 R Read
Write Type
W W Write
value
formula.
register array.

2.15.6.1 XINT1CR Register (Offset = 0h) [reset = 0h]

XINT1CR is shown in Figure 2-68 and described in Table 2-70.
XINT1 configuration register
Figure 2-68. XINT1CR Register

15 14 13 12 11 10 9 8
RESERVED
R=0-0h
7 6 5 4 3 2 1 0
RESERVED POLARITY RESERVED ENABLE
R=0-0h R/W-0h R=0-0h R/W-0h
Table 2-70. XINT1CR Register Field Descriptions

3-2 POLARITY R/W 0h 00: Interrupt is selected as negative edge triggered
01: Interrupt is selected as positive edge triggered
10: Interrupt is selected as negative edge triggered
11: Interrupt is selected as positive or negative edge triggered
Reset type: SYSRSn
0 ENABLE R/W 0h 0: Interrupt Disabled
1: Interrupt Enabled
Reset type: SYSRSn



15 14 13 12 11 10 9 8
RESERVED
R=0-0h
7 6 5 4 3 2 1 0
R=0-0h R/W-0h R=0-0h R/W-0h

Reset type: SYSRSn
Reset type: SYSRSn



15 14 13 12 11 10 9 8
RESERVED
R=0-0h
7 6 5 4 3 2 1 0
R=0-0h R/W-0h R=0-0h R/W-0h

Reset type: SYSRSn
Reset type: SYSRSn



15 14 13 12 11 10 9 8
RESERVED
R=0-0h
7 6 5 4 3 2 1 0
R=0-0h R/W-0h R=0-0h R/W-0h

Reset type: SYSRSn
Reset type: SYSRSn



15 14 13 12 11 10 9 8
RESERVED
R=0-0h
7 6 5 4 3 2 1 0
R=0-0h R/W-0h R=0-0h R/W-0h

Reset type: SYSRSn
Reset type: SYSRSn

2.15.6.6 XINT1CTR Register (Offset = 8h) [reset = 0h]

XINT1CTR is shown in Figure 2-73 and described in Table 2-75.
XINT1 counter register
Figure 2-73. XINT1CTR Register

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INTCTR
R-0h
Table 2-75. XINT1CTR Register Field Descriptions

15-0 INTCTR R 0h This is a free running 16-bit up-counter that is clocked at the
SYSCLKOUT rate. The counter value is reset to 0x0000 when a
valid interrupt edge is detected and then continues counting until the
next valid interrupt edge is detected. The counter must only be reset
by the selected POLARITY edge as selected in the respective
interrupt control register. When the interrupt is disabled, the counter
will stop. The counter is a free-running counter and will wrap around
to zero when the max value is reached. The counter is a read only
register and can only be reset to zero by a valid interrupt edge or by
reset.
Reset type: SYSRSn

2.15.6.7 XINT2CTR Register (Offset = 9h) [reset = 0h]


15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INTCTR
R-0h

reset.
Reset type: SYSRSn

2.15.6.8 XINT3CTR Register (Offset = Ah) [reset = 0h]


15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INTCTR
R-0h

reset.
Reset type: SYSRSn

2.15.7 DMA_CLA_SRC_SEL_REGS Registers

Table 2-78 lists the memory-mapped registers for the DMA_CLA_SRC_SEL_REGS. All register offset
addresses not listed in Table 2-78 should be considered as reserved locations and the register contents
should not be modified.
Table 2-78. DMA_CLA_SRC_SEL_REGS Registers

0h CLA1TASKSRCSELLOCK CLA1 Task Trigger Source Select Lock Register EALLOW Go
4h DMACHSRCSELLOCK DMA Channel Triger Source Select Lock EALLOW Go
Register
6h CLA1TASKSRCSEL1 CLA1 Task Trigger Source Select Register-1 EALLOW Go
8h CLA1TASKSRCSEL2 CLA1 Task Trigger Source Select Register-2 EALLOW Go
16h DMACHSRCSEL1 DMA Channel Trigger Source Select Register-1 EALLOW Go
18h DMACHSRCSEL2 DMA Channel Trigger Source Select Register-2 EALLOW Go
Table 2-79. DMA_CLA_SRC_SEL_REGS Access Type

Codes
Read Type
R R Read
R=0 R Read
Write Type
W W Write
WSOnce SOnce Set once
W Write
value
formula.
register array.

2.15.7.1 CLA1TASKSRCSELLOCK Register (Offset = 0h) [reset = 0h]

CLA1TASKSRCSELLOCK is shown in Figure 2-76 and described in Table 2-80.
CLA1 Task Trigger Source Select Lock Register
Figure 2-76. CLA1TASKSRCSELLOCK Register

31 30 29 28 27 26 25 24
RESERVED
R=0-0h
23 22 21 20 19 18 17 16
RESERVED
R=0-0h
15 14 13 12 11 10 9 8
RESERVED
R=0-0h
7 6 5 4 3 2 1 0
RESERVED CLA1TASKSR CLA1TASKSR
CSEL2 CSEL1
R=0-0h R/WSOnce-0h R/WSOnce-0h
Table 2-80. CLA1TASKSRCSELLOCK Register Field Descriptions

1 CLA1TASKSRCSEL2 R/WSOnce 0h CLA1TASKSRCSEL2 Register Lock bit:
0: Respective register is not locked
1: Respective register is locked.
Notes:
[1] Any SOnce bit in this register, once set can only be cleared
through a SYSRSn. Write of 0 to any bit of this register has no effect
[2] The locking mechanism applies to only writes. Reads to the
registers which have LOCK protection are always allowed
Reset type: SYSRSn
0 CLA1TASKSRCSEL1 R/WSOnce 0h CLA1TASKSRCSEL1 Register Lock bit:
Notes:
Reset type: SYSRSn

2.15.7.2 DMACHSRCSELLOCK Register (Offset = 4h) [reset = 0h]

DMACHSRCSELLOCK is shown in Figure 2-77 and described in Table 2-81.
DMA Channel Triger Source Select Lock Register
Figure 2-77. DMACHSRCSELLOCK Register

31 30 29 28 27 26 25 24
RESERVED
R=0-0h
23 22 21 20 19 18 17 16
RESERVED
R=0-0h
15 14 13 12 11 10 9 8
RESERVED
R=0-0h
7 6 5 4 3 2 1 0
RESERVED DMACHSRCSE DMACHSRCSE
L2 L1
R=0-0h R/WSOnce-0h R/WSOnce-0h
Table 2-81. DMACHSRCSELLOCK Register Field Descriptions

1 DMACHSRCSEL2 R/WSOnce 0h DMACHSRCSEL2 Register Lock bit:
Notes:
Reset type: SYSRSn
0 DMACHSRCSEL1 R/WSOnce 0h DMACHSRCSEL1 Register Lock bit:
Notes:
Reset type: SYSRSn

2.15.7.3 CLA1TASKSRCSEL1 Register (Offset = 6h) [reset = 0h]

CLA1TASKSRCSEL1 is shown in Figure 2-78 and described in Table 2-82.
CLA1 Task Trigger Source Select Register-1
Figure 2-78. CLA1TASKSRCSEL1 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TASK4 TASK3 TASK2 TASK1
R/W-0h R/W-0h R/W-0h R/W-0h
Table 2-82. CLA1TASKSRCSEL1 Register Field Descriptions

31-24 TASK4 R/W 0h Selects the Trigger Source for TASK4 of CLA1
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn

2.15.7.4 CLA1TASKSRCSEL2 Register (Offset = 8h) [reset = 0h]

CLA1TASKSRCSEL2 is shown in Figure 2-79 and described in Table 2-83.
CLA1 Task Trigger Source Select Register-2
Figure 2-79. CLA1TASKSRCSEL2 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TASK8 TASK7 TASK6 TASK5
Table 2-83. CLA1TASKSRCSEL2 Register Field Descriptions

Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn

2.15.7.5 DMACHSRCSEL1 Register (Offset = 16h) [reset = 0h]

DMACHSRCSEL1 is shown in Figure 2-80 and described in Table 2-84.
DMA Channel Trigger Source Select Register-1
Figure 2-80. DMACHSRCSEL1 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH4 CH3 CH2 CH1
Table 2-84. DMACHSRCSEL1 Register Field Descriptions

31-24 CH4 R/W 0h Selects the Trigger and Sync Source CH4 of DMA
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn

2.15.7.6 DMACHSRCSEL2 Register (Offset = 18h) [reset = 0h]

DMACHSRCSEL2 is shown in Figure 2-81 and described in Table 2-85.
DMA Channel Trigger Source Select Register-2
Figure 2-81. DMACHSRCSEL2 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED CH6 CH5
R=0-0h R/W-0h R/W-0h
Table 2-85. DMACHSRCSEL2 Register Field Descriptions

Reset type: SYSRSn
Reset type: SYSRSn

2.15.8 FLASH_PUMP_SEMAPHORE_REGS Registers

Table 2-86 lists the memory-mapped registers for the FLASH_PUMP_SEMAPHORE_REGS. All register
offset addresses not listed in Table 2-86 should be considered as reserved locations and the register
contents should not be modified.
Table 2-86. FLASH_PUMP_SEMAPHORE_REGS Registers

0h PUMPREQUEST Flash programming semaphore PUMP request EALLOW Go
register
Table 2-87. FLASH_PUMP_SEMAPHORE_REGS

Access Type Codes
Read Type
R R Read
R=0 R Read
Write Type
W W Write
value
formula.
register array.

2.15.8.1 PUMPREQUEST Register (Offset = 0h) [reset = 0h]

PUMPREQUEST is shown in Figure 2-82 and described in Table 2-88.
Flash programming semaphore PUMP request register
Figure 2-82. PUMPREQUEST Register

31 30 29 28 27 26 25 24
KEY
R=0/W-0h
23 22 21 20 19 18 17 16
KEY
R=0/W-0h
15 14 13 12 11 10 9 8
RESERVED
R=0-0h
7 6 5 4 3 2 1 0
RESERVED PUMP_OWNERSHIP
R=0-0h R/W-0h
Table 2-88. PUMPREQUEST Register Field Descriptions

31-16 KEY R=0/W 0h In order to write to the semaphore bits, 0x5a5a must be written to
these key bits at the same time. Otherwise, writes are ignored. The
key is cleared immediately after writing, so it must be written again
for every semaphore change.
Reset type: CPU1.SYSRSn
1-0 PUMP_OWNERSHIP R/W 0h These bits configure which CPU has control of the flash pump, which
allows write access to the flash memory. The possible values are:
00 or 11: Read-only state. CPU1 has control of the pump, but CPU2
may seize control at any time.
01: CPU2 has exclusive control of the pump and of these
semaphore bits. CPU2 can relinquish control by setting the bits back
to 00 or 11.
10: CPU1 has exclusive control of the pump and of these
semaphore bits. CPU1 can relinquish control by setting the bits back
to 00 or 11.
Going from 01->10 or 10->01 is not allowed. Going from 00->11 or

11->00 is allowed, but has no effect. The semaphore bits [1:0] must
be written along with the correct key in bits [31:16].

2.15.9 DEV_CFG_REGS Registers

Table 2-89 lists the memory-mapped registers for the DEV_CFG_REGS. All register offset addresses not
modified.
Table 2-89. DEV_CFG_REGS Registers

0h DEVCFGLOCK1 Lock bit for CPUSELx registers EALLOW Go
8h PARTIDL_1 Lower 32-bit of Device PART Identification Go
Number
Ah PARTIDH_1 Upper 32-bit of Device PART Identification Go
Number
Ch REVID Device Revision Number Go
10h DC0_1 Device Capability: Device Information Go
12h DC1_1 Device Capability: Processing Block Go
Customization
14h DC2_1 Device Capability: EMIF Customization Go
16h DC3_1 Device Capability: Peripheral Customization Go
1Ah DC5_1 Device Capability: Peripheral Customization Go
1Ch DC6_1 Device Capability: Peripheral Customization Go
1Eh DC7_1 Device Capability: Peripheral Customization Go
2Ah DC13_1 Device Capability: Peripheral Customization Go
2Ch DC14_1 Device Capability: Analog Modules Go
Customization
2Eh DC15_1 Device Capability: Analog Modules Go
Customization
32h DC17_1 Device Capability: Analog Modules Go
Customization
34h DC18_1 Device Capability: CPU1 Lx SRAM Go
Customization
36h DC19_1 Device Capability: CPU2 Lx SRAM Go
Customization
38h DC20_1 Device Capability: GSx SRAM Customization Go
60h PERCNF1_1 Peripheral Configuration register Go
74h FUSEERR e-Fuse error Status register Go
82h SOFTPRES0 Processing Block Software Reset register EALLOW Go
84h SOFTPRES1 EMIF Software Reset register EALLOW Go
86h SOFTPRES2 Peripheral Software Reset register EALLOW Go
8Ah SOFTPRES4 Peripheral Software Reset register EALLOW Go
8Eh SOFTPRES6 Peripheral Software Reset register EALLOW Go
9Ch SOFTPRES13 Peripheral Software Reset register EALLOW Go

Table 2-89. DEV_CFG_REGS Registers (continued)

9Eh SOFTPRES14 Peripheral Software Reset register EALLOW Go
A2h SOFTPRES16 Peripheral Software Reset register EALLOW Go
D6h CPUSEL0 CPU Select register for common peripherals EALLOW Go
D8h CPUSEL1 CPU Select register for common peripherals EALLOW Go
DAh CPUSEL2 CPU Select register for common peripherals EALLOW Go
DCh CPUSEL3 CPU Select register for common peripherals EALLOW Go
DEh CPUSEL4 CPU Select register for common peripherals EALLOW Go
E0h CPUSEL5 CPU Select register for common peripherals EALLOW Go
ECh CPUSEL11 CPU Select register for common peripherals EALLOW Go
EEh CPUSEL12 CPU Select register for common peripherals EALLOW Go
F2h CPUSEL14 CPU Select register for common peripherals EALLOW Go
122h CPU2RESCTL CPU2 Reset Control Register EALLOW Go
124h RSTSTAT Reset Status register for secondary C28x CPUs Go
125h LPMSTAT LPM Status Register for secondary C28x CPUs Go
12Ch SYSDBGCTL System Debug Control register EALLOW Go
Table 2-90. DEV_CFG_REGS Access Type Codes

Read Type
R R Read
R=0 R Read
Write Type
W W Write
W=1 W Write
WOnce W Write
W Write
value
formula.
register array.

2.15.9.1 DEVCFGLOCK1 Register (Offset = 0h) [reset = 0h]

DEVCFGLOCK1 is shown in Figure 2-83 and described in Table 2-91.
Lock bit for CPUSELx registers
The locking mechanism applies to only writes. Reads to the registers which have LOCK protection are
always allowed
Note:
Any SOnce bit in this register, once set can only be cleared through a CPU1.SYSRSn. Write of 0 to any
bit of this register has no effect
Figure 2-83. DEVCFGLOCK1 Register

31 30 29 28 27 26 25 24
RESERVED
R=0-0h
23 22 21 20 19 18 17 16
RESERVED
R=0-0h
15 14 13 12 11 10 9 8
RESERVED CPUSEL14 CPUSEL13 CPUSEL12 CPUSEL11 CPUSEL10 CPUSEL9 CPUSEL8
R=0-0h R/WSOnce-0h R/WSOnce-0h R/WSOnce-0h R/WSOnce-0h R/WSOnce-0h R/WSOnce-0h R/WSOnce-0h
7 6 5 4 3 2 1 0
CPUSEL7 CPUSEL6 CPUSEL5 CPUSEL4 CPUSEL3 CPUSEL2 CPUSEL1 CPUSEL0
R/WSOnce-0h R/WSOnce-0h R/WSOnce-0h R/WSOnce-0h R/WSOnce-0h R/WSOnce-0h R/WSOnce-0h R/WSOnce-0h
Table 2-91. DEVCFGLOCK1 Register Field Descriptions

14 CPUSEL14 R/WSOnce 0h Lock bit for CPUSEL14 register:
0: Register is not locked
1: Register is locked

Table 2-91. DEVCFGLOCK1 Register Field Descriptions (continued)


2.15.9.2 PARTIDL_1 Register (Offset = 8h) [reset = X]

PARTIDL_1 is shown in Figure 2-84 and described in Table 2-92.
Lower 32-bit of Device PART Identification Number
Figure 2-84. PARTIDL_1 Register

31 30 29 28 27 26 25 24
PARTID_FORMAT_REVISION RESERVED
R/WOnce-X R/WOnce-X
23 22 21 20 19 18 17 16
FLASH_SIZE
R/WOnce-X
15 14 13 12 11 10 9 8
RESERVED INSTASPIN RESERVED RESERVED PIN_COUNT
R/WOnce-X R/WOnce-X R-0h R-0h R/WOnce-X
7 6 5 4 3 2 1 0
QUAL RESERVED RESERVED RESERVED
R/WOnce-X R/WOnce-X R-0h R-0h
Table 2-92. PARTIDL_1 Register Field Descriptions

31-28 PARTID_FORMAT_REVI R/WOnce X Revision of the PARTID format
SION
Reset type: XRSn
27-24 RESERVED R/WOnce X Reserved
23-16 FLASH_SIZE R/WOnce X 0x7 - 512KB
0x6 - 256KB
Note: This field shows flash size on CPU1 (see datasheet for flash
size available)
Reset type: XRSn
15 RESERVED R/WOnce X Reserved
14-13 INSTASPIN R/WOnce X 0 = Reserved for future
1 = Reserved for future
2 = Reserved for future
3 = NONE
Reset type: XRSn
10-8 PIN_COUNT R/WOnce X 0 = reserved for future
1 = reserved for future
5 = 100 pin
6 = 176 pin
7 = 337 pin
Reset type: XRSn

Table 2-92. PARTIDL_1 Register Field Descriptions (continued)

7-6 QUAL R/WOnce X 0 = Engineering sample.(TMX)
1 = Pilot production (TMP)
2 = Fully qualified (TMS)
Reset type: XRSn
5 RESERVED R/WOnce X Reserved

2.15.9.3 PARTIDH_1 Register (Offset = Ah) [reset = X]

PARTIDH_1 is shown in Figure 2-85 and described in Table 2-93.
Upper 32-bit of Device PART Identification Number
Figure 2-85. PARTIDH_1 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DEVICE_CLASS_ID PARTNO
R/WOnce-X R/WOnce-X
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FAMILY RESERVED
R/WOnce-X R/WOnce-X
Table 2-93. PARTIDH_1 Register Field Descriptions

31-24 DEVICE_CLASS_ID R/WOnce X Reserved
Reset type: XRSn
23-16 PARTNO R/WOnce X Refer to Datasheet for Device Part Number
Reset type: XRSn
15-8 FAMILY R/WOnce X Device Family
0x3 - DELFINO DUAL CORE
0x4 - DELFINO SINGLE CORE
0x5 - PICCOLO SINGLE CORE
Other values Reserved
Reset type: XRSn
7-0 RESERVED R/WOnce X Reserved

2.15.9.4 REVID Register (Offset = Ch) [reset = X]

REVID is shown in Figure 2-86 and described in Table 2-94.
Device Revision Number
Figure 2-86. REVID Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REVID
R-X
Table 2-94. REVID Register Field Descriptions

31-0 REVID R X These 32-bits specify the silicon revision. See your device specific
datasheet for details.
Reset type: N/A

2.15.9.5 DC0_1 Register (Offset = 10h) [reset = X]

DC0_1 is shown in Figure 2-87 and described in Table 2-95.
Device Capability: Device Information
Figure 2-87. DC0_1 Register

31 30 29 28 27 26 25 24
RESERVED
R=0-0h
23 22 21 20 19 18 17 16
RESERVED
R=0-0h
15 14 13 12 11 10 9 8
RESERVED
R=0-0h
7 6 5 4 3 2 1 0
RESERVED SINGLE_CORE
R=0-0h R/WOnce-X
Table 2-95. DC0_1 Register Field Descriptions

0 SINGLE_CORE R/WOnce X Single Core vs Dual Core
0: Single Core
1: Dual Core
Reset type: XRSn


Device Capability: Processing Block Customization

31 30 29 28 27 26 25 24
RESERVED
R=0-0h
23 22 21 20 19 18 17 16
RESERVED
R=0-0h
15 14 13 12 11 10 9 8
RESERVED RESERVED CPU2_CLA1
R=0-0h R-0h R/WOnce-X
7 6 5 4 3 2 1 0
RESERVED CPU1_CLA1 RESERVED CPU2_VCU CPU1_VCU CPU2_FPU_T CPU1_FPU_T
MU MU
R-0h R/WOnce-X R=0-0h R/WOnce-X R/WOnce-X R/WOnce-X R/WOnce-X

8 CPU2_CLA1 R/WOnce X 0 - feature is not present on this device
1 - feature is present on this device
Reset type: XRSn
6 CPU1_CLA1 R/WOnce X 0 - feature is not present on this device
Reset type: XRSn
3 CPU2_VCU R/WOnce X 0 - feature is not present on this device
Reset type: XRSn
2 CPU1_VCU R/WOnce X 0 - feature is not present on this device
Reset type: XRSn
1 CPU2_FPU_TMU R/WOnce X 0 - feature is not present on this device
Reset type: XRSn
0 CPU1_FPU_TMU R/WOnce X 0 - feature is not present on this device
Reset type: XRSn


Device Capability: EMIF Customization

31 30 29 28 27 26 25 24
RESERVED
R=0-0h
23 22 21 20 19 18 17 16
RESERVED
R=0-0h
15 14 13 12 11 10 9 8
RESERVED
R=0-0h
7 6 5 4 3 2 1 0
RESERVED EMIF2 EMIF1
R=0-0h R/WOnce-X R/WOnce-X

1 EMIF2 R/WOnce X EMIF2 :
0: Feature not present on the device
1: Feature present on the device
Reset type: XRSn
0 EMIF1 R/WOnce X EMIF1 :
Reset type: XRSn


Device Capability: Peripheral Customization

31 30 29 28 27 26 25 24
RESERVED
R=0-0h
23 22 21 20 19 18 17 16
RESERVED
R=0-0h
15 14 13 12 11 10 9 8
RESERVED RESERVED RESERVED RESERVED EPWM12 EPWM11 EPWM10 EPWM9
R-0h R-0h R-0h R-0h R/WOnce-X R/WOnce-X R/WOnce-X R/WOnce-X
7 6 5 4 3 2 1 0
EPWM8 EPWM7 EPWM6 EPWM5 EPWM4 EPWM3 EPWM2 EPWM1
R/WOnce-X R/WOnce-X R/WOnce-X R/WOnce-X R/WOnce-X R/WOnce-X R/WOnce-X R/WOnce-X

11 EPWM12 R/WOnce X EPWM12 :
Reset type: XRSn
Reset type: XRSn
Reset type: XRSn
Reset type: XRSn
Reset type: XRSn

Table 2-98. DC3_1 Register Field Descriptions (continued)

Reset type: XRSn
Reset type: XRSn
Reset type: XRSn
Reset type: XRSn
Reset type: XRSn
Reset type: XRSn
Reset type: XRSn



31 30 29 28 27 26 25 24
RESERVED
R=0-0h
23 22 21 20 19 18 17 16
RESERVED
R=0-0h
15 14 13 12 11 10 9 8
RESERVED
R=0-0h
7 6 5 4 3 2 1 0
RESERVED RESERVED ECAP6 ECAP5 ECAP4 ECAP3 ECAP2 ECAP1
R-0h R-0h R/WOnce-X R/WOnce-X R/WOnce-X R/WOnce-X R/WOnce-X R/WOnce-X

5 ECAP6 R/WOnce X ECAP6 :
Reset type: XRSn
Reset type: XRSn
Reset type: XRSn
Reset type: XRSn
Reset type: XRSn
Reset type: XRSn

2.15.9.10 DC5_1 Register (Offset = 1Ah) [reset = X]


31 30 29 28 27 26 25 24
RESERVED
R=0-0h
23 22 21 20 19 18 17 16
RESERVED
R=0-0h
15 14 13 12 11 10 9 8
RESERVED
R=0-0h
7 6 5 4 3 2 1 0
RESERVED RESERVED EQEP3 EQEP2 EQEP1
R=0-0h R-0h R/WOnce-X R/WOnce-X R/WOnce-X

2 EQEP3 R/WOnce X EQEP3 :
Reset type: XRSn
Reset type: XRSn
Reset type: XRSn

2.15.9.11 DC6_1 Register (Offset = 1Ch) [reset = X]


31 30 29 28 27 26 25 24
RESERVED
R=0-0h
23 22 21 20 19 18 17 16
RESERVED
R=0-0h
15 14 13 12 11 10 9 8
RESERVED
R=0-0h
7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED RESERVED CLB4 CLB3 CLB2 CLB1
R-0h R-0h R-0h R-0h R/WOnce-X R/WOnce-X R/WOnce-X R/WOnce-X

3 CLB4 R/WOnce X CLB4 :
Reset type: XRSn
Reset type: XRSn
Reset type: XRSn
Reset type: XRSn

2.15.9.12 DC7_1 Register (Offset = 1Eh) [reset = X]


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R=0-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED RESE RESE RESE RESE RESE RESE SD2 SD1
RVED RVED RVED RVED RVED RVED
R=0-0h R-0h R-0h R-0h R-0h R-0h R-0h R/WO R/WO
nce-X nce-X

1 SD2 R/WOnce X SD2 :
Reset type: XRSn
0 SD1 R/WOnce X SD1 :
Reset type: XRSn



31 30 29 28 27 26 25 24
RESERVED
R=0-0h
23 22 21 20 19 18 17 16
RESERVED
R=0-0h
15 14 13 12 11 10 9 8
RESERVED
R=0-0h
7 6 5 4 3 2 1 0
RESERVED SCI_D SCI_C SCI_B SCI_A
R=0-0h R/WOnce-X R/WOnce-X R/WOnce-X R/WOnce-X

3 SCI_D R/WOnce X SCI_D :
Reset type: XRSn
2 SCI_C R/WOnce X SCI_C :
Reset type: XRSn
1 SCI_B R/WOnce X SCI_B :
Reset type: XRSn
0 SCI_A R/WOnce X SCI_A :
Reset type: XRSn



31 30 29 28 27 26 25 24
RESERVED
R=0-0h
23 22 21 20 19 18 17 16
RESERVED RESERVED RESERVED
R=0-0h R-0h R-0h
15 14 13 12 11 10 9 8
RESERVED
R=0-0h
7 6 5 4 3 2 1 0
RESERVED RESERVED SPI_C SPI_B SPI_A

2 SPI_C R/WOnce X SPI_C :
Reset type: XRSn
1 SPI_B R/WOnce X SPI_B :
Reset type: XRSn
0 SPI_A R/WOnce X SPI_A :
Reset type: XRSn



31 30 29 28 27 26 25 24
RESERVED
R=0-0h
23 22 21 20 19 18 17 16
R=0-0h R-0h R-0h
15 14 13 12 11 10 9 8
RESERVED
R=0-0h
7 6 5 4 3 2 1 0
RESERVED I2C_B I2C_A

1 I2C_B R/WOnce X I2C_B :
Reset type: XRSn
0 I2C_A R/WOnce X I2C_A :
Reset type: XRSn



31 30 29 28 27 26 25 24
RESERVED
R=0-0h
23 22 21 20 19 18 17 16
RESERVED
R=0-0h
15 14 13 12 11 10 9 8
RESERVED
R=0-0h
7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED CAN_B CAN_A
R=0-0h R-0h R-0h R/WOnce-X R/WOnce-X

1 CAN_B R/WOnce X CAN_B :
Reset type: XRSn
0 CAN_A R/WOnce X CAN_A :
Reset type: XRSn



31 30 29 28 27 26 25 24
RESERVED
R=0-0h
23 22 21 20 19 18 17 16
RESERVED RESERVED USB_A
15 14 13 12 11 10 9 8
RESERVED
R=0-0h
7 6 5 4 3 2 1 0
RESERVED McBSP_B McBSP_A

17-16 USB_A R/WOnce X Capability of the USB_A Module:
2'b00: No USB function
2'b01: Device Only
2'b10: Device or Host
2'b11: OTG
Reset type: XRSn
1 McBSP_B R/WOnce X McBSP_B :
Reset type: XRSn
0 McBSP_A R/WOnce X McBSP_A :
Reset type: XRSn

2.15.9.18 DC13_1 Register (Offset = 2Ah) [reset = X]


31 30 29 28 27 26 25 24
RESERVED
R=0-0h
23 22 21 20 19 18 17 16
RESERVED
R=0-0h
15 14 13 12 11 10 9 8
RESERVED
R=0-0h
7 6 5 4 3 2 1 0
RESERVED RESERVED uPP_A

0 uPP_A R/WOnce X uPP_A :
Reset type: XRSn

2.15.9.19 DC14_1 Register (Offset = 2Ch) [reset = X]

Device Capability: Analog Modules Customization

31 30 29 28 27 26 25 24
RESERVED
R=0-0h
23 22 21 20 19 18 17 16
RESERVED
R=0-0h
15 14 13 12 11 10 9 8
RESERVED
R=0-0h
7 6 5 4 3 2 1 0
RESERVED ADC_D ADC_C ADC_B ADC_A

3 ADC_D R/WOnce X ADC_D :
Reset type: XRSn
2 ADC_C R/WOnce X ADC_C :
Reset type: XRSn
1 ADC_B R/WOnce X ADC_B :
Reset type: XRSn
0 ADC_A R/WOnce X ADC_A :
Reset type: XRSn

2.15.9.20 DC15_1 Register (Offset = 2Eh) [reset = X]


31 30 29 28 27 26 25 24
RESERVED
R=0-0h
23 22 21 20 19 18 17 16
RESERVED
R=0-0h
15 14 13 12 11 10 9 8
RESERVED
R=0-0h
7 6 5 4 3 2 1 0
CMPSS8 CMPSS7 CMPSS6 CMPSS5 CMPSS4 CMPSS3 CMPSS2 CMPSS1

7 CMPSS8 R/WOnce X CMPSS8 :
Reset type: XRSn
Reset type: XRSn
Reset type: XRSn
Reset type: XRSn
Reset type: XRSn
Reset type: XRSn


Reset type: XRSn
Reset type: XRSn



31 30 29 28 27 26 25 24
RESERVED
R=0-0h
23 22 21 20 19 18 17 16
RESERVED RESERVED DAC_C DAC_B DAC_A
15 14 13 12 11 10 9 8
RESERVED
R=0-0h
7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED RESERVED RESERVED
R=0-0h R-0h R-0h R-0h R-0h

18 DAC_C R/WOnce X Buffered-DAC_C :
Reset type: XRSn
17 DAC_B R/WOnce X Buffered-DAC_B :
Reset type: XRSn
16 DAC_A R/WOnce X Buffered-DAC_A :
Reset type: XRSn


Device Capability: CPU1 Lx SRAM Customization

31 30 29 28 27 26 25 24
RESERVED
R=0-0h
23 22 21 20 19 18 17 16
RESERVED
R=0-0h
15 14 13 12 11 10 9 8
RESERVED
R=0-0h
7 6 5 4 3 2 1 0
RESERVED LS5_1 LS4_1 LS3_1 LS2_1 LS1_1 LS0_1
R=0-0h R/WOnce-X R/WOnce-X R/WOnce-X R/WOnce-X R/WOnce-X R/WOnce-X

5 LS5_1 R/WOnce X LS5_1 :
Reset type: XRSn
Reset type: XRSn
Reset type: XRSn
Reset type: XRSn
Reset type: XRSn
Reset type: XRSn


Device Capability: CPU2 Lx SRAM Customization

31 30 29 28 27 26 25 24
RESERVED
R=0-0h
23 22 21 20 19 18 17 16
RESERVED
R=0-0h
15 14 13 12 11 10 9 8
RESERVED
R=0-0h
7 6 5 4 3 2 1 0
RESERVED LS5_2 LS4_2 LS3_2 LS2_2 LS1_2 LS0_2
R=0-0h R/WOnce-X R/WOnce-X R/WOnce-X R/WOnce-X R/WOnce-X R/WOnce-X

Reset type: XRSn
Reset type: XRSn
Reset type: XRSn
Reset type: XRSn
Reset type: XRSn
Reset type: XRSn


Device Capability: GSx SRAM Customization

31 30 29 28 27 26 25 24
RESERVED
R=0-0h
23 22 21 20 19 18 17 16
RESERVED
R=0-0h
15 14 13 12 11 10 9 8
GS15 GS14 GS13 GS12 GS11 GS10 GS9 GS8
7 6 5 4 3 2 1 0
GS7 GS6 GS5 GS4 GS3 GS2 GS1 GS0

15 GS15 R/WOnce X GS15 :
Reset type: XRSn
Reset type: XRSn
Reset type: XRSn
Reset type: XRSn
Reset type: XRSn
Reset type: XRSn


Reset type: XRSn
Reset type: XRSn
Reset type: XRSn
Reset type: XRSn
Reset type: XRSn
Reset type: XRSn
Reset type: XRSn
Reset type: XRSn
Reset type: XRSn
Reset type: XRSn

2.15.9.25 PERCNF1_1 Register (Offset = 60h) [reset = X]

PERCNF1_1 is shown in Figure 2-107 and described in Table 2-115.
Peripheral Configuration register
Figure 2-107. PERCNF1_1 Register

31 30 29 28 27 26 25 24
RESERVED
R=0-0h
23 22 21 20 19 18 17 16
RESERVED RESERVED USB_A_PHY
15 14 13 12 11 10 9 8
RESERVED
R=0-0h
7 6 5 4 3 2 1 0
RESERVED ADC_D_MODE ADC_C_MODE ADC_B_MODE ADC_A_MODE
Table 2-115. PERCNF1_1 Register Field Descriptions

16 USB_A_PHY R/WOnce X Internal PHY is present present or not for the USB_A module:
0: Internal USB PHY Module is not present

1: Internal USB PHY Module is present.
Reset type: XRSn
3 ADC_D_MODE R/WOnce X 0: 16-bit or 12-bit configurable in software
1: Only 12-bit operation available
Reset type: XRSn
2 ADC_C_MODE R/WOnce X 0: 16-bit or 12-bit configurable in software
Reset type: XRSn
1 ADC_B_MODE R/WOnce X 0: 16-bit or 12-bit configurable in software
Reset type: XRSn
0 ADC_A_MODE R/WOnce X 0: 16-bit or 12-bit configurable in software
Reset type: XRSn

2.15.9.26 FUSEERR Register (Offset = 74h) [reset = 0h]

FUSEERR is shown in Figure 2-108 and described in Table 2-116.
e-Fuse error Status register
Figure 2-108. FUSEERR Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R=0-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED ERR ALERR
R=0-0h R-0h R-0h
Table 2-116. FUSEERR Register Field Descriptions

5 ERR R 0h Efuse Self Test Error Status set by hardware after fuse self test
completes, in case of self test error
0: No error during fuse self test

1: Fuse self test error
Reset type: XRSn
4-0 ALERR R 0h Efuse Autoload Error Status set by hardware after fuse auto load
completes
00000: No error in auto load

Other: Non zero value indicates error in autoload
Reset type: XRSn

2.15.9.27 SOFTPRES0 Register (Offset = 82h) [reset = 0h]

SOFTPRES0 is shown in Figure 2-109 and described in Table 2-117.
Processing Block Software Reset register
When bits in this register are set, the respective module is in reset. All design data is lost and the module
registers are returned to their reset states. Bits must be manually cleared after being set.
Figure 2-109. SOFTPRES0 Register

31 30 29 28 27 26 25 24
RESERVED
R=0-0h
23 22 21 20 19 18 17 16
RESERVED
R=0-0h
15 14 13 12 11 10 9 8
RESERVED
R=0-0h
7 6 5 4 3 2 1 0
RESERVED RESERVED CPU2_CLA1 RESERVED CPU1_CLA1
R=0-0h R-0h R/W-0h R-0h R/W-0h
Table 2-117. SOFTPRES0 Register Field Descriptions

2 CPU2_CLA1 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
0 CPU1_CLA1 R/W 0h 1: Module is under reset


EMIF Software Reset register

31 30 29 28 27 26 25 24
RESERVED
R=0-0h
23 22 21 20 19 18 17 16
RESERVED
R=0-0h
15 14 13 12 11 10 9 8
RESERVED
R=0-0h
7 6 5 4 3 2 1 0

1 EMIF2 R/W 0h When this bit is set, only the control logic of the respective EMIF2 is
reset. It does not reset the internal registers except the Total Access
register and the Total Activate register.
This bit must be manually cleared after being set.
1: EMIF2 is under SOFTRESET

0: Module reset is determined by the device Reset Network
0 EMIF1 R/W 0h When this bit is set, only the control logic of the respective EMIF1 is
reset. It does not reset the internal registers except the Total Access
register and the Total Activate register.
This bit must be manually cleared after being set.
1: EMIF1 is under SOFTRESET

0: Module reset is determined by the device Reset Network


Peripheral Software Reset register
When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral

31 30 29 28 27 26 25 24
RESERVED
R=0-0h
23 22 21 20 19 18 17 16
RESERVED
R=0-0h
15 14 13 12 11 10 9 8
R-0h R-0h R-0h R-0h R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0

11 EPWM12 R/W 0h 1: Module is under reset

Table 2-119. SOFTPRES2 Register Field Descriptions (continued)




31 30 29 28 27 26 25 24
RESERVED
R=0-0h
23 22 21 20 19 18 17 16
RESERVED
R=0-0h
15 14 13 12 11 10 9 8
RESERVED
R=0-0h
7 6 5 4 3 2 1 0
R-0h R-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

5 ECAP6 R/W 0h 1: Module is under reset

2.15.9.31 SOFTPRES4 Register (Offset = 8Ah) [reset = 0h]


31 30 29 28 27 26 25 24
RESERVED
R=0-0h
23 22 21 20 19 18 17 16
RESERVED
R=0-0h
15 14 13 12 11 10 9 8
RESERVED
R=0-0h
7 6 5 4 3 2 1 0
R=0-0h R-0h R/W-0h R/W-0h R/W-0h

2 EQEP3 R/W 0h 1: Module is under reset

2.15.9.32 SOFTPRES6 Register (Offset = 8Eh) [reset = 0h]


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R=0-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R=0-0h R-0h R-0h R-0h R-0h R-0h R-0h R/W- R/W-
0h 0h

1 SD2 R/W 0h 1: Module is under reset
0 SD1 R/W 0h 1: Module is under reset



31 30 29 28 27 26 25 24
RESERVED
R=0-0h
23 22 21 20 19 18 17 16
RESERVED
R=0-0h
15 14 13 12 11 10 9 8
RESERVED
R=0-0h
7 6 5 4 3 2 1 0
R=0-0h R/W-0h R/W-0h R/W-0h R/W-0h

3 SCI_D R/W 0h 1: Module is under reset
2 SCI_C R/W 0h 1: Module is under reset
1 SCI_B R/W 0h 1: Module is under reset
0 SCI_A R/W 0h 1: Module is under reset



31 30 29 28 27 26 25 24
RESERVED
R=0-0h
23 22 21 20 19 18 17 16
R=0-0h R-0h R-0h
15 14 13 12 11 10 9 8
RESERVED
R=0-0h
7 6 5 4 3 2 1 0

2 SPI_C R/W 0h 1: Module is under reset
1 SPI_B R/W 0h 1: Module is under reset
0 SPI_A R/W 0h 1: Module is under reset



31 30 29 28 27 26 25 24
RESERVED
R=0-0h
23 22 21 20 19 18 17 16
R=0-0h R-0h R-0h
15 14 13 12 11 10 9 8
RESERVED
R=0-0h
7 6 5 4 3 2 1 0

1 I2C_B R/W 0h 1: Module is under reset
0 I2C_A R/W 0h 1: Module is under reset



31 30 29 28 27 26 25 24
RESERVED
R=0-0h
23 22 21 20 19 18 17 16
R=0-0h R-0h R/W-0h
15 14 13 12 11 10 9 8
RESERVED
R=0-0h
7 6 5 4 3 2 1 0

16 USB_A R/W 0h 1: Module is under reset
1 McBSP_B R/W 0h 1: Module is under reset
0 McBSP_A R/W 0h 1: Module is under reset

2.15.9.37 SOFTPRES13 Register (Offset = 9Ch) [reset = 0h]


31 30 29 28 27 26 25 24
RESERVED
R=0-0h
23 22 21 20 19 18 17 16
RESERVED
R=0-0h
15 14 13 12 11 10 9 8
RESERVED
R=0-0h
7 6 5 4 3 2 1 0

3 ADC_D R/W 0h 1: Module is under reset
2 ADC_C R/W 0h 1: Module is under reset
1 ADC_B R/W 0h 1: Module is under reset
0 ADC_A R/W 0h 1: Module is under reset

2.15.9.38 SOFTPRES14 Register (Offset = 9Eh) [reset = 0h]


31 30 29 28 27 26 25 24
RESERVED
R=0-0h
23 22 21 20 19 18 17 16
RESERVED
R=0-0h
15 14 13 12 11 10 9 8
RESERVED
R=0-0h
7 6 5 4 3 2 1 0

7 CMPSS8 R/W 0h 1: Module is under reset

2.15.9.39 SOFTPRES16 Register (Offset = A2h) [reset = 0h]


31 30 29 28 27 26 25 24
RESERVED
R=0-0h
23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8
RESERVED
R=0-0h
7 6 5 4 3 2 1 0
R=0-0h R-0h R-0h R-0h R-0h

18 DAC_C R/W 0h 1: Module is under reset
17 DAC_B R/W 0h 1: Module is under reset
16 DAC_A R/W 0h 1: Module is under reset

2.15.9.40 CPUSEL0 Register (Offset = D6h) [reset = 0h]

CPUSEL0 is shown in Figure 2-122 and described in Table 2-130.
CPU Select register for common peripherals
This register must be configured prior to enabling the peripheral clocks.
The clock for each peripheral is derived from the selected CPU subsystem. The clock mux controlled by
this register is not glitch-free, therefore the CPUSELx register must be configured before the PCLKCRx
register.
The reset for each peripheral is also driven from the selected CPU.
Figure 2-122. CPUSEL0 Register

31 30 29 28 27 26 25 24
RESERVED
R=0-0h
23 22 21 20 19 18 17 16
RESERVED
R=0-0h
15 14 13 12 11 10 9 8
7 6 5 4 3 2 1 0
Table 2-130. CPUSEL0 Register Field Descriptions

11 EPWM12 R/W 0h 0: Connected to CPU1
1: Connected to CPU2

Table 2-130. CPUSEL0 Register Field Descriptions (continued)


2.15.9.41 CPUSEL1 Register (Offset = D8h) [reset = 0h]

register.

31 30 29 28 27 26 25 24
RESERVED
R=0-0h
23 22 21 20 19 18 17 16
RESERVED
R=0-0h
15 14 13 12 11 10 9 8
RESERVED
R=0-0h
7 6 5 4 3 2 1 0

5 ECAP6 R/W 0h 0: Connected to CPU1

2.15.9.42 CPUSEL2 Register (Offset = DAh) [reset = 0h]

register.

31 30 29 28 27 26 25 24
RESERVED
R=0-0h
23 22 21 20 19 18 17 16
RESERVED
R=0-0h
15 14 13 12 11 10 9 8
RESERVED
R=0-0h
7 6 5 4 3 2 1 0

2 EQEP3 R/W 0h 0: Connected to CPU1

2.15.9.43 CPUSEL3 Register (Offset = DCh) [reset = 0h]

register.

31 30 29 28 27 26 25 24
RESERVED
R=0-0h
23 22 21 20 19 18 17 16
RESERVED
R=0-0h
15 14 13 12 11 10 9 8
RESERVED
R=0-0h
7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED


2.15.9.44 CPUSEL4 Register (Offset = DEh) [reset = 0h]

register.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R=0-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0h 0h

1 SD2 R/W 0h 0: Connected to CPU1
0 SD1 R/W 0h 0: Connected to CPU1

2.15.9.45 CPUSEL5 Register (Offset = E0h) [reset = 0h]

register.

31 30 29 28 27 26 25 24
RESERVED
R=0-0h
23 22 21 20 19 18 17 16
RESERVED
R=0-0h
15 14 13 12 11 10 9 8
RESERVED
R=0-0h
7 6 5 4 3 2 1 0

3 SCI_D R/W 0h 0: Connected to CPU1
2 SCI_C R/W 0h 0: Connected to CPU1
1 SCI_B R/W 0h 0: Connected to CPU1
0 SCI_A R/W 0h 0: Connected to CPU1


register.

31 30 29 28 27 26 25 24
RESERVED
R=0-0h
23 22 21 20 19 18 17 16
R=0-0h R-0h R-0h
15 14 13 12 11 10 9 8
RESERVED
R=0-0h
7 6 5 4 3 2 1 0

2 SPI_C R/W 0h 0: Connected to CPU1
1 SPI_B R/W 0h 0: Connected to CPU1
0 SPI_A R/W 0h 0: Connected to CPU1


register.

31 30 29 28 27 26 25 24
RESERVED
R=0-0h
23 22 21 20 19 18 17 16
R=0-0h R-0h R-0h
15 14 13 12 11 10 9 8
RESERVED
R=0-0h
7 6 5 4 3 2 1 0

1 I2C_B R/W 0h 0: Connected to CPU1
0 I2C_A R/W 0h 0: Connected to CPU1


register.

31 30 29 28 27 26 25 24
RESERVED
R=0-0h
23 22 21 20 19 18 17 16
RESERVED
R=0-0h
15 14 13 12 11 10 9 8
RESERVED
R=0-0h
7 6 5 4 3 2 1 0
R=0-0h R-0h R-0h R/W-0h R/W-0h

1 CAN_B R/W 0h 0: Connected to CPU1
0 CAN_A R/W 0h 0: Connected to CPU1


register.

31 30 29 28 27 26 25 24
RESERVED
R=0-0h
23 22 21 20 19 18 17 16
RESERVED
R=0-0h
15 14 13 12 11 10 9 8
RESERVED
R=0-0h
7 6 5 4 3 2 1 0

1 McBSP_B R/W 0h 0: Connected to CPU1
0 McBSP_A R/W 0h 0: Connected to CPU1

2.15.9.50 CPUSEL11 Register (Offset = ECh) [reset = 0h]

register.

31 30 29 28 27 26 25 24
RESERVED
R=0-0h
23 22 21 20 19 18 17 16
RESERVED
R=0-0h
15 14 13 12 11 10 9 8
RESERVED
R=0-0h
7 6 5 4 3 2 1 0

3 ADC_D R/W 0h 0: Connected to CPU1
Note:
[1] These CPUSEL bits affect the ownership of only ADC
Configuration registers by CPU1 or CPU2 (which are mapped on the
mapped to VBUS32). ADC result registers are readable from all
masters without any CPUSEL dependency.
2 ADC_C R/W 0h 0: Connected to CPU1
Note:


1 ADC_B R/W 0h 0: Connected to CPU1
Note:
0 ADC_A R/W 0h 0: Connected to CPU1
Note:

2.15.9.51 CPUSEL12 Register (Offset = EEh) [reset = 0h]

register.

31 30 29 28 27 26 25 24
RESERVED
R=0-0h
23 22 21 20 19 18 17 16
RESERVED
R=0-0h
15 14 13 12 11 10 9 8
RESERVED
R=0-0h
7 6 5 4 3 2 1 0

7 CMPSS8 R/W 0h 0: Connected to CPU1



2.15.9.52 CPUSEL14 Register (Offset = F2h) [reset = 0h]

register.

31 30 29 28 27 26 25 24
RESERVED
R=0-0h
23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8
RESERVED
R=0-0h
7 6 5 4 3 2 1 0
R=0-0h R-0h R-0h R-0h R-0h

18 DAC_C R/W 0h 0: Connected to CPU1
17 DAC_B R/W 0h 0: Connected to CPU1
16 DAC_A R/W 0h 0: Connected to CPU1

2.15.9.53 CPU2RESCTL Register (Offset = 122h) [reset = 1h]

CPU2RESCTL is shown in Figure 2-135 and described in Table 2-143.
CPU2 Reset Control Register
Figure 2-135. CPU2RESCTL Register

31 30 29 28 27 26 25 24
KEY
R=0/W-0h
23 22 21 20 19 18 17 16
KEY
R=0/W-0h
15 14 13 12 11 10 9 8
RESERVED
R=0-0h
7 6 5 4 3 2 1 0
RESERVED RESET
R=0-0h R/W-1h
Table 2-143. CPU2RESCTL Register Field Descriptions

31-16 KEY R=0/W 0h Write to this register succeeds only if this field is written with a value
of 0xa5a5
Note:
[1] Due to this KEY, only 32-bit writes will succeed (provided the
KEY matches). 16-bit writes to the upper or lower half of this register
will be ignored
Reset type: N/A
0 RESET R/W 1h This bit controls the reset input of CPU2 core.
1: CPU2 is held in reset (CPU2.RSn = 0)

0: CPU2 reset is deactivated (CPU2.RSn = 1)
Note:
[1] If CPU2 is not used at-all by an application, it's advisable to put
CPU2 in STANDBY mode rather than in reset to save on active
power component on the CPU2 subsystem. This is because, all
clocks keep toggling when reset is active on the CPU2 sub-system.
[2] Note: If CPU2 is in Standby mode, writing to this bit will have no
effect. CPU2 may be reset by any Chip-level reset (POR, XRSn,
CPU1.WDRSn, or CPU1.NMIWDRSn) or HIBRESETn. Alternately
CPU2 may be woken up by any configured wake-up event.

2.15.9.54 RSTSTAT Register (Offset = 124h) [reset = 0h]

RSTSTAT is shown in Figure 2-136 and described in Table 2-144.
Reset Status register for secondary C28x CPUs
Figure 2-136. RSTSTAT Register

15 14 13 12 11 10 9 8
RESERVED
R=0-0h
7 6 5 4 3 2 1 0
RESERVED CPU2HWBIST CPU2HWBIST CPU2NMIWDR CPU2RES
RST1 RST0 ST
R=0-0h R/W=1-0h R/W=1-0h R/W=1-0h R-0h
Table 2-144. RSTSTAT Register Field Descriptions

3 CPU2HWBISTRST1 R/W=1 0h CPU2HWBISTRST0 and CPU2HWBISTRST1 together indicates
whether a HWBIST reset was issued to CPU2 or not
00: CPU2 was not reset by the CPU2 HWBIST

11: CPU2 was reset due to CPU2 HWBIST reset
This status bit is a latched flag. This flag can be cleared by the
CPU1 by writing a 1
2 CPU2HWBISTRST0 R/W=1 0h CPU2HWBISTRST0 and CPU2HWBISTRST1 together indicates
whether a HWBIST reset was issued to CPU2 or not
00: CPU2 was not reset by the CPU2 HWBIST

11: CPU2 was reset due to CPU2 HWBIST reset
This status bit is a latched flag. This flag can be cleared by the
CPU1 by writing a 1
1 CPU2NMIWDRST R/W=1 0h Indicates whether a CPU2.NMIWD reset was issued to CPU2 or not
0: CPU2 was not reset by the CPU2.NMIWD

1: CPU2 was reset due to CPU2.NMIWD reset
This status bit is a latched flag.This flag can be cleared by the CPU1
by writing a 1
0 CPU2RES R 0h Reset status of CPU2 to CPU1
0: CPU2 core is in reset

1: CPU2 core is out of reset

2.15.9.55 LPMSTAT Register (Offset = 125h) [reset = 0h]

LPMSTAT is shown in Figure 2-137 and described in Table 2-145.
LPM Status Register for secondary C28x CPUs
Figure 2-137. LPMSTAT Register

15 14 13 12 11 10 9 8
RESERVED
R=0-0h
7 6 5 4 3 2 1 0
RESERVED CPU2LPMSTAT
R=0-0h R-0h
Table 2-145. LPMSTAT Register Field Descriptions

1-0 CPU2LPMSTAT R 0h These bits indicate the power mode CPU2
00: CPU2 is in ACTIVE mode

01: CPU2 is in IDLE mode
10: CPU2 is in STANDBY mode
11: Reserved

2.15.9.56 SYSDBGCTL Register (Offset = 12Ch) [reset = 0h]

SYSDBGCTL is shown in Figure 2-138 and described in Table 2-146.
System Debug Control register
Figure 2-138. SYSDBGCTL Register

31 30 29 28 27 26 25 24
RESERVED
R=0-0h
23 22 21 20 19 18 17 16
RESERVED
R=0-0h
15 14 13 12 11 10 9 8
RESERVED
R=0-0h
7 6 5 4 3 2 1 0
RESERVED BIT_0
R=0-0h R/W-0h
Table 2-146. SYSDBGCTL Register Field Descriptions

0 BIT_0 R/W 0h This bit is for use in PLL startup and is only reset by POR.
Reset type: PORn

2.15.10 CLK_CFG_REGS Registers

Table 2-147 lists the memory-mapped registers for the CLK_CFG_REGS. All register offset addresses not
modified.
Table 2-147. CLK_CFG_REGS Registers

0h CLKSEM Clock Control Semaphore Register EALLOW Go
2h CLKCFGLOCK1 Lock bit for CLKCFG registers EALLOW Go
8h CLKSRCCTL1 Clock Source Control register-1 EALLOW Go
Ah CLKSRCCTL2 Clock Source Control register-2 EALLOW Go
Ch CLKSRCCTL3 Clock Source Control register-3 EALLOW Go
Eh SYSPLLCTL1 SYSPLL Control register-1 EALLOW Go
14h SYSPLLMULT SYSPLL Multiplier register EALLOW Go
16h SYSPLLSTS SYSPLL Status register Go
18h AUXPLLCTL1 AUXPLL Control register-1 EALLOW Go
1Eh AUXPLLMULT AUXPLL Multiplier register EALLOW Go
20h AUXPLLSTS AUXPLL Status register Go
22h SYSCLKDIVSEL System Clock Divider Select register EALLOW Go
24h AUXCLKDIVSEL Auxillary Clock Divider Select register EALLOW Go
26h PERCLKDIVSEL Peripheral Clock Divider Selet register EALLOW Go
28h XCLKOUTDIVSEL XCLKOUT Divider Select register EALLOW Go
2Ch LOSPCP Low Speed Clock Source Prescalar EALLOW Go
2Eh MCDCR Missing Clock Detect Control Register EALLOW Go
30h X1CNT 10-bit Counter on X1 Clock Go
Table 2-148. CLK_CFG_REGS Access Type Codes

Read Type
R R Read
R=0 R Read
Write Type
W W Write
W=1 W Write
W Write
value
formula.

Table 2-148. CLK_CFG_REGS Access Type

Codes (continued)
register array.

2.15.10.1 CLKSEM Register (Offset = 0h) [reset = 0h]

CLKSEM is shown in Figure 2-139 and described in Table 2-149.
Clock Control Semaphore Register
Figure 2-139. CLKSEM Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
KEY
R=0/W-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED SEM
R=0-0h R/W-0h
Table 2-149. CLKSEM Register Field Descriptions

31-16 KEY R=0/W 0h Writing the value 0xa5a5 will allow the writing of the SEM bits, else
writes are ignored. Reads will return 0.
Note:
[1] Due to this KEY, only 32-bit writes will succeed (provided the
KEY matches). 16-bit writes to the upper or lower half of this register
will be ignored
Reset type: N/A
1-0 SEM R/W 0h This register provides a mechanism to acquire all the CLKCFG
registers (except this register) by CPU1 or CPU2. A CPU can
perform read/writes to any of the CLKCFG registers (except this
register) only if it owns the semaphore. Otherwise, writes are ignored
and reads will return 0x0.
Semaphore State Transitions:

A value of 00, 10, 11 gives ownership to CPU1
A value of 01 gives ownership to CPU2.
The following are the only state transitions allowed on these bits.
00,11 <-> 01 (allowed by CPU2)
00,11 <-> 10 (allowed by CPU1)
If a CPU doesn't own the CLK_CFG_REGS set of registers (as

defined by the state of this semaphore), reads from that CPU to all
those registers return 0x0 and writes are ignore. Note that this is not
true of CLKSEM register. The CLKSEM register's reads and writes
are always allowed from both CPU1 and CPU2.

2.15.10.2 CLKCFGLOCK1 Register (Offset = 2h) [reset = 0h]

CLKCFGLOCK1 is shown in Figure 2-140 and described in Table 2-150.
Lock bit for CLKCFG registers
Notes:
[1] Any bit in this register, once set can only be cleared through a CPU1.SYSRSn. Write of 0 to any bit of
this register has no effect
[2] The locking mechanism applies to only writes. Reads to the registers which have LOCK protection are
always allowed
Figure 2-140. CLKCFGLOCK1 Register

31 30 29 28 27 26 25 24
RESERVED
R=0-0h
23 22 21 20 19 18 17 16
RESERVED
R=0-0h
15 14 13 12 11 10 9 8
LOSPCP RESERVED PERCLKDIVSE AUXCLKDIVSE SYSCLKDIVSE AUXPLLMULT RESERVED RESERVED
L L L
R/WSOnce-0h R=0-0h R/WSOnce-0h R/WSOnce-0h R/WSOnce-0h R/WSOnce-0h R=0-0h R=0-0h
7 6 5 4 3 2 1 0
AUXPLLCTL1 SYSPLLMULT SYSPLLCTL3 SYSPLLCTL2 SYSPLLCTL1 CLKSRCCTL3 CLKSRCCTL2 CLKSRCCTL1
Table 2-150. CLKCFGLOCK1 Register Field Descriptions

15 LOSPCP R/WSOnce 0h Lock bit for LOSPCP register:
13 PERCLKDIVSEL R/WSOnce 0h Lock bit for PERCLKDIVSEL register:
12 AUXCLKDIVSEL R/WSOnce 0h Lock bit for AUXCLKDIVSEL register:
11 SYSCLKDIVSEL R/WSOnce 0h Lock bit for SYSCLKDIVSEL register:
10 AUXPLLMULT R/WSOnce 0h Lock bit for AUXPLLMULT register:

Table 2-150. CLKCFGLOCK1 Register Field Descriptions (continued)

7 AUXPLLCTL1 R/WSOnce 0h Lock bit for AUXPLLCTL1 register:
6 SYSPLLMULT R/WSOnce 0h Lock bit for SYSPLLMULT register:
5 SYSPLLCTL3 R/WSOnce 0h Lock bit for SYSPLLCTL3 register:
2 CLKSRCCTL3 R/WSOnce 0h Lock bit for CLKSRCCTL3 register:

2.15.10.3 CLKSRCCTL1 Register (Offset = 8h) [reset = 0h]

CLKSRCCTL1 is shown in Figure 2-141 and described in Table 2-151.
Clock Source Control register-1
Figure 2-141. CLKSRCCTL1 Register

31 30 29 28 27 26 25 24
RESERVED
R=0-0h
23 22 21 20 19 18 17 16
RESERVED
R=0-0h
15 14 13 12 11 10 9 8
RESERVED
R=0-0h
7 6 5 4 3 2 1 0
RESERVED WDHALTI XTALOFF INTOSC2OFF RESERVED OSCCLKSRCSEL
R=0-0h R/W-0h R/W-0h R/W-0h R=0-0h R/W-0h
Table 2-151. CLKSRCCTL1 Register Field Descriptions

5 WDHALTI R/W 0h Watchdog HALT Mode Ignore Bit: This bit determines if CPU1.WD is
functional in the HALT mode or not.
0 = CPU1.WD is not functional in the HALT mode. Clock to

CPU1.WD is gated when system enters HALT mode. Additionally,
INTOSC1 and INTOSC2 are powered-down when system enters
HALT mode
1 = CPU1.WD is functional in the HALT mode. Clock to CPU1.WD is
not gated and INTOSC1/2 are not powered-down when system
enters HALT mode
Notes:
[1] Clock to CPU2.WD clocks is always gated in the HALT mode.
Reset type: XRSn
4 XTALOFF R/W 0h Crystal (External) Oscillator Off Bit: This bit turns external oscillator
off:
0 = Crystal (External) Oscillator On (default on reset)
1 = Crystal (External) Oscillator Off
NOTE: Ensure no resources are using a clock source prior to
disabling it. For example OSCCLKSRCSEL (SYSPLL),
AUXOSCCLKSRCSEL (AUXPLL), CANxBCLKSEL (CAN Clock),
TMR2CLKSRCSEL (CPUTIMER2) and XCLKOUTSEL(XCLKOUT).
Reset type: XRSn

Table 2-151. CLKSRCCTL1 Register Field Descriptions (continued)

3 INTOSC2OFF R/W 0h Internal Oscillator 2 Off Bit: This bit turns oscillator 2 off:
0 = Internal Oscillator 2 On (default on reset)
1 = Internal Oscillator 2 Off
This bit could be used by the user to turn off the internal oscillator 2
if it is not used.
NOTE: Ensure no resources are using a clock source prior to

disabling it. For example OSCCLKSRCSEL (SYSPLL),
AUXOSCCLKSRCSEL (AUXPLL), TMR2CLKSRCSEL
(CPUTIMER2) and XCLOCKOUT (XCLKOUT).
Reset type: XRSn
1-0 OSCCLKSRCSEL R/W 0h Oscillator Clock Source Select Bit: This bit selects the source for
OSCCLK.
00 = INTOSC2 (default on reset)
01 = External Oscillator (XTAL)
10 = INTOSC1
11 = reserved (default to INTOSC1)
At power-up or after an XRSn, INTOSC2 is selected by default.

Whenever the user changes the clock source using these bits,
the SYSPLLMULT register will be forced to zero and the PLL will
be bypassed and powered down. This prevents potential PLL
overshoot. The user will then have to write to the SYSPLLMULT
register to configure the appropriate multiplier.
The user must wait 10 OSCCLK cycles before writing to

SYSPLLMULT
or disabling the previous clock source to allow the change to
complete..
Notes:
[1] Reserved selection defaults to 00 configuration
[2] INTOSC1 is recommended to be used only after missing clock
detection. If user wants to re-lock the PLL with INTOSC1 (the back-
up clock source) after missing clock is detected, he can do a
MCLKCLR and lock the PLL.
Reset type: XRSn

2.15.10.4 CLKSRCCTL2 Register (Offset = Ah) [reset = 0h]


31 30 29 28 27 26 25 24
RESERVED
R=0-0h
23 22 21 20 19 18 17 16
RESERVED
R=0-0h
15 14 13 12 11 10 9 8
RESERVED RESERVED
R=0-0h R-0h
7 6 5 4 3 2 1 0
RESERVED CANBBCLKSEL CANABCLKSEL AUXOSCCLKSRCSEL
R-0h R/W-0h R/W-0h R/W-0h

5-4 CANBBCLKSEL R/W 0h CANB Bit-Clock Source Select Bit:
00 = PERx.SYSCLK (default on reset)
10 = AUXCLKIN (from GPIO)
11 = Reserved
Missing clock detect circuit doesnt have any impact on these bits.
Reset type: XRSn
3-2 CANABCLKSEL R/W 0h CANA Bit-Clock Source Select Bit:
00 = PERx.SYSCLK (default on reset)
11 = Reserved
Missing clock detect circuit doesnt have any impact on these bits.
Reset type: XRSn

Table 2-152. CLKSRCCTL2 Register Field Descriptions (continued)

1-0 AUXOSCCLKSRCSEL R/W 0h Oscillator Clock Source Select Bit: This bit selects the source for
AUXOSCCLK:
00 = INTOSC2 (default on reset)
11 = Reserved
Whenever the user changes the clock source using these bits,
the AUXPLLMULT register will be forced to zero and the PLL will
be bypassed and powered down. This prevents potential PLL
overshoot. The user will then have to write to the AUXPLLMULT
register to configure the appropriate multiplier.
The user must wait 10 OSCCLK cycles before writing to

AUXPLLMULT
or disabling the previous clock source to allow the change to
complete.
The missing clock detection circuit does not affect these bits.
Reset type: XRSn

2.15.10.5 CLKSRCCTL3 Register (Offset = Ch) [reset = 0h]


31 30 29 28 27 26 25 24
RESERVED
R=0-0h
23 22 21 20 19 18 17 16
RESERVED
R=0-0h
15 14 13 12 11 10 9 8
RESERVED
R=0-0h
7 6 5 4 3 2 1 0
RESERVED XCLKOUTSEL
R=0-0h R/W-0h

2-0 XCLKOUTSEL R/W 0h XCLKOUT Source Select Bit: This bit selects the source for
XCLKOUT:
000 = PLLSYSCLK (default on reset)
001 = PLLRAWCLK
010 = CPU1.SYSCLK
011 = CPU2.SYSCLK
100 = AUXPLLRAWCLK
101 = INTOSC1
110 = INTOSC2
111 = Reserved

2.15.10.6 SYSPLLCTL1 Register (Offset = Eh) [reset = 0h]

SYSPLLCTL1 is shown in Figure 2-144 and described in Table 2-154.
SYSPLL Control register-1
Figure 2-144. SYSPLLCTL1 Register

31 30 29 28 27 26 25 24
RESERVED
R=0-0h
23 22 21 20 19 18 17 16
RESERVED
R=0-0h
15 14 13 12 11 10 9 8
RESERVED
R=0-0h
7 6 5 4 3 2 1 0
RESERVED PLLCLKEN PLLEN
Table 2-154. SYSPLLCTL1 Register Field Descriptions

1 PLLCLKEN R/W 0h SYSPLL bypassed or included in the PLLSYSCLK path: This bit
decides if the SYSPLL is bypassed when PLLSYSCLK is generated
1 = PLLSYSCLK is fed from the SYSPLL clock output. Users need

to make sure that the PLL is locked before enabling this clock to the
system.
0 = SYSPLL is bypassed. Clock to system is direct feed from
OSCCLK
Reset type: XRSn
0 PLLEN R/W 0h SYSPLL enabled or disabled: This bit decides if the SYSPLL is
enabled or not
1 = SYSPLL is enabled
0 = SYSPLL is powered off. Clock to system is direct feed from
OSCCLK
Reset type: XRSn

2.15.10.7 SYSPLLMULT Register (Offset = 14h) [reset = 0h]

SYSPLLMULT is shown in Figure 2-145 and described in Table 2-155.
SYSPLL Multiplier register
NOTE: FMULT and IMULT fields must be written at the same time for correct PLL operation.
Figure 2-145. SYSPLLMULT Register

31 30 29 28 27 26 25 24
RESERVED
R=0-0h
23 22 21 20 19 18 17 16
RESERVED
R=0-0h
15 14 13 12 11 10 9 8
RESERVED FMULT
R=0-0h R/W-0h
7 6 5 4 3 2 1 0
RESERVED IMULT
R=0-0h R/W-0h
Table 2-155. SYSPLLMULT Register Field Descriptions

9-8 FMULT R/W 0h SYSPLL Fractional Multiplier:
00 Fractional Multiplier = 0
01 Fractional Multiplier = 0.25
Reset type: XRSn
6-0 IMULT R/W 0h SYSPLL Integer Multiplier:
For 0000000 Fout = Fref (PLLBYPASS) Integer Multiplier = 1
0000001 Integer Multiplier = 1
.......
1111111 Integer Multipler = 127
Reset type: XRSn

2.15.10.8 SYSPLLSTS Register (Offset = 16h) [reset = 0h]

SYSPLLSTS is shown in Figure 2-146 and described in Table 2-156.
SYSPLL Status register
Figure 2-146. SYSPLLSTS Register

31 30 29 28 27 26 25 24
RESERVED
R=0-0h
23 22 21 20 19 18 17 16
RESERVED
R=0-0h
15 14 13 12 11 10 9 8
RESERVED
R=0-0h
7 6 5 4 3 2 1 0
RESERVED SLIPS LOCKS
R=0-0h R-0h R-0h
Table 2-156. SYSPLLSTS Register Field Descriptions

1 SLIPS R 0h SYSPLL Slip Status Bit: This bit indicates whether the SYSPLL is
out of lock range
0 = SYSPLL is not out of lock

1 = SYSPLL is out of loc
The SLIPS bit will only be set on a PLL slip condition after the PLL is
used as the SYSCLK source by seting the
SYSPLLCTL1[PLLCLKEN] bit. Disabling and re-enabling the PLL
with PLLEN is the only way to clear this bit.
Note:
[1] If SYSPLL out of lock condition is detected then interrupts are
fired to CPU1 and CPU2 through their respective ePIE modules.
Software can decide to relock the PLL or switch to PLL bypass mode
in the interrupt handler
Reset type: XRSn
0 LOCKS R 0h SYSPLL Lock Status Bit: This bit indicates whether the SYSPLL is
locked or not
0 = SYSPLL is not yet locked

1 = SYSPLL is locked
Reset type: XRSn

2.15.10.9 AUXPLLCTL1 Register (Offset = 18h) [reset = 0h]

AUXPLLCTL1 is shown in Figure 2-147 and described in Table 2-157.
AUXPLL Control register-1
Figure 2-147. AUXPLLCTL1 Register

31 30 29 28 27 26 25 24
RESERVED
R=0-0h
23 22 21 20 19 18 17 16
RESERVED
R=0-0h
15 14 13 12 11 10 9 8
RESERVED
R=0-0h
7 6 5 4 3 2 1 0
RESERVED PLLCLKEN PLLEN
Table 2-157. AUXPLLCTL1 Register Field Descriptions

1 PLLCLKEN R/W 0h AUXPLL bypassed or included in the AUXPLLCLK path: This bit
decides if the AUXPLL is bypassed when AUXPLLCLK is generated
1 = AUXPLLCLK is fed from the AUXPLL clock output. Users need

to make sure that the PLL is locked before enabling this clock to the
AUXPLLCLK connected modules.
0 = AUXPLL is bypassed. Clock to modules connected to
AUXPLLCLK is direct feed from AUXOSCCLK
Reset type: XRSn
0 PLLEN R/W 0h AUXPLL enabled or disabled: This bit decides if the AUXPLL is
enabled or not
1 = AUXPLL is enabled
0 = AUXPLL is powered off. Clock to system is direct feed from
AUXOSCCLK
Reset type: XRSn

2.15.10.10 AUXPLLMULT Register (Offset = 1Eh) [reset = 0h]

AUXPLLMULT is shown in Figure 2-148 and described in Table 2-158.
AUXPLL Multiplier register
NOTE: FMULT and IMULT fields must be written at the same time for correct PLL operation.
Figure 2-148. AUXPLLMULT Register

31 30 29 28 27 26 25 24
RESERVED
R=0-0h
23 22 21 20 19 18 17 16
RESERVED
R=0-0h
15 14 13 12 11 10 9 8
RESERVED FMULT
R=0-0h R/W-0h
7 6 5 4 3 2 1 0
RESERVED IMULT
R=0-0h R/W-0h
Table 2-158. AUXPLLMULT Register Field Descriptions

9-8 FMULT R/W 0h AUXPLL Fractional Multiplier :
00 Fractional Multiplier = 0
Reset type: XRSn
6-0 IMULT R/W 0h AUXPLL Integer Multiplier:
For 0000000 Fout = Fref (PLLBYPASS) Integer Multiplier = 1
.......
1111111 Integer Multipler = 127
Reset type: XRSn

2.15.10.11 AUXPLLSTS Register (Offset = 20h) [reset = 0h]

AUXPLLSTS is shown in Figure 2-149 and described in Table 2-159.
AUXPLL Status register
Figure 2-149. AUXPLLSTS Register

31 30 29 28 27 26 25 24
RESERVED
R=0-0h
23 22 21 20 19 18 17 16
RESERVED
R=0-0h
15 14 13 12 11 10 9 8
RESERVED
R=0-0h
7 6 5 4 3 2 1 0
RESERVED SLIPS LOCKS
R=0-0h R-0h R-0h
Table 2-159. AUXPLLSTS Register Field Descriptions

1 SLIPS R 0h AUXPLL Slip Status Bit: This bit indicates whether the AUXPLL is
out of lock range
0 = AUXPLL is not out of lock

1 = AUXPLL is out of lock
The SLIPS bit will only be set on a PLL slip condition after the PLL is
used as the AUXPLLCLK source by seting the
AUXPLLCTL1[PLLCLKEN] bit. Disabling and re-enabling the PLL
with PLLEN is the only way to clear this bit.
Note:
[1] If AUXPLL out of lock condition is detected then interrupts are
fired to CPU1 and CPU2 through their respective ePIE modules.
Software can decide to relock the PLL or switch to PLL bypass mode
in the interrupt handler
Reset type: XRSn
0 LOCKS R 0h AUXPLL Lock Status Bit: This bit indicates whether the AUXPLL is
locked or not
0 = AUXPLL is not yet locked

1 = AUXPLL is locked
Reset type: XRSn

2.15.10.12 SYSCLKDIVSEL Register (Offset = 22h) [reset = 2h]

SYSCLKDIVSEL is shown in Figure 2-150 and described in Table 2-160.
System Clock Divider Select register
Figure 2-150. SYSCLKDIVSEL Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R=0-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED PLLSYSCLKDIV
R=0-0h R/W-2h
Table 2-160. SYSCLKDIVSEL Register Field Descriptions

5-0 PLLSYSCLKDIV R/W 2h PLLSYSCLK Divide Select: This bit selects the divider setting for the
PLLSYSCLK.
000000 = /1
000001 = /2
000010 = /4 (default on reset)
000011 = /6
000100 = /8
......
111111 = /126
Reset type: XRSn

2.15.10.13 AUXCLKDIVSEL Register (Offset = 24h) [reset = 1h]

AUXCLKDIVSEL is shown in Figure 2-151 and described in Table 2-161.
Auxillary Clock Divider Select register
Figure 2-151. AUXCLKDIVSEL Register

31 30 29 28 27 26 25 24
RESERVED
R=0-0h
23 22 21 20 19 18 17 16
RESERVED
R=0-0h
15 14 13 12 11 10 9 8
RESERVED
R=0-0h
7 6 5 4 3 2 1 0
RESERVED AUXPLLDIV
R=0-0h R/W-1h
Table 2-161. AUXCLKDIVSEL Register Field Descriptions

1-0 AUXPLLDIV R/W 1h AUXPLLCLK Divide Select: This bit selects the divider setting for the
AUXPLLCK.
00 = /1
10 = /4
11 = /8
Reset type: XRSn

2.15.10.14 PERCLKDIVSEL Register (Offset = 26h) [reset = 51h]

PERCLKDIVSEL is shown in Figure 2-152 and described in Table 2-162.
Peripheral Clock Divider Selet register
Figure 2-152. PERCLKDIVSEL Register

31 30 29 28 27 26 25 24
RESERVED
R=0-0h
23 22 21 20 19 18 17 16
RESERVED
R=0-0h
15 14 13 12 11 10 9 8
RESERVED
R=0-0h
7 6 5 4 3 2 1 0
RESERVED EMIF2CLKDIV RESERVED EMIF1CLKDIV RESERVED EPWMCLKDIV
R=0-0h R/W-1h R=0-0h R/W-1h R-0h R/W-1h
Table 2-162. PERCLKDIVSEL Register Field Descriptions

6 EMIF2CLKDIV R/W 1h EMIF2 Clock Divide Select: This bit selects whether the EMIF2
module run with a /1 or /2 clock.
0: /1 of CPU1.SYSCLK is selected
4 EMIF1CLKDIV R/W 1h EMIF1 Clock Divide Select: This bit selects whether the EMIF1
module run with a /1 or /2 clock.
For single core device

For Dual core device
0: /1 of PLLSYSCLK is selected
1: /2 of PLLSYSCLK is selected
1-0 EPWMCLKDIV R/W 1h EPWM Clock Divide Select: This bit selects whether the EPWM
modules run with a /1 or /2 clock. This divider sits in front of the
PLLSYSCLK
x0 = /1 of PLLSYSCLK
x1 = /2 of PLLSYSLCK (default on reset)
Note: Refer to your device specific datasheet for maximum EPWM

Frequency

2.15.10.15 XCLKOUTDIVSEL Register (Offset = 28h) [reset = 3h]

XCLKOUTDIVSEL is shown in Figure 2-153 and described in Table 2-163.
XCLKOUT Divider Select register
Figure 2-153. XCLKOUTDIVSEL Register

31 30 29 28 27 26 25 24
RESERVED
R=0-0h
23 22 21 20 19 18 17 16
RESERVED
R=0-0h
15 14 13 12 11 10 9 8
RESERVED
R=0-0h
7 6 5 4 3 2 1 0
RESERVED XCLKOUTDIV
R=0-0h R/W-3h
Table 2-163. XCLKOUTDIVSEL Register Field Descriptions

1-0 XCLKOUTDIV R/W 3h XCLKOUT Divide Select: This bit selects the divider setting for the
XCLKOUT.
00 = /1
01 = /2
10 = /4

2.15.10.16 LOSPCP Register (Offset = 2Ch) [reset = 2h]

LOSPCP is shown in Figure 2-154 and described in Table 2-164.
Low Speed Clock Source Prescalar
Figure 2-154. LOSPCP Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R=0-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED LSPCLKDIV
R=0-0h R/W-2h
Table 2-164. LOSPCP Register Field Descriptions

2-0 LSPCLKDIV R/W 2h These bits configure the low-speed peripheral clock (LSPCLK) rate
relative to SYSCLK of CPU1 and CPU2.
000,LSPCLK = / 1
001,LSPCLK = / 2
010,LSPCLK = / 4 (default on reset)
011,LSPCLK = / 6
100,LSPCLK = / 8
101,LSPCLK = / 10
110,LSPCLK = / 12
111,LSPCLK = / 14
Note:
[1] This clock is used as strobe for the SCI and SPI modules.

2.15.10.17 MCDCR Register (Offset = 2Eh) [reset = 0h]

MCDCR is shown in Figure 2-155 and described in Table 2-165.
Missing Clock Detect Control Register
Figure 2-155. MCDCR Register

31 30 29 28 27 26 25 24
RESERVED
R=0-0h
23 22 21 20 19 18 17 16
RESERVED
R=0-0h
15 14 13 12 11 10 9 8
RESERVED
R=0-0h
7 6 5 4 3 2 1 0
RESERVED OSCOFF MCLKOFF MCLKCLR MCLKSTS
R=0-0h R/W-0h R/W-0h R=0/W=1-0h R-0h
Table 2-165. MCDCR Register Field Descriptions

3 OSCOFF R/W 0h Oscillator Clock Off Bit:
0 = OSCCLK Connected to OSCCLK Counter in MCD module
1 = OSCCLK Disconnected to OSCCLK Counter in MCD module
Reset type: XRSn
2 MCLKOFF R/W 0h Missing Clock Detect Off Bit:
0 = Missing Clock Detect Circuit Enabled
1 = Missing Clock Detect Circuit Disabled
Reset type: XRSn
1 MCLKCLR R=0/W=1 0h Missing Clock Clear Bit:
Write 1" to this bit to clear MCLKSTS bit and reset the missing clock
detect circuit."
Reset type: XRSn
0 MCLKSTS R 0h Missing Clock Status Bit:
0 = OSCCLK Is OK
1 = OSCCLK Detected Missing, CLOCKFAILn Generated
Reset type: XRSn

2.15.10.18 X1CNT Register (Offset = 30h) [reset = 0h]

X1CNT is shown in Figure 2-156 and described in Table 2-166.
10-bit Counter on X1 Clock
Figure 2-156. X1CNT Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R=0-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED X1CNT
R=0-0h R-0h
Table 2-166. X1CNT Register Field Descriptions

9-0 X1CNT R 0h X1 Counter:
- This counter increments on every X1 CLOCKs positive-edge.
- Once it reaches the values of 0x3ff, it freezes
- Before switching from INTOSC2 to X1, application must check this
counter and make sure that it has saturated. This will guarantee that
the Crystal connected to X1/X2 is powered Up.
Reset type: PORn

2.15.11 CPU_SYS_REGS Registers

Table 2-167 lists the memory-mapped registers for the CPU_SYS_REGS. All register offset addresses not
modified.
Table 2-167. CPU_SYS_REGS Registers

0h CPUSYSLOCK1 Lock bit for CPUSYS registers EALLOW Go
6h HIBBOOTMODE HIB Boot Mode Register EALLOW Go
8h IORESTOREADDR IORestore() routine Address Register EALLOW Go
Ah PIEVERRADDR PIE Vector Fetch Error Address register EALLOW Go
22h PCLKCR0 Peripheral Clock Gating Registers EALLOW Go
2Ah PCLKCR4 Peripheral Clock Gating Registers EALLOW Go
2Eh PCLKCR6 Peripheral Clock Gating Registers EALLOW Go
3Ah PCLKCR12 Peripheral Clock Gating Registers EALLOW Go
3Ch PCLKCR13 Peripheral Clock Gating Registers EALLOW Go
3Eh PCLKCR14 Peripheral Clock Gating Registers EALLOW Go
74h SECMSEL_1 Secondary Master Select register for common EALLOW Go
peripherals: Selects between CLA & DMA
76h LPMCR LPM Control Register EALLOW Go
78h GPIOLPMSEL0 GPIO LPM Wakeup select registers EALLOW Go
7Ah GPIOLPMSEL1 GPIO LPM Wakeup select registers EALLOW Go
7Ch TMR2CLKCTL Timer2 Clock Measurement functionality control EALLOW Go
register
80h RESC Reset Cause register Go
Table 2-168. CPU_SYS_REGS Access Type Codes

Read Type
R R Read
R=0 R Read
Write Type
W W Write
W=1 W Write
W Write
value

Table 2-168. CPU_SYS_REGS Access Type

Codes (continued)
formula.
register array.

2.15.11.1 CPUSYSLOCK1 Register (Offset = 0h) [reset = 0h]

CPUSYSLOCK1 is shown in Figure 2-157 and described in Table 2-169.
Lock bit for CPUSYS registers
Notes:
[1] Any bit in this register, once set can only be cleared through a CPU1.SYSRSn. Write of 0 to any bit of
this register has no effect
[2] The locking mechanism applies to only writes. Reads to the registers which have LOCK protection are
always allowed
Figure 2-157. CPUSYSLOCK1 Register

31 30 29 28 27 26 25 24
RESERVED
R=0-0h
23 22 21 20 19 18 17 16
GPIOLPMSEL1 GPIOLPMSEL0 LPMCR SECMSEL PCLKCR16 PCLKCR15 PCLKCR14 PCLKCR13
15 14 13 12 11 10 9 8
PCLKCR12 PCLKCR11 PCLKCR10 PCLKCR9 PCLKCR8 PCLKCR7 PCLKCR6 PCLKCR5
7 6 5 4 3 2 1 0
PCLKCR4 PCLKCR3 PCLKCR2 PCLKCR1 PCLKCR0 PIEVERRADD IORESTOREA HIBBOOTMOD
R DDR E
Table 2-169. CPUSYSLOCK1 Register Field Descriptions

23 GPIOLPMSEL1 R/WSOnce 0h Lock bit for GPIOLPMSEL1 Register:
Reset type: SYSRSn

22 GPIOLPMSEL0 R/WSOnce 0h Lock bit for GPIOLPMSEL0 Register:
Reset type: SYSRSn

21 LPMCR R/WSOnce 0h Lock bit for LPMCR Register:
Reset type: SYSRSn

20 SECMSEL R/WSOnce 0h Lock bit for SECMSEL Register:
Reset type: SYSRSn

19 PCLKCR16 R/WSOnce 0h Lock bit for PCLKCR16 Register:
Reset type: SYSRSn

Table 2-169. CPUSYSLOCK1 Register Field Descriptions (continued)

Reset type: SYSRSn

Reset type: SYSRSn

Reset type: SYSRSn

Reset type: SYSRSn

Reset type: SYSRSn

Reset type: SYSRSn

Reset type: SYSRSn

Reset type: SYSRSn

Reset type: SYSRSn

Reset type: SYSRSn

Table 2-169. CPUSYSLOCK1 Register Field Descriptions (continued)

Reset type: SYSRSn

Reset type: SYSRSn

Reset type: SYSRSn

Reset type: SYSRSn

Reset type: SYSRSn

Reset type: SYSRSn
2 PIEVERRADDR R/WSOnce 0h Lock bit for PIEVERRADDR Register:
Reset type: SYSRSn
1 IORESTOREADDR R/WSOnce 0h Lock bit for IORESTOREADDR Register:
Reset type: SYSRSn
0 HIBBOOTMODE R/WSOnce 0h Lock bit for HIBBOOTMODE register:
Reset type: SYSRSn

2.15.11.2 HIBBOOTMODE Register (Offset = 6h) [reset = Fh]

HIBBOOTMODE is shown in Figure 2-158 and described in Table 2-170.
HIB Boot Mode Register
Figure 2-158. HIBBOOTMODE Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BMODE
R/W-Fh
Table 2-170. HIBBOOTMODE Register Field Descriptions

31-0 BMODE R/W Fh This register defined the boot mode on a HIB Wakeup. Its the
responsibility of user to initialize the appropriate boot mode before
going into HIB mode. Refer to the Boot ROM section for more details
on this register
Reset type: PORn

2.15.11.3 IORESTOREADDR Register (Offset = 8h) [reset = 003FFFFFh]

IORESTOREADDR is shown in Figure 2-159 and described in Table 2-171.
IORestore() routine Address Register
Figure 2-159. IORESTOREADDR Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED ADDR
R=0-0h R/W-003FFFFFh
Table 2-171. IORESTOREADDR Register Field Descriptions

21-0 ADDR R/W 003FFFFFh This register defines the address of the restoreIO() routine on a HIB
wakeup. Its the responsibility of user to initialize this register with the
restoreIO() routine address before going into HIB mode. Refer to the
Boot ROM section for more details on this register.
Reset type: PORn

2.15.11.4 PIEVERRADDR Register (Offset = Ah) [reset = 003FFFFFh]

PIEVERRADDR is shown in Figure 2-160 and described in Table 2-172.
PIE Vector Fetch Error Address register
Figure 2-160. PIEVERRADDR Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED ADDR
R=0-0h R/W-003FFFFFh
Table 2-172. PIEVERRADDR Register Field Descriptions

21-0 ADDR R/W 003FFFFFh This register defines the address of the PIE Vector Fetch Error
handler routine. Its the responsibility of user to initialize this register.
If this register is not initialized, a default error handler at address
0x3fffbe will get executed. Refer to the Boot ROM section for more
details on this register.
Reset type: XRSn

2.15.11.5 PCLKCR0 Register (Offset = 22h) [reset = 38h]

PCLKCR0 is shown in Figure 2-161 and described in Table 2-173.
Peripheral Clock Gating Registers
Figure 2-161. PCLKCR0 Register

31 30 29 28 27 26 25 24
RESERVED
R=0-0h
23 22 21 20 19 18 17 16
RESERVED GTBCLKSYNC TBCLKSYNC RESERVED HRPWM
R=0-0h R/W-0h R/W-0h R=0-0h R/W-0h
15 14 13 12 11 10 9 8
RESERVED
R=0-0h
7 6 5 4 3 2 1 0
RESERVED CPUTIMER2 CPUTIMER1 CPUTIMER0 DMA RESERVED CLA1
R=0-0h R/W-1h R/W-1h R/W-1h R/W-0h R-0h R/W-0h
Table 2-173. PCLKCR0 Register Field Descriptions

19 GTBCLKSYNC R/W 0h EPWM Time Base Clock Global sync: When set by CPU1, PWM
time bases of all modules start counting. The effect of this bit is seen
on all the EPMW modules irrespective of their partitioning based on
CPUSEL
Notes:
1. This bit on the CPU2.PCLKCR0 register has no effect.
2. Writing '1' to this bit overrides the effect of write '1' to the
TBCLKSYNC bit at the same time
Reset type: SYSRSn
18 TBCLKSYNC R/W 0h EPWM Time Base Clock sync: When set PWM time bases of all the
PWM modules belonging to the same CPU-Subsystem (as
partitioned using their CPUSEL bits) start counting
Notes:
1. This bit from CPU1.PCLKCR0 or CPU2.PCLKCR0 is selected and
fed to the individual EPWM modules based on their respective
CPUSEL bit.
Reset type: SYSRSn
16 HRPWM R/W 0h HRPWM Clock Enable Bit: When set, this enables the clock to the
HRPWM module
1: HRPWM clock is enabled
0: HRPWM clock is disabled
Note:
[1] This bit is present only in CPU1.PCLKCR0. This bit is not used
(R/W) in CPU2.PCLKCR0
Reset type: SYSRSn

Table 2-173. PCLKCR0 Register Field Descriptions (continued)

5 CPUTIMER2 R/W 1h CPUTIMER2 Clock Enable bit:
0: Module clock is gated-off

1: Module clock is turned-on
Reset type: SYSRSn


Reset type: SYSRSn


Reset type: SYSRSn

2 DMA R/W 0h DMA Clock Enable bit:

Reset type: SYSRSn

0 CLA1 R/W 0h CLA1 Clock Enable Bit:

Reset type: SYSRSn



31 30 29 28 27 26 25 24
RESERVED
R=0-0h
23 22 21 20 19 18 17 16
RESERVED
R=0-0h
15 14 13 12 11 10 9 8
RESERVED
R=0-0h
7 6 5 4 3 2 1 0

1 EMIF2 R/W 0h EMIF2 Clock Enable bit:

Notes:
[1] These bits are not used (R/W) in CPU2.PCLKCR1 register.
EMIF1 & EMIF2 clock enabled are controlled only from
CPU1.PCLKCR1 register.
Reset type: SYSRSn
0 EMIF1 R/W 0h EMIF1 Clock Enable bit:

Notes:
[1] These bits are not used (R/W) in CPU2.PCLKCR1 register.
EMIF1 & EMIF2 clock enabled are controlled only from
CPU1.PCLKCR1 register.
Reset type: SYSRSn



31 30 29 28 27 26 25 24
RESERVED
R=0-0h
23 22 21 20 19 18 17 16
RESERVED
R=0-0h
15 14 13 12 11 10 9 8
7 6 5 4 3 2 1 0

11 EPWM12 R/W 0h EPWM12 Clock Enable bit:

Reset type: SYSRSn

Reset type: SYSRSn

Reset type: SYSRSn

Reset type: SYSRSn

Reset type: SYSRSn



Reset type: SYSRSn

Reset type: SYSRSn

Reset type: SYSRSn

Reset type: SYSRSn

Reset type: SYSRSn

Reset type: SYSRSn

Reset type: SYSRSn



31 30 29 28 27 26 25 24
RESERVED
R=0-0h
23 22 21 20 19 18 17 16
RESERVED
R=0-0h
15 14 13 12 11 10 9 8
RESERVED
R=0-0h
7 6 5 4 3 2 1 0

5 ECAP6 R/W 0h ECAP6 Clock Enable bit:

Reset type: SYSRSn

Reset type: SYSRSn

Reset type: SYSRSn

Reset type: SYSRSn

Reset type: SYSRSn



Reset type: SYSRSn

2.15.11.9 PCLKCR4 Register (Offset = 2Ah) [reset = 0h]


31 30 29 28 27 26 25 24
RESERVED
R=0-0h
23 22 21 20 19 18 17 16
RESERVED
R=0-0h
15 14 13 12 11 10 9 8
RESERVED
R=0-0h
7 6 5 4 3 2 1 0

2 EQEP3 R/W 0h EQEP3 Clock Enable bit:

Reset type: SYSRSn

Reset type: SYSRSn

Reset type: SYSRSn

2.15.11.10 PCLKCR6 Register (Offset = 2Eh) [reset = 0h]


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R=0-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0h 0h

1 SD2 R/W 0h SD2 Clock Enable bit:

Reset type: SYSRSn
0 SD1 R/W 0h SD1 Clock Enable bit:

Reset type: SYSRSn



31 30 29 28 27 26 25 24
RESERVED
R=0-0h
23 22 21 20 19 18 17 16
RESERVED
R=0-0h
15 14 13 12 11 10 9 8
RESERVED
R=0-0h
7 6 5 4 3 2 1 0

3 SCI_D R/W 0h SCI_D Clock Enable bit:

Reset type: SYSRSn
2 SCI_C R/W 0h SCI_C Clock Enable bit:

Reset type: SYSRSn
1 SCI_B R/W 0h SCI_B Clock Enable bit:

Reset type: SYSRSn
0 SCI_A R/W 0h SCI_A Clock Enable bit:

Reset type: SYSRSn



31 30 29 28 27 26 25 24
RESERVED
R=0-0h
23 22 21 20 19 18 17 16
R=0-0h R-0h R-0h
15 14 13 12 11 10 9 8
RESERVED
R=0-0h
7 6 5 4 3 2 1 0

2 SPI_C R/W 0h SPI_C Clock Enable bit:

Reset type: SYSRSn
1 SPI_B R/W 0h SPI_B Clock Enable bit:

Reset type: SYSRSn
0 SPI_A R/W 0h SPI_A Clock Enable bit:

Reset type: SYSRSn



31 30 29 28 27 26 25 24
RESERVED
R=0-0h
23 22 21 20 19 18 17 16
R=0-0h R-0h R-0h
15 14 13 12 11 10 9 8
RESERVED
R=0-0h
7 6 5 4 3 2 1 0

1 I2C_B R/W 0h I2C_B Clock Enable bit:

Reset type: SYSRSn
0 I2C_A R/W 0h I2C_A Clock Enable bit:

Reset type: SYSRSn



31 30 29 28 27 26 25 24
RESERVED
R=0-0h
23 22 21 20 19 18 17 16
RESERVED
R=0-0h
15 14 13 12 11 10 9 8
RESERVED
R=0-0h
7 6 5 4 3 2 1 0
R=0-0h R-0h R-0h R/W-0h R/W-0h

1 CAN_B R/W 0h CAN_B Clock Enable bit:

Reset type: SYSRSn
0 CAN_A R/W 0h CAN_A Clock Enable bit:

Reset type: SYSRSn



31 30 29 28 27 26 25 24
RESERVED
R=0-0h
23 22 21 20 19 18 17 16
R=0-0h R-0h R/W-0h
15 14 13 12 11 10 9 8
RESERVED
R=0-0h
7 6 5 4 3 2 1 0

16 USB_A R/W 0h USB_A Clock Enable bit:

Notes:
[1] This bit is not used (R/W) in CPU2.PCLKCR11 register. USB_A
clock enabled is controlled only from CPU1.PCLKCR11 register
Reset type: SYSRSn
1 McBSP_B R/W 0h McBSP_B Clock Enable bit:

Reset type: SYSRSn
0 McBSP_A R/W 0h McBSP_A Clock Enable bit:

Reset type: SYSRSn

2.15.11.16 PCLKCR12 Register (Offset = 3Ah) [reset = 0h]


31 30 29 28 27 26 25 24
RESERVED
R=0-0h
23 22 21 20 19 18 17 16
RESERVED
R=0-0h
15 14 13 12 11 10 9 8
RESERVED
R=0-0h
7 6 5 4 3 2 1 0
RESERVED RESERVED uPP_A
R=0-0h R-0h R/W-0h

0 uPP_A R/W 0h uPP_A Clock Enable bit:

Notes:
[1]] This bit also affects the uPP message RAM wrapper associated
with the respective uPP module
[2] This bit is not used (R/W) in CPU2.PCLKCR12 register. UPP_A
clock enabled is controlled only from CPU1.PCLKCR12 register
Reset type: SYSRSn

2.15.11.17 PCLKCR13 Register (Offset = 3Ch) [reset = 0h]


31 30 29 28 27 26 25 24
RESERVED
R=0-0h
23 22 21 20 19 18 17 16
RESERVED
R=0-0h
15 14 13 12 11 10 9 8
RESERVED
R=0-0h
7 6 5 4 3 2 1 0

3 ADC_D R/W 0h ADC_D Clock Enable bit:

Reset type: SYSRSn
2 ADC_C R/W 0h ADC_C Clock Enable bit:

Reset type: SYSRSn
1 ADC_B R/W 0h ADC_B Clock Enable bit:

Reset type: SYSRSn
0 ADC_A R/W 0h ADC_A Clock Enable bit:

Reset type: SYSRSn

2.15.11.18 PCLKCR14 Register (Offset = 3Eh) [reset = 0h]


31 30 29 28 27 26 25 24
RESERVED
R=0-0h
23 22 21 20 19 18 17 16
RESERVED
R=0-0h
15 14 13 12 11 10 9 8
RESERVED
R=0-0h
7 6 5 4 3 2 1 0

7 CMPSS8 R/W 0h CMPSS8 Clock Enable bit:

Reset type: SYSRSn

Reset type: SYSRSn

Reset type: SYSRSn

Reset type: SYSRSn

Reset type: SYSRSn

Reset type: SYSRSn



Reset type: SYSRSn

Reset type: SYSRSn



31 30 29 28 27 26 25 24
RESERVED
R=0-0h
23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8
RESERVED
R=0-0h
7 6 5 4 3 2 1 0
R=0-0h R-0h R-0h R-0h R-0h

18 DAC_C R/W 0h Buffered_DAC_C Clock Enable Bit:

Reset type: SYSRSn
17 DAC_B R/W 0h Buffered_DAC_B Clock Enable Bit:

Reset type: SYSRSn
16 DAC_A R/W 0h Buffered_DAC_A Clock Enable Bit:

Reset type: SYSRSn

2.15.11.20 SECMSEL_1 Register (Offset = 74h) [reset = 0h]

SECMSEL_1 is shown in Figure 2-176 and described in Table 2-188.
Secondary Master Select register for common peripherals: Selects between CLA & DMA
Figure 2-176. SECMSEL_1 Register

31 30 29 28 27 26 25 24
RESERVED
R=0-0h
23 22 21 20 19 18 17 16
RESERVED
R=0-0h
15 14 13 12 11 10 9 8
RESERVED RESERVED RESERVED RESERVED
R=0-0h R-0h R-0h R-0h
7 6 5 4 3 2 1 0
RESERVED RESERVED PF2SEL PF1SEL
R-0h R-0h R/W-0h R/W-0h
Table 2-188. SECMSEL_1 Register Field Descriptions

3-2 PF2SEL R/W 0h This bit selects whether the dual ported bridge is connected with
DMA or CLA as the secondary master (C28x is always connected as
primary master)
x0: Bridge is connected to CLA

x1: Bridge is connected to DMA
Reset type: SYSRSn
1-0 PF1SEL R/W 0h This bit selects whether the dual ported bridge is connected with
DMA or CLA as the secondary master (C28x is always connected as
primary master)
x0: Bridge is connected to CLA

x1: Bridge is connected to DMA
Reset type: SYSRSn

2.15.11.21 LPMCR Register (Offset = 76h) [reset = FCh]

LPMCR is shown in Figure 2-177 and described in Table 2-189.
LPM Control Register
Figure 2-177. LPMCR Register

31 30 29 28 27 26 25 24
IOISODIS RESERVED
R/W=1-0h R=0-0h
23 22 21 20 19 18 17 16
RESERVED M0M1MODE
R=0-0h R/W-0h
15 14 13 12 11 10 9 8
WDINTE RESERVED
R/W-0h R=0-0h
7 6 5 4 3 2 1 0
QUALSTDBY LPM
R/W-3Fh R/W-0h
Table 2-189. LPMCR Register Field Descriptions

31 IOISODIS R/W=1 0h 0: Indicates IO ISOLATION is not turned ON
1: Indicates IO ISOLATION is turned ON. This bit is set one by
hardware ONLY during HIB. This bit cant be set to 1 by software
Writing 0 to this bit has not effect.

Writing 1 to this bit deactivates IO ISOLATION
Notes:
[1] This bit is reserved in the register mapped to CPU2
Reset type: raw-XRSn
17-16 M0M1MODE R/W 0h These bit control the state of CPU1's and CPU2's M0 & M1
memories when Device goes into HIB mode.
00: CPUx's M0 & M1 memories ON with low-leakage mode

01: CPUx's M0 & M1 memories OFF
1x: Reserved
Notes:
[1] Low-leakage mode for M0 & M1 memories uses the "Retention"
feature of the SRAMs.
[2] These bits take effect only when device goes into HIB mode. If
the device is not in HIB mode, the value in this bit doesn't control the
state of CPU1's and CPU2's M0 & M1 memories
Reset type: PORn
15 WDINTE R/W 0h When this bit is set to 1, it enables the watchdog interrupt signal to
wake the device from STANDBY mode.
Note:
[1] To use this signal, the user must also enable the WDINTn signal
using the WDENINT bit in the SCSR register. This signal will not
wake the device from HALT mode because the clock to watchdog
module is turned off
Reset type: SYSRSn

Table 2-189. LPMCR Register Field Descriptions (continued)

7-2 QUALSTDBY R/W 3Fh Select number of OSCCLK clock cycles to qualify the selected inputs
when waking the from STANDBY mode:
000000 = 2 OSCCLKs
000001 = 3 OSCCLKs
......
111111 = 65 OSCCLKs
Note: The LPMCR.QUALSTDBY register should be set to a value

greater than the ratio of INTOSC1/PLLSYSCLK to ensure proper
wake up.
Reset type: SYSRSn
1-0 LPM R/W 0h These bits set the low power mode for the device. Takes effect when
CPU executes the IDLE instruction (when IDLE instruction is out of
EXE Phase of the Pipeline)
00: IDLE Mode

01: STANDBY Mode
10: HALT Mode (treated as STANDBY for CPU2)
11: HIB Mode (treated as STANDBY for CPU2)
Reset type: SYSRSn

2.15.11.22 GPIOLPMSEL0 Register (Offset = 78h) [reset = 0h]

GPIOLPMSEL0 is shown in Figure 2-178 and described in Table 2-190.
GPIO LPM Wakeup select registers
Connects the selected pin to the LPM circuit. Refer to LPM section of the TRM for the wakeup capabilities
of the selected pin.
Figure 2-178. GPIOLPMSEL0 Register

31 30 29 28 27 26 25 24
GPIO31 GPIO30 GPIO29 GPIO28 GPIO27 GPIO26 GPIO25 GPIO24
23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8
7 6 5 4 3 2 1 0
Table 2-190. GPIOLPMSEL0 Register Field Descriptions

31 GPIO31 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn

Table 2-190. GPIOLPMSEL0 Register Field Descriptions (continued)

Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn


Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn

2.15.11.23 GPIOLPMSEL1 Register (Offset = 7Ah) [reset = 0h]

GPIOLPMSEL1 is shown in Figure 2-179 and described in Table 2-191.
GPIO LPM Wakeup select registers
Connects the selected pin to the LPM circuit. Refer to LPM section of the TRM for the wakeup capabilities
of the selected pin.
Figure 2-179. GPIOLPMSEL1 Register

31 30 29 28 27 26 25 24
23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8
7 6 5 4 3 2 1 0
Table 2-191. GPIOLPMSEL1 Register Field Descriptions

Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn


Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn


Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn

2.15.11.24 TMR2CLKCTL Register (Offset = 7Ch) [reset = 0h]

TMR2CLKCTL is shown in Figure 2-180 and described in Table 2-192.
Timer2 Clock Measurement functionality control register
Figure 2-180. TMR2CLKCTL Register

31 30 29 28 27 26 25 24
RESERVED
R=0-0h
23 22 21 20 19 18 17 16
RESERVED
R=0-0h
15 14 13 12 11 10 9 8
RESERVED
R=0-0h
7 6 5 4 3 2 1 0
RESERVED TMR2CLKPRESCALE TMR2CLKSRCSEL
Table 2-192. TMR2CLKCTL Register Field Descriptions

5-3 TMR2CLKPRESCALE R/W 0h CPU Timer 2 Clock Pre-Scale Value: These bits select the pre-scale
value for the selected clock source for CPU Timer 2:
0,0,0,/1 (default on reset)
0,0,1,/2,
0,1,0,/4
0,1,1,/8
1,0,0,/16
1,0,1,spare (defaults to /16)
Note:
[1] The CPU Timer2s Clock sync logic detects an input clock edge
when configured for any clock source other than SYSCLK and
generates an appropriate clock pulse to the CPU timer2. If SYSCLK
is approximately the same or less then the input clock source, then
the user would need to configure the pre-scale value such that
SYSCLK is at least twice as fast as the pre-scaled value.
[2] Pre-scaler is bypassed if SYSCLK is selected as the source of
CPU Timer 2 in TMR2CLKSRCSEL of TMR2CLKCTL.
Reset type: SYSRSn

Table 2-192. TMR2CLKCTL Register Field Descriptions (continued)

2-0 TMR2CLKSRCSEL R/W 0h CPU Timer 2 Clock Source Select Bit: This bit selects the source for
CPU Timer 2:
000 =SYSCLK Selected (default on reset, pre-scale is bypassed)
001 = INTOSC1
010 = INTOSC2
011 = XTAL
100 = Reserved
101 = Reserved
110 = AUXPLLCLK
111 = reserved
Reset type: SYSRSn

2.15.11.25 RESC Register (Offset = 80h) [reset = X]

RESC is shown in Figure 2-181 and described in Table 2-193.
Reset Cause register
Figure 2-181. RESC Register

31 30 29 28 27 26 25 24
TRSTn_pin_sta XRSn_pin_stat RESERVED
tus us
R-X R-X R=0-0h
23 22 21 20 19 18 17 16
RESERVED
R=0-0h
15 14 13 12 11 10 9 8
RESERVED SCCRESETn
R=0-0h R/W=1-0h
7 6 5 4 3 2 1 0
RESERVED HIBRESETn HWBISTn RESERVED NMIWDRSn WDRSn XRSn POR
R=0-0h R/W=1-0h R/W=1-0h R=0-0h R/W=1-0h R/W=1-0h R/W=1-1h R/W=1-1h
Table 2-193. RESC Register Field Descriptions

31 TRSTn_pin_status R X Reading this bit provides the current status of TRSTn at the
respective C28x CPUs TRSTn input port. Reset value is reflective of
the pin status.
Reset type: N/A
30 XRSn_pin_status R X Reading this bit provides the current status of the XRSn pin. Reset
value is reflective of the pin status.
Reset type: N/A
8 SCCRESETn R/W=1 0h If this bit is set, indicates that the device was reset by SCCRESETn
(fired by DCSM).
Writing a 1 to this bit will force the bit to 0

Writing of 0 will have no effect.
Reset type: PORn
6 HIBRESETn R/W=1 0h If this bit is set, indicates that the device was reset due to a
Hibernate mode Wakeup.

Reset type: raw-XRSn
5 HWBISTn R/W=1 0h If this bit is set, indicates that the device was reset by HWBIST.

Reset type: PORn

Table 2-193. RESC Register Field Descriptions (continued)

3 NMIWDRSn R/W=1 0h If this bit is set, indicates that the device was reset by NMIWDRSn.

To know the exact cause of NMI after the reset, software needs to
read CPU1/2.NMISHDFLG registers
Reset type: PORn
2 WDRSn R/W=1 0h If this bit is set, indicates that the device was reset by WDRSn.

Reset type: PORn
1 XRSn R/W=1 1h If this bit is set, indicates that the device was reset by XRSn.

Reset type: PORn
0 POR R/W=1 1h If this bit is set, indicates that the device was reset by PORn.

Reset type: PORn

2.15.12 ROM_PREFETCH_REGS Registers

Table 2-194 lists the memory-mapped registers for the ROM_PREFETCH_REGS. All register offset
Table 2-194. ROM_PREFETCH_REGS Registers

0h ROMPREFETCH ROM Prefetch Configuration Register EALLOW Go
Table 2-195. ROM_PREFETCH_REGS Access Type

Codes
Read Type
R R Read
Write Type
W W Write
value
formula.
register array.

2.15.12.1 ROMPREFETCH Register (Offset = 0h) [reset = 0h]

ROMPREFETCH is shown in Figure 2-182 and described in Table 2-196.
ROM Prefetch Configuration Register
Figure 2-182. ROMPREFETCH Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED PFENABLE
R-0h R/W-0h
Table 2-196. ROMPREFETCH Register Field Descriptions

0 PFENABLE R/W 0h 0: Prefetch is disabled for secure ROM and boot ROM.
1: Prefetch is enabled for secure ROM and boot ROM.
Reset type: SYSRSn

2.15.13 DCSM_Z1_OTP Registers

Table 2-197 lists the memory-mapped registers for the DCSM_Z1_OTP. All register offset addresses not
modified.
Table 2-197. DCSM_Z1_OTP Registers

0h Z1OTP_LINKPOINTER1 Zone 1 Link Pointer1 in Z1 OTP Go
10h Z1OTP_PSWDLOCK Secure Password Lock in Z1 OTP Go
14h Z1OTP_CRCLOCK Secure CRC Lock in Z1 OTP Go
1Eh Z1OTP_BOOTCTRL Boot Mode in Z1 OTP Go
Table 2-198. DCSM_Z1_OTP Access Type Codes

Read Type
R R Read
value
formula.
register array.

2.15.13.1 Z1OTP_LINKPOINTER1 Register (Offset = 0h) [reset = FFFFFFFFh]

Z1OTP_LINKPOINTER1 is shown in Figure 2-183 and described in Table 2-199.
Zone 1 Link Pointer1 in Z1 OTP
Figure 2-183. Z1OTP_LINKPOINTER1 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z1OTP_LINKPOINTER1
R-FFFFFFFFh
Table 2-199. Z1OTP_LINKPOINTER1 Register Field Descriptions

31-0 Z1OTP_LINKPOINTER1 R FFFFFFFFh Zone1 Link Pointer 1 location in USER OTP.
Reset type: SYSRSn



31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z1OTP_LINKPOINTER2
R-FFFFFFFFh

Reset type: SYSRSn



31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z1OTP_LINKPOINTER3
R-FFFFFFFFh

Reset type: SYSRSn

2.15.13.4 Z1OTP_PSWDLOCK Register (Offset = 10h) [reset = FFFFFFFFh]

Z1OTP_PSWDLOCK is shown in Figure 2-186 and described in Table 2-202.
Secure Password Lock in Z1 OTP
Figure 2-186. Z1OTP_PSWDLOCK Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z1OTP_PSWDLOCK
R-FFFFFFFFh
Table 2-202. Z1OTP_PSWDLOCK Register Field Descriptions

31-0 Z1OTP_PSWDLOCK R FFFFFFFFh Zone1 password lock location in USER OTP.
Reset type: SYSRSn

2.15.13.5 Z1OTP_CRCLOCK Register (Offset = 14h) [reset = FFFFFFFFh]

Z1OTP_CRCLOCK is shown in Figure 2-187 and described in Table 2-203.
Secure CRC Lock in Z1 OTP
Figure 2-187. Z1OTP_CRCLOCK Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z1OTP_CRCLOCK
R-FFFFFFFFh
Table 2-203. Z1OTP_CRCLOCK Register Field Descriptions

31-0 Z1OTP_CRCLOCK R FFFFFFFFh Zone1 CRC lock location in USER OTP.
Reset type: SYSRSn

2.15.13.6 Z1OTP_BOOTCTRL Register (Offset = 1Eh) [reset = FFFFFFFFh]

Z1OTP_BOOTCTRL is shown in Figure 2-188 and described in Table 2-204.
Boot Mode in Z1 OTP
Figure 2-188. Z1OTP_BOOTCTRL Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z1OTP_BOOTCTRL
R-FFFFFFFFh
Table 2-204. Z1OTP_BOOTCTRL Register Field Descriptions

31-0 Z1OTP_BOOTCTRL R FFFFFFFFh Zone1 Boot control location in USER OTP.
Reset type: SYSRSn

2.15.14 DCSM_Z2_OTP Registers

Table 2-205 lists the memory-mapped registers for the DCSM_Z2_OTP. All register offset addresses not
modified.
Table 2-205. DCSM_Z2_OTP Registers

10h Z2OTP_PSWDLOCK Secure Password Lock in Z2 OTP Go
14h Z2OTP_CRCLOCK Secure CRC Lock in Z2 OTP Go
1Eh Z2OTP_BOOTCTRL Boot Mode in Z2 OTP Go
Table 2-206. DCSM_Z2_OTP Access Type Codes

Read Type
R R Read
value
formula.
register array.



31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z2OTP_LINKPOINTER1
R-FFFFFFFFh

Reset type: SYSRSn



31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z2OTP_LINKPOINTER2
R-FFFFFFFFh

Reset type: SYSRSn



31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z2OTP_LINKPOINTER3
R-FFFFFFFFh

Reset type: SYSRSn

2.15.14.4 Z2OTP_PSWDLOCK Register (Offset = 10h) [reset = FFFFFFFFh]

Z2OTP_PSWDLOCK is shown in Figure 2-192 and described in Table 2-210.
Secure Password Lock in Z2 OTP
Figure 2-192. Z2OTP_PSWDLOCK Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z2OTP_PSWDLOCK
R-FFFFFFFFh
Table 2-210. Z2OTP_PSWDLOCK Register Field Descriptions

31-0 Z2OTP_PSWDLOCK R FFFFFFFFh Zone2 password lock location in USER OTP.
Reset type: SYSRSn

2.15.14.5 Z2OTP_CRCLOCK Register (Offset = 14h) [reset = FFFFFFFFh]

Z2OTP_CRCLOCK is shown in Figure 2-193 and described in Table 2-211.
Secure CRC Lock in Z2 OTP
Figure 2-193. Z2OTP_CRCLOCK Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z2OTP_CRCLOCK
R-FFFFFFFFh
Table 2-211. Z2OTP_CRCLOCK Register Field Descriptions

31-0 Z2OTP_CRCLOCK R FFFFFFFFh Zone2 CRC lock location in USER OTP.
Reset type: SYSRSn

2.15.14.6 Z2OTP_BOOTCTRL Register (Offset = 1Eh) [reset = FFFFFFFFh]

Z2OTP_BOOTCTRL is shown in Figure 2-194 and described in Table 2-212.
Boot Mode in Z2 OTP
Figure 2-194. Z2OTP_BOOTCTRL Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z2OTP_BOOTCTRL
R-FFFFFFFFh
Table 2-212. Z2OTP_BOOTCTRL Register Field Descriptions

31-0 Z2OTP_BOOTCTRL R FFFFFFFFh Zone2 Boot control location in USER OTP.
Reset type: SYSRSn

2.15.15 DCSM_Z1_REGS Registers

Table 2-213 lists the memory-mapped registers for the DCSM_Z1_REGS. All register offset addresses not
modified.
Table 2-213. DCSM_Z1_REGS Registers

0h Z1_LINKPOINTER Zone 1 Link Pointer Go
2h Z1_OTPSECLOCK Zone 1 OTP Secure JTAG lock Go
4h Z1_BOOTCTRL Boot Mode Go
6h Z1_LINKPOINTERERR Link Pointer Error Go
10h Z1_CSMKEY0 Zone 1 CSM Key 0 Go
19h Z1_CR Zone 1 CSM Control Register Go
1Ah Z1_GRABSECTR Zone 1 Grab Flash Sectors Register Go
1Ch Z1_GRABRAMR Zone 1 Grab RAM Blocks Register Go
1Eh Z1_EXEONLYSECTR Zone 1 Flash Execute_Only Sector Register Go
20h Z1_EXEONLYRAMR Zone 1 RAM Execute_Only Block Register Go
Table 2-214. DCSM_Z1_REGS Access Type Codes

Read Type
R R Read
R=0 R Read
Write Type
W W Write
value
formula.
register array.

2.15.15.1 Z1_LINKPOINTER Register (Offset = 0h) [reset = E0000000h]

Z1_LINKPOINTER is shown in Figure 2-195 and described in Table 2-215.
Zone 1 Link Pointer
Figure 2-195. Z1_LINKPOINTER Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED LINKPOINTER
R-7h R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LINKPOINTER
R-0h
Table 2-215. Z1_LINKPOINTER Register Field Descriptions

28-0 LINKPOINTER R 0h This is resolved Link-Pointer value which is generated by looking at
the three physical Link-Pointer values loaded from OTP.
Reset type: SYSRSn

2.15.15.2 Z1_OTPSECLOCK Register (Offset = 2h) [reset = FFFh]

Z1_OTPSECLOCK is shown in Figure 2-196 and described in Table 2-216.
Zone 1 OTP Secure JTAG lock
Figure 2-196. Z1_OTPSECLOCK Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED CRCLOCK PSWDLOCK RESERVED
R-0h R-Fh R-Fh R-0h
Table 2-216. Z1_OTPSECLOCK Register Field Descriptions

11-8 CRCLOCK R Fh Value in this field gets loaded from Z1_CRCLOCK[11:8] when a read
is issued to address location of Z1_CRCLOCK in OTP.
1111 : VCU has ability to calculate CRC on secure memories.

Other Value : VCU doesn't have ability to calculate CRC on secure
memories.
Reset type: SYSRSn
7-4 PSWDLOCK R Fh Value in this field gets loaded from Z1_PSWDLOCK[7:4] when a
read is issued to address location of Z1_PSWDLOCK in OTP.
1111 : CSM password locations in OTP are not protected and can
be read from debugger as well as code running from anywhere.
Other Value : CSM password locations in OTP are protected and
can't be read without unlocking CSM of that zone.
Reset type: SYSRSn

2.15.15.3 Z1_BOOTCTRL Register (Offset = 4h) [reset = 0h]

Z1_BOOTCTRL is shown in Figure 2-197 and described in Table 2-217.
Boot Mode
Figure 2-197. Z1_BOOTCTRL Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BOOTPIN1 BOOTPIN0 BMODE KEY
R-0h R-0h R-0h R-0h
Table 2-217. Z1_BOOTCTRL Register Field Descriptions

31-24 BOOTPIN1 R 0h This field gets loaded with Z1_BOOTCTRL[31:24] when a dummy
read is issued to address location of Z1_BOOTCTRL in OTP.
This assigns the pin to be used as BOOTPIN1.
0 : Pick default bootmode pin.
1 : Pick GPIO0 as BOOTPIN1.
....
....
n : Pick GPIOn-1 as BOOTPIN1.
Reset type: SYSRSn
....
....
Reset type: SYSRSn
15-8 BMODE R 0h This field gets loaded with Z1_BOOTCTRL[16:8] when a dummy
Reset type: SYSRSn
7-0 KEY R 0h This field gets loaded with Z1_BOOTCTRL[7:0] when a dummy read
is issued to address location of Z1_BOOTCTRL in OTP.
Reset type: SYSRSn

2.15.15.4 Z1_LINKPOINTERERR Register (Offset = 6h) [reset = FFFFFFFFh]

Z1_LINKPOINTERERR is shown in Figure 2-198 and described in Table 2-218.
Link Pointer Error
Figure 2-198. Z1_LINKPOINTERERR Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z1_LINKPOINTERERR
R-FFFFFFFFh
Table 2-218. Z1_LINKPOINTERERR Register Field Descriptions

31-0 Z1_LINKPOINTERERR R FFFFFFFFh These bits indicate errors during formation of the resolved Link-
Pointer value after the three physical Link-Pointer values loaded of
OTP.
0 : No Error.
Other : Error on bit positions which is set to 1.
Reset type: SYSRSn

2.15.15.5 Z1_CSMKEY0 Register (Offset = 10h) [reset = 0h]

Z1_CSMKEY0 is shown in Figure 2-199 and described in Table 2-219.
Zone 1 CSM Key 0
Figure 2-199. Z1_CSMKEY0 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z1_CSMKEY0
R-0h
Table 2-219. Z1_CSMKEY0 Register Field Descriptions

31-0 Z1_CSMKEY0 R 0h To unclock Zone1, user needs to write this regsiter with exact value
as Z1_CSMPSWD0, programmed in OTP (zone gets unlock only if
128 bit password in OTP match with value written in four CSMKEY
registers.)
Reset type: SYSRSn


Zone 1 CSM Key 1

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z1_CSMKEY1
R-0h

registers.)
Reset type: SYSRSn


Zone 1 CSM Key 2

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z1_CSMKEY2
R-0h

registers.)
Reset type: SYSRSn


Zone 1 CSM Key 3

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z1_CSMKEY3
R-0h

registers.)
Reset type: SYSRSn

2.15.15.9 Z1_CR Register (Offset = 19h) [reset = 8h]

Z1_CR is shown in Figure 2-203 and described in Table 2-223.
Zone 1 CSM Control Register
Figure 2-203. Z1_CR Register

15 14 13 12 11 10 9 8
FORCESEC RESERVED
R=0/W-0h R-0h
7 6 5 4 3 2 1 0
RESERVED ARMED UNSECURE ALLONE ALLZERO RESERVED
R-0h R-0h R-0h R-0h R-1h R-0h
Table 2-223. Z1_CR Register Field Descriptions

15 FORCESEC R=0/W 0h A write '1' to this fields resets the state of zone. If zone is unlocked,
it'll lock(secure) the zone and also resets all the bits in this register.
Reset type: SYSRSn
6 ARMED R 0h 0 : Dummy read to CSM Password locations in OTP hasn't been
performed.
1 : Dummy read to CSM Password locations in OTP has been
performed.
Reset type: SYSRSn
5 UNSECURE R 0h Indiacates the state of Zone.
0 : Zone is in lock(secure) state.

1 : Zone is in unlock(unsecure) state.
Reset type: SYSRSn
4 ALLONE R 0h Indicates the state of CSM passowrds.
0 : CSM Passwords are not all ones.

1 : CSM Passwords are all ones and zone is in unlock state.
Reset type: SYSRSn
3 ALLZERO R 1h Indicates the state of CSM passowrds.
0 : CSM Passwords are not all zeros.

1 : CSM Passwords are all zero and device is permanently locked.
Reset type: SYSRSn

2.15.15.10 Z1_GRABSECTR Register (Offset = 1Ah) [reset = 0h]

Z1_GRABSECTR is shown in Figure 2-204 and described in Table 2-224.
Zone 1 Grab Flash Sectors Register
Figure 2-204. Z1_GRABSECTR Register

31 30 29 28 27 26 25 24
RESERVED RESERVED GRAB_SECTN GRAB_SECTM
R-0h R-0h R-0h R-0h
23 22 21 20 19 18 17 16
GRAB_SECTL GRAB_SECTK GRAB_SECTJ GRAB_SECTI
R-0h R-0h R-0h R-0h
15 14 13 12 11 10 9 8
GRAB_SECTH GRAB_SECTG GRAB_SECTF GRAB_SECTE
R-0h R-0h R-0h R-0h
7 6 5 4 3 2 1 0
GRAB_SECTD GRAB_SECTC GRAB_SECTB GRAB_SECTA
R-0h R-0h R-0h R-0h
Table 2-224. Z1_GRABSECTR Register Field Descriptions

27-26 GRAB_SECTN R 0h Value in this field gets loaded from Z1_GRABSECT[27:26] when a
read is issued to address location of Z1_GRABSECT in OTP.
00 : Invalid. Flash Sector N is inaccessible.

01 : Request to allocate Flash Sector N to Zone1.
11 : Request to make Flash sector N Non-Secure.
Reset type: SYSRSn
25-24 GRAB_SECTM R 0h Value in this field gets loaded from Z1_GRABSECT[25:24] when a
00 : Invalid. Flash Sector M is inaccessible.

01 : Request to allocate Flash Sector M to Zone1.
11 : Request to make Flash sector M Non-Secure.
Reset type: SYSRSn
23-22 GRAB_SECTL R 0h Value in this field gets loaded from Z1_GRABSECT[23:22] when a
00 : Invalid. Flash Sector L is inaccessible.

01 : Request to allocate Flash Sector L to Zone1.
11 : Request to make Flash sector L Non-Secure.
Reset type: SYSRSn

Table 2-224. Z1_GRABSECTR Register Field Descriptions (continued)

21-20 GRAB_SECTK R 0h Value in this field gets loaded from Z1_GRABSECT[21:20] when a
00 : Invalid. Flash Sector K is inaccessible.

01 : Request to allocate Flash Sector K to Zone1.
11 : Request to make Flash sector K Non-Secure.
Reset type: SYSRSn
19-18 GRAB_SECTJ R 0h Value in this field gets loaded from Z1_GRABSECT[19:18] when a
00 : Invalid. Flash Sector J is inaccessible.

01 : Request to allocate Flash Sector J to Zone1.
11 : Request to make Flash sector J Non-Secure.
Reset type: SYSRSn
17-16 GRAB_SECTI R 0h Value in this field gets loaded from Z1_GRABSECT[17:16] when a
00 : Invalid. Flash Sector I is inaccessible.

01 : Request to allocate Flash Sector I to Zone1.
11 : Request to make Flash sector I Non-Secure.
Reset type: SYSRSn
15-14 GRAB_SECTH R 0h Value in this field gets loaded from Z1_GRABSECT[15:14] when a
00 : Invalid. Flash Sector H is inaccessible.

01 : Request to allocate Flash Sector H to Zone1.
11 : Request to make Flash sector H Non-Secure.
Reset type: SYSRSn
13-12 GRAB_SECTG R 0h Value in this field gets loaded from Z1_GRABSECT[13:12] when a
00 : Invalid. Flash Sector G is inaccessible.

01 : Request to allocate Flash Sector G to Zone1.
11 : Request to make Flash sector G Non-Secure.
Reset type: SYSRSn
11-10 GRAB_SECTF R 0h Value in this field gets loaded from Z1_GRABSECT[11:10] when a
00 : Invalid. Flash Sector F is inaccessible.

01 : Request to allocate Flash Sector F to Zone1.
11 : Request to make Flash sector F Non-Secure.
Reset type: SYSRSn
9-8 GRAB_SECTE R 0h Value in this field gets loaded from Z1_GRABSECT[9:8] when a read
is issued to address location of Z1_GRABSECT in OTP.
00 : Invalid. Flash Sector E is inaccessible.

01 : Request to allocate Flash Sector E to Zone1.
11 : Request to make Flash sector E Non-Secure.
Reset type: SYSRSn


7-6 GRAB_SECTD R 0h Value in this field gets loaded from Z1_GRABSECT[7:6] when a read
00 : Invalid. Flash Sector D is inaccessible.

01 : Request to allocate Flash Sector D to Zone1.
11 : Request to make Flash sector D Non-Secure.
Reset type: SYSRSn
5-4 GRAB_SECTC R 0h Value in this field gets loaded from Z1_GRABSECT[5:4] when a read
00 : Invalid. Flash Sector C is inaccessible.

01 : Request to allocate Flash Sector C to Zone1.
11 : Request to make Flash sector C Non-Secure.
Reset type: SYSRSn
3-2 GRAB_SECTB R 0h Value in this field gets loaded from Z1_GRABSECT[3:2] when a read
00 : Invalid. Flash Sector B is inaccessible.

01 : Request to allocate Flash Sector B to Zone1.
11 : Request to make Flash sector B Non-Secure.
Reset type: SYSRSn
1-0 GRAB_SECTA R 0h Value in this field gets loaded from Z1_GRABSECT[1:0] when a read
00 : Invalid. Flash Sector A is inaccessible.

01 : Request to allocate Flash Sector A to Zone1.
11 : Request to make Flash sector A Non-Secure.
Reset type: SYSRSn

2.15.15.11 Z1_GRABRAMR Register (Offset = 1Ch) [reset = 0h]

Z1_GRABRAMR is shown in Figure 2-205 and described in Table 2-225.
Zone 1 Grab RAM Blocks Register
Figure 2-205. Z1_GRABRAMR Register

31 30 29 28 27 26 25 24
RESERVED GRAB_CLA1 RESERVED
R-0h R-0h R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
GRAB_RAM7 GRAB_RAM6 GRAB_RAM5 GRAB_RAM4
R-0h R-0h R-0h R-0h
7 6 5 4 3 2 1 0
R-0h R-0h R-0h R-0h
Table 2-225. Z1_GRABRAMR Register Field Descriptions

29-28 GRAB_CLA1 R 0h Value in this field gets loaded from Z1_GRABRAM[29:28] when a
read is issued to address location of Z1_GRABRAM in OTP.
00 : Invalid. CLA1 is inaccessible.

01 : Request to allocate CLA1 to Zone1.
11 : Request to make CLA1 Non-Secure.
Reset type: SYSRSn
15-14 GRAB_RAM7 R 0h Value in this field gets loaded from Z1_GRABRAM[15:14] when a
00 : Invalid. D1 RAM is inaccessible.

01 : Request to allocate D1 RAM to Zone1.
11 : Request to make D1 RAM Non-Secure.
Reset type: SYSRSn

Reset type: SYSRSn

Table 2-225. Z1_GRABRAMR Register Field Descriptions (continued)

00 : Invalid. LS5 RAM is inaccessible.

01 : Request to allocate LS5 RAM to Zone1.
11 : Request to make LS5 RAM Non-Secure.
Reset type: SYSRSn
9-8 GRAB_RAM4 R 0h Value in this field gets loaded from Z1_GRABRAM[9:8] when a read
is issued to address location of Z1_GRABRAM in OTP.

Reset type: SYSRSn

Reset type: SYSRSn

Reset type: SYSRSn

Reset type: SYSRSn

Reset type: SYSRSn

2.15.15.12 Z1_EXEONLYSECTR Register (Offset = 1Eh) [reset = 0h]

Z1_EXEONLYSECTR is shown in Figure 2-206 and described in Table 2-226.
Zone 1 Flash Execute_Only Sector Register
Figure 2-206. Z1_EXEONLYSECTR Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED RESERVED EXEONLY_SE EXEONLY_SE EXEONLY_SE EXEONLY_SE EXEONLY_SE EXEONLY_SE
CTN CTM CTL CTK CTJ CTI
7 6 5 4 3 2 1 0
EXEONLY_SE EXEONLY_SE EXEONLY_SE EXEONLY_SE EXEONLY_SE EXEONLY_SE EXEONLY_SE EXEONLY_SE
CTH CTG CTF CTE CTD CTC CTB CTA
Table 2-226. Z1_EXEONLYSECTR Register Field Descriptions

13 EXEONLY_SECTN R 0h Value in this field gets loaded from Z1_EXEONLYSECT[13:13] when
a read is issued to Z1_EXEONLYSECT address location in OTP.
0 : Execute-Only protection is enabled for Flash Sector N (only if it's

allocated to Zone1)
1 : Execute-Only protection is disabled for Flash Sector N (only if it's
allocated to Zone1)
Reset type: SYSRSn
12 EXEONLY_SECTM R 0h Value in this field gets loaded from Z1_EXEONLYSECT[12:12] when
0 : Execute-Only protection is enabled for Flash Sector M (only if it's

allocated to Zone1)
1 : Execute-Only protection is disabled for Flash Sector M (only if it's
allocated to Zone1)
Reset type: SYSRSn
11 EXEONLY_SECTL R 0h Value in this field gets loaded from Z1_EXEONLYSECT[11:11] when
0 : Execute-Only protection is enabled for Flash Sector L (only if it's

allocated to Zone1)
1 : Execute-Only protection is disabled for Flash Sector L (only if it's
allocated to Zone1)
Reset type: SYSRSn

Table 2-226. Z1_EXEONLYSECTR Register Field Descriptions (continued)

10 EXEONLY_SECTK R 0h Value in this field gets loaded from Z1_EXEONLYSECT[10:10] when
0 : Execute-Only protection is enabled for Flash Sector K (only if it's

allocated to Zone1)
1 : Execute-Only protection is disabled for Flash Sector K (only if it's
allocated to Zone1)
Reset type: SYSRSn
9 EXEONLY_SECTJ R 0h Value in this field gets loaded from Z1_EXEONLYSECT[9:9] when a
read is issued to Z1_EXEONLYSECT address location in OTP.
0 : Execute-Only protection is enabled for Flash Sector J (only if it's

allocated to Zone1)
1 : Execute-Only protection is disabled for Flash Sector J (only if it's
allocated to Zone1)
Reset type: SYSRSn
8 EXEONLY_SECTI R 0h Value in this field gets loaded from Z1_EXEONLYSECT[8:8] when a
0 : Execute-Only protection is enabled for Flash Sector I (only if it's

allocated to Zone1)
1 : Execute-Only protection is disabled for Flash Sector I (only if it's
allocated to Zone1)
Reset type: SYSRSn
7 EXEONLY_SECTH R 0h Value in this field gets loaded from Z1_EXEONLYSECT[7:7] when a
0 : Execute-Only protection is enabled for Flash Sector H (only if it's

allocated to Zone1)
1 : Execute-Only protection is disabled for Flash Sector H (only if it's
allocated to Zone1)
Reset type: SYSRSn
6 EXEONLY_SECTG R 0h Value in this field gets loaded from Z1_EXEONLYSECT[6:6] when a
0 : Execute-Only protection is enabled for Flash Sector G (only if it's

allocated to Zone1)
1 : Execute-Only protection is disabled for Flash Sector G (only if it's
allocated to Zone1)
Reset type: SYSRSn
5 EXEONLY_SECTF R 0h Value in this field gets loaded from Z1_EXEONLYSECT[5:5] when a
0 : Execute-Only protection is enabled for Flash Sector F (only if it's

allocated to Zone1)
1 : Execute-Only protection is disabled for Flash Sector F (only if it's
allocated to Zone1)
Reset type: SYSRSn
4 EXEONLY_SECTE R 0h Value in this field gets loaded from Z1_EXEONLYSECT[4:4] when a
0 : Execute-Only protection is enabled for Flash Sector E (only if it's

allocated to Zone1)
1 : Execute-Only protection is disabled for Flash Sector E (only if it's
allocated to Zone1)
Reset type: SYSRSn


3 EXEONLY_SECTD R 0h Value in this field gets loaded from Z1_EXEONLYSECT[3:3] when a
0 : Execute-Only protection is enabled for Flash Sector D (only if it's

allocated to Zone1)
1 : Execute-Only protection is disabled for Flash Sector D (only if it's
allocated to Zone1)
Reset type: SYSRSn
2 EXEONLY_SECTC R 0h Value in this field gets loaded from Z1_EXEONLYSECT[2:2] when a
0 : Execute-Only protection is enabled for Flash Sector C (only if it's

allocated to Zone1)
1 : Execute-Only protection is disabled for Flash Sector C (only if it's
allocated to Zone1)
Reset type: SYSRSn
1 EXEONLY_SECTB R 0h Value in this field gets loaded from Z1_EXEONLYSECT[1:1] when a
0 : Execute-Only protection is enabled for Flash Sector B (only if it's

allocated to Zone1)
1 : Execute-Only protection is disabled for Flash Sector B (only if it's
allocated to Zone1)
Reset type: SYSRSn
0 EXEONLY_SECTA R 0h Value in this field gets loaded from Z1_EXEONLYSECT[0:0] when a
0 : Execute-Only protection is enabled for Flash Sector A (only if it's

allocated to Zone1)
1 : Execute-Only protection is disabled for Flash Sector A (only if it's
allocated to Zone1)
Reset type: SYSRSn

2.15.15.13 Z1_EXEONLYRAMR Register (Offset = 20h) [reset = 0h]

Z1_EXEONLYRAMR is shown in Figure 2-207 and described in Table 2-227.
Zone 1 RAM Execute_Only Block Register
Figure 2-207. Z1_EXEONLYRAMR Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
EXEONLY_RA EXEONLY_RA EXEONLY_RA EXEONLY_RA EXEONLY_RA EXEONLY_RA EXEONLY_RA EXEONLY_RA
M7 M6 M5 M4 M3 M2 M1 M0
Table 2-227. Z1_EXEONLYRAMR Register Field Descriptions

7 EXEONLY_RAM7 R 0h Value in this field gets loaded from Z1_EXEONLYRAM[7:7] when a
read is issued to Z1_EXEONLYRAM address location in OTP.
0 : Execute-Only protection is enabled for D1 RAM (only if it's

allocated to Zone1)
1 : Execute-Only protection is disabled for D1 RAM (only if it's
allocated to Zone1)
Reset type: SYSRSn

allocated to Zone1)
allocated to Zone1)
Reset type: SYSRSn
0 : Execute-Only protection is enabled for LS5 RAM (only if it's

allocated to Zone1)
1 : Execute-Only protection is disabled for LS5 RAM (only if it's
allocated to Zone1)
Reset type: SYSRSn

allocated to Zone1)
allocated to Zone1)
Reset type: SYSRSn

Table 2-227. Z1_EXEONLYRAMR Register Field Descriptions (continued)


allocated to Zone1)
allocated to Zone1)
Reset type: SYSRSn

allocated to Zone1)
allocated to Zone1)
Reset type: SYSRSn

allocated to Zone1)
allocated to Zone1)
Reset type: SYSRSn

allocated to Zone1)
allocated to Zone1)
Reset type: SYSRSn

2.15.16 DCSM_Z2_REGS Registers

Table 2-228 lists the memory-mapped registers for the DCSM_Z2_REGS. All register offset addresses not
modified.
Table 2-228. DCSM_Z2_REGS Registers

0h Z2_LINKPOINTER Zone 2 Link Pointer Go
2h Z2_OTPSECLOCK Zone 2 OTP Secure JTAG lock Go
4h Z2_BOOTCTRL Boot Mode Go
6h Z2_LINKPOINTERERR Link Pointer Error Go
19h Z2_CR Zone 2 CSM Control Register Go
1Ah Z2_GRABSECTR Zone 2 Grab Flash Sectors Register Go
1Ch Z2_GRABRAMR Zone 2 Grab RAM Blocks Register Go
1Eh Z2_EXEONLYSECTR Zone 2 Flash Execute_Only Sector Register Go
20h Z2_EXEONLYRAMR Zone 2 RAM Execute_Only Block Register Go
Table 2-229. DCSM_Z2_REGS Access Type Codes

Read Type
R R Read
R=0 R Read
Write Type
W W Write
value
formula.
register array.

2.15.16.1 Z2_LINKPOINTER Register (Offset = 0h) [reset = E0000000h]

Z2_LINKPOINTER is shown in Figure 2-208 and described in Table 2-230.
Zone 2 Link Pointer
Figure 2-208. Z2_LINKPOINTER Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED LINKPOINTER
R-7h R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LINKPOINTER
R-0h
Table 2-230. Z2_LINKPOINTER Register Field Descriptions

28-0 LINKPOINTER R 0h This is the Resolved Link-Pointer value which is generated by
looking at the three physical Link-Pointer values loaded from OTP.
Reset type: SYSRSn

2.15.16.2 Z2_OTPSECLOCK Register (Offset = 2h) [reset = FFFh]

Z2_OTPSECLOCK is shown in Figure 2-209 and described in Table 2-231.
Zone 2 OTP Secure JTAG lock
Figure 2-209. Z2_OTPSECLOCK Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED CRCLOCK PSWDLOCK RESERVED
R-0h R-Fh R-Fh R-0h
Table 2-231. Z2_OTPSECLOCK Register Field Descriptions

11-8 CRCLOCK R Fh Value in this field gets loaded from Z2_CRCLOCK[11:8] when a read
is issued to address location of Z2_CRCLOCK in OTP.
1111 : VCU has ability to calculate CRC on secure memories.

Other Value : VCU doesn't have ability to calculate CRC on secure
memories.
Reset type: SYSRSn
7-4 PSWDLOCK R Fh Value in this field gets loaded from Z2_PSWDLOCK[7:4] when a
read is issued to address location of Z2_PSWDLOCK in OTP.
1111 : CSM password locations in OTP are not protected and can
be read from debugger as well as code running from anywhere.
Other Value : CSM password locations in OTP are protected and
can't be read without unlocking CSM of that zone.
Reset type: SYSRSn

2.15.16.3 Z2_BOOTCTRL Register (Offset = 4h) [reset = 0h]

Z2_BOOTCTRL is shown in Figure 2-210 and described in Table 2-232.
Boot Mode
Figure 2-210. Z2_BOOTCTRL Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BOOTPIN1 BOOTPIN0 BMODE KEY
R-0h R-0h R-0h R-0h
Table 2-232. Z2_BOOTCTRL Register Field Descriptions

....
....
Reset type: SYSRSn
....
....
Reset type: SYSRSn
15-8 BMODE R 0h This field gets loaded with Z2_BOOTCTRL[16:8] when a dummy
Reset type: SYSRSn
7-0 KEY R 0h This field gets loaded with Z2_BOOTCTRL[7:0] when a dummy read
is issued to address location of Z2_BOOTCTRL in OTP.
Reset type: SYSRSn

2.15.16.4 Z2_LINKPOINTERERR Register (Offset = 6h) [reset = FFFFFFFFh]

Z2_LINKPOINTERERR is shown in Figure 2-211 and described in Table 2-233.
Link Pointer Error
Figure 2-211. Z2_LINKPOINTERERR Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z2_LINKPOINTERERR
R-FFFFFFFFh
Table 2-233. Z2_LINKPOINTERERR Register Field Descriptions

31-0 Z2_LINKPOINTERERR R FFFFFFFFh These bits indicate errors during formation of the resolved Link-
Pointer value after the three physical Link-Pointer values loaded of
OTP.
0 : No Error.
Other : Error on bit positions which is set to 1.
Reset type: SYSRSn


Zone 2 CSM Key 0

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z2_CSMKEY0
R-0h

registers.)
Reset type: SYSRSn


Zone 2 CSM Key 1

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z2_CSMKEY1
R-0h

registers.)
Reset type: SYSRSn


Zone 2 CSM Key 2

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z2_CSMKEY2
R-0h

registers.)
Reset type: SYSRSn


Zone 2 CSM Key 3

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z2_CSMKEY3
R-0h

registers.)
Reset type: SYSRSn

2.15.16.9 Z2_CR Register (Offset = 19h) [reset = 8h]

Z2_CR is shown in Figure 2-216 and described in Table 2-238.
Zone 2 CSM Control Register
Figure 2-216. Z2_CR Register

15 14 13 12 11 10 9 8
FORCESEC RESERVED
R=0/W-0h R=0-0h
7 6 5 4 3 2 1 0
RESERVED ARMED UNSECURE ALLONE ALLZERO RESERVED
Table 2-238. Z2_CR Register Field Descriptions

15 FORCESEC R=0/W 0h A write '1' to this fields resets the state of zone. If zone is unlocked,
it'll lock(secure) the zone and also resets all the bits in this register.
Reset type: SYSRSn
6 ARMED R 0h 0 : Dummy read to CSM Password locations in OTP hasn't been
performed.
1 : Dummy read to CSM Password locations in OTP has been
performed.
Reset type: SYSRSn
5 UNSECURE R 0h Indiacates the state of Zone.
0 : Zone is in lock(secure) state.

1 : Zone is in unlock(unsecure) state.
Reset type: SYSRSn
4 ALLONE R 0h Indicates the state of CSM passowrds.
0 : CSM Passwords are not all ones.

1 : CSM Passwords are all ones and zone is in unlock state.
Reset type: SYSRSn
3 ALLZERO R 1h Indicates the state of CSM passowrds.
0 : CSM Passwords are not all zeros.

1 : CSM Passwords are all zero and device is permanently locked.
Reset type: SYSRSn

2.15.16.10 Z2_GRABSECTR Register (Offset = 1Ah) [reset = 0h]

Z2_GRABSECTR is shown in Figure 2-217 and described in Table 2-239.
Zone 2 Grab Flash Sectors Register
Figure 2-217. Z2_GRABSECTR Register

31 30 29 28 27 26 25 24
RESERVED RESERVED GRAB_SECTN GRAB_SECTM
R-0h R-0h R-0h R-0h
23 22 21 20 19 18 17 16
GRAB_SECTL GRAB_SECTK GRAB_SECTJ GRAB_SECTI
R-0h R-0h R-0h R-0h
15 14 13 12 11 10 9 8
GRAB_SECTH GRAB_SECTG GRAB_SECTF GRAB_SECTE
R-0h R-0h R-0h R-0h
7 6 5 4 3 2 1 0
GRAB_SECTD GRAB_SECTC GRAB_SECTB GRAB_SECTA
R-0h R-0h R-0h R-0h
Table 2-239. Z2_GRABSECTR Register Field Descriptions

27-26 GRAB_SECTN R 0h Value in this field gets loaded from Z2_GRABSECT[27:26] when a
00 : Invalid. Flash Sector N is inaccessible.

11 : Request to make Flash sector N Non-Secure.
Reset type: SYSRSn
25-24 GRAB_SECTM R 0h Value in this field gets loaded from Z2_GRABSECT[25:24] when a
00 : Invalid. Flash Sector M is inaccessible.

11 : Request to make Flash sector M Non-Secure.
Reset type: SYSRSn
23-22 GRAB_SECTL R 0h Value in this field gets loaded from Z2_GRABSECT[23:22] when a
00 : Invalid. Flash Sector L is inaccessible.

11 : Request to make Flash sector L Non-Secure.
Reset type: SYSRSn


21-20 GRAB_SECTK R 0h Value in this field gets loaded from Z2_GRABSECT[21:20] when a
00 : Invalid. Flash Sector K is inaccessible.

11 : Request to make Flash sector K Non-Secure.
Reset type: SYSRSn
19-18 GRAB_SECTJ R 0h Value in this field gets loaded from Z2_GRABSECT[19:18] when a
00 : Invalid. Flash Sector J is inaccessible.

11 : Request to make Flash sector J Non-Secure.
Reset type: SYSRSn
17-16 GRAB_SECTI R 0h Value in this field gets loaded from Z2_GRABSECT[17:16] when a
00 : Invalid. Flash Sector I is inaccessible.

11 : Request to make Flash sector I Non-Secure.
Reset type: SYSRSn
15-14 GRAB_SECTH R 0h Value in this field gets loaded from Z2_GRABSECT[15:14] when a
00 : Invalid. Flash Sector H is inaccessible.

11 : Request to make Flash sector H Non-Secure.
Reset type: SYSRSn
13-12 GRAB_SECTG R 0h Value in this field gets loaded from Z2_GRABSECT[13:12] when a
00 : Invalid. Flash Sector G is inaccessible.

11 : Request to make Flash sector G Non-Secure.
Reset type: SYSRSn
11-10 GRAB_SECTF R 0h Value in this field gets loaded from Z2_GRABSECT[11:10] when a
00 : Invalid. Flash Sector F is inaccessible.

11 : Request to make Flash sector F Non-Secure.
Reset type: SYSRSn
9-8 GRAB_SECTE R 0h Value in this field gets loaded from Z2_GRABSECT[9:8] when a read
00 : Invalid. Flash Sector E is inaccessible.

11 : Request to make Flash sector E Non-Secure.
Reset type: SYSRSn


7-6 GRAB_SECTD R 0h Value in this field gets loaded from Z2_GRABSECT[7:6] when a read
00 : Invalid. Flash Sector D is inaccessible.

11 : Request to make Flash sector D Non-Secure.
Reset type: SYSRSn
5-4 GRAB_SECTC R 0h Value in this field gets loaded from Z2_GRABSECT[5:4] when a read
00 : Invalid. Flash Sector C is inaccessible.

11 : Request to make Flash sector C Non-Secure.
Reset type: SYSRSn
3-2 GRAB_SECTB R 0h Value in this field gets loaded from Z2_GRABSECT[3:2] when a read
00 : Invalid. Flash Sector B is inaccessible.

11 : Request to make Flash sector B Non-Secure.
Reset type: SYSRSn
1-0 GRAB_SECTA R 0h Value in this field gets loaded from Z2_GRABSECT[1:0] when a read
00 : Invalid. Flash Sector A is inaccessible.

11 : Request to make Flash sector A Non-Secure.
Reset type: SYSRSn

2.15.16.11 Z2_GRABRAMR Register (Offset = 1Ch) [reset = 0h]

Z2_GRABRAMR is shown in Figure 2-218 and described in Table 2-240.
Zone 2 Grab RAM Blocks Register
Figure 2-218. Z2_GRABRAMR Register

31 30 29 28 27 26 25 24
RESERVED GRAB_CLA1 RESERVED
R-0h R-0h R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
R-0h R-0h R-0h R-0h
7 6 5 4 3 2 1 0
R-0h R-0h R-0h R-0h
Table 2-240. Z2_GRABRAMR Register Field Descriptions

29-28 GRAB_CLA1 R 0h Value in this field gets loaded from Z2_GRABRAM[29:28] when a
00 : Invalid. CLA1 is inaccessible.

11 : Request to make CLA1 Non-Secure.
Reset type: SYSRSn

Reset type: SYSRSn

Reset type: SYSRSn

Table 2-240. Z2_GRABRAMR Register Field Descriptions (continued)


Reset type: SYSRSn

Reset type: SYSRSn

Reset type: SYSRSn

Reset type: SYSRSn

Reset type: SYSRSn

Reset type: SYSRSn

2.15.16.12 Z2_EXEONLYSECTR Register (Offset = 1Eh) [reset = 0h]

Z2_EXEONLYSECTR is shown in Figure 2-219 and described in Table 2-241.
Zone 2 Flash Execute_Only Sector Register
Figure 2-219. Z2_EXEONLYSECTR Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED RESERVED EXEONLY_SE EXEONLY_SE EXEONLY_SE EXEONLY_SE EXEONLY_SE EXEONLY_SE
CTN CTM CTL CTK CTJ CTI
7 6 5 4 3 2 1 0
EXEONLY_SE EXEONLY_SE EXEONLY_SE EXEONLY_SE EXEONLY_SE EXEONLY_SE EXEONLY_SE EXEONLY_SE
CTH CTG CTF CTE CTD CTC CTB CTA
Table 2-241. Z2_EXEONLYSECTR Register Field Descriptions

13 EXEONLY_SECTN R 0h Value in this field gets loaded from Z2_EXEONLYSECT[13:13] when
0 : Execute-Only protection is enabled for Flash Sector N (only if it's

allocated to Zone2)
1 : Execute-Only protection is disabled for Flash Sector N (only if it's
allocated to Zone2)
Reset type: SYSRSn
12 EXEONLY_SECTM R 0h Value in this field gets loaded from Z2_EXEONLYSECT[12:12] when
0 : Execute-Only protection is enabled for Flash Sector M (only if it's

allocated to Zone2)
1 : Execute-Only protection is disabled for Flash Sector M (only if it's
allocated to Zone2)
Reset type: SYSRSn
11 EXEONLY_SECTL R 0h Value in this field gets loaded from Z2_EXEONLYSECT[11:11] when
0 : Execute-Only protection is enabled for Flash Sector L (only if it's

allocated to Zone2)
1 : Execute-Only protection is disabled for Flash Sector L (only if it's
allocated to Zone2)
Reset type: SYSRSn


10 EXEONLY_SECTK R 0h Value in this field gets loaded from Z2_EXEONLYSECT[10:10] when
0 : Execute-Only protection is enabled for Flash Sector K (only if it's

allocated to Zone2)
1 : Execute-Only protection is disabled for Flash Sector K (only if it's
allocated to Zone2)
Reset type: SYSRSn
9 EXEONLY_SECTJ R 0h Value in this field gets loaded from Z2_EXEONLYSECT[9:9] when a
0 : Execute-Only protection is enabled for Flash Sector J (only if it's

allocated to Zone2)
1 : Execute-Only protection is disabled for Flash Sector J (only if it's
allocated to Zone2)
Reset type: SYSRSn
8 EXEONLY_SECTI R 0h Value in this field gets loaded from Z2_EXEONLYSECT[8:8] when a
0 : Execute-Only protection is enabled for Flash Sector I (only if it's

allocated to Zone2)
1 : Execute-Only protection is disabled for Flash Sector I (only if it's
allocated to Zone2)
Reset type: SYSRSn
7 EXEONLY_SECTH R 0h Value in this field gets loaded from Z2_EXEONLYSECT[7:7] when a
0 : Execute-Only protection is enabled for Flash Sector H (only if it's

allocated to Zone2)
1 : Execute-Only protection is disabled for Flash Sector H (only if it's
allocated to Zone2)
Reset type: SYSRSn
6 EXEONLY_SECTG R 0h Value in this field gets loaded from Z2_EXEONLYSECT[6:6] when a
0 : Execute-Only protection is enabled for Flash Sector G (only if it's

allocated to Zone2)
1 : Execute-Only protection is disabled for Flash Sector G (only if it's
allocated to Zone2)
Reset type: SYSRSn
5 EXEONLY_SECTF R 0h Value in this field gets loaded from Z2_EXEONLYSECT[5:5] when a
0 : Execute-Only protection is enabled for Flash Sector F (only if it's

allocated to Zone2)
1 : Execute-Only protection is disabled for Flash Sector F (only if it's
allocated to Zone2)
Reset type: SYSRSn
4 EXEONLY_SECTE R 0h Value in this field gets loaded from Z2_EXEONLYSECT[4:4] when a
0 : Execute-Only protection is enabled for Flash Sector E (only if it's

allocated to Zone2)
1 : Execute-Only protection is disabled for Flash Sector E (only if it's
allocated to Zone2)
Reset type: SYSRSn


3 EXEONLY_SECTD R 0h Value in this field gets loaded from Z2_EXEONLYSECT[3:3] when a
0 : Execute-Only protection is enabled for Flash Sector D (only if it's

allocated to Zone2)
1 : Execute-Only protection is disabled for Flash Sector D (only if it's
allocated to Zone2)
Reset type: SYSRSn
2 EXEONLY_SECTC R 0h Value in this field gets loaded from Z2_EXEONLYSECT[2:2] when a
0 : Execute-Only protection is enabled for Flash Sector C (only if it's

allocated to Zone2)
1 : Execute-Only protection is disabled for Flash Sector C (only if it's
allocated to Zone2)
Reset type: SYSRSn
1 EXEONLY_SECTB R 0h Value in this field gets loaded from Z2_EXEONLYSECT[1:1] when a
0 : Execute-Only protection is enabled for Flash Sector B (only if it's

allocated to Zone2)
1 : Execute-Only protection is disabled for Flash Sector B (only if it's
allocated to Zone2)
Reset type: SYSRSn
0 EXEONLY_SECTA R 0h Value in this field gets loaded from Z2_EXEONLYSECT[0:0] when a
0 : Execute-Only protection is enabled for Flash Sector A (only if it's

allocated to Zone2)
1 : Execute-Only protection is disabled for Flash Sector A (only if it's
allocated to Zone2)
Reset type: SYSRSn

2.15.16.13 Z2_EXEONLYRAMR Register (Offset = 20h) [reset = 0h]

Z2_EXEONLYRAMR is shown in Figure 2-220 and described in Table 2-242.
Zone 2 RAM Execute_Only Block Register
Figure 2-220. Z2_EXEONLYRAMR Register

31 30 29 28 27 26 25 24
RESERVED
R=0-0h
23 22 21 20 19 18 17 16
RESERVED
R=0-0h
15 14 13 12 11 10 9 8
RESERVED
R=0-0h
7 6 5 4 3 2 1 0
EXEONLY_RA EXEONLY_RA EXEONLY_RA EXEONLY_RA EXEONLY_RA EXEONLY_RA EXEONLY_RA EXEONLY_RA
M7 M6 M5 M4 M3 M2 M1 M0
Table 2-242. Z2_EXEONLYRAMR Register Field Descriptions


allocated to Zone2)
allocated to Zone2)
Reset type: SYSRSn

allocated to Zone2)
allocated to Zone2)
Reset type: SYSRSn

allocated to Zone2)
allocated to Zone2)
Reset type: SYSRSn

allocated to Zone2)
allocated to Zone2)
Reset type: SYSRSn

Table 2-242. Z2_EXEONLYRAMR Register Field Descriptions (continued)


allocated to Zone2)
allocated to Zone2)
Reset type: SYSRSn

allocated to Zone2)
allocated to Zone2)
Reset type: SYSRSn

allocated to Zone2)
allocated to Zone2)
Reset type: SYSRSn

allocated to Zone2)
allocated to Zone2)
Reset type: SYSRSn

2.15.17 DCSM_COMMON_REGS Registers

Table 2-243 lists the memory-mapped registers for the DCSM_COMMON_REGS. All register offset
Table 2-243. DCSM_COMMON_REGS Registers

0h FLSEM Flash Wrapper Semaphore Register Go
2h SECTSTAT Sectors Status Register Go
4h RAMSTAT RAM Status Register Go
Table 2-244. DCSM_COMMON_REGS Access Type

Codes
Read Type
R R Read
R=0 R Read
Write Type
W W Write
value
formula.
register array.

2.15.17.1 FLSEM Register (Offset = 0h) [reset = 0h]

FLSEM is shown in Figure 2-221 and described in Table 2-245.
Flash Wrapper Semaphore Register
Figure 2-221. FLSEM Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY RESERVED SEM
R=0/W-0h R-0h R/W-0h
Table 2-245. FLSEM Register Field Descriptions

15-8 KEY R=0/W 0h Writing a value 0xA5 into this field will allow the writing of the SEM
bits, else writes are ignored. Reads will return 0.
Reset type: SYSRSn
1-0 SEM R/W 0h 00 : C28X Flash Wrapper registers can be written by code running
from non-secure zone.
01 : Flash Wrapper registers can be written by code running from
Zone1 security zone only. User must set this value to perform flash
operation on flash sectors of Zone1.
10 : C28X Flash Wrapper registers can be written by code running
from Zone2 security zone only. User must set this value to perform
flash operation on flash sectors of Zone2.
11 : C28X Flash Wrapper registers can be written by code running
from non-secure zone.
Allowed State Transitions in this field.

00 to 11 : Code running from anywhere.
11 to 00 : Not allowed.
00/11 to 01 : Code running from Zone1 only can perform this
transition.
01 to 00/11 : Code running from Zone1 only can perform this
transition.
00/11 to 10 : Code running from Zone2 only can perform this
transition.
10 to 00/11 : Code running from Zone2 can perform this transition
Reset type: SYSRSn

2.15.17.2 SECTSTAT Register (Offset = 2h) [reset = 0h]

SECTSTAT is shown in Figure 2-222 and described in Table 2-246.
Sectors Status Register
Figure 2-222. SECTSTAT Register

31 30 29 28 27 26 25 24
RESERVED RESERVED STATUS_SECTN STATUS_SECTM
R-0h R-0h R-0h R-0h
23 22 21 20 19 18 17 16
STATUS_SECTL STATUS_SECTK STATUS_SECTJ STATUS_SECTI
R-0h R-0h R-0h R-0h
15 14 13 12 11 10 9 8
STATUS_SECTH STATUS_SECTG STATUS_SECTF STATUS_SECTE
R-0h R-0h R-0h R-0h
7 6 5 4 3 2 1 0
STATUS_SECTD STATUS_SECTC STATUS_SECTB STATUS_SECTA
R-0h R-0h R-0h R-0h
Table 2-246. SECTSTAT Register Field Descriptions

27-26 STATUS_SECTN R 0h Reflects the status of flash sector N.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
25-24 STATUS_SECTM R 0h Reflects the status of flash sector M.
access to it.
Reset type: SYSRSn
23-22 STATUS_SECTL R 0h Reflects the status of flash sector L.
access to it.
Reset type: SYSRSn

Table 2-246. SECTSTAT Register Field Descriptions (continued)

21-20 STATUS_SECTK R 0h Reflects the status of flash sector K.
access to it.
Reset type: SYSRSn
19-18 STATUS_SECTJ R 0h Reflects the status of flash sector J.
access to it.
Reset type: SYSRSn
17-16 STATUS_SECTI R 0h Reflects the status of flash sector I.
access to it.
Reset type: SYSRSn
15-14 STATUS_SECTH R 0h Reflects the status of flash sector H.
access to it.
Reset type: SYSRSn
13-12 STATUS_SECTG R 0h Reflects the status of flash sector G.
access to it.
Reset type: SYSRSn
11-10 STATUS_SECTF R 0h Reflects the status of flash sector F.
access to it.
Reset type: SYSRSn
9-8 STATUS_SECTE R 0h Reflects the status of flash sector E.
access to it.
Reset type: SYSRSn

Table 2-246. SECTSTAT Register Field Descriptions (continued)

7-6 STATUS_SECTD R 0h Reflects the status of flash sector D.
access to it.
Reset type: SYSRSn
5-4 STATUS_SECTC R 0h Reflects the status of flash sector C.
access to it.
Reset type: SYSRSn
3-2 STATUS_SECTB R 0h Reflects the status of flash sector B.
access to it.
Reset type: SYSRSn
1-0 STATUS_SECTA R 0h Reflects the status of flash sector A.
access to it.
Reset type: SYSRSn

2.15.17.3 RAMSTAT Register (Offset = 4h) [reset = 0h]

RAMSTAT is shown in Figure 2-223 and described in Table 2-247.
RAM Status Register
Figure 2-223. RAMSTAT Register

31 30 29 28 27 26 25 24
RESERVED STATUS_CLA1 RESERVED
R-0h R-0h R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
STATUS_RAM7 STATUS_RAM6 STATUS_RAM5 STATUS_RAM4
R-0h R-0h R-0h R-0h
7 6 5 4 3 2 1 0
STATUS_RAM3 STATUS_RAM2 STATUS_RAM1 STATUS_RAM0
R-0h R-0h R-0h R-0h
Table 2-247. RAMSTAT Register Field Descriptions

29-28 STATUS_CLA1 R 0h Reflects the status of CLA1.
00 : CLA is in-accessible
01 : CLA belongs to Zone1.
10 : CLA belongs to Zone2.
11: CLA is un-secure and code running in both zone have full access
to it.
Reset type: SYSRSn
15-14 STATUS_RAM7 R 0h Reflects the status of D1 RAM.
00 : RAM is in-accessible
01 : RAM belongs to Zone1.
11: RAM is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
13-12 STATUS_RAM6 R 0h Reflects the status of D0 RAM.
access to it.
Reset type: SYSRSn

Table 2-247. RAMSTAT Register Field Descriptions (continued)

11-10 STATUS_RAM5 R 0h Reflects the status of LS5 RAM.
access to it.
Reset type: SYSRSn
access to it.
Reset type: SYSRSn
access to it.
Reset type: SYSRSn
access to it.
Reset type: SYSRSn
access to it.
Reset type: SYSRSn
access to it.
Reset type: SYSRSn

2.15.18 MEM_CFG_REGS Registers

Table 2-248 lists the memory-mapped registers for the MEM_CFG_REGS. All register offset addresses
not listed in Table 2-248 should be considered as reserved locations and the register contents should not
be modified.
Table 2-248. MEM_CFG_REGS Registers

0h DxLOCK Dedicated RAM Config Lock Register EALLOW Go
2h DxCOMMIT Dedicated RAM Config Lock Commit Register EALLOW Go
8h DxACCPROT0 Dedicated RAM Config Register EALLOW Go
10h DxTEST Dedicated RAM TEST Register EALLOW Go
12h DxINIT Dedicated RAM Init Register EALLOW Go
14h DxINITDONE Dedicated RAM InitDone Status Register Go
20h LSxLOCK Local Shared RAM Config Lock Register EALLOW Go
22h LSxCOMMIT Local Shared RAM Config Lock Commit Register EALLOW Go
24h LSxMSEL Local Shared RAM Master Sel Register EALLOW Go
26h LSxCLAPGM Local Shared RAM Prog/Exe control Register EALLOW Go
28h LSxACCPROT0 Local Shared RAM Config Register 0 EALLOW Go
2Ah LSxACCPROT1 Local Shared RAM Config Register 1 EALLOW Go
30h LSxTEST Local Shared RAM TEST Register EALLOW Go
32h LSxINIT Local Shared RAM Init Register EALLOW Go
34h LSxINITDONE Local Shared RAM InitDone Status Register Go
40h GSxLOCK Global Shared RAM Config Lock Register EALLOW Go
42h GSxCOMMIT Global Shared RAM Config Lock Commit EALLOW Go
Register
44h GSxMSEL Global Shared RAM Master Sel Register EALLOW Go
48h GSxACCPROT0 Global Shared RAM Config Register 0 EALLOW Go
4Ah GSxACCPROT1 Global Shared RAM Config Register 1 EALLOW Go
4Ch GSxACCPROT2 Global Shared RAM Config Register 2 EALLOW Go
4Eh GSxACCPROT3 Global Shared RAM Config Register 3 EALLOW Go
50h GSxTEST Global Shared RAM TEST Register EALLOW Go
52h GSxINIT Global Shared RAM Init Register EALLOW Go
54h GSxINITDONE Global Shared RAM InitDone Status Register Go
70h MSGxTEST Message RAM TEST Register EALLOW Go
72h MSGxINIT Message RAM Init Register EALLOW Go
74h MSGxINITDONE Message RAM InitDone Status Register Go
Table 2-249. MEM_CFG_REGS Access Type Codes

Read Type
R R Read
R=0 R Read
Write Type
W W Write
W=1 W Write
W Write

Table 2-249. MEM_CFG_REGS Access Type

Codes (continued)
value
formula.
register array.

2.15.18.1 DxLOCK Register (Offset = 0h) [reset = 0h]

DxLOCK is shown in Figure 2-224 and described in Table 2-250.
Dedicated RAM Config Lock Register
Figure 2-224. DxLOCK Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED LOCK_D1 LOCK_D0 RESERVED
R-0h R/W-0h R/W-0h R-0h
Table 2-250. DxLOCK Register Field Descriptions

3 LOCK_D1 R/W 0h Locks the write to access protection and master select fields for D1
RAM:
0: Write to ACCPROT and Mselect fields are allowed.
1: Write to ACCPROT and Mselect fields are blocked.
Reset type: SYSRSn
2 LOCK_D0 R/W 0h Locks the write to access protection and master select fields for D0
RAM:
Reset type: SYSRSn

2.15.18.2 DxCOMMIT Register (Offset = 2h) [reset = 0h]

DxCOMMIT is shown in Figure 2-225 and described in Table 2-251.
Dedicated RAM Config Lock Commit Register
Figure 2-225. DxCOMMIT Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED COMMIT_D1 COMMIT_D0 RESERVED
R-0h R/WSOnce-0h R/WSOnce-0h R-0h
Table 2-251. DxCOMMIT Register Field Descriptions

3 COMMIT_D1 R/WSOnce 0h Permanently Locks the write to access protection and master select
fields for D1 RAM:
0: Write to ACCPROT and Mselect fields are allowed based on value
of lock field in DxLOCK register.
1: Write to ACCPROT and Mselect fields are permanently blocked.
Reset type: SYSRSn
2 COMMIT_D0 R/WSOnce 0h Permanently Locks the write to access protection and master select
fields for D0 RAM:
of lock field in DxLOCK register.
Reset type: SYSRSn

2.15.18.3 DxACCPROT0 Register (Offset = 8h) [reset = 0h]

DxACCPROT0 is shown in Figure 2-226 and described in Table 2-252.
Dedicated RAM Config Register
Figure 2-226. DxACCPROT0 Register

31 30 29 28 27 26 25 24
RESERVED CPUWRPROT_ FETCHPROT_
D1 D1
R-0h R/W-0h R/W-0h
23 22 21 20 19 18 17 16
D0 D0
R-0h R/W-0h R/W-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED
R-0h
Table 2-252. DxACCPROT0 Register Field Descriptions

25 CPUWRPROT_D1 R/W 0h CPU WR Protection For D1 RAM:
0: CPU Writes are allowed.
1: CPU Writes are blocked.
Reset type: SYSRSn
24 FETCHPROT_D1 R/W 0h Fetch Protection For D1 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.
Reset type: SYSRSn
17 CPUWRPROT_D0 R/W 0h CPU WR Protection For D0 RAM:
1: CPU Writes are block.
Reset type: SYSRSn
16 FETCHPROT_D0 R/W 0h Fetch Protection For D0 RAM:
Reset type: SYSRSn

2.15.18.4 DxTEST Register (Offset = 10h) [reset = 0h]

DxTEST is shown in Figure 2-227 and described in Table 2-253.
Dedicated RAM TEST Register
Figure 2-227. DxTEST Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
TEST_D1 TEST_D0 TEST_M1 TEST_M0
Table 2-253. DxTEST Register Field Descriptions

7-6 TEST_D1 R/W 0h Selects the defferent modes for D1 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to ECC bits.
10: Writes are allowed to ECC bits only. No write to data bits.
Reset type: SYSRSn
5-4 TEST_D0 R/W 0h Selects the defferent modes for D0 RAM:
Reset type: SYSRSn
3-2 TEST_M1 R/W 0h Selects the defferent modes for M1 RAM:
Reset type: SYSRSn
1-0 TEST_M0 R/W 0h Selects the defferent modes for M0 RAM:
Reset type: SYSRSn

2.15.18.5 DxINIT Register (Offset = 12h) [reset = 0h]

DxINIT is shown in Figure 2-228 and described in Table 2-254.
Dedicated RAM Init Register
Figure 2-228. DxINIT Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED INIT_D1 INIT_D0 INIT_M1 INIT_M0
R-0h R=0/W=1-0h R=0/W=1-0h R=0/W=1-0h R=0/W=1-0h
Table 2-254. DxINIT Register Field Descriptions

3 INIT_D1 R=0/W=1 0h RAM Initialization control for D1 RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn
2 INIT_D0 R=0/W=1 0h RAM Initialization control for D0 RAM:
0: None.
Reset type: SYSRSn
1 INIT_M1 R=0/W=1 0h RAM Initialization control for M1 RAM:
0: None.
Reset type: SYSRSn
0 INIT_M0 R=0/W=1 0h RAM Initialization control for M0 RAM:
0: None.
Reset type: SYSRSn

2.15.18.6 DxINITDONE Register (Offset = 14h) [reset = 0h]

DxINITDONE is shown in Figure 2-229 and described in Table 2-255.
Dedicated RAM InitDone Status Register
Figure 2-229. DxINITDONE Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED INITDONE_D1 INITDONE_D0 INITDONE_M1 INITDONE_M0
R-0h R-0h R-0h R-0h R-0h
Table 2-255. DxINITDONE Register Field Descriptions

3 INITDONE_D1 R 0h RAM Initialization status for D1 RAM:
0: RAM Initialization has completed.
Reset type: SYSRSn
2 INITDONE_D0 R 0h RAM Initialization status for D0 RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn
1 INITDONE_M1 R 0h RAM Initialization status for M1 RAM:
Reset type: SYSRSn
0 INITDONE_M0 R 0h RAM Initialization status for M0 RAM:
Reset type: SYSRSn

2.15.18.7 LSxLOCK Register (Offset = 20h) [reset = 0h]

LSxLOCK is shown in Figure 2-230 and described in Table 2-256.
Local Shared RAM Config Lock Register
Figure 2-230. LSxLOCK Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED LOCK_LS5 LOCK_LS4 LOCK_LS3 LOCK_LS2 LOCK_LS1 LOCK_LS0
R-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
Table 2-256. LSxLOCK Register Field Descriptions

5 LOCK_LS5 R/W 0h Locks the write to access protection and master select fields for LS5
RAM:
Reset type: SYSRSn
RAM:
Reset type: SYSRSn
RAM:
Reset type: SYSRSn
RAM:
Reset type: SYSRSn
RAM:
Reset type: SYSRSn

Table 2-256. LSxLOCK Register Field Descriptions (continued)

RAM:
Reset type: SYSRSn

2.15.18.8 LSxCOMMIT Register (Offset = 22h) [reset = 0h]

LSxCOMMIT is shown in Figure 2-231 and described in Table 2-257.
Local Shared RAM Config Lock Commit Register
Figure 2-231. LSxCOMMIT Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED COMMIT_LS5 COMMIT_LS4 COMMIT_LS3 COMMIT_LS2 COMMIT_LS1 COMMIT_LS0
R-0h R/WSOnce-0h R/WSOnce-0h R/WSOnce-0h R/WSOnce-0h R/WSOnce-0h R/WSOnce-0h
Table 2-257. LSxCOMMIT Register Field Descriptions

5 COMMIT_LS5 R/WSOnce 0h Permanently Locks the write to access protection and master select
fields for LS5 RAM:
of lock field in LSxLOCK register.
Reset type: SYSRSn
fields for LS4 RAM:
Reset type: SYSRSn
fields for LS3 RAM:
Reset type: SYSRSn
fields for LS2 RAM:
Reset type: SYSRSn

Table 2-257. LSxCOMMIT Register Field Descriptions (continued)

fields for LS1 RAM:
Reset type: SYSRSn
fields for LS0 RAM:
Reset type: SYSRSn

2.15.18.9 LSxMSEL Register (Offset = 24h) [reset = 0h]

LSxMSEL is shown in Figure 2-232 and described in Table 2-258.
Local Shared RAM Master Sel Register
Figure 2-232. LSxMSEL Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED MSEL_LS5 MSEL_LS4
R-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
MSEL_LS3 MSEL_LS2 MSEL_LS1 MSEL_LS0
Table 2-258. LSxMSEL Register Field Descriptions

11-10 MSEL_LS5 R/W 0h Master Select for LS5 RAM:
00: Memory is dedicated to CPU.
01: Memory is shared between CPU and CLA1.
10: Reserved.
11: Reserved.
Reset type: SYSRSn
10: Reserved.
11: Reserved.
Reset type: SYSRSn
10: Reserved.
11: Reserved.
Reset type: SYSRSn
10: Reserved.
11: Reserved.
Reset type: SYSRSn

Table 2-258. LSxMSEL Register Field Descriptions (continued)

10: Reserved.
11: Reserved.
Reset type: SYSRSn
10: Reserved.
11: Reserved.
Reset type: SYSRSn

2.15.18.10 LSxCLAPGM Register (Offset = 26h) [reset = 0h]

LSxCLAPGM is shown in Figure 2-233 and described in Table 2-259.
Local Shared RAM Prog/Exe control Register
Figure 2-233. LSxCLAPGM Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED CLAPGM_LS5 CLAPGM_LS4 CLAPGM_LS3 CLAPGM_LS2 CLAPGM_LS1 CLAPGM_LS0
R-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
Table 2-259. LSxCLAPGM Register Field Descriptions

5 CLAPGM_LS5 R/W 0h Selects LS5 RAM as program vs data memory for CLA:
0: CLA Data memory.
1: CLA Program memory.
Reset type: SYSRSn
0: CLA Data memory.
Reset type: SYSRSn
0: CLA Data memory.
Reset type: SYSRSn
0: CLA Data memory.
Reset type: SYSRSn
0: CLA Data memory.
Reset type: SYSRSn
0: CLA Data memory.
Reset type: SYSRSn

2.15.18.11 LSxACCPROT0 Register (Offset = 28h) [reset = 0h]

LSxACCPROT0 is shown in Figure 2-234 and described in Table 2-260.
Local Shared RAM Config Register 0
Figure 2-234. LSxACCPROT0 Register

31 30 29 28 27 26 25 24
LS3 LS3
R-0h R/W-0h R/W-0h
23 22 21 20 19 18 17 16
LS2 LS2
R-0h R/W-0h R/W-0h
15 14 13 12 11 10 9 8
LS1 LS1
R-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
LS0 LS0
R-0h R/W-0h R/W-0h
Table 2-260. LSxACCPROT0 Register Field Descriptions

25 CPUWRPROT_LS3 R/W 0h CPU WR Protection For LS3 RAM:
Reset type: SYSRSn
24 FETCHPROT_LS3 R/W 0h Fetch Protection For LS3 RAM:
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn

Table 2-260. LSxACCPROT0 Register Field Descriptions (continued)

Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn

2.15.18.12 LSxACCPROT1 Register (Offset = 2Ah) [reset = 0h]

LSxACCPROT1 is shown in Figure 2-235 and described in Table 2-261.
Local Shared RAM Config Register 1
Figure 2-235. LSxACCPROT1 Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
LS5 LS5
R-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
LS4 LS4
R-0h R/W-0h R/W-0h
Table 2-261. LSxACCPROT1 Register Field Descriptions

Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn

2.15.18.13 LSxTEST Register (Offset = 30h) [reset = 0h]

LSxTEST is shown in Figure 2-236 and described in Table 2-262.
Local Shared RAM TEST Register
Figure 2-236. LSxTEST Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED TEST_LS5 TEST_LS4
R-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
TEST_LS3 TEST_LS2 TEST_LS1 TEST_LS0
Table 2-262. LSxTEST Register Field Descriptions

11-10 TEST_LS5 R/W 0h Selects the defferent modes for LS5 RAM:
01: Writes are allowed to data bits only. No write to parity bits.
10: Writes are allowed to parity bits only. No write to data bits.
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn

Table 2-262. LSxTEST Register Field Descriptions (continued)

Reset type: SYSRSn
Reset type: SYSRSn

2.15.18.14 LSxINIT Register (Offset = 32h) [reset = 0h]

LSxINIT is shown in Figure 2-237 and described in Table 2-263.
Local Shared RAM Init Register
Figure 2-237. LSxINIT Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED INIT_LS5 INIT_LS4 INIT_LS3 INIT_LS2 INIT_LS1 INIT_LS0
R-0h R=0/W=1-0h R=0/W=1-0h R=0/W=1-0h R=0/W=1-0h R=0/W=1-0h R=0/W=1-0h
Table 2-263. LSxINIT Register Field Descriptions

5 INIT_LS5 R=0/W=1 0h RAM Initialization control for LS5 RAM:
0: None.
Reset type: SYSRSn
0: None.
Reset type: SYSRSn
0: None.
Reset type: SYSRSn
0: None.
Reset type: SYSRSn
0: None.
Reset type: SYSRSn
0: None.
Reset type: SYSRSn

2.15.18.15 LSxINITDONE Register (Offset = 34h) [reset = 0h]

LSxINITDONE is shown in Figure 2-238 and described in Table 2-264.
Local Shared RAM InitDone Status Register
Figure 2-238. LSxINITDONE Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED INITDONE_LS5 INITDONE_LS4 INITDONE_LS3 INITDONE_LS2 INITDONE_LS1 INITDONE_LS0
R-0h R-0h R-0h R-0h R-0h R-0h R-0h
Table 2-264. LSxINITDONE Register Field Descriptions

5 INITDONE_LS5 R 0h RAM Initialization status for LS5 RAM:
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn

2.15.18.16 GSxLOCK Register (Offset = 40h) [reset = 0h]

GSxLOCK is shown in Figure 2-239 and described in Table 2-265.
Global Shared RAM Config Lock Register
Figure 2-239. GSxLOCK Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
LOCK_GS15 LOCK_GS14 LOCK_GS13 LOCK_GS12 LOCK_GS11 LOCK_GS10 LOCK_GS9 LOCK_GS8
7 6 5 4 3 2 1 0
LOCK_GS7 LOCK_GS6 LOCK_GS5 LOCK_GS4 LOCK_GS3 LOCK_GS2 LOCK_GS1 LOCK_GS0
Table 2-265. GSxLOCK Register Field Descriptions

15 LOCK_GS15 R/W 0h Locks the write to access protection and master select fields for
GS15 RAM:
Reset type: SYSRSn
GS14 RAM:
Reset type: SYSRSn
GS13 RAM:
Reset type: SYSRSn
GS12 RAM:
Reset type: SYSRSn
GS11 RAM:
Reset type: SYSRSn

Table 2-265. GSxLOCK Register Field Descriptions (continued)

GS10 RAM:
Reset type: SYSRSn
9 LOCK_GS9 R/W 0h Locks the write to access protection and master select fields for GS9
RAM:
Reset type: SYSRSn
RAM:
Reset type: SYSRSn
RAM:
Reset type: SYSRSn
RAM:
Reset type: SYSRSn
RAM:
Reset type: SYSRSn
RAM:
Reset type: SYSRSn
RAM:
Reset type: SYSRSn
RAM:
Reset type: SYSRSn
RAM:
Reset type: SYSRSn

Table 2-265. GSxLOCK Register Field Descriptions (continued)

RAM:
Reset type: SYSRSn

2.15.18.17 GSxCOMMIT Register (Offset = 42h) [reset = 0h]

GSxCOMMIT is shown in Figure 2-240 and described in Table 2-266.
Global Shared RAM Config Lock Commit Register
Figure 2-240. GSxCOMMIT Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
COMMIT_GS1 COMMIT_GS1 COMMIT_GS1 COMMIT_GS1 COMMIT_GS1 COMMIT_GS1 COMMIT_GS9 COMMIT_GS8
5 4 3 2 1 0
7 6 5 4 3 2 1 0
COMMIT_GS7 COMMIT_GS6 COMMIT_GS5 COMMIT_GS4 COMMIT_GS3 COMMIT_GS2 COMMIT_GS1 COMMIT_GS0
Table 2-266. GSxCOMMIT Register Field Descriptions

15 COMMIT_GS15 R/WSOnce 0h Permanently Locks the write to access protection and master select
fields for GS15 RAM:
of lock field in GSxLOCK register.
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn

Table 2-266. GSxCOMMIT Register Field Descriptions (continued)

Reset type: SYSRSn
fields for GS9 RAM:
Reset type: SYSRSn
fields for GS2 RAM:
Reset type: SYSRSn
fields for GS7 RAM:
Reset type: SYSRSn
fields for GS6 RAM:
Reset type: SYSRSn
fields for GS5 RAM:
Reset type: SYSRSn
fields for GS4 RAM:
Reset type: SYSRSn
fields for GS3 RAM:
Reset type: SYSRSn
fields for GS2 RAM:
Reset type: SYSRSn

Table 2-266. GSxCOMMIT Register Field Descriptions (continued)

fields for GS1 RAM:
Reset type: SYSRSn
fields for GS0 RAM:
Reset type: SYSRSn

2.15.18.18 GSxMSEL Register (Offset = 44h) [reset = 0h]

GSxMSEL is shown in Figure 2-241 and described in Table 2-267.
Global Shared RAM Master Sel Register
Figure 2-241. GSxMSEL Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
MSEL_GS15 MSEL_GS14 MSEL_GS13 MSEL_GS12 MSEL_GS11 MSEL_GS10 MSEL_GS9 MSEL_GS8
7 6 5 4 3 2 1 0
MSEL_GS7 MSEL_GS6 MSEL_GS5 MSEL_GS4 MSEL_GS3 MSEL_GS2 MSEL_GS1 MSEL_GS0
Table 2-267. GSxMSEL Register Field Descriptions

15 MSEL_GS15 R/W 0h Master Select for GS15 RAM:
0: CPU1 is master for this memory.

Table 2-267. GSxMSEL Register Field Descriptions (continued)


2.15.18.19 GSxACCPROT0 Register (Offset = 48h) [reset = 0h]

GSxACCPROT0 is shown in Figure 2-242 and described in Table 2-268.
Global Shared RAM Config Register 0
Figure 2-242. GSxACCPROT0 Register

31 30 29 28 27 26 25 24
RESERVED DMAWRPROT CPUWRPROT_ FETCHPROT_
_GS3 GS3 GS3
23 22 21 20 19 18 17 16
_GS2 GS2 GS2
15 14 13 12 11 10 9 8
_GS1 GS1 GS1
7 6 5 4 3 2 1 0
_GS0 GS0 GS0
Table 2-268. GSxACCPROT0 Register Field Descriptions

26 DMAWRPROT_GS3 R/W 0h DMA WR Protection For GS3 RAM:
0: DMA Writes are allowed.
1: DMA Writes are blocked.
Reset type: SYSRSn
25 CPUWRPROT_GS3 R/W 0h CPU WR Protection For GS3 RAM:
Reset type: SYSRSn
24 FETCHPROT_GS3 R/W 0h Fetch Protection For GS3 RAM:
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn

Table 2-268. GSxACCPROT0 Register Field Descriptions (continued)

Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn

2.15.18.20 GSxACCPROT1 Register (Offset = 4Ah) [reset = 0h]


31 30 29 28 27 26 25 24
_GS7 GS7 GS7
23 22 21 20 19 18 17 16
_GS6 GS6 GS6
15 14 13 12 11 10 9 8
_GS5 GS5 GS5
7 6 5 4 3 2 1 0
_GS4 GS4 GS4

Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn


Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn

2.15.18.21 GSxACCPROT2 Register (Offset = 4Ch) [reset = 0h]


31 30 29 28 27 26 25 24
_GS11 GS11 GS11
23 22 21 20 19 18 17 16
_GS10 GS10 GS10
15 14 13 12 11 10 9 8
_GS9 GS9 GS9
7 6 5 4 3 2 1 0
_GS8 GS8 GS8

Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn


Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn

2.15.18.22 GSxACCPROT3 Register (Offset = 4Eh) [reset = 0h]


31 30 29 28 27 26 25 24
_GS15 GS15 GS15
23 22 21 20 19 18 17 16
_GS14 GS14 GS14
15 14 13 12 11 10 9 8
_GS13 GS13 GS13
7 6 5 4 3 2 1 0
_GS12 GS12 GS12

Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn


Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn

2.15.18.23 GSxTEST Register (Offset = 50h) [reset = 0h]

GSxTEST is shown in Figure 2-246 and described in Table 2-272.
Global Shared RAM TEST Register
Figure 2-246. GSxTEST Register

31 30 29 28 27 26 25 24
TEST_GS15 TEST_GS14 TEST_GS13 TEST_GS12
23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8
7 6 5 4 3 2 1 0
Table 2-272. GSxTEST Register Field Descriptions

31-30 TEST_GS15 R/W 0h Selects the defferent modes for GS15 RAM:
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn

Table 2-272. GSxTEST Register Field Descriptions (continued)

Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn

Table 2-272. GSxTEST Register Field Descriptions (continued)

Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn

2.15.18.24 GSxINIT Register (Offset = 52h) [reset = 0h]

GSxINIT is shown in Figure 2-247 and described in Table 2-273.
Global Shared RAM Init Register
Figure 2-247. GSxINIT Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
INIT_GS15 INIT_GS14 INIT_GS13 INIT_GS12 INIT_GS11 INIT_GS10 INIT_GS9 INIT_GS8
R=0/W=1-0h R=0/W=1-0h R=0/W=1-0h R=0/W=1-0h R=0/W=1-0h R=0/W=1-0h R=0/W=1-0h R=0/W=1-0h
7 6 5 4 3 2 1 0
INIT_GS7 INIT_GS6 INIT_GS5 INIT_GS4 INIT_GS3 INIT_GS2 INIT_GS1 INIT_GS0
R=0/W=1-0h R=0/W=1-0h R=0/W=1-0h R=0/W=1-0h R=0/W=1-0h R=0/W=1-0h R=0/W=1-0h R=0/W=1-0h
Table 2-273. GSxINIT Register Field Descriptions

15 INIT_GS15 R=0/W=1 0h RAM Initialization control for GS15 RAM:
0: None.
Reset type: SYSRSn
0: None.
Reset type: SYSRSn
0: None.
Reset type: SYSRSn
0: None.
Reset type: SYSRSn
0: None.
Reset type: SYSRSn
0: None.
Reset type: SYSRSn

Table 2-273. GSxINIT Register Field Descriptions (continued)

0: None.
Reset type: SYSRSn
0: None.
Reset type: SYSRSn
0: None.
Reset type: SYSRSn
0: None.
Reset type: SYSRSn
0: None.
Reset type: SYSRSn
0: None.
Reset type: SYSRSn
0: None.
Reset type: SYSRSn
0: None.
Reset type: SYSRSn
0: None.
Reset type: SYSRSn
0: None.
Reset type: SYSRSn

2.15.18.25 GSxINITDONE Register (Offset = 54h) [reset = 0h]

GSxINITDONE is shown in Figure 2-248 and described in Table 2-274.
Global Shared RAM InitDone Status Register
Figure 2-248. GSxINITDONE Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
INITDONE_GS INITDONE_GS INITDONE_GS INITDONE_GS INITDONE_GS INITDONE_GS INITDONE_GS INITDONE_GS
15 14 13 12 11 10 9 8
7 6 5 4 3 2 1 0
INITDONE_GS INITDONE_GS INITDONE_GS INITDONE_GS INITDONE_GS INITDONE_GS INITDONE_GS INITDONE_GS
7 6 5 4 3 2 1 0
Table 2-274. GSxINITDONE Register Field Descriptions

15 INITDONE_GS15 R 0h RAM Initialization status for GS15 RAM:
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn

Table 2-274. GSxINITDONE Register Field Descriptions (continued)

Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn
Reset type: SYSRSn

2.15.18.26 MSGxTEST Register (Offset = 70h) [reset = 0h]

MSGxTEST is shown in Figure 2-249 and described in Table 2-275.
Message RAM TEST Register
Figure 2-249. MSGxTEST Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED RESERVED
R-0h R-0h
7 6 5 4 3 2 1 0
RESERVED TEST_CLA1TOCPU TEST_CPUTOCLA1 TEST_CPUTOCPU
Table 2-275. MSGxTEST Register Field Descriptions

5-4 TEST_CLA1TOCPU R/W 0h Selects the defferent modes for CLA1TOCPU MSG RAM:
Reset type: SYSRSn
3-2 TEST_CPUTOCLA1 R/W 0h Selects the defferent modes for CPUTOCLA1 MSG RAM:
Reset type: SYSRSn
1-0 TEST_CPUTOCPU R/W 0h Selects the defferent modes for CPUTOCPU MSG RAM:
Reset type: SYSRSn

2.15.18.27 MSGxINIT Register (Offset = 72h) [reset = 0h]

MSGxINIT is shown in Figure 2-250 and described in Table 2-276.
Message RAM Init Register
Figure 2-250. MSGxINIT Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED INIT_CLA1TOC INIT_CPUTOC INIT_CPUTOC
PU LA1 PU
R-0h R-0h R-0h R=0/W=1-0h R=0/W=1-0h R=0/W=1-0h
Table 2-276. MSGxINIT Register Field Descriptions

2 INIT_CLA1TOCPU R=0/W=1 0h RAM Initialization control for CLA1TOCPU MSG RAM:
0: None.
Reset type: SYSRSn
1 INIT_CPUTOCLA1 R=0/W=1 0h RAM Initialization control for CPUTOCLA1 MSG RAM:
0: None.
Reset type: SYSRSn
0 INIT_CPUTOCPU R=0/W=1 0h RAM Initialization control for CPUTOCPU MSG RAM:
0: None.
Reset type: SYSRSn

2.15.18.28 MSGxINITDONE Register (Offset = 74h) [reset = 0h]

MSGxINITDONE is shown in Figure 2-251 and described in Table 2-277.
Message RAM InitDone Status Register
Figure 2-251. MSGxINITDONE Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED INITDONE_CL INITDONE_CP INITDONE_CP
A1TOCPU UTOCLA1 UTOCPU
Table 2-277. MSGxINITDONE Register Field Descriptions

2 INITDONE_CLA1TOCPU R 0h RAM Initialization status for CLA1TOCPU MSG RAM:
Reset type: SYSRSn
1 INITDONE_CPUTOCLA1 R 0h RAM Initialization status for CPUTOCLA1 MSG RAM:
Reset type: SYSRSn
0 INITDONE_CPUTOCPU R 0h RAM Initialization status for CPUTOCPU MSG RAM:
Reset type: SYSRSn

2.15.19 ACCESS_PROTECTION_REGS Registers

Table 2-278 lists the memory-mapped registers for the ACCESS_PROTECTION_REGS. All register offset
Table 2-278. ACCESS_PROTECTION_REGS Registers

0h NMAVFLG Non-Master Access Violation Flag Register Go
2h NMAVSET Non-Master Access Violation Flag Set Register EALLOW Go
4h NMAVCLR Non-Master Access Violation Flag Clear Register EALLOW Go
6h NMAVINTEN Non-Master Access Violation Interrupt Enable EALLOW Go
Register
8h NMCPURDAVADDR Non-Master CPU Read Access Violation Go
Address
Ah NMCPUWRAVADDR Non-Master CPU Write Access Violation Address Go
Ch NMCPUFAVADDR Non-Master CPU Fetch Access Violation Go
Address
Eh NMDMAWRAVADDR Non-Master DMA Write Access Violation Go
Address
10h NMCLA1RDAVADDR Non-Master CLA1 Read Access Violation Go
Address
12h NMCLA1WRAVADDR Non-Master CLA1 Write Access Violation Go
Address
14h NMCLA1FAVADDR Non-Master CLA1 Fetch Access Violation Go
Address
20h MAVFLG Master Access Violation Flag Register Go
22h MAVSET Master Access Violation Flag Set Register EALLOW Go
24h MAVCLR Master Access Violation Flag Clear Register EALLOW Go
26h MAVINTEN Master Access Violation Interrupt Enable EALLOW Go
Register
28h MCPUFAVADDR Master CPU Fetch Access Violation Address Go
2Ah MCPUWRAVADDR Master CPU Write Access Violation Address Go
2Ch MDMAWRAVADDR Master DMA Write Access Violation Address Go
Table 2-279. ACCESS_PROTECTION_REGS Access

Type Codes
Read Type
R R Read
R=0 R Read
Write Type
W W Write
W=1 W Write
value

Table 2-279. ACCESS_PROTECTION_REGS Access

Type Codes (continued)
formula.
register array.

2.15.19.1 NMAVFLG Register (Offset = 0h) [reset = 0h]

NMAVFLG is shown in Figure 2-252 and described in Table 2-280.
Non-Master Access Violation Flag Register
Figure 2-252. NMAVFLG Register

31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
R-0h R-0h R-0h
7 6 5 4 3 2 1 0
RESERVED CLA1FETCH CLA1WRITE CLA1READ DMAWRITE CPUFETCH CPUWRITE CPUREAD
Table 2-280. NMAVFLG Register Field Descriptions

6 CLA1FETCH R 0h Non Master CLA1 Fetch Access Violation Flag:
0: No violation.
1: Access violation occured.
Reset type: SYSRSn
5 CLA1WRITE R 0h Non Master CLA1 Write Access Violation Flag:
0: No violation.
Reset type: SYSRSn
4 CLA1READ R 0h Non Master CLA1 Read Access Violation Flag:
0: No violation.
Reset type: SYSRSn
3 DMAWRITE R 0h Non Master DMA Write Access Violation Flag:
0: No violation.
Reset type: SYSRSn
2 CPUFETCH R 0h Non Master CPU Fetch Access Violation Flag:
0: No violation.
Reset type: SYSRSn

Table 2-280. NMAVFLG Register Field Descriptions (continued)

1 CPUWRITE R 0h Non Master CPU Write Access Violation Flag:
0: No violation.
Reset type: SYSRSn
0 CPUREAD R 0h Non Master CPU Read Access Violation Flag:
0: No violation.
Reset type: SYSRSn


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TMS320F2837xD Dual-Core Delfino

Technical Reference Manual

Literature Number: SPRUHM8G

2 Contents SPRUHM8G – December 2013 – Revised September 2017

2.7.2 Derived Clocks ................................................................................................... 111

SPRUHM8G – December 2013 – Revised September 2017 Contents 3

2.15.15 DCSM_Z1_REGS Registers ................................................................................. 402

4 Contents SPRUHM8G – December 2013 – Revised September 2017

4.8.3 Revision Register (REVISION)................................................................................. 644

SPRUHM8G – December 2013 – Revised September 2017 Contents 5

6.1 Inter-Processor Communication ........................................................................................ 834

6 Contents SPRUHM8G – December 2013 – Revised September 2017

10.1.5 SOC Configuration Examples ............................................................................... 1396

SPRUHM8G – December 2013 – Revised September 2017 Contents 7

13.8.1 SDFM Base Addresses....................................................................................... 1637

8 Contents SPRUHM8G – December 2013 – Revised September 2017

SPRUHM8G – December 2013 – Revised September 2017 Contents 9

17.3.2 Functional Description ........................................................................................ 2072

10 Contents SPRUHM8G – December 2013 – Revised September 2017

19.6 SCI Programmable Data Format ...................................................................................... 2168

SPRUHM8G – December 2013 – Revised September 2017 Contents 11

21.2 Configuring Device Pins ................................................................................................ 2242

12 Contents SPRUHM8G – December 2013 – Revised September 2017

21.8.15 Set the Receive Frame-Synchronization Mode .......................................................... 2291

SPRUHM8G – December 2013 – Revised September 2017 Contents 13

22 Controller Area Network (CAN) ......................................................................................... 2351

14 Contents SPRUHM8G – December 2013 – Revised September 2017

23 Universal Serial Bus (USB) Controller................................................................................ 2445

USBTXCSRL[15]) .............................................................................................. 2512

16 Contents SPRUHM8G – December 2013 – Revised September 2017

25.2 Configuring Device Pins ................................................................................................ 2596

SPRUHM8G – December 2013 – Revised September 2017 Contents 17

18 List of Figures SPRUHM8G – December 2013 – Revised September 2017

2-48. PIEIER9 Register ......................................................................................................... 203

SPRUHM8G – December 2013 – Revised September 2017 List of Figures 19

2-97. DC10_1 Register.......................................................................................................... 275

20 List of Figures SPRUHM8G – December 2013 – Revised September 2017

2-146. SYSPLLSTS Register .................................................................................................... 335

SPRUHM8G – December 2013 – Revised September 2017 List of Figures 21

2-195. Z1_LINKPOINTER Register ............................................................................................. 403

22 List of Figures SPRUHM8G – December 2013 – Revised September 2017

2-244. GSxACCPROT2 Register ............................................................................................... 483

SPRUHM8G – December 2013 – Revised September 2017 List of Figures 23

2-293. FRD_INTF_CTRL Register .............................................................................................. 547

24 List of Figures SPRUHM8G – December 2013 – Revised September 2017

3-20. 8-Bit Parallel GetWord Function ........................................................................................ 608

SPRUHM8G – December 2013 – Revised September 2017 List of Figures 25

5-15. MICLROVF Register ..................................................................................................... 812

26 List of Figures SPRUHM8G – December 2013 – Revised September 2017

7-1. GPIO Logic for a Single Pin ............................................................................................. 906

SPRUHM8G – December 2013 – Revised September 2017 List of Figures 27

7-50. GPCCSEL1 Register.................................................................................................... 1001

28 List of Figures SPRUHM8G – December 2013 – Revised September 2017

7-99. GPFCSEL2 Register .................................................................................................... 1082

SPRUHM8G – December 2013 – Revised September 2017 List of Figures 29

8-23. XBARCLR1 Register .................................................................................................... 1172

30 List of Figures SPRUHM8G – December 2013 – Revised September 2017