1/3-Inch CMOS Digital Image Sensor: AR0134 Developer Guide, Rev. C

Aptina Confidential and Proprietary
AR0134: Developer Guide
1/3-Inch CMOS Digital Image Sensor

AR0134 Developer Guide, Rev. C
For the latest data sheet, refer to Aptina’s Web site: www.aptina.com
AR0134 Developer Guide
.
AR0134_DG - Rev. C Pub 6/14 EN 1 ©2013 Aptina Imaging Corporation. All rights reserved.

Table of Contents
Table of Contents
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Optimal Setting Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Frame Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Blanking Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Pixel Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Pixel Array Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Default Readout Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Output Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Readout Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Parallel Output Data Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
LV and FV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
LV Format Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
High Speed Serial Pixel Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
HiSPi Physical Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
DLL Timing Adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Frame Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Exposure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Row-Time Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Exposure Indicator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Real-Time Context Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Operational Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Master Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Trigger Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Hard Reset of Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Soft Reset of Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Output Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
PLL-Generated Master Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Spread-Spectrum Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Stream/Standby Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Soft Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Hard Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Window Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Blanking Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Readout Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Digital Binning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Skipping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Mirror . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Column Mirror Image. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Row Mirror Image . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Maintaining a Constant Frame Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Synchronizing Register Writes to Frame Boundaries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Restart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Auto Exposure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Auto Exposure Implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
AE Embedded Statistics and Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
AE Target Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
.

Table of Contents
Exposure Control System. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

Auto Exposure Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
AE Frame Synchronization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Digital Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Column Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Black Level Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Row-wise Noise Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Column Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Column Correction Triggering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Column Triggering on Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Column Correction Retriggering Due to Mode Change . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Test Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Color Field. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Vertical Color Bars. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Walking 1s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Two-Wire Serial Interface CRC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Two-Wire Serial Interface Sequential Writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Reading the Sensor CRA and Chromaticity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
.

List of Figures
List of Figures
Figure 1: Pixel Array Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Figure 2: Pixel Color Pattern Detail (Top Right Corner) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Figure 3: Imaging a Scene . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Figure 4: Spatial Illustration of Image Readout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Figure 5: Default Pixel Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Figure 6: LV Format Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Figure 7: HiSPi Transmitter and Receiver Interface Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Figure 8: Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Figure 9: Block Diagram of DLL Timing Adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Figure 10: Delaying the Clock with Respect to Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Figure 11: Delaying Data with Respect to the Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Figure 12: Line Timing and FRAME_VALID/LINE_VALID Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Figure 13: Master Mode Synchronization Waveform #1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Figure 14: Master Mode Synchronization Waveform #2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Figure 15: Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Figure 16: Pulsed Trigger Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Figure 17: Automatic Trigger Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Figure 18: PLL Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Figure 19: Pixel Readout (no skipping) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Figure 20: Pixel Readout (Row Skip 2X Bayer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Figure 21: Pixel Readout (Row Skip 2X Monochrome) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Figure 22: Six Rows in Normal and Row Mirror Readout Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Figure 23: Latency For Single Buffered Registers - Coarse Integration Time Example. . . . . . . . . . . . . . . . . . . . . .35
Figure 24: Latency For Double Buffered Registers - Column Gain Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Figure 25: Latency For Double Buffered Registers - Fine Integration Time Example. . . . . . . . . . . . . . . . . . . . . . .36
Figure 26: Calculating Temperature Sensor Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Figure 27: AE Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Figure 28: AE Stats Calculation Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Figure 29: Frame Format with Embedded Data Lines Enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Figure 30: Embedded Statistics Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Figure 31: Exposure Control System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Figure 32: Selecting the ROI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Figure 33: Automatic Gain Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Figure 34: AE Frame Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Figure 35: Solid Color . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Figure 36: Vertical Color Bars . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Figure 37: Walking 1s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Figure 38: Checksum Generation Flow Within the Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Figure 39: Definition of 16-bit CRC Shift Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
.

List of Tables
List of Tables
Table 1: AR0134 HiSPi Protocol Configuration Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Table 2: Frame Time (Example Based on 1280 x 960, 54 Frames Per Second) . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Table 3: Frame Time: Long Integration Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Table 4: Real-Time Context-Switchable Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Table 5: Exposure Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Table 6: Snapshot Mode Register Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Table 7: Example 1 (With Default Setting for Full Resolution) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Table 8: Example 2 (With Default Settings for 720p) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Table 9: PLL Parameters for the Parallel Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Table 10: Example PLL Configuration for the Parallel Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Table 11: PLL Parameters for the Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Table 12: Example PLL Configurations for the Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Table 13: Skip Mode Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Table 14: Six Pixels in Normal and Column Mirror Readout Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Table 15: Exposure Control Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Table 16: AE Enable Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Table 17: Auto Exposure Control Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Table 18: Test Pattern Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Table 19: CRA Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
.

Introduction
Introduction
This Developer Guide provides detailed descriptions and usage guidelines for various
features of the AR0134 Global Shutter Sensor. Also provided are guidelines for optimal
settings for various use cases. For detailed electrical and timing specifications or register
descriptions, refer to the AR0134 Data Sheet and the AR0134 Register Reference docu-
ments, respectively.
Optimal Setting Guidelines

The AR0134 Global Shutter Sensor has many built-in features and is capable of many
resolutions and frame rates. Guidelines for setting resolution and frame rate are
provided in this section. Detailed settings for the many features are provided throughout
the remainder of this Developer Guide. Window registers are also provided to enable
context switching. See the section on Real-Time Context Switching and the register
reference guide for more details.
Resolution
Aptina's AR0134 sensor is capable of a maximum resolution of 1280 x 960 at up to 54 fps,
or it may be configured to run 720p at 60fps. Registers y_addr_start, x_addr_start, y_ad-
dr_end, and x_addr_end are used to specify the image window. The minimum value for
x_addr_start is 0 and the maximum value for x_addr_end is 1279. The minimum y_ad-
dr_start and maximum y_addr_end are 0 and 975, respectively.
Frame Rate
Achieving the desired frame rate at the proper resolution is a balancing act between row
timing and the number of rows in the image. Integration time and the pixel clock
frequency are additional factors. The minimum line length is 1388 pixel clocks which
enables a frame rate of 54 fps. When using trigger mode, the minimum line length is
1650 pixel clocks.
Blanking Control
Horizontal blanking and vertical blanking times are controlled by the Line_length_Pck
and Frame_Length_Lines registers, respectively.
• Horizontal blanking is specified in terms of pixel clocks. It is calculated by subtracting
the X window size from the Line_Length_Pck register. The minimum horizontal
blanking time is 108 pixel clocks when the X window is set to 1280. If the X window
size is configured to less than 1280, the sum of the X window size and the horizontal
blanking must be equal to or greater than 1388.
• Vertical blanking is specified in terms of numbers of lines. It is calculated by
subtracting the Y window size from the Frame_Length_Lines register. The minimum
value for vertical blanking is 23 lines.
The actual imager timing is described in the Frame Time section of this Developer
Guide.
.

Pixel Data Format
Pixel Data Format

Pixel Array Structure
The AR0134 pixel array is configured as 1412 columns by 1028 rows, (see Figure 1). The
dark pixels are optically black and are used internally to monitor black level. Of the right
108 columns, 64 are dark pixels used for row noise correction. Of the top 24 rows of
pixels, 12 of the dark rows are used for black level correction. There are 1296 columns by
976 rows of optically active pixels. While the sensor's format is 1280 x 960, the additional
active columns and active rows are included for use when horizontal or vertical mirrored
readout is enabled, to allow readout to start on the same pixel. The pixel adjustment is
always performed for monochrome or color versions. The active area is surrounded with
optically transparent dummy pixels to improve image uniformity within the active area.
Not all dummy pixels or barrier pixels can be read out.
Figure 1: Pixel Array Description
1412
2 light dummy + 4 barrier + 24 dark + 4 barrier + 6 dark dummy
1296 x 976 (1288 x 968 active)

4.86 x 3.66 mm2 (4.83 x 3.63 mm2)
1028
2 light dummy + 4 barrier + 100 dark + 4 barrier

2 light dummy + 4 barrier
2 light dummy + 4 barrier + 6 dark dummy
Dark pixel Barrier pixel Light dummy Active pixel

pixel
.

Pixel Data Format
Figure 2: Pixel Color Pattern Detail (Top Right Corner)
Column Readout Direction
First Adressable Pixel (0,0)

Row Readout Direction Physical Location (112, 44)
R G R G R G R G
G B G B G B G B
R G R G R G R G
G B G B G B G B
R G R G R G R G
G B G B G B G B
Default Readout Order

By convention, the sensor core pixel array is shown with the first addressable (logical)
pixel (0,0) in the top right corner (see Figure 2). This reflects the actual layout of the array
on the die. Also, the physical location of the first pixel data read out of the sensor in
default condition is that of pixel (112, 44).
When the sensor is imaging, the active surface of the sensor faces the scene as shown in
Figure 3. When the image is read out of the sensor, it is read one row at a time, with the
rows and columns sequenced as shown in Figure 3 on page 8.
Figure 3: Imaging a Scene
Lens
Scene
Sensor (rear view)
Row
Readout
Order
Column Readout Order Pixel (0,0)
.

Output Data Format
Output Data Format

The AR0134 image data is read out in a progressive scan. Valid image data is surrounded
by horizontal and vertical blanking (see Figure 4). The amount of horizontal row time (in
clocks) is programmable through R0x300C. The amount of vertical frame time (in rows)
is programmable through R0x300A. Line_Valid (LV) is HIGH during the shaded region of
Figure 4. Optional embedded register setup information and histogram statistic infor-
mation are available in the first two and the last two rows of image data.
Figure 4: Spatial Illustration of Image Readout
P0,0 P0,1 P0,2.....................................P0,n-1 P0,n 00 00 00 .................. 00 00 00

P1,0 P1,1 P1,2.....................................P1,n-1 P1,n 00 00 00 .................. 00 00 00
VALID IMAGE HORIZONTAL

BLANKING
Pm-1,0 Pm-1,1.....................................Pm-1,n-1 Pm-1,n 00 00 00 .................. 00 00 00

Pm,0 Pm,1.....................................Pm,n-1 Pm,n 00 00 00 .................. 00 00 00
00 00 00 ..................................... 00 00 00 00 00 00 .................. 00 00 00
00 00 00 ..................................... 00 00 00 00 00 00 .................. 00 00 00
VERTICAL BLANKING VERTICAL/HORIZONTAL

BLANKING
00 00 00 ..................................... 00 00 00 00 00 00 .................. 00 00 00
00 00 00 ..................................... 00 00 00 00 00 00 .................. 00 00 00
Readout Sequence
Typically, the readout window is set to a region including only active pixels. The user has
the option of reading out dark regions of the array, but if this is done, consideration must
be given to how the sensor reads the dark regions for its own purposes.
.

Output Data Format
Parallel Output Data Timing

The output images are divided into frames, which are further divided into lines. By
default, the sensor produces 964 rows of 1280 columns each. The FV and LV signals indi-
cate the boundaries between frames and lines, respectively. PIXCLK can be used as a
clock to latch the data. One 12-bit pixel datum is launched on the DOUT pins for each
falling edge of PIXCLK. The launch edge of PIXCLK may be set in register R0x3028. When
both FV and LV are asserted, the pixel is valid. PIXCLK cycles that occur when FV is de-
asserted are called vertical blanking. PIXCLK cycles that occur when only LV is de-
asserted are called horizontal blanking.
To enable the parallel output pins, set R0x301A[7] = 1, and set R0x301A[12] = 1 to disable
the HiSPi serializer. The parallel input pins (i.e. TRIGGER, STANDBY, etc) may be
enabled by setting R0x301A[8] = 1. Only one output interface should be enabled at a
time.
Figure 5: Default Pixel Output Timing
PIXCLK
FV
LV
DOUT[11:0] P0 P1 P2 P3 Pn
Vertical Blanking Horiz Blanking Valid Image Data Horiz Blanking Vertical Blanking
LV and FV
The timing of the FV and LV outputs is closely related to the row time and the frame time.
FV will be asserted for an integral number of row times, which will normally be equal to
the height of the output image.
LV will be asserted during the valid pixels of each row. The leading edge of LV will be
offset from the leading edge of FV by 6 PIXCLKs. Normally, LV will only be asserted if FV
is asserted; this is configurable as described below.
LV Format Options
The default situation (R0x306E[1:0] = 0x0) is for LV to be de-asserted when FV is de-
asserted. By setting R0x306E[1:0]= 0x1, a continuous LV signal will be output. The
formats for reading out four lines and two vertical blanking lines are shown in Figure 6.
.

Output Data Format
Figure 6: LV Format Options
FV
Default
LV
FV
Continuous LV LV
The timing of an entire frame is shown in Figure 12: “Line Timing and FRAME_VALID/
LINE_VALID Signals,” on page 14. For detailed timing diagrams and switching parame-
ters, refer to the AR0134 data sheet.
High Speed Serial Pixel Interface

The AR0134 also uses Aptina's High-Speed Serial Pixel Interface (HiSPi™). The AR0134
HiSPi interface supports two protocols, Streaming-SP, and Packetized SP. The streaming
protocol conforms to a standard video application where each line of active or intra-
frame blanking provided by the sensor is transmitted at the same length. The Packetized
SP protocol will transmit only the active data ignoring line-to-line and frame-to-frame
blanking data. Refer to Table 1 for HiSPi protocol and lane settings.
Table 1: AR0134 HiSPi Protocol Configuration Settings
Protocol R0x31C6
Streaming-SP 2 Lane 0x0004
Streaming-SP 3 Lane 0x000C
Packetized-SP 2 Lane 0x0000
Packetized-SP 3 Lane 0x0008
These protocols are further described in the High-Speed Serial Pixel (HiSPi™) Interface
Protocol Specification V1.50.00.
The HiSPi interface building block is a unidirectional differential serial interface with
four data and one double data rate (DDR) clock lanes. One clock for every four serial
data lanes is provided for phase alignment across multiple lanes. Figure 7 shows the
configuration between the HiSPi transmitter and the receiver.
To enable the serial interface, set R0x301A[7] = 0, and set R0x301A[12] = 0 to enable the
HiSPi serializer. Refer to “Clocks” on page 26 for PLL configuration when using the HiSPi
interface.
.

Output Data Format
Figure 7: HiSPi Transmitter and Receiver Interface Block Diagram
A camera containing A host (DSP) containing

the HiSPi transmitter the HiSPi receiver
Dp0 Dp0
Dn0 Dn0
Dp1 Dp1
Dn1 Dn1
Tx Dp2 Dp2 Rx
PHY0 Dn2 Dn2
PHY0
(Dp3) Dp3
(Dn3) Dn3
Cp0 Cp0
Cn0 Cn0
HiSPi Physical Layer

The HiSPi physical layer is partitioned into blocks of four data lanes and an associated
clock lane. Depending on the operating mode and data rate, it can be configured from
two to three lanes. Dp3 and Dn3 are not supported by the AR0134 but pins are
connected on the package. The PHY will serialize a 12-bit data word and transmit on
both edges of the clock. Figure 8 shows bit transmission. In this example, the word is
transmitted in order of MSB to LSB. The receiver latches data at the rising and falling
edge of the clock. The AR0134 supports only the SLVS mode of the HiSPi electrical speci-
fication. For detailed timing and electrical specifications for the HiSPi interface, refer to
the AR0134 Datasheet.
Figure 8: Timing Diagram
TxPost
cp
….
cn
TxPre
dp
….
MSB LSB
dn
1 UI
.

Output Data Format
DLL Timing Adjustment

The AR0134 includes a DLL to compensate for differences in group delay for each data
lane. The DLL is connected to the clock lane and each data lane, which acts as a control
master for the output delay buffers. Once the DLL has gained phase lock, each lane can
be delayed in 1/8 unit interval (UI) steps. This additional delay allows the user to
increase the setup or hold time at the receiver circuits and can be used to compensate
for skew introduced in PCB design.
Delay compensation may be set for clock and/or data lines in the hispi_timing register
R0x31C0. If the DLL timing adjustment is not required, the data and clock lane delay
settings should be set to a default code of 0x000 to reduce jitter, skew, and power dissipa-
tion.
Figure 9: Block Diagram of DLL Timing Adjustment

CLOCK_DEL[2:0]
DATA1_DEL[2:0]
DATA3_DEL[2:0]
DATA2_DEL[2:0]
DATA0_DEL[2:0]
delay delay delay delay delay
data _lane 0 data _lane 1 clock _lane 0 data _lane 2 (data_lane 3)
Figure 10: Delaying the Clock with Respect to Data
1 UI
dataN (DATAN_DEL = 000)
cp (CLOCK_DEL = 000)
c p (CLOCK_DEL = 110)
cp (CLOCK_DEL =111)
increasing CLOCK_DEL[2:0] increases clock delay
.

Output Data Format
Figure 11: Delaying Data with Respect to the Clock
cp ( CLOCK_DEL = 000)
dataN (DATAN_DEL = 000)
dataN(DATAN_DEL = 001)
increasing DATAN_DEL[2:0] increases data delay
t 1 UI
DLLSTEP
Frame Time
The pixel clock (PIXCLK) represents the time needed to sample one pixel from the array.
The sensor outputs data at the maximum rate of one pixel per PIXCLK. One row time
(tROW) is the period from the first pixel output in a row to the first pixel output in the
next row. The row time and frame time are defined by equations in Table 2.
Figure 12: Line Timing and FRAME_VALID/LINE_VALID Signals
...
FRAME_VALID
...
LINE_VALID
...
Number of master clocks P1 A Q A Q A P2
Table 2: Frame Time (Example Based on 1280 x 960, 54 Frames Per Second)
Default Timing
Parameter Name Equation at 74.25 MHz
A Active data time Context A: R0x3008 - R0x3004 + 1 1280 pixel clocks
Context B: R0x308E - R0x308A + 1 = 17.23s
P1 Frame start blanking 6 (fixed) 6 pixel clocks
= 0.08s
P2 Frame end blanking 6 (fixed) 6 pixel clocks
= 0.08s
Q Horizontal blanking R0x300C - A 108 pixel clocks
= 1.45s
.

Output Data Format
Table 2: Frame Time (Example Based on 1280 x 960, 54 Frames Per Second)
Default Timing
Parameter Name Equation at 74.25 MHz
A+Q Row Time (tROW) R0x300C 1388 pixel clocks
= 18.69s
V Vertical blanking Context A: [(R0x300A - (R0x3006 - R0x3002 + 1)) * (A + Q)] 51,356 pixel clocks
Context B: [(R0x300A - (R0x3090 R0x308C + 1)) * (A + Q)] = 691.7s
Nrows * (A + Q) Frame valid time Context A: ((R0x3006-R0x3002+1)*(A+Q))-Q+P1+P2 1,332,384 pixel clocks
Context B: ((R0x3090-R0x308C+1)*(A+Q))-Q+P1+P2 = 17.94ms
F Total frame time V + (Nrows * (A + Q)) 1,383,836 pixel clocks
= 18.6ms
Sensor timing is shown in terms of pixel clock cycles (see Figure 5: “Default Pixel Output
Timing,” on page 10). The recommended pixel clock frequency is 74.25 MHz. The
vertical blanking and the total frame time equations assume that the integration time
(coarse integration time plus fine integration time) is less than the number of active
lines plus the blanking lines:
Coarse Integration Time < Window Height + Vertical Blanking (EQ 1)
If this is not the case, the number of integration lines must be used instead to determine
the frame time, (see Table 3). In this example, it is assumed that the coarse integration
time control is programmed with 2000 rows and the fine shutter width total is zero.
For Master mode, if the integration time registers exceed the total readout time, then the
vertical blanking time is internally extended automatically to adjust for the additional
integration time required. This extended value is not written back to the
frame_length_lines register. The frame_length_lines register can be used to adjust
frame-to-frame readout time. This register does not affect the exposure time but it may
extend the readout time.
Table 3: Frame Time: Long Integration Time
Equation Default Timing

Parameter Name (Number of Pixel Clock Cycles) at 74.25 MHz
Total frame time (long Context A: (R0x3012 * (A + Q)) - R0x3014 + P1 + P2 2,776,012 pixel clocks
F’
integration time) Context B: (R0x3016 * (A + Q)) - R0x3018 + P1 + P2 = 37.4ms
.

Exposure
Exposure
Total integration time is the result of coarse_integration_time and fine_integration_time
registers, and depends also on whether manual or automatic exposure is selected.
The actual total integration time, tINT is defined as:
tINT = tINTCoarse + tINTFine (EQ 2)
= (number of lines of integration * line time) + (number of pixels of integration * pixel
time)
where:
• Number of Lines of Integration (Auto Exposure Control: Enabled)
When automatic exposure control (AEC) is enabled, the number of lines of integra-
tion may vary from frame to frame, with the limits controlled by R0x311E (minimum
auto exposure time) and R0x311C (maximum auto exposure time). For a specific
frame output, the exposure time (in rows) can be read in R0x30AC. Fine integration
time is not used by the auto exposure function.
• Number of Lines of Integration (Auto Exposure Control: Disabled)

Context A: the number of lines of integration equals the value in R0x3012.
Context B: the number of lines of integration equals the value in R0x3016.
• Number of Pixels of Integration (Auto Exposure Control: Disabled.)

Context A: the number of pixels of integration equals the value in R0x3014.
Context B: the number of pixels of integration equals the value in R0x3018.
Maximum value for tINTFine is line_length_pck - 742.
If the exposure time is to be set to approximately 2.22ms and default settings are being
used (where one row-time equals 22.22μs), a value of “100” is entered in R0x3012
(2.22ms / 22.22μs = 100). In this mode, only whole number row-time increments are
allowed—no fractional time increments can be achieved. It may be possible to adjust the
number of horizontal active or blanking pixels to bring the desired exposure time to a
whole number row-time increment.
The exposure time using the default power up settings of the sensor can be determined
as follows:
exposure_time = coarse_integration_time  row_time (EQ 3)
exposure_time =  100 rows    22.22  s  = 2.22ms (EQ 4)

–
Typically, the value of the coarse_integration_time register is limited to the number of
lines per frame (which includes vertical blanking lines), such that the frame rate is not
affected by the integration time.
Row-Time Definition
One row-time is equal to the sum of the number of active pixels (columns) and the
number of horizontal blanking pixels divided by the pixel readout rate:
active_pixels + horizontal_blank_pixels
row_time = -------------------------------------------------------------------------------------------------- (EQ 5)
PIXCLK_frequency
.

Real-Time Context Switching
line_length_pck  R0x300C  1388

row_time default_settings = ------------------------------------------------------------------- = -------------------------- = 18.69  s (EQ 6)
PIXCLK_frequency 74.25MHz
Exposure Indicator
The AR0134 provides an output pin, FLASH, to indicate when the exposure takes place.
When R0x3046[8]is set, FLASH is HIGH during exposure. By using R0x3046[7], the
polarity of the FLASH pin can be inverted.
Real-Time Context Switching

In the AR0134, the user may switch between two full register sets (listed in Table 4) by
writing to a context switch change bit in R0x30B0[13]. This context switch will change all
registers (no shadowing) at the frame start time and have the new values apply to the
immediate next exposure and readout time.
Table 4: Real-Time Context-Switchable Registers
Register Number
Register Description Context A Context B
y_addr_start R0x3002 R0x308C
x_addr_start R0x3004 R0x308A
y_addr_end R0x3006 R0x3090
x_addr_end R0x3008 R0x308E
coarse_integration_time R0x3012 R0x3016
fine_integration_time R0x3014 R0x3018
y_odd_Inc R0x30A6 R0x30A8
green1_gain (GreenR) R0x3056 R0x30BC
blue_gain R0x3058 R0x30BE
red_gain R0x305A R0x30C0
green2_gain (GreenB) R0x305C R0x30C2
global_gain R0x305E R0x30C4
frame_length_lines R0x300A R0x30AA
digital_binning R0x3032[1:0] R0x3032[5:4]
column_gain R0x30B0[5:4] R0x30B0[9:8]
.

Features
Features
Note: See the AR0134 Register Reference for additional details.
Operational Modes
The AR0134 works in master (video) or trigger (single frame) modes. In master mode, the
sensor generates the integration and readout timing. In trigger mode, it accepts an
external trigger to start exposure, then generates the exposure and readout timing. The
exposure time is programmed through the two-wire serial interface for both modes.
Note: Trigger mode is not compatible with the HiSPi interface.
Master Mode
In master mode, the exposure period occurs simultaneously with the frame readout (see
Figures 13 and 14). This makes master mode the fastest mode of operation. When expo-
sure time is greater than the frame length, the number of vertical blanking rows is
increased automatically to accommodate the exposure time.
Figure 13: Master Mode Synchronization Waveform #1
Readout Time > Exposure Time
FLASH
Exposure Time
FRAME_VALID Vertical Blanking
LINE_VALID
DOUT(11) xxx xxx xxx
Figure 14: Master Mode Synchronization Waveform #2
Exposure Time > Readout Time
FLASH
Exposure Time
Vertical Blanking
FRAME_VALID
LINE_VALID
DOUT(11) xxx xxx xxx
.

Features
Trigger Mode
In trigger mode, the exposure period and the frame readout occur sequentially (see
Figure 16 and Figure 17 on page 20). This makes trigger mode slower than master mode.
Two options of triggering are made available. A Pulsed Trigger mode where only a single
frame is output, and an Automatic Trigger mode where a series of frames are output.
Triggered System Details

Many imaging applications commonly require the image sensor to capture an image
only after a triggering action has taken place. This triggering action can be the passing of
an object on a conveyor belt, the flash of a strobe light, or the press of a button.
The AR0134 offers the ability to synchronize the start of the image sensor's exposure
with this triggering action. This synchronization is controlled on the image sensor
through the use of the TRIGGER input signal. Additionally, the image sensor offers the
flexibility to program the exposure time remotely. This Developer Guide only addresses
the single image sensor (non-stereoscopic) mode of operation.
Figure 15: Block Diagram

EXTCLK
TRIGGER
AR0134
CONTROLLER
PIXCLK
FRAME_VALID
LINE_VALID
FLASH
DOUT[11:0]
Trigger Mode Overview

When the image sensor is set to trigger mode, the beginning and duration of the expo-
sure time are controlled. The global shutter feature of the image sensor allows all pixels
to be exposed in parallel—all pixels start exposing (integrating charge) simultaneously
and stop exposing simultaneously. When exposure stops, the per-pixel integrated
charges are digitized and read out of the chip. A new exposure begins only after the
readout of all pixels is complete. If the TRIGGER input is left in the asserted state, the
sensor will automatically initiate a new frame acquisition sequence upon completion of
the current frame.
.

Features
Figure 16: Pulsed Trigger Mode
TTT
TRIGGER TTPW
EXPOSURE
TIME
TTF
FLASH
TFFV
FRAME_VALID
TVB
LINE_VALID
FRAME TIME
Notes: 1. Not drawn to scale.

2. Frame readout shortened for clarity.
3. Progressive scan readout mode shown.
Figure 17: Automatic Trigger Mode
TRIGGER
EXPOSURE EXPOSURE EXPOSURE

TIME TIME TIME
TTF FRAME A FRAME B FRAME C
FLASH
TFFV
FRAME_VALID FRAME A FRAME B
TVB
LINE_VALID
FRAME TIME
Table 5: Exposure Timing
Symbol Description Value

TTT TRIGGER signal period TTF + EXPOSURE TIME + TFFV + FRAME TIME
TTPW TRIGGER signal pulse width 10 row times (MIN)
TTF TRIGGER to FLASH 8.21 row-times
TFFV FLASH to FRAME_VALID 18.21 row times
TVB Vertical blanking time R0x300A - (R0X3006 - R0x3002 + 1)) * (Active Data Time + Horizontal Blanking
Time) (MIN 23Lines)
Notes: 1. EXTCLK-cycle unit is defined as the reciprocal of the EXTCLK input frequency.
2. See “Exposure and Data Synchronization Outputs” on page 22 for the row-time unit definition.
3. To change exposure time, change the coarse integration time registers R0x3012 for Context A or
R0x3016 for Context B.
4. To change frame rate, change the TTT value.
.

Features
Register Settings
The TRIGGER mode of operation requires that register R0x301A (Reset Register) bit 2 be
set to “0”. Setting this register to “1” will switch the sensor back to the master mode of
operation. The general purpose I/O (GPI) pins must also be enabled as shown in Table 6.
Table 6: Snapshot Mode Register Settings
Value in
Register Register Name Bit Bit Name Bit Description Dec (Hex)
R0x301A Reset Register 2 Stream 0 = Trigger mode 0
1 = master mode
R0x301A Reset Register 8 GPI_EN 0 = GPI input buffers disabled 1
1 =GPI input buffers enabled
R0x301A Reset Register 11 forced_pll_on 0 = PLL powered down in standby 1
1 =PLL always powered
Start of Exposure
The start of exposure is controlled by the TRIGGER input on the image sensor. Normally,
TRIGGER is held in a LOW state. To start exposing, this signal is changed to a HIGH state.
This HIGH state is then sampled on the rising edge of the master clock (EXTCLK) of the
image sensor. TRIGGER must be held HIGH for greater than 10 row times.
Duration of Exposure
The duration of the exposure is set by the value stored in R0x3012, which represents an
equivalent number of row-times (see “Exposure and Data Synchronization Outputs” on
page 22) to the actual exposure time.
The minimum exposure time supported by the AR0134 image sensor in trigger mode is 3
row-times.
A restriction exists on coarse integration time when using trigger mode to ensure correct
output of the FLASH signal. The following values for coarse integration time should be
avoided:
coarse_integration_time = frame_length_lines - (active_rows + col_correction_rows (8) + delta_dark_rows (6) +
embedded_stats (2) + 7) (EQ 7)
As an example, if frame_length_lines is 990 and the number of active rows is 960 (964
minus 4 embedded stats and data rows), then an integration time of:
 CIT = 990 –  960 + 8 + 6 + 2 + 7   = 7 (EQ 8)
should be avoided to ensure proper exposure in trigger mode. This restriction does not
apply to master mode operation. If column correction is disabled, the 8 rows in EQ5
should be replaced with zero.
.

Features
Exposure and Data Synchronization Outputs

The AR0134 image sensor offers an output synchronization signal (FLASH) that can be
used to control the flash of a light source. The timing of this signal in trigger mode is
similar to the other exposure modes. The signal is normally held in a LOW state. FLASH
changes to a HIGH state when the image sensor is exposing (integrating charge). FLASH
returns to the normal LOW state once the exposure (set by register R0x3012 (Context A),
or register R0x3016 (Context B)) has timed out.
To indicate a valid frame of video data is being output from the image sensor,
FRAME_VALID switches to a HIGH state. The change of state occurs slightly over
18 row-times after the exposure time ends. FRAME_VALID returns to a LOW state after
the active rows have been read out. The number of active rows plus vertical blanking is
stored in the FRAME_LENGTH_LINES register (R0x300A) (default value is 990).
During the valid video frame state, LINE_VALID switches to a HIGH state to indicate a
valid row of video data is being presented. LINE_VALID returns to a LOW state after a set
number of PIXCLK cycles corresponding to the number of active pixels per line. The
number of active pixels plus horizontal blanking is stored in the LINE_LENGTH_PCK
register (R0x300C) (required value for trigger mode is 1650).
TRIGGER Input Restrictions

The minimum time between two successive TRIGGER input pulses (shown as TTT in
Figure 16 on page 20) is calculated from the exposure time and the frame time. The
exposure time is described in “Exposure and Data Synchronization Outputs” on page 22.
The frame time may be calculated from two variables: the row-time, and the number of
rows-per-frame. The number of rows-per-frame is equal to the sum (R0x300A) of the
number of active rows and the number of vertical blanking rows:
rows_per_frame = active rows + vertical blanking rows (EQ 9)
rows_per_frame = frame_length_lines (R0x300A)=990 rows (EQ 10)

default_settings
The frame time is equal to the product of the number of rows-per-frame and the row-
time.
frame_time = rows_per_frame x (row_time) (EQ 11)
22.22  s
frame_time default_settings =  990 rows x  -------------------- = 22.0ms (EQ 12)
 row 
The minimum time between two successive TRIGGER pulses equals the sum of the
frame time, the exposure time, TTF and TFFV:
T TT =  frame_time +  exp osure_time +  T TF + T FFV  (EQ 13)
.

Features
Further, the maximum allowable frame rate may be calculated from these same three
variables. The maximum frame rate is the reciprocal of the sum of the frame time, the
exposure time, trigger to flash, and flash to frame valid times:.
1
frame_rate= -------------------------------------------------------------------------------------------------------- (EQ 14)
frame_time + exposure_time + T TF + T FFV
The TRIGGER pulse period should correspond to the desired frame rate. For individual
(asynchronous) trigger pulses, the TRIGGER signal should be asserted no sooner than
FRAME_VALID is deasserted, and the minimum of 23 rows of vertical blanking has
elapsed.
Example Frame Rate Calculations

Two examples follow on performing frame rate calculations for the AR0134 image
sensors, shown in Table 7 below and Table 8 on page 24.
Example 1 shows maximum allowable frame rate or case where trigger pin is only
asserted once per frame:
Table 7: Example 1 (With Default Setting for Full Resolution)
Image Sensor Condition Setting Description Register [Bits] = Value

Exposure mode Trigger R0x301A[2] = 0
R0x301A[8] = 1
R0x301A[11] = 1
PIXCLK frequency 74.25 MHz N/A
Window height 9641 R0x3006 = 959
R0x3002 = 0
Window width 1280 R0x3008 = 1279
R0x3004 = 0
line_length_pck 1650 R0x300C = 1650
frame_length_lines 990 R0x300A = 990
Integration time 100 R0x3012 = 100
Notes: 1. Window height is 964 rows with embedded stats and data enabled.
Step 1: Calculate the row-time.

line_length_pck
row_time= ----------------------------------------------- (EQ 15)
PIXCLK_frequency
1650
row_time = ---------------------------- = 22.22  s (EQ 16)
74.25 MHz
Step 2: Calculate the rows-per-frame read out.
rows_per_frame=frame_length_lines (EQ 17)
rows_per_frame =990 rows (EQ 18)
.

Features
Step 3: Calculate the frame time.

frame_time =  rows_per_frame x  row_time  (EQ 19)
22.22  s
frame_time=  990 rows x  -------------------- = 22.0ms (EQ 20)
 row 
Step 4: Calculate the actual exposure time.

exposure_time=  integration_time    row_time 
· (EQ 21)
exposure_time =  100 rows   22.22  s =2.22ms
Step 5: Calculate TTF + TFFV.
T TF + T FFV =  8.21 rows + 18.21 rows   row_time

(EQ 22)
= 26.42 rows  22.22  s
= 587  s
(EQ 23)
Step 6: Calculate the maximum allowable frame rate.
1
frame_rate = --------------------------------------------------------------------------------------------------------
1
frame_rate = ----------------------------------------------------------------
22.0ms + 2.22ms + 587  s (EQ 24)
1
frame_rate = = --------------------
24.81ms
frame_rate = = 40.3Hz
Table 8: Example 2 (With Default Settings for 720p)
Image Sensor Condition Setting Description Register[Bits] = Value

Exposure mode Trigger R0x301A[2] = 0
R0x301A[8] = 1
R0x301A[11] = 1
PIXCLK frequency 74.25 MHz N/A
Window height 720 R0x3006 = 839
R0x3002 = 120
Window width 1280 R0x3008 = 1279
R0x3004 = 0
line_length_pck 1650 R0x300C = 1650
frame_length_lines 747 R0x300A = 747
Integration time 100 R0x3012 = 100
.

Features
Step 1: Calculate the row-time.

line_length_pck
row_time= ----------------------------------------------- (EQ 25)
PIXCLK_frequency
1650
row_time = ---------------------------- = 22.22  s (EQ 26)
74.25 MHz
Step 2: Calculate the rows-per-frame read out.
rows_per_frame = frame_length_lines (EQ 27)
row_per_frame = 747 rows (EQ 28)
Step 3: Calculate the frame time.

frame_time =  rows_per_frame x  row_time  (EQ 29)
22.22  s
frame_time=  747 rows x  -------------------- =16.6ms (EQ 30)
 row 
Step 4: Calculate the actual exposure time.

exposure_time=  integration_time x  row_time  (EQ 31)
exposure_time=  100 rows  22.22  s = 2.22ms (EQ 32)
Step 5: Calculate TTF + TFFV.
T TF + T FFV =  8.21 rows + 18.21 rows   row_time

= 26.42 rows  22.22  s (EQ 33)
= 587  s
(EQ 34)
Step 6: Calculate the maximum allowable frame rate.
1
frame_rate = --------------------------------------------------------------------------------------------------------
1
frame_rate = ---------------------------------------------------------------
16.6ms + 2.22ms + 587  s (EQ 35)
1
frame_rate = = -------------------
19.4 ms
frame_rate = = 51.5Hz
.

Features
Reset
The AR0134 may be reset by using RESET_BAR or the reset register.
Hard Reset of Logic

The host system can reset the image sensor by bringing the RESET_BAR pin to a LOW
state. Alternatively, the RESET_BAR pin can be connected to an external RC circuit for
simplicity. Registers written via the two-wire interface will not be preserved following a
hard reset.
Soft Reset of Logic

Soft reset of logic is controlled by bit 0 of the R0x301A Reset register. This bit is a self-
resetting bit and also returns to “0” during two-wire serial interface reads. Registers
written via the two wire interface will not be preserved following a soft reset.
Output Enable
The AR0134’s outputs can be tri-stated with the OE_BAR pin. Before the external pin can
be used to control output enable, set register R0x301A[6] = 0 to disable the output
drivers. Then set R0x301A[8] = 1 to enable the input pins (OE_BAR, TRIGGER, and
STANDBY). Driving OE_BAR low will enable the output drivers, while driving it high will
tri-state the parallel output pins. The parallel outputs can also be tri-stated by setting
R0x301A[7] = 0.
Clocks
PLL-Generated Master Clock
The PLL contains a prescaler to divide the input clock applied on EXTCLK, a VCO to
multiply the prescaler output, and two divider stages to generate the output clock. The
clocking structure is shown in Figure 18. The AR0134 default power up state for the PLL
dividers is for a pixel clock of 74.25 MHz that is generated from a 27 MHz EXTCLK. PLL
control registers can be programmed to generate frequencies other than the default
power up state. Refer to Table 9 on page 27 for PLL parameters for the parallel interface,
and Table 11 on page 27 for the HISPi interface. Example PLL configurations are also
provided using an EXTCLK of 27MHz.
Note: The PLL control registers must be programmed while the sensor is in the software
Standby state. The effect of programming the PLL divisors while the sensor is in the
streaming state is undefined.
Figure 18: PLL Block Diagram
PLL Input Clock PLL Output Clock HiSPi Bit Clock
Pre PLL PLL PLL PLL

EXTCLK Div Multiplier Output Output SYSCLK (PIXCLK)
(PFD) (VCO) Div 1 Div 2
N M P1 P2
pre_pll_clk_div pll_multiplier vt_sys_clk_div vt_pix_clk_div
(0x302E) (0x3030) (0x302C) (0x302A)
The PLL is enabled by default on the AR0134. To configure and use the PLL:
.

Features
1. Bring the AR0134 up as normal; make sure that fEXTCLK is between 6 and 50 MHz
and ensure the sensor is in software standby (R0x301A[2]= 0). PLL control registers
must be set in software standby.
2. Set pll_multiplier, pre_pll_clk_div, vt_sys_clk_div, and vt_pix_clk_div based on the
desired input (fEXTCLK) and output (fPIXCLK) frequencies. Determine the M, N, P1, and
P2 values to achieve the desired fPIXCLK using the formula:
fPIXCLK = (fEXTCLK × M) / (N × P1 x P2) (EQ 36)

where
M = pll_multiplier
N = pre_pll_clk_div
P1 = vt_sys_clk_div
P2 = vt_pix_clk_div
3. Wait 1ms to ensure that the VCO has locked.
4. Set R0x301A[2]=1 to enable streaming and to switch from EXTCLK to the PLL-gener-
ated clock.
Table 9: PLL Parameters for the Parallel Interface
Parameter Symbol Min Max Unit

External Clock EXTCLK 6 50 MHz
VCO Clock FVCO 384 768 MHz
Output Clock PIXCLK 74.25 Mpixel/s
Table 10: Example PLL Configuration for the Parallel Interface
Parameter Register Value Output

FVCO 594 MHz
pre_pll_clk_div (N) 2
pll_multiplier (M) 44
vt_sys_clk_div 1
vt_pix_clk_div 8
PIXCLK 74.25 MPixel/s
Output pixel rate 74.25 MPixel/s
Table 11: PLL Parameters for the Serial Interface
Parameter Symbol Min Max Unit

External Clock EXTCLK 6 50 MHz
VCO Clock FVCO 384 768 MHz
Readout Clock PIXCLK 74.25 Mpixel/s
Output Serial Data Rate Per Lane FSERIAL 280 (HiSPi) 700 (HiSPi) Mbps
Output Serial Clock Speed Per Lane FSERIAL_CLK 140 (HiSPi) 350(HiSPi) MHz
.

Features
Table 12: Example PLL Configurations for the Serial Interface
Register Value
Parameter 3-lane 2-lane Units
FVCO 742.5 445.5 MHz
pre_pll_clk_div 2 2
pll_multiplier 55 33
vt_sys_clk_div 2 1
vt_pix_clk_div 5 6
HiSPi Bit Clock 371.25 445.5 MHz
HiSPi Differential Clock 185.63 222.75 MHz
PIXCLK 74.25 74.25 Mpixel/s
Notes: 1. The PLL can be bypassed at any time (sensor will run directly off EXTCLK) by setting R0x30B0[14]=1.
However, only the parallel data interface is supported with the PLL bypassed. The PLL is always
bypassed in software standby mode. PLL bypass should only be enabled or disabled while the sen-
sor is in standby.
2. The following restrictions apply to the PLL tuning parameters:
32 M 255
1 N 63
1  P116
4P2 16
3. The VCO frequency, defined as fVCO = fEXTCLK × M/N must be within 384–768 MHz.
4. If using HiSPi output mode, use the following settings for P2 (vt_pix_clk_div).
4a. If 12-bit mode (3 lanes): set P2 (R0x302A) = 5
4b. If 12-bit mode (2 lanes): set P2 (R0x302A) = 6
The user can utilize the Register Wizard tool accompanying DevWare to generate PLL
settings given a supplied input clock and desired output frequency.
Spread-Spectrum Clocking
To facilitate improved EMI performance, the external clock input allows for spread spec-
trum sources, with no impact on image quality. Limits of the spread spectrum input
clock are:
• 5% maximum clock modulation
• 35 kHz maximum modulation frequency
• Accepts triangle wave modulation, as well as sine or modified triangle modulations.
Stream/Standby Control
The sensor supports two standby modes: Hard Standby and Soft Standby. In both
modes, external clock can be optionally disabled to further minimize power consump-
tion. If this is done, then the power-up sequence described in the AR0134 data sheet
must be followed.
Soft Standby
Soft Standby is a low power state that is controlled through register R0x301A[2].
Depending on the value of R0x301A[4], the sensor will go to standby after completion of
the current frame readout (default behavior) or after the completion of the current row
readout. When the sensor comes back from Soft Standby, previously written register
settings are still maintained. Soft standby will not occur if the TRIGGER pin is held high.
A specific sequence needs to be followed to enter and exit from Soft Standby.
.

Features
Entering Soft Standby:

1. Set R0x301A[12] = 1 if serial mode was used
2. Set R0x301A[2] = 0 and drive the TRIGGER pin LOW.
3. External clock can be turned off to further minimize power consumption (Optional)
Exiting Soft Standby:

1. Enable external clock if it was turned off
2. R0x301A[2] = 1 or drive the TRIGGER pin HIGH.
3. R0x301A[12] = 0 if serial mode is used
Hard Standby
Hard Standby puts the sensor in a lower power state. Register settings will be preserved.
A specific sequence needs to be followed to enter and exit from Hard Standby.
Entering Hard Standby:
1. R0x301A[8] = 1
2. R0x301A[12] = 1 if serial mode was used
3. Assert STANDBY pin
4. External clock can be turned off to further minimize power consumption (optional)
Exiting Hard Standby:

1. Enable external clock if it was turned off
2. De-assert STANDBY pin
3. Set R0x301A[8] = 0 (unless other inputs are used such as trigger, output_en, etc.)
Window Control
Registers x_addr_start, x_addr_end, y_addr_start, and y_addr_end control the size and
starting coordinates of the image window.
The exact window height and width out of the sensor is determined by the difference
between the Y address start and end registers or the X address start and end registers,
respectively.
The AR0134 allows different window sizes for context A and context B.
Blanking Control
Horizontal blank and vertical blank times are controlled by the line_length_pck and
frame_length_lines registers, respectively.
• Horizontal blanking is specified in terms of pixel clocks. It is calculated by subtracting
the X window size from the line_length_pck register. The minimum horizontal
blanking is 108 pixel clocks.
• Vertical blanking is specified in terms of numbers of lines. It is calculated by
subtracting the Y window size from the frame_length_lines register. The minimum
vertical blanking is 23 lines.
The actual imager timing can be calculated using Table 2 on page 14 and Table 3 on
page 15, which describe the Line Timing and FV/LV signals.
.

Features
Readout Modes
By default, the resolution of the output image is the full width and height of the FOV as
defined above. The output resolution can be reduced by digital binning.
Digital Binning
All of the pixels in the FOV contribute to the output image in digital binning mode. This
can result in a more pleasing output image with reduced artifacts. It also improves low-
light performance. For RGB and monochrome mode, the digital binning factor is set by
the register DIGITAL_BINNING (R0x3032). For Context A, use bits [1:0], for Context B,
use bits [5:4]. Available settings are: 00 = No binning; 01 = Horizontal binning; 10 = Hori-
zontal and vertical binning. For RGB mode, resampling must be enabled by setting bit 4
of register 0x306E. For monochrome operation, R0x30B0[7] must be set to 1. Enabling
horizontal or vertical binning mode does not affect the sensor frame rate.
Skipping
Skipping reduces resolution by using only selected rows from the FOV in the output
image. In skip mode, entire rows of pixels are not sampled, resulting in a lower resolution
output image. A skip 2X mode skips one Bayer pair of pixels for every pair output. Skip-
ping is set by R0x30A6 (context A) and R0x30A8 (context B). The maximum supported
skip is 64 rows. Both Bayer and monochrome skip modes are supported. Refer to
Table 13 on page 30 for supported skip factors.
When enabling a skip mode, register R0x30B0[10] should be set low. It should be
returned to the default state (R0x30B0[10]=1) when exiting skip modes. If this is not
done, a noticeable change in intensity may be observed when entering and exiting skip
mode.
Table 13: Skip Mode Settings
Skip Factor R0x30A6 (R0x30A8)

No Skip 0x0001
2 0x0003
4 0x0007
8 0x000F
16 0x001F
32 0x003F
64 0x007F
.

Features
Figure 19: Pixel Readout (no skipping)
X incrementing
Y incrementing
Figure 20: Pixel Readout (Row Skip 2X Bayer)
X incrementing Y incrementing
.

Features
Figure 21: Pixel Readout (Row Skip 2X Monochrome)
X incrementing
Y incrementing
.

Features
Mirror
Column Mirror Image
By setting R0x3040[14] = 1, the readout order of the columns is reversed, as shown in
Figure . The starting color, and therefore the Bayer pattern, is preserved when mirroring
the columns.
When using horizontal mirror mode, the user must retrigger column correction. Refer to
the column correction section to see the procedure for column correction retriggering.
Bayer resampling must be enabled, by setting bit 4 of register 0 x 306E[4] = 1.
Table 14: Six Pixels in Normal and Column Mirror Readout Modes
LV
Normal readout
G0[11:0] R0[11:0] G1[11:0] R1[11:0] G2[11:0] R2[11:0]
DOUT[11:0]
Reverse readout
DOUT[11:0] G3[11:0] R2[11:0] G2[11:0] R1[11:0] G1[11:0] R0[11:0]
Row Mirror Image

By setting R0x3040[15] = 1, the readout order of the rows is reversed as shown in
Figure 22. The starting Bayer color pixel is maintained in this mode by a 1-pixel shift in
the imaging array. When using horizontal mirror mode, the user must retrigger column
correction. Refer to the column correction section to see the procedure for column
correction retriggering.
Bayer resampling must be enabled, by setting bit 4 of register 0 x 306E[4] = 1.
Figure 22: Six Rows in Normal and Row Mirror Readout Modes
FV
Normal readout Row0 [11:0] Row1 [11:0] Row2 [11:0] Row3 [11:0] Row4 [11:0] Row5 [11:0]
DOUT[11:0]
Reverse readout
DOUT[11:0] Row6 [11:0] Row5 [11:0] Row4 [11:0] Row3 [11:0] Row2 [11:0] Row1 [11:0]
.

Features
Maintaining a Constant Frame Rate

Maintaining a constant frame rate while continuing to have the ability to adjust certain
parameters is the desired scenario. This is not always possible, however, because register
updates are synchronized to the read pointer, and the shutter pointer for a frame is
usually active during the readout of the previous frame. Therefore, any register changes
that could affect the row time or the set of rows sampled causes the shutter pointer to
start over at the beginning of the next frame.
By default, the following register fields cause a “bubble” in the output rate (that is, the
vertical blank increases for one frame) if they are written in video mode, even if the new
value would not change the resulting frame rate. The following list shows only a few
examples of such registers; a full listing can be seen in the AR0134 Register Reference.
• X_Addr_Start
• X_Addr_End
• Y_Addr_Start
• Y_Addr_End
• Frame_Length_Lines
• Line_Length_Pclk
• Coarse_Integration_Time
• Fine_Integration_Time
• Read_Mode
The size of this bubble is (Integration_Time × tROW), calculating the row time according
to the new settings.
The Coarse_Integration_Time and Fine_Integration_Time fields may be written to
without causing a bubble in the output rate under certain circumstances. Because the
shutter sequence for the next frame often is active during the output of the current
frame, this would not be possible without special provisions in the hardware. Writes to
these registers take effect two frames after the frame they are written, which allows the
integration time to increase without interrupting the output or producing a corrupt
frame (as long as the change in integration time does not affect the frame time).
Synchronizing Register Writes to Frame Boundaries

Changes to most register fields that affect the size or brightness of an image take effect
on the frame after the one during which they are written. These fields are noted as
“synchronized to frame boundaries” in the AR0134 Register Reference. To ensure that a
register update takes effect on the next frame, the write operation must be completed
after the leading edge of FV and before the trailing edge of FV.
As a special case, in trigger mode, register writes that occur after FV but before the next
trigger will take effect immediately on the next frame, as if there had been a Restart.
However, if the trigger for the next frame occurs during FV, register writes take effect as
with video mode.
Fields not identified as being frame-synchronized are updated immediately after the
register write is completed. The effect of these registers on the next frame can be difficult
to predict if they affect the shutter pointer.
.

Features
Figure 23: Latency For Single Buffered Registers - Coarse Integration Time Example
write new settings

(Exp “B”)
frame n frame n+1 frame n+2
Two-wire
serial Interface idle idle
(Input)
FLASH Exp “A” Exp “A” Exp “B” Exp “B” Exp “B”
(Output)
FRAME_VALID
Readout Exp “A” Readout Exp “A” Readout Exp “B” Readout Exp “B” Readout Exp “B”
(Output)
frame-start frame-start new image available

activates new at output
settings (Exp “B”)
Figure 24: Latency For Double Buffered Registers - Column Gain Example
write new settings

(Col_Gain “A”)
Two-wire
(Input)
FLASH Exp “A” Exp “A” Exp “A” Exp “A” Exp “A”
(Output)
FRAME_VALID
Readout Exp “A” Readout Exp “A” Readout Exp “A” Readout Exp “A” Readout Exp “A”
(Output)
Readout frame contains

frame-start new Col_Gain setting
.

Features
Figure 25: Latency For Double Buffered Registers - Fine Integration Time Example
write new settings

(Fine Exp “B”)
frame n+3
Two-wire
(Input)
FLASH Fine Exp “A” Fine Exp “A” Fine Exp “A” Fine Exp “B” Fine Exp “B”
(Output)
FRAME_VALID
Readout Fine Exp “A” Readout Fine Exp “A” Readout Fine Exp “A” Readout Fine Exp “B” Readout Fine Exp “B”
(Output)
new image available

frame-start at output
Restart
To restart the AR0134 at any time during the operation of the sensor, write a “1” to the
Restart register (R0x301A[1] = 1). This has two effects: first, the current frame is read out
and the sensor enters standby. Second, any writes to frame-synchronized registers and
the shutter width registers take effect immediately, and a new frame starts. The current
frame completes before the new frame is started, so the time between issuing the Restart
and the beginning of the next frame is a maximum of tFRAME.
Temperature Sensor
The AR0134 sensor has a built-in PTAT-based (Proportional To Absolute Temperature)
temperature sensor, accessible through registers, that is capable of measuring die junc-
tion temperature. The temperature sensor can be enabled by writing R0x30B4[0]=1 and
R0x30B4[4]=1. After this, the temperature sensor output value can be read from
R0x30B2[10:0].
The value read out from the temperature sensor register is an ADC output value that
needs to be converted downstream to a final temperature value in degrees Celsius. Since
the PTAT device characteristic response is quite linear in the temperature range of oper-
ation required, a simple linear function as in Equation 37 can be used to convert the
ADC output value to the final temperature in degrees Celsius.
Temperature = slope × R0x30B2[10:0]+ T0 (EQ 37)
For this conversion, a minimum of 2 known points are needed to construct the line
formula by identifying the slope and y-intercept “T0”. These calibration values can be
read from registers R0x30C6 and R0x30C8 which correspond to values read at 70°C and
55°C respectively. Once read, the slope and y-intercept values can be calculated and
used in the above equation.
Example: What is the temperature in degrees Celsius when R0x30B2 = 0x1A2 (418)?
.

Features
For this particular sensor, the 70°C calibration data reads R0x30C6 = 0x01D2 (466), and
the 50°C calibration data reads R0x30C8 = 0x01BD (445). From these values, the correct
temperature reading can be found as follows:
Figure 26: Calculating Temperature Sensor Value
70
Temperature (C)
55
T0
R0x30C8 = 445 R0x30C6 = 466

Temp Sensor Values
slope = (70 - 55) / (466 - 445) = (15/21) = 0.714

From here, the intercept T0 can be found:
55 = (0.714) x (445) + T0
T0 = -262.73
Now, the temperature corresponding to a register reading of 0x1A2 can be determined:
Temperature = (0.714) x (418) - 262.73
Temperature = 35.7°C
For more information on the temperature sensor registers, refer to the AR0134 Register
Reference.
Auto Exposure
The integrated automatic exposure control (AEC) is responsible for ensuring that
optimal settings of exposure and gain are computed and updated every other frame.
AEC can be enabled or disabled by R0x3100[0]. When AEC is disabled (R0x3100[0] = 0),
the sensor uses the manual exposure value in the coarse and fine integration time regis-
ters and the manual gain value in the gain registers. When AEC is enabled
(R0x3100[0]=1), the target luma value is set by AE_LUMA_TARGET_REG (R0x3102). For
AR0134, this target luma has a default value of 0x0500. The luma target maximum auto
exposure value is limited by R0x311C; the minimum auto exposure is limited by
R0x311E. These values are in units of line-times. The minimum value for register 0x311E
is 1 line. The exposure control measures current scene luminosity by accumulating a
histogram of Gr pixel values while reading out a frame. It then compares the current
luminosity to the desired output luminosity. Finally, the appropriate adjustments are
made to the exposure time and gain.
.

Features
Auto Exposure Implementation

The AR0134 Auto Exposure control is implemented as three main blocks - AE Stats
Calculation, AE Target Selection, and an Exposure Control System. See Figure 27 for
details.
Figure 27: AE Block Diagram

12 bit im age (Gr pixels)
Se n so r D ig ita l Blo ck
AE Ta rg e t
AE STATS AE Statistics
Se le ctio n
Auto _ AG_ enable
M an_AG
T argetR atio
AG ae_enable
auto_ag_en
C urrent dark level auto_dg_en
Auto _D G_enable
Exp o su re C o n tro l m in_ana_gain
C urrent exposure tim e
A E U S E R IN TE R FA C E R E G IS T E RS (R/ W )
M an_D G Syste m
ae_roi_x_start_offset
DG ae_roi_x_size
ae_roi_y_start_offset
Auto_D G_gain ae_roi_y_size
Auto_AG_gain
ae_m ean_l
In te g ra tio n tim e ae_ag_exposure_hi

ae_ag_exposure_lo
ae_lum a_target_reg
ae_m in _ev _step_reg

ae_m ax_ev _step_reg
ae_dam p_offset_reg
A E s t at us m on ito r/d eb u g Re g is t ers (R on ly )
ae_dam p_gain_reg
ae_dam p_m ax_reg
ae_m ax_exposure_reg
ae_m in _exposure_reg
AR0134 Ou tp u t Im a g e ae_m ean_l
ae_dark_cur_thresh_reg
ae_dig_gain
ae_ana_gain
Footer: ae_coarse_integration_tim e
H isto g ra m
AE sta tu s m o n ito rin g \ d e b u g re g iste rs
.

Features
AE Embedded Statistics and Data

The AE Stats Calculation block (Figure 28) takes the user specified Region of Interest
(ROI) and creates a histogram of 64 evenly distributed bins from 0 to the maximum code
value of 4095 based on Gr pixels. If no ROI is specified, statistics are gathered from the
full output frame. From this histogram, all relevant auto exposure statistics are gener-
ated:
Figure 28: AE Stats Calculation Block
AE Stats AE Histogram
AE Histogram (for ROI)

12 bit image
Signal levels 0 to 212: 64 bins mean mean
Gr pixels
ROI selection
1.AE Histogram: 64 evenly spaced bins for digital code values 0 to 4095, If a ROI is speci-
fied, the histogram is populated only with Gr pixels which lie in the ROI.
2.mean: Mean code value of AE Histogram
The generation of statistics for use by off-chip AE algorithms must be enabled by setting
register R0x3064[7] = 1. Embedded statistics will not be output if this register is not set.
Embedded data may also be enabled by setting register R0x3064[8] = 1, but is not neces-
sary for statistics generation. To enable on-chip auto exposure, however, both
embedded stats and data must be enabled.
All the statistics data (including histogram data) is embedded in the two rows immedi-
ately following the image. The embedded statistics are output as shown in Figure 30. The
first line contains histogram data. Only histogram data for bins 0 to 63 are relevant -
higher bins will output all zeros. The second line contains statistics based on the histo-
gram for the current frame. The only relevant statistic for AR0134 auto exposure is the
mean. If the on-chip auto exposure is not used, it is recommended that auto exposure
algorithms be developed based on the histogram data found in line 1.
.

Features
Figure 29: Frame Format with Embedded Data Lines Enabled
Register Data
Image HBlank
Status & Statistics Data
VBlank
Figure 30: Embedded Statistics Format
The embedded data contains the configuration of the image being displayed, and is
found in the first two rows of the image. This includes all register settings used to capture
the current frame. The registers embedded in these rows are as follows:
Line 1: Registers R0x3000 to R0x312F
Line 2: Registers R0x3136 to R0x31BF, R0x31D0 to R0x31FF
Only values for registers found in the Register Reference document are relevant. The
format of the embedded register data transmission is as follows. In parallel mode, since
the pixel word depth is 12 bits/pixel, the sensor's 16-bit register data will be transferred
.

Features
over 2 pixels where the register data will be broken up into 8msb and 8 LSB. The align-
ment of the 8-bit data will be on the 8 MSB bits of the 12-bit pixel word. For example, if a
register value of 0x1234 is to be transmitted, it will be transmitted over two 12-bit pixels
as follows: 0x120, 0x340. The 10-bit histogram data is not broken up and is output msb
aligned over the 12 bit parallel interface and padded with zeros.
AE Target Selection
The Exposure Target Selection block determines a ratio based on the mean value of the
generated histogram of the current frame, and the target mean value as specified by the
user (R0x3102). This ratio allows the Control System to determine how much and in
what direction to adjust the exposure relative to the current exposure value.
The mean target ratio (TargetRatio) is the exposure change, expressed as a ratio, to move
the current image mean (CurrentMean) to a user-specified mean target (TargetMean).
See the “Exposure Control System” section and Figure 31 for more information.
Exposure Control System

The Exposure Control System outputs the new integration time along with a damping
factor to prevent too rapid of a response. If enabled, analog and digital gains will be
selected as well. The Control System will also monitor the dark current. If the Exposure
Target Selection block indicates that the exposure should be increased, but the dark
current exceeds a user specified threshold, the Control System will maintain the current
integration time. The automatic digital and analog gains and exposure limits enclosed
by the dashed line in Figure 31 is illustrated in more detail in Figure 33 on page 45 and
described in “Controlling Auto Exposure” on page 43.
.

Features
Figure 31: Exposure Control System
ae_luma_target (0x3102) TargetRatio

ae_mean_l (0x3152) (TargetMean/CurrentMean) Current dark level Current exposure time
EVNewExp =log2(TargetRatio)
ae_damp_offset_reg
(0x310C) RecursiveDamp =
ae_damp_gain_reg dampOffset + abs(EVNewExp)*dampGain
(0x310E)
ae_damp_max_reg Limit to less than

(0x3110) RecursiveDamp_Max
EVNewExp_damped =
RecursiveDamp*EVNewExp
ae_min_ev_step_reg
Limit abs(EVNewExp_damped)
(0x3108)
to between Max_EV_stepsize and
ae_max_ev_step_reg Min_EV_stepsize
(0x310A)
See
SeeFigure
Figure 6 29.
NewExpRatio>1
and Dark Current >
NewExp =
NewExpRatio = 2EVNewExp_damped DarkCurrentThresh No
NewExpRatio*currentExpTime
ae_dark_cur_thresh_reg
(0x3124)
Yes
ae_max_exposure_reg
(0x311C) Set Max Integration
New integration time Time
= current integration
time
(no change in
exposure)
auto_ag_en (0x3100[1]) ae_ana_gain

(0x312A[9:8])
ae_ag_exposure_hi (0x3166) Analog Gain
Digital Gain
ae_ag_exposure_lo (0x3168) Control Logic ae_dig_gain
auto_dg_en (0x3100[4]) (0x312A[7:0])
ae_min_exposure_reg (0x311E)
Limit new integration time to between Max_int_time and Min_int_time
ae_max_exposure_reg (0x311C)
New integration time

ae_coarse_integration_time
(0x3164)
Values found here are described in Table 15 on page 43.
.

Features
Table 15: Exposure Control Variables
Internal Value Description

EVNewExp Target ratio translated into EV units (stops). Can be positive or negative. In
EV units, >0 means exposure is increasing, <0 means exposure is
decreasing.
RecursiveDamp Damping factor. Should be >0 and <1 for desirable AE operation. If less than
0, AE will step further from the target; if greater than 1, AE will overstep
the target.
EVNewExp_damped New exposure step in EV units. Can be positive or negative.
NewExpRatio New exposure step as ratio. Should be positive. As ratio, >1 means
exposure is increasing, <1 means exposure is decreasing.
NewExp New exposure expressed as rows of integration or possibly msec (depends
on rest of system).
Auto Exposure Control
Enabling Auto Exposure

Several registers are used to enable various features of the automatic exposure control.
The auto exposure block is enabled or disabled by register R0x3100[0]. By default, the
AEC will only modify the coarse integration time to reach the target exposure. If enabled,
analog and digital gains may be adjusted as well. Analog gain adjustment is enabled by
setting auto_ag_en (R0x3100[1] = 1), and digital gain adjustment is enabled by setting
auto_dg_en (R0x3100[4] = 1). A minimum column gain (1x, 2x, 4x, 8x), min_ana_gain,
may be defined in register R0x3100[6:5]. Digital gain may be adjusted from 1x to 7.97x. A
summary of AEC enable registers is listed in Table 16.
Table 16: AE Enable Registers
Register Name Function

0x3100[0] ae_enable 0: On-chip AE disabled
1: On-chip AE enabled
0x3100[1] auto_ag_en 0: AE will not control analog gain
1: AE will control analog gain
0x3100[4] auto_dg_en 0: AE will not control digital gain
1: AE will control digital gain
0x3100[6:5] min_ana_gain Minimum analog gain to be used by AE
00: 1x (default)
01: 2x
10: 4x
11: 8x
Controlling Auto Exposure

The histogram is generated and statistics calculated based on the Gr pixels within a user
specified region of interest. The ROI is specified by four programmable register values -
ae_roi_x_start_offset, ae_roi_y_start_offset, ae_roi_x_size and ae_roi_y_size. The
ae_roi_x_start_offset and ae_roi_y_start_offset values define the starting coordinate of
the ROI with respect to the image window that is output and the ae_roi_x_size and
ae_roi_y_size values define the dimensions of the ROI. Each value must be an even
number. If the requested ROI extends 'beyond' the image window then it will be
restricted in size such that the final pixel of the ROI will be the final pixel of the image
window, as illustrated in Figure 32
.

Features
Figure 32: Selecting the ROI
The target luma value may be set in the ae_luma_target_reg register. The AE Target
Selection block will use this value to determine the target ratio provided to the Exposure
Control System as illustrated in Figure 31 on page 42. The exposure range can be limited
by setting values for ae_max_exposure_reg and ae_min_exposure_reg. The integration
time fed back to the Sensor Digital Block (see Figure 27 on page 38) will not fall outside
of this specified range.
To extend the exposure range, the AE logic can also automatically adjust analog gain and
digital gain. The controls for enabling automatic analog and digital gain selection may
be found in Table 16 on page 43. The control flow chart is shown in Figure 33 and is an
expanded view of the portion of Figure 31 on page 42 that is enclosed by the dashed line.
.

Features
Figure 33: Automatic Gain Control
New_Exposure_Time =
Current_Exposure_Time*
NewExpRatio
Yes
No
NewExpRatio>1
Yes Current_DG
=1
No
DG=
Current_DG*
NewExpRatio
No
DG<1
DG=1
No AG>
Min_AG
Yes
No New Exposure Time
> AG_Hi_thresh
New Exposure Time No
< AG_Lo_thresh Yes
Yes
AG=3
Yes
or
New_Exposure_Time = Auto AG disabled
New_Exposure_Time *
AG_gain_factor
No
AG=AG-1
New_Exposure_Time =
New_Exposure_Time /
AG_gain_factor
AG=AG+1
No Current_exposure_time
=Max_int_time
Yes
DG=
New_exposure_ratio*
Current_DG
Output New_Exposure_Time, AG, DG

END
.

Features
If auto_ag_en is set, the automatic adjustment of analog gains may be restricted based
on integration time. By setting a value for ae_ag_exposure_hi, the analog gain will not be
increased until the integration time set by this register is reached. Similarly, the analog
gain will not be decreased unless the integration time is reduced below the value set in
ae_ag_exposure_lo. To avoid oscillation, the ae_ag_exposure_lo setting should be lower
than the ae_ag_exposure_hi setting. Refer to Table 17 on page 47 for auto exposure
control registers.
The integration time and analog gain selected by the exposure control system may be
found in the ae_coarse_integration_time (R0x3164) and ae_ana_gain(R0x312A[9:8])
registers, respectively. The minimum analog gain to be selected may be set in the
min_ana_gain (R0x3100[6:5]) register, and can be 1x, 2x, 4x, or 8x. If auto_dg_en
(R0x3100[4]) is set, the digital gain selected by the exposure control system can be read
from register ae_dig_gain (R0x312A[7:0]). The digital gain can vary from 1 to 7.97. The
minimum step is 1/32.
The step size of the AE control may be configured. Both a minimum and maximum step
size may be set in units of EV (exposure value) steps in registers 0x3108 and 0x310A,
respectively. The step size represents the minimum or maximum value that the AE
Target Selection will use for the next exposure value. It does not represent the incre-
mental change from frame to frame. The selected new exposure value will be clipped to
the minimum EV step if it is less than the value specified in R0x3108. Because the
minimum step size in EV units is typically a small number less than one, it should be
scaled by 256 before setting the register value.
Changes in exposure are smoothed based on damping parameters. A maximum
damping value may be specified in R0x3110. Additional damping controls include
ae_damp_gain_reg and ae_damp_offset_reg. These can be thought of as a coarse and
fine damping control, respectively.
At high temperature, the sensor may have high dark current which will increase with
longer exposures. To avoid increasing the exposure when there is excessive dark current,
AE has a dark current check. The sensor supplies the current dark current level to AE and
if the dark current is greater than the user-specified (R0x3124) darkCurrentThresh, AE
does not increase exposure.
If (NewExpRatio > 1) & (DarkCurrent > DarkCurrentThresh)

NewExpRatio = 1; //Do not increase exposure
End
.

Features
Table 17: Auto Exposure Control Registers
Register Name Function

0x3140 ae_roi_x_start_offset Number of pixels into each row before the ROI starts
0x3142 ae_roi_y_start_offset Number of rows into each frame before the ROI starts
0x3144 ae_roi_x_size Number of columns in the ROI
0x3146 ae_roi_y_size Number of rows in the ROI
0x3102 ae_luma_target_reg Average luma target value to be reached by the auto exposure
0x3108 ae_min_ev_step_reg Minimum exposure value step size. Since min_ev_step sizes are
small (typically less than 1), they are multiplied by 256 and then the
value is written to this register.
0x310A ae_max_ev_step_reg Maximum exposure value step size. Since this value is always greater
than 1 there is no need to multiply by 256 as in the case of
min_EV_stepsize.
0x310C ae_damp_offset_reg Adjusts step size and settling speed.
0x310E ae_damp_gain_reg Adjusts step size and settling speed.
0x3110 ae_damp_max_reg Max value allowed for damping (multiplied by 256 since internal
value is typically <1). For most applications, the value of damping
should be <1, otherwise AE will overshoot the target. For
applications with fast settling required, it may be desirable to allow
damping >1. Default value: 0.875 * 256 = 0x00E0
0x311C ae_max_exposure_reg Maximum integration (exposure) time in rows to be used by AE.
0x311E ae_min_exposure_reg Minimum integration (exposure) time in rows to be used by AE.
0x3166 ae_ag_exposure_hi At this integration time, the analog gain is increased (when AE is
enabled to control analog gain).
0x3168 ae_ag_exposure_lo At this integration time, the analog gain is reduced (when AE is
enabled to control analog gain).
0x3124 ae_dark_cur_thresh_reg The dark current level that stops AE from increasing integration time.
Note that increased integration time would increase dark current as
well and signal level (SNR) would drop because photo diode well
capacity is limited.
.

Features
AE Frame Synchronization
A delay is incurred between the time when a frame with the newly updated AE value
applied is seen by the AE module and when it reaches the sensor core logic (which sets
the exposure times for the sensor). This delay is associated with the Delay Buffers and
Sensor Data Path delays. The AE module will perform its calculations during the vertical
blanking time and the new exposure value will be seen by the sensor core logic after the
next frame has started. Therefore the result is that the third frame after the current frame
will reflect the new exposure time. Figure 34 illustrates how the exposure changes every
two frames.
Figure 34: AE Frame Synchronization

p
T0 T1 T2
E xposure changes every 2 frames
N- n
row s T0 T0 T1 T1 T2
n row s T0( S tats) T1( S tats) T2( S tats)
V B LA N K S et T1 S et T2 S et T3
row s
N = total number of active pixel

row s
n = number of row s required to Output Output Output Output
compute A E stats Frame Frame Frame Frame
E xp = T 0 E xp = T 1 E xp = T 1 E xp = T 2
V B LA N K = vertical blank row s
.

Features
Gain
Digital Gain
Digital gain can be controlled globally by R0x305E (Context A) or R0x30C4 (Context B).
There are also registers that allow individual control over each Bayer color channel:
GreenR R0x3056
GreenB R0x305C
Red R0x305A
Blue R0x3058
The format for digital gain setting is xxx.yyyyy where 0b00100000 represents a 1x gain
setting and 0b00110000 represents a 1.5x gain setting. The step size for yyyyy is 0.03125
while the step size for xxx is 1. Therefore to set a gain of 2.09375 one would set digital
gain to 01000011. The maximum digital gain is 7.97x.
Column Gain
The AR0134 has a column parallel architecture and therefore has an analog gain stage
per column. The column (analog) gain can be set to 1x, 2x, 4x or 8x. This can be set in
R0x30B0[5:4](Context A) or R0x30B0[9:8] (Context B).
Black Level Correction

Black level correction is handled automatically by the image sensor. No adjustments are
provided except to enable or disable this feature. Setting R0x30EA[15] disables the auto-
matic black level correction. Default setting is for automatic black level calibration to be
enabled.
The automatic black level correction measures the average value of pixels from a set of
optically black lines in the image sensor. The pixels are averaged as if they were light-
sensitive and passed through the appropriate gain. This line average is then digitally
low-pass filtered over many frames to remove temporal noise and random instabilities
associated with this measurement. The new filtered average is then compared to a
minimum acceptable level, low threshold, and a maximum acceptable level, high
threshold. If the average is lower than the minimum acceptable level, the offset correc-
tion value is increased by a predetermined amount. If it is above the maximum level, the
offset correction value is decreased by a predetermined amount. The high and low
thresholds have been calculated to avoid oscillation of the black level from below to
above the targeted black level.
Row-wise Noise Correction

Row (Line)-wise Noise Correction is handled automatically by the image sensor. No
adjustments are provided except to enable or disable this feature. Clearing R0x3044[10]
disables the row noise correction. Default setting is for row noise correction to be
enabled.
Row-wise noise correction is performed by calculating an average from a set of optically
black pixels at the start of each line and then applying each average to all the active
pixels of the line.
.

Features
Column Correction
The AR0134 uses a column parallel readout architecture to achieve fast frame rates.
Without any corrections, the consequence of this architecture is that different column
signal paths have slightly different offsets that might show up on the final image as
structured fixed pattern noise.
The AR0134 has column correction circuitry that measures this offset and removes it
from the image before output. This is done by sampling dark rows containing tied pixels
and measuring an offset coefficient per column to be corrected later in the signal path.
Column correction can be enabled/disabled via R0x30D4[15]. Additionally, the number
of rows used for this offset coefficient measurement is set in R0x30D4[3:0]. By default
this register is set to 0x7, which means that 8 rows are used. This is the recommended
value. Other control features regarding column correction can be viewed in the AR0134
Register reference. Any changes to column correction settings need to be done when the
sensor streaming is disabled and the appropriate triggering sequence must be followed
as described below.
Column Correction Triggering

Column correction requires a special procedure to trigger depending on which state the
sensor is in.
Column Triggering on Startup

When streaming the sensor for the first time after powerup, a special sequence needs to
be followed to make sure that the column correction coefficients are internally calcu-
lated properly.
1. Follow proper power up sequence for power supplies and clocks.
2. Apply sequencer settings.
3. Apply frame timing and PLL settings as required by application.
4. Set analog and digital gains to 1x.
5. Enable column correction and settings (R0x30D4 = 0xE007).
6. Enable streaming (R0x301A[2]=1)or drive the TRIGGER pin HIGH.
7. Wait 8 frames to settle.
8. Disable streaming (R0x301A[2]=0) or drive the TRIGGER pin LOW.
After this, the sensor has calculated the proper column correction coefficients and the
sensor is ready for streaming. Any other settings (including gain, integration time, etc.)
can be done afterwards without affecting column correction.
Column Correction Retriggering Due to Mode Change

Since column offsets are sensitive to changes in the analog signal path, such changes
require column correction circuitry to be retriggered for the new path. Examples of such
mode changes include: horizontal mirror, vertical flip, changes to column correction
settings.
When such changes take place, the following sequence needs to take place:
1. Disable streaming (R0x301A[2]=0) or drive the TRIGGER pin LOW.
2. Enable streaming (R0x301A[2]=1) or drive the TRIGGER pin HIGH.
3. Wait 9 frames to settle.
Note: The above steps are not needed if the sensor is being reset (soft or hard reset) upon
the mode change.
.

Features
Test Patterns
The AR0134 has the capability of injecting a number of test patterns into the top of the
datapath to debug the digital logic. With one of the test patterns activated, any of the
datapath functions can be enabled to exercise it in a deterministic fashion. Test patterns
are selected by test_pattern_mode register (R0x3070). Only one of the test patterns can
be enabled at a given point in time by setting the test_pattern_mode register according
to Table 18. When test patterns are enabled the active area will receive the value speci-
fied by the selected test pattern and the dark pixels will receive the value in test_pat-
tern_green (R0x3074 and R0x3078) for green pixels, test_pattern_blue (R0x3076) for blue
pixels, and test_pattern_red (R0x3072) for red pixels.
Table 18: Test Pattern Modes
Test_Pattern_Mode Test Pattern Output

0 No test pattern (normal operation)
1 Solid color test pattern
2 100% color bar test pattern
3 Fade-to-grey color bar test pattern
256 Walking 1s test pattern (12-bit)
Color Field
When the color field mode is selected, the value for each pixel is determined by its color.
Green pixels will receive the value in test_pattern_green, red pixels will receive the value
in test_pattern_red, and blue pixels will receive the value in test_pattern_blue. See
Figure 35 for a solid green pattern with Gr = Gb = 3072.
Figure 35: Solid Color
Vertical Color Bars

When the vertical color bars mode is selected, a typical color bar pattern will be sent
through the digital pipeline. See Figure 36:
.

Features
Figure 36: Vertical Color Bars
Walking 1s
When the walking 1s mode is selected, a walking 1s pattern will be sent through the
digital pipeline. The first value in each row is 1. See Figure 37:
Figure 37: Walking 1s
.

Two-Wire Serial Interface CRC

AR0134 includes a means of validating two-wire serial interface communications. The
AR0134 confirms that all two-wire serial interface write requests to the device are
successful by means of a checksum, generated from all address and data values associ-
ated with such transactions.
These requirements are interpreted as follows:
• For all two-wire serial interface writes to the camera the 16-bit register address and 2
bytes of data are fed into a 16-bit CRC to generate a checksum.
• That checksum is stored in a two-wire serial interface accessible register at address
0x31D6.
• The checksum can be read via two-wire serial interface and will also be output in the
embedded registers (if enabled).
• A write via two-wire serial interface to the checksum register will reset the checksum
to the start value of 0xFFFF.
.

Figure 38: Checksum Generation Flow Within the Sensor
Two-wire serial interface

required for this device?
Yes
Addressing
Write or Read? Read Yes Read back checksum.
checksum register?
Write
Addressing Reset checksum

Yes
checksum register? (to all 1s)
Input 16-bit
address to CRC
Input 16-bit data

value to CRC
The 16-bit value will be input to the CRC MSB first, i.e., b15 through b0. The CRC used
will implement the polynomial x16 + x12 + x5 + 1, as illustrated inFigure 39 on page 55.
.

Figure 39: Definition of 16-bit CRC Shift Register
The recommended procedure to use CRC checksum as follows:

Step 1: Reset CRC checksum register(R0x31D6) by writing R0x31D6 with any value to
reset CRC checksum register before write two-wire serial interface write command.
Step 2: Conduct two-wire serial interface write command to a desired register
Step3: Read CRC checksum register (R0x31D6) to verify that two-wire serial interface
write command was done successfully by comparing the read CRC checksum
register(R0x31D6) with a expected CRC checksum value.
Step4: Go back to step 1.
Reset CRC checksum

R0x31D6 = 0x1234
Conduct
Try current Go to next 2-wire serial IF write
2-wire serial IF write 2-wire serial IF write R0x301A = 0x0058
transaction again transaction
CRC checksum
matches
CRC checksum
does not match
Read R0x31D6
to verify 2-wire serial
IF transaction by
checking CRC
checksum
.

Two-Wire Serial Interface Sequential Writes

The input to the 16-bit CRC logic is either a 16-bit address or a 16-bit write data value. If
the 16-bit address matches the CRC register, the CRC register is initialized to all ones.
Otherwise, the 16-bit write data value is input (serially) into the CRC generator, and a 16-
bit CRC value results unique to that 16-bit write data value. Sequentially, either CRC
address or other addressed data values are presented to the CRC generator and resulting
CRC register. At the end of a sequential write of addresses with 16-bit address data
values, the CRC register contains the CRC value of sequentially processed write data
values that were sequentially addressed.
Note, if the two-wire serial interface write is only 8-bits to a single register address, that
write is serviced by reading the pair of 8-bit addresses addressed by the 15 MSBs of the
8-bit address, and the 8-bit write data value that is being modified is combined with the
8-bit data address value NOT being modified, and the resulting 16-bits is input into the
CRC for that 8-bit address.
In summary, the CRC checksum(R0x31D6) continues to update, as all non-CRC registers
are written. At any time, if CRC register is read, the current CRC register value is read
back. At any time, if CRC register is written (with any value), the CRC register is initial-
ized to all ones.
Reading the Sensor CRA and Chromaticity

Follow the steps below to obtain the CRA value of the Image Sensor:
1. Set the register bit field R0x301A[5] = 1.
2. Read the register bit fields R0x31FA[11:8].
3. Determine the CRA value according to Table 19.
Table 19: CRA Value
Hex Value of R0x31FA[11:8] CRA Value Chromaticity

0x01 0 Mono
0x1 0 Mono
0x2 25 Mono
0x3 25 Mono
0x4 0 Color
0x5 0 Color
.

Revision History
Revision History
Rev. C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6/13/14
• Updated corporate address on last page
• Updated “Blanking Control” on page 6
• Updated Figure 7: “HiSPi Transmitter and Receiver Interface Block Diagram,” on
page 12
• Updated Figure 9: “Block Diagram of DLL Timing Adjustment,” on page 13
• Updated Table 5, “Exposure Timing,” on page 20
• Updated“Exposure and Data Synchronization Outputs” on page 22
• Updated“TRIGGER Input Restrictions” on page 22
• Updated“Blanking Control” on page 29
• Updated Figure 23: “Latency For Single Buffered Registers - Coarse Integration Time
Example,” on page 35
• Added Figure 24: “Latency For Double Buffered Registers - Column Gain Example,” on
page 35
• Updated Figure 25: “Latency For Double Buffered Registers - Fine Integration Time
Example,” on page 36
• Added “Two-Wire Serial Interface CRC” on page 53
• Updated Figure 38: “Checksum Generation Flow Within the Sensor,” on page 54
• Added “Reading the Sensor CRA and Chromaticity” on page 56
Rev. B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6/11/13
• Updated to Production
• Updated Table 4, “Real-Time Context-Switchable Registers,” on page 17
• Updated “Frame Rate” on page 6
• Added Figure 9: “Block Diagram of DLL Timing Adjustment,” on page 13
• Updated “Exposure” on page 16
• Updated Table 4, “Real-Time Context-Switchable Registers,” on page 17
• Updated “Operation Details” and changed title to “Triggered System Details” on
page 19
• Updated “Trigger Mode” on page 19
• Updated last paragraph of “Duration of Exposure” on page 21 (including Equation 8
on page 21
• Updated “Exposure and Data Synchronization Outputs” on page 22
• Updated “TRIGGER Input Restrictions” on page 22
• Updated Table 7, “Example 1 (With Default Setting for Full Resolution),” on page 23
• Updated Equation 16 on page 23, Equation 21, Equation 22, Equation 23, and Equa-
tion 24 on page 24
• Updated “Reset” on page 26
• Updated “Hard Reset of Logic” on page 26
• Updated “Blanking Control” on page 29
• Moved Figure 23, Latency For Single Buffered Registers - Coarse Integration Time
Example and Figure 24, Latency For Double Buffered Registers - Column Gain
Example to page 35
• Updated “Restart” on page 36
• Moved Figure 29, Frame Format with Embedded Data Lines Enabled to page 40
• Moved section on Two-wire Serial Register Interface to the data sheet.
.

Revision History
Rev. A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1/23/13
• Initial release
180 Clemenceau Avenue, #05-02/04 Haw Par Centre, Singapore 239922 prodmktg@aptina.com www.aptina.com
Aptina, Aptina Imaging, and the Aptina logo are the property of Aptina Imaging Corporation
All other trademarks are the property of their respective owners.
.
AR0134_DG - Rev. C Pub 6/14 EN 58 ©2013 Aptina Imaging Corporation All rights reserved.

1/3-Inch CMOS Digital Image Sensor: AR0134 Developer Guide, Rev. C

Uploaded by

Copyright:

Available Formats

1/3-Inch CMOS Digital Image Sensor: AR0134 Developer Guide, Rev. C

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

1/3-Inch CMOS Digital Image Sensor: AR0134 Developer Guide, Rev. C

Uploaded by

Copyright:

Available Formats

Aptina Confidential and Proprietary

AR0134: Developer Guide