Last Time Buy: 16-Bit Serial Input, Constant-Current Latched LED Driver
Last Time Buy: 16-Bit Serial Input, Constant-Current Latched LED Driver
Last Time Buy: 16-Bit Serial Input, Constant-Current Latched LED Driver
Deadline for receipt of LAST TIME BUY orders: April 30, 2011
Recommended Substitutions:
For existing customer transition, and for new customers or new appli-
cations, contact Allegro Sales.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, revisions to the anticipated product life cycle plan
for a product to accommodate changes in production capabilities, alternative product availabilities, or market demand. The
information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no respon-
sibility for its use; nor for any infringements of patents or other rights of third parties which may result from its use.
A6276
16-Bit Serial Input, Constant-Current
Latched LED Driver
Features and Benefits Description
▪ Up to 90 mA constant-current outputs The A6276 is specifically designed for LED-display
▪ Undervoltage lockout applications. Each BiCMOS device includes a 16-bit CMOS
▪ Low-power CMOS logic and latches shift register, accompanying data latches, and 16 NPN constant-
▪ High data input rate current sink drivers. Except for package style and allowable
▪ Functional replacement for TB62706BN/BF package power dissipation, the device options are identical.
The CMOS shift register and latches allow direct interfacing
with microprocessor-based systems. With a 5 V logic supply,
typical serial data-input rates are up to 20 MHz. The LED drive
current is determined by the user selection of a single resistor.
Packages A CMOS serial data output permits cascaded connections in
applications requiring additional drive lines. For inter-digit
blanking, all output drivers can be disabled with an ENABLE
24-pin DIP input high. Similar 8-bit devices are available as the A6275.
(A package) Two package styles are provided: through-hole DIP (suffix A)
and surface-mount SOIC (suffix LW). In normal applications,
the copper leadframe and low logic-power dissipation of the
24-pin SOICW DIP allow it to sink maximum rated current through all outputs
(LW package) continuously over the operating temperature range (90 mA,
0.75 V drop, 85°C). Both packages are lead (Pb) free, with
100% matte tin leadframe plating.
Not to scale
26185.201I
16-Bit Serial Input, Constant-Current
A6276
Latched LED Driver
Selection Guide
Ambient
Part Number Package Packing
Temperature (°C)
A6276EA-T 24-pin DIP 15 per tube –40 to 85
A6276ELWTR-T 24-pin SOICW 1000 per reel –40 to 85
Thermal Characteristics may require derating at maximum conditions, see application information
Characteristic Symbol Test Conditions* Value Units
Package A, 1-layer PCB based on JEDEC standard 50 ºC/W
Package Thermal Resistance RθJA
Package LW, 1-layer PCB based on JEDEC standard 85 ºC/W
4.0
3.5
ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS
3.0
24-PIN DIP, RQJA = 50°C/W
2.5
24-LEAD SOIC, RQJA = 85°C/W
2.0
1.5
1.0
0.5
0
25 50 75 100 125 150
AMBIENT TEMPERATURE IN ° C
*Mounted on single-layer, two-sided PCB, with 3.8 in2 copper each side;
additional information on Allegro Web site
Pin-out Diagram
(A and LW packages)
V DD LOGIC
GROUND 1 24
SUPPLY
SERIAL IO
2 23 R EXT
DATA IN REGULATOR
SERIAL
CLOCK 3 CK 22 DATA OUT
LATCH 4 L OE 21 OUTPUT
ENABLE ENABLE
REGISTER
OUT 0 5 LATCHES 20 OUT 15
OUT 1 6 19 OUT 14
OUT 2 7 18 OUT 13
OUT 3 8 17 OUT 12
OUT 4 9 16 OUT 11
OUT 5 10 15 OUT 10
OUT 6 11 14 OUT 9
OUT 7 12 13 OUT 8
Terminal Description
V DD
V DD
IN IN
V DD V DD
IN OUT
Dwg. EP-063-6
Dwg. EP-010-13
TRUTH TABLE
Serial Shift Register Contents Serial Latch Latch Contents Output Output Contents
Data Clock Data Enable Enable
Input Input I1 I2 I3 ... IN-1 IN Output Input I1 I2 I3 ... IN-1 IN Input I1 I2 I3 ... IN-1 IN
X R1 R2 R3 ... RN-1 RN RN
X X X ... X X H H H H ... H H
L = Low Logic (Voltage) Level H = High Logic (Voltage) Level X = Irrelevant P = Present State R = Previous State
Limits
Limits
CLOCK 50%
A B
tp
D E
LATCH
50%
ENABLE
OUTPUT
ENABLE LOW = ALL OUTPUTS ENABLED
90%
50%
NOTE: Timing is representative of a 10 MHz clock. Sig-
OUT N DATA
t pHL 10% nificantly higher speeds are attainable.
Max. Clock Transition Time, tr or tf ....................... 10 μs
Dwg. WP-030-1A
Serial data present at the input is transferred to the shift long as the LATCH ENABLE is held high. Applications where
register on the logic 0-to-logic 1 transition of the CLOCK input the latches are bypassed (LATCH ENABLE tied high) will
pulse. On succeeding CLOCK pulses, the registers shift data in- require that the OUTPUT ENABLE input be high during serial
formation towards the SERIAL DATA OUTPUT. The serial data data entry.
must appear at the input prior to the rising edge of the CLOCK When the OUTPUT ENABLE input is high, the output sink
input waveform. drivers are disabled (OFF). The information stored in the latches
Information present at any register is transferred to the is not affected by the OUTPUT ENABLE input. With the OUT-
respective latch when the LATCH ENABLE is high (serial-to- PUT ENABLE input low, the outputs are controlled by the state
parallel conversion). The latches continue to accept new data as of their respective latches.
60 60
VCE = 3 V
VCE = 4 V
VCE = 4 V
40 40
TA = +25oC TA = +25oC
20 VDD = 5 V 20 VDD = 5 V
RQJA = 50oC/W RQJA = 75oC/W
0 0
0 20 40 60 80 100 0 20 40 60 80 100
100 100
VCE = 1 V VCE = 0.7 V
ALLOWABLE OUTPUT CURRENT IN mA/BIT
ALLOWABLE OUTPUT CURRENT IN mA/BIT
80 80
VCE = 2 V VCE = 1 V
VCE = 3 V
60 VCE = 2 V
60
VCE = 3 V
VCE = 4 V
40 40
VCE = 4 V
TA = +50oC TA = +50oC
20 VDD = 5 V 20 VDD = 5 V
RQJA = 50oC/W RQJA = 75oC/W
0 0
0 20 40 60 80 100 0 20 40 60 80 100
DUTY CYCLE IN PER CENT DUTY CYCLE IN PER CENT
Dwg. GP-062-10 Dwg. GP-062-7
80 VCE = 1 V 80
VCE = 0.7 V
VCE = 1 V
60 VCE = 2 V 60
VCE = 3 V VCE = 2 V
VCE = 3 V
40 40
VCE = 4 V
VCE = 4 V
TA = +85oC TA = +85oC
VDD = 5 V 20 VDD = 5 V
20
RQJA = 50oC/W RQJA = 75oC/W
0 0
0 20 40 60 80 100 0 20 40 60 80 100
TYPICAL CHARACTERISTICS
60
OUTPUT CURRENT IN mA/BIT
40
20 TA = +25oC
REXT = 500 7
0
0 0.5 1.0 1.5 2.0
VCE IN VOLTS
Dwg. GP-063
Applications Information
The load current per bit (IO) is set by the external resistor diode (VZ), or a series string of diodes (approximately
(REXT) as shown in the figure below. 0.7 V per diode) for a group of drivers. If the available
voltage source will cause unacceptable dissipation and
100
series resistors or diode(s) are undesirable, a regulator
such as the Sanken Series SAI or Series SI can be used to
80
V CE = 0.7 V
provide supply voltages as low as 3.3 V.
For reference, typical LED forward voltages are:
White 3.5 – 4.0 V
60
Blue 3.0 – 4.0 V
Green 1.8 – 2.2 V
40 Yellow 2.0 – 2.1 V
Amber 1.9 – 2.65 V
Red 1.6 – 2.25 V
20 Infrared 1.2 – 1.5 V
Pattern Layout. This device has a common logic-ground
0 and power-ground terminal. If ground pattern layout
2k 3k 5k
100 200 300 500 700 1k
contains large common-mode resistance, and the voltage
CURRENT-CONTROL RESISTANCE, R EXT IN OHMS
Dwg. GP-061
between the system ground and the LATCH ENABLE or
Package Power Dissipation (PD). The maximum al- CLOCK terminals exceeds 2.5 V (because of switching
lowable package power dissipation is determined as noise), these devices may not operate correctly.
PD(max) = (150 - TA)/RJA.
The actual package power dissipation is
PD(act) = DC • (VCE • IO • 16) + (VDD • IDD) ,
V
where DC is the duty cycle. LED
24
+0.10
0.38 –0.05
+0.76 +0.38
6.35 –0.25 10.92 –0.25 7.62
1 2
+0.25
1.52 –0.38
0.018
0.46 ±0.12
15.40±0.20
4° ±4 24
24
+0.07 2.20
0.27 –0.06
A
+0.44
0.84 –0.43
1 2
1 2 0.65
1.27
0.25