AND8182/D

100 Watt Universal Input

PFC Boost Using NCP1601A

Prepared by: Kahou Wong

ON Semiconductor

INTRODUCTION

This application note presents a Power Factor Correction (PFC) boost regulator example circuit
using NCP1601A in Figure 1 with the design steps and measurement. The measurement shows
that the circuit has a greater than 0.9 Power Factor under the universal input (85 to 265 Vac).
The NCP1601A is one of the latest ON Semiconductor low−power PFC products which can
operate in both Discontinuous Conduction Mode (DCM) and Critical Mode (CRM). The DCM
feature limits the maximum switching frequency for easier front−ended EMI filter design and
the CRM feature limits the current stress on inductor, MOSFET and diode for better cost, size,
and reliability.

Figure 1. Application Schematic of the Example Circuit Common low−power PFC method is
usually presented in Critical Mode (CRM) which is with changing switching frequency. The CRM
switching frequency can become dramatically very high at the zero−crossing moment of the
sinusoidal waveform. Sometimes, the high switching frequency makes CRM not desirable due
to EMI problem.

However, CRM has an advantage over fixed−frequency DCM for lower peak current which is
important so that CRM is preferable in the high current stress moment. As a result, the
NCP1601 is developed to have both DCM and CRM.

The converter using NCP1601 is intended to operate in CRM in the most stressful moment and
in DCM in the zero−crossing moment. The mode of operation of NCP1601 is summarized in
Figure 2.

DESIGN STEPS

Step 1. Define the Specifications

Table 1. Specifications

Input 85 Vac to 265 Vac, 50 Hz

Output 100 W, 390 Vdc

Switching frequency Around 100 kHz

The maximum overvoltage threshold is limited to 225 A which

Vout

200 1.95 M

390 V

Step 2. Bias Supply Design

A 1/2 W axial 150 k resistor is used to charge up the VCC capacitor in startup. The worst case
power dissipation on this resistor is 0.47 W which is smaller than 1/2 W.

Figure 3. Auxiliary Winding Bias Supply.

The auxiliary winding bias supply in Figure 3 is to provide a VCC bias voltage after startup. The
VCC needs to be higher than its minimum operating voltage VCC(off) (9 V typical).

When the PFC stage MOSFET is on, the primary winding is with a voltage Vin and the
secondary winding is with a voltage Vin / n. This voltage goes to capacitor C1. When the PFC
stage diode is on, the primary winding is with a voltage (Vout – Vin) and the secondary winding
is with a voltage (Vout – Vin) / n. This voltage goes to capacitor C2. As a result, the VCC biasing
voltage will be Vout / n which is almost constant and independent of the 50 Hz variation of the
input voltage.

Hence, the auxiliary winding turn ratio n is selected as 25:1 so that VCC is 15.6 V.

A 470 F VCC capacitor is experimentally found to be enough

For protection purpose, a clamping Zener MZP4745A is added to prevent any unwanted
transient overvoltage damage.

It is noted that the circuit needs typical 11.4 sec to let the VCC capacitor reach the starting
threshold (13.75 typical) in the worst condition Vin = 85 Vac.

Step 3. Take an Assumption on Efficiency The efficiency h is usually assumed to be 90%. Then,
the input power Pin is 111 W. This input power will be frequently used in the next few design
steps.

Step 4. Calculate the Current Stress The worst case input current rating happens when input is
85 Vac. The input RMS current Iac is 1.31 Aac. The suffix ac denotes that it is RMS value. This
current stress is mainly on the front−ended rectifier.

The instantaneous maximum current stress in the PFC stage will be 3.7 A in critical mode.

This current stress affects the component selections on the current sense resistor, MOSFET,
diode, and inductor.
Step 5. Oscillator Capacitor Design

The switching frequency can be set by either oscillator mode or synchronization mode in the
NCP1601. In this application, it is set at oscillator mode. Figure 34 in the NCP1601 data sheet
shows that a 100 pF capacitor can set the frequency to 107 kHz. Actually, this frequency is only
valid for the DCM operation because CRM is with a lower switching frequency. However, this
frequency provides a reference on calculating the inductor for CRM in the next design step.

Step 6. Inductor Design

The minimum CRM inductance L(CRM) at low line is obtained as follows

The maximum value of L(CRM) is at low line. Hence, a value greater than L(CRM) can make the
circuit to operate in CRM. The inductor L is therefore set to be 230
H. The switching frequency is 99 kHz and it is in CRM.

Step 7. Ramp Capacitor Design

Maximum power can be obtained when Vcontrol = 1 V.

Worst case is at low line 85 Vac.

There is a typical 20 pF background capacitance on the ramp pin in the NCP1601. The Cramp is
selected to be as small as possible to limit the maximum power transfer.

Marginally, an external 680 pF capacitor is good enough for this application.

With this value of Cramp, the control voltage Vcontrol in high line and low line condition are
obtained.

In low line 85 Vac, Step 8. Check the Switching Periods to Ensure CRM in the Sinusoidal Peaks

In low line 85 Vac, the switching period (t1 + t2) and MOSFET on time (t1) are as followed.

In high line 265 Vac, the switching period (t1 + t2) and MOSFET on time (t1) are as followed.

As long as the switching period is larger than the DCM switching period T, the circuit operates
in CRM and the maximum current stress is minimized.

Step 9. Current Sense Resistors Design

The settings of current sense resistor RCS and sense resistor RS defines the zero current
threshold IL(ZCD) and overcurrent protection threshold IL(OCP) by the following two design
equations.

Because the IL(ZCD) has to be greater than zero, RS has to be greater than 535.7 which gives
IL(ZCD) > 0. When RS is very close to 535.7 (say RS = 536 ), IL(OCP) / IL(ZCD) = 26000 and
IL(ZCD) can be very small with a finite IL(OCP).

For example, if the maximum stress is 3.7 A, then RCS is 28 m and IL(ZCD) is 143
A.
However, tolerance exists in real world and the actual design can only be closed to this one.

When the value of RCS is 0.05 , its power dissipation Pd is 129 mW.

Step 10. Output Capacitor Design

The choice of output capacitance is usually dictated by the required hold−up time or the
acceptable output ripple voltage for a given application. As a rule of thumb, output
capacitance is generally set at 1 F/W. Hence, a 100 W
application needs 100 F output capacitance.

The hold−up time tHOLD which is the time a power supply needs to maintain its voltage with
the specified range after a dropout of the line voltage.

where Vout_min is the minimum value of the regulated output voltage at full load and
Vop_min is the minimum input voltage of the driven load of the PFC. Because there is no
particular specification on the hold−up time, this term is not further studied here.

The major output ripple component in a PFC circuit is usually its rectified line frequency
because it cannot be easily filtered out by inductors and capacitors. The CCM or DCM
operations mainly affect the switching frequency ripple which is always much smaller than the
rectified line frequency ripple and hence generally neglected.

The low frequency output stage of a PFC stage can be simplified into Figure 4. The line
frequency current source is a rectified sinusoidal (if only low frequency is considered) and its
rms value Iout(rms) is simply Pout/Vout. Hence, peak−to−peak value Iout(pk−pk) is as follow:

Now that the capacitor is the only energy storage media in the circuit in Figure 4 and the
discharging time is one−fourth of the line frequency as shown in Figure 5.

Hence, the low frequency output ripple can be obtained as following:

For the sake of safety, 450 V rating output capacitor is always recommended if the nominal
output voltage of the circuit is 400 V.

On the other hand, in a NCP1601 PFC circuit the instantaneous output voltage affects the
instantaneous control voltage Vcontrol. If the output voltage ripple is too high, it will make a
large ripple on control voltage and the power factor can be dramatically reduced for highly
dynamic control voltage.

Step 11. Input Filter Design

CRM and/or DCM PFC circuit needs an input filtering circuit to bypass the high frequency
current so that the input current consists of the low frequency part only. The simplest filtering
circuit is a capacitor CF across the input lines in Figure 6. An input impedance Zin is assumed to
be with the input AC source but the value of the input impedance is usually unavailable and
negligible in most of the application. Hence, a differential mode filtering inductor LF is added in
the calculation of the currents in Figure 6. This differential mode inductor usually exists in the
form of common mode inductors.
The high frequency source in Figure 6 is the inductor current IL. A high frequency equivalent
circuit of Figure 6 is shown in Figure 7. Therefore, the phasor diagram is drawn and the
percentage of the high frequency current (IL) getting into the input side (Iin) is as follows.

when LF = 1 mH and CF = 1 F.

On the other hand, the addition of the filtering capacitor CF also draws a low frequency (i.e.,
line frequency fL) current IF in Figure 8. It increases the overall magnitude of the input current
Iin for the same power IL. The low frequency equivalent circuit of Figure 6 is shown in

Figure 8. The equivalent resistance Req is the PFC circuit equivalent resistance which can be
modeled to be purely resistive for its PFC property and Req is expressed as follows.

Therefore, the percentage of the increase of the input current due to the addition of the
filtering capacitor is obtained.

Step 12. Layout Design

Figures 9 and 10 illustrate the layout of the 100 W circuit.

As one of the layout rules, the control circuit is located at a corner of the PCB to prevent any
unwanted high frequency noise from the main power switching circuit. The NCP1601A is
associated with a bunch of pF order capacitors which are very sensitive. The best way to
handle them is to minimize the PCB trace distance. Hence, this bunch of pF capacitors are
ideally located at the bottom layer of the NCP1601A.

The PCB trace connected to the low impedance current sense resistor is a major source of
noise or error. It is recommended to minimize this PCB trace distance. Finally, the circuit is
layout in a single PCB layer board. As a result, a 10 resistor is added between the MOSFET gate
and the NCP1601A output. This circuit path provides a large amount of high current ac noise so
that the nearby trace on the output feedback is easily polluted. Hence, some surface mounted
decoupling capacitors are located there for the noise.

Step 13. Fine Tuning Capacitor on Vcontrol Pin

The unity power factor in the NCP1601 PFC circuit greatly relies on how steady the control
voltage in the Vcontrol pin (pin 2). A large external capacitor on this pin can help to reduce the
noise and dynamics of this voltage and give a decent power factor. However, if the capacitor is
too large, it will reduce the dynamic response or startup transient of the circuit.

MEASUREMENT

The performance of the example PFC circuit is listed in Table 2. The waveforms with different
input voltages are also shown in Figures 11 to 14. In Figures 11 to 14, the upper trace is the
input current with 1 A/div. The center trace is the output voltage with 100 V/div. And the
lower trace is the boost input voltage with 100V/div. The output voltage of the circuit is set by
a (1.8 M + 150 k) × 200 A = 390 V.

There is roughly 374 V (96% × 390) to 390 V (100%) regulation window in the NCP1601. It
explains the variation of the output voltage over the wide input range in Table 2.
The THD can be improved by 2 or 3% if the front−ended 1 F
capacitor is reduced.