Republic of the Philippines

BATANGAS STATE UNIVERSITY

Pablo Borbon Main II
Batangas City

COLLEGE OF ENGINEERING, ARCHITECTURE & FINE ARTS

Electronics, Instrumentation and Control, and Mechatronics
Engineering Department

LABORATORY EXPERIMENT NO. 2

FREQUENCY RESPONSE

ECE 3101

CUETO, KHRYZZ LYDEN G.

SANTOS, RICKY MAE V

ENGR. ANELA SALVADOR

NOVEMBER 16, 2020

 OBJECTIVES:

• To measure the bandwidth of a transistor circuit.

• To draw the frequency and phase plot of a transistor amplifier circuit.

EQUIPMENTS REQUIRED

• Laptop • NI Multisim Software

o BJT Transistor
o JFET Transistor
o Resistors
o Oscilloscope
o Coupling Capacitors
o Reference Ground
o Voltage Probe

INTRODUCTION

Frequency Response defines how the gain of an amplifier responds or changes with respect to the
input signals at different frequencies. This gain is the size of the output signal corresponding to the input
signal. Furthermore, it also illustrates how the phase shifts or changes as the frequency of the signal is
varied depending upon the design of the amplifier.

There’s only a select range of frequency that a transistor is most effective in amplifying. This is
known by plotting the gain of amplification against the frequency scale where the amplifier is expected to
operate. This range or band is referred to as bandwidth and the plot that demonstrates it called the Bode
Plot – where the x-axis contains the frequency and the y-axis axis contains the gain. Other than its
bandwidth, the low frequency response and high frequency response is also expected to be observed here.
It is said that a too-narrow bandwidth results in the loss of signal frequency and a too-wide bandwidth
introduces unnecessary signals.

An amplifier must hold up an acceptable gain on the band of frequencies it was designed to amplify
for. By knowing the gain at each frequency it was expected to operate, it can be easily understood or
analyzed how good the amplifier design is. In this experiment, using a 2n2222 BJT and a 2n3891 JFET,
different configurations of a transistor amplifier were designed and constructed in NI Multisim to analyze
their frequency response. Using the different simulations and measuring tools, the bode plot containing the
bandwidth, and the phase shift plot will be analyzed.
 FREQUENCY RESPONSE OF THE BJT AMPLIFIERS

PROCEDURE

The circuits for a BJT amplifier from the previous laboratory experiment were rebuilt in NI
Multisim. Instead of using a 1uF capacitors as couplers, a 10uF, 6uF and 20uF capacitors was used this
time and was expected to make significant changes to the gain. The initial circuit has no source resistor and
load resistor connected to it while the other two circuit has both source and load resistors. The second circuit
have a 100Ω source resistance and 1kΩ load resistance. On the other hand, the third circuit have a 220Ω
source resistance and 2kΩ load resistance.

Below are the circuits constructed:

 Using a function generator, a sinusoidal input with 5mVp amplitude was applied to the transistor
amplifier. The frequency was varied with a step of 10 (10 Hz, 100 Hz, 1 kHz, 10 kHz, 100 kHz, 1 MHz, 10
MHz, 100 MHz). The voltage output and input for each frequency were measured using an oscilloscope.
𝑣𝑜𝑢𝑡
The voltage gain was then computed using the formula 𝐴𝑣 = . The time delay was also measured from
𝑣𝑖𝑛

the oscilloscope and the period was derived as the time quantity defined by its relationship with frequency
1
𝑇= 𝑓
. Using these values, the phase shift was computed using the formula indicated in the laboratory

handout.

In order to draw the frequency and phase plot, the AC Sweep was utilized. The start frequency was
set to 10 Hz while the stop frequency was set to 100MHz. Its sweep type was set to decade with 10 number
of points per decade and its vertical scale was in decibels. The output selected was the net name of the wire
on the circuit’s output. When the simulation was run, the plot for frequency and phase was shown. To
specify the values in each decade, the cursor was move to locate the frequency per decade and the label was
added along with it.

To show the bandwidth, the bode plot was generated was utilized. Using the cursor, the Ymax was
located and to determine the high cutoff and low cutoff frequency, the value of the max gain was subtracted
to 3dB. As the cut off frequency was located, the label was added to it. Using the values for low and high
cutoff frequency the bandwidth of the circuits was determined.
RESULTS AND DISCUSSIONS

Figure 1: BJT Amplifier 1

Figure 2: Frequency and Phase Plot of BJT Amplifier 1

Using the AC Sweep, the bode and phase plot on the first BJT circuit was obtained. Based on the
bode plot, the gain rises from -23.27dB to 1.88dB at points between 10Hz to 1kHz. Between the points
10kHz to 100kHz, the gain seems to be constant with approximately 2.08dB. The gain started to decrease
from 1.89dB to -24.58dB from 1MHz to 100MHz. The lower graph shows how the phase went down as
the frequency increases from 10Hz – 100MHz. The phase started at -115.15 degrees to -279.94 degrees
 Figure 3: Bandwidth of BJT Amplifier 1

The critical points from the figure above has less than 3dB of the maximum gain obtained from the
plot. Low cutoff frequency obtained was 212.0818Hz while the high cutoff frequency was 4.8679MHz.
The bandwith was between the points of low and high cutoff frequency so the difference between the
frequencies would be the bandwidth of this plot.

𝐵𝑊 = 𝑓𝐶𝐻 − 𝑓𝐶𝐿

𝐵𝑊 = 4.8769𝑀𝐻𝑧 − 212.0818𝐻𝑧

𝐵𝑊 = 4.8766𝑀𝐻𝑧
 Table 1: BJT Amplifier 1
Bode Plot Phase Plot
Frequency Vin Vout Gain Gain (dB) Δt Period Phase Shift
10 4.99E-03 6.90E-05 0.013828 -37.185 3.17E-02 0.1 114.246
100 4.99E-03 0.53 106.2124 40.52351 3.26E-03 0.01 117.288
1.00E+03 4.99E-03 1.235 247.495 47.87133 4.62E-04 0.001 166.36356
1.00E+04 4.99E-03 1.265 253.507 48.0798 4.96E-05 0.0001 178.6356
1.00E+05 4.99E-03 1.265 253.507 48.0798 5.04E-06 0.00001 181.368
1.00E+06 4.99E-03 1.24 248.497 47.90642 5.34E-07 0.000001 192.27276
1.00E+07 4.99E-03 0.535 107.2144 40.60506 6.86E-08 1E-07 246.8196
1.00E+08 4.99E-03 5.85E-02 11.72345 21.38111 7.77E-09 1E-08 279.54

The table above shows the recorded values needed to obtain the bode and phase shift plot. For the
bode plot, the recroded voltage output and input values were used to get the gain which was coverted into
decibels using the formula Av=20log(vout/vin). For the phase plot, on the other hand, the time delay and
the compute period were used to get the phase shift.

It can be obeserved from the values shown above that at 10 Hz and 100 Hz the gain of the amplifier
starts to rise until it reached its somewhat constant state from 1 kHz which persist to have a gain that was
significantly large and the values were stable with significantly less difference up to 10 MHz. From
frequency greater than 10 MHz, the gain rapidly drops. This shows how the amplifier was able to amplify
at this range of frequency and implies that the bandwidth at which the amplifier operates best is contained
within this range. Ultimately, this was proven as the previous plot shows that the bandwidth is contained
within the low frequency 219.80 Hz and 4.86 Mhz.

Regarding the phase shift, it can be observed that as the input frequency increases in decades the
phase shifts also increase with increasing magnitude. This is because as the frequency increases the period
decreases and therefore provides a much larger time delay to period ratio. As obtained in the simulated plot,
the phase shifts values are the same with minimal differences in the magnitude of the values.
 Figure 4: BJT Amplifier 2

Figure 5: Frequency and Phase Plot of BJT Amplifier 2

Like the initial circuit, the bode and phase plot on the second BJT circuit was obtained through AC
Sweep. The bode plot above shows the gain rises from -44.17dB to 13.76dB at points between 10Hz to
100kHz. Between the points 10kHz to 1kHz, the gain was almost constant with approximately 13.08dB.
The gain started to decrease from 13.27dB to -40.05dB from 1MHz to 100MHz. The other part of the figure
shows that phase plot wherein the phase started -100.4 degrees at 10Hz and decreases to -290.24 degrees
as it reached 100MHz.
 Figure 6: Bandwidth of BJT Amplifier 2

Compared to the initial circuit, the bode plot for the second circuit is much steeper. This shows that
the bandwidth would be less than the initial circuit. The plot has narrow margin between the two cutoff
frequencies. The calculated bandwidth below proved that the observation for the narrower bandwidth of
the plot on the second circuit.

𝐵𝑊 = 𝑓𝐶𝐻 − 𝑓𝐶𝐿

𝐵𝑊 = 4.7349𝑀𝐻𝑧 − 414.5150𝐻𝑧

𝐵𝑊 = 4.7345𝑀𝐻𝑧
 Table 2: BJT Amplifier 2
Bode Plot Phase Plot
Phase
Frequency Vin Vout Gain Gain (dB) Δt Period Shift
10 4.99E-03 6.20E-03 1.242485 1.885823 2.80E-02 0.1 100.6596
100 4.99E-03 5.25E-01 105.2104 40.44118 2.91E-03 0.01 104.868
1.00E+03 4.99E-03 2.05E-01 40.98196 32.25186 4.32E-04 0.001 155.5909
1.00E+04 4.99E-03 2.20E-01 44.08818 32.88644 4.88E-05 0.0001 175.5756
1.00E+05 4.99E-03 2.22E-01 44.38878 32.94546 5.02E-06 0.00001 180.72
1.00E+06 4.99E-03 2.17E-01 43.48697 32.76718 5.35E-07 0.000001 192.442
1.00E+07 4.99E-03 9.45E-02 18.93788 25.54663 6.89E-08 1E-07 248.1804
1.00E+08 4.99E-03 7.00E-03 1.402806 2.93995 8.07E-09 1E-08 290.448

The table above shows the recorded values needed to obtain the bode and phase shift plot. For the
bode plot, the recroded voltage output and input values were used to get the gain which was coverted into
decibels using the formula Av=20log(vout/vin). For the phase plot, on the other hand, the time delay and
the compute period were used to get the phase shift.

Similar to the first BJT amplifier, at 10 Hz and 100 Hz the gain of the amplifier starts to rise until
it reached its somewhat constant state from 1 kHz which persist to have a gain that was significantly large
and the values were stable with significantly less difference up to 10 MHz. From frequency greater than 10
MHz, the gain rapidly drops. This shows how the amplifier was able to amplify at this range of frequency
and implies that the bandwidth at which the amplifier operates best is contained within this range.
Ultimately, this was proven as the previous plot shows that the bandwidth is contained within the low
frequency 412.27 Hz and 4.73 Mhz. Compared to the bandwidth of the first BJT amplifier circuit, the
bandwidth of the second BJT amplifier amplifier seems to be much narrower due to the effect of the sense
and load resistances.

Regarding the phase shift, it can be observed that as the input frequency increases in decades the
phase shifts also increase with increasing magnitude. This is because as the frequency increases the period
decreases and therefore provides a much larger time delay to period ratio. As obtained in the simulated plot,
the phase shifts values are the same with minimal differences in the magnitude of the values.
 Figure 7: BJT Amplifier 3

Figure 8: Frequency and Phase Plot of BJT Amplifier 3

The figure above shows the bode and phase plot for the third circuit using bjt transistor. The bode
plot above shows the gain rises from -39dB to -9.52dB at points between 10Hz to 1kHz. From the points
10kHz to 100kHz, the gain was almost constant with approximately 9dB. The gain started to decrease from
-10.44dB to -45.61dB from 1MHz to 100MHz. Looking at the phase plot, the curve moves down as the
frequency increases from 10Hz to 100MHz. Initially the phase was -101.84 degrees at 10Hz until it reach -
284.23 degrees on 100MHz.
 Figure 5: Bandwidth of BJT Amplifier 3

From the first two circuit, the bandwidth seems to narrow as a source and load resistance was
applied to the circuit. For the third circuit, the source and load resistance were higher compared to the
source and load resistance of the second circuit. Based on the calculations made below, the bandwidth of
higher source and load resistance is narrower compared to the second circuit. This shows that as the load
and load resistance were raised, the bandwidth decreases.

𝐵𝑊 = 𝑓𝐶𝐻 − 𝑓𝐶𝐿

𝐵𝑊 = 1.5769𝑀𝐻𝑧 − 370.1160𝐻𝑧

𝐵𝑊 = 1.5765𝑀𝐻𝑧
 Table 3: BJT Amplifier 3
Bode Plot Phase Plot
Frequency Vin Vout Gain Gain (dB) Δt Period Phase Shift
10 4.99E-03 1.13E-03 0.225451 -12.939 2.83E-02 0.1 101.9988
100 4.99E-03 9.45E-02 18.93788 25.54663 3.00E-03 0.01 107.82
1.00E+03 4.99E-03 0.3335 66.83367 36.49991 4.39E-04 0.001 158.1653
1.00E+04 4.99E-03 0.353 70.74148 36.99348 4.89E-05 0.0001 175.9104
1.00E+05 4.99E-03 0.354 70.94188 37.01805 5.08E-06 0.00001 182.736
1.00E+06 4.99E-03 0.299 59.91984 35.55141 5.93E-07 0.000001 213.5272
1.00E+07 4.99E-03 5.55E-02 11.12224 20.92385 7.31E-08 1E-07 263.1816
1.00E+08 4.99E-03 5.20E-03 1.042084 0.358056 8.18E-09 1E-08 294.552

The table above shows the recorded values needed to obtain the bode and phase shift plot. For the
bode plot, the recroded voltage output and input values were used to get the gain which was coverted into
decibels using the formula Av=20log(vout/vin). For the phase plot, on the other hand, the time delay and
the compute period were used to get the phase shift.

Just like the first and second BJT amplifier, at 10 Hz and 100 Hz the gain of the amplifier starts to
rise until it reached its somewhat constant state from 1 kHz which, again, persist to have a gain that was
significantly large and the values were stable with significantly less difference up to 10 MHz. From
frequency greater than 10 MHz, the gain rapidly drops. This shows how the amplifier was able to amplify
at this range of frequency and implies that the bandwidth at which the amplifier operates best is contained
within this range. Ultimately, this was proven as the previous plot shows that the bandwidth is contained
within the low frequency 369.96 Hz and 1.58 Mhz. Compared to the bandwidth of the first and secon BJT
amplifier circuit, the bandwidth of the second BJT amplifier amplifier seems to be much narrower due to
the effect of the sense and load resistances. However, it seems that the resistance value can greatly affect
the selectivity of the amplifier because the bandwidth of this amplifier is much narrower with large
difference from the first and second amplifiers. It can be said that as the resistances increaes, the bandwidth
decreases and the amplifier becomes more selective in terms of the frequency where it gives acceptable
gains.

Regarding the phase shift, it can be observed that as the input frequency increases in decades the
phase shifts also increase with increasing magnitude. This is because as the frequency increases the period
decreases and therefore provides a much larger time delay to period ratio. As obtained in the simulated plot,
the phase shifts values are the same with minimal differences in the magnitude of the values.
 FREQUENCY RESPONSE OF THE JFET AMPLIFIERS

PROCEDURE
The second figure on the previous laboratory experiment was utilized to create another circuit. The
three circuit for this figure was connected to a 1uF capacitor on its input or gate terminal, a 6.8uF capacitor
on its output or drain terminal and 20uF capacitor on its source terminal. The initial circuit has no source
resistor and load resistor connected to it while the other two circuit has both source and load resistors. The
second circuit have a 100Ω source resistance and 1kΩ load resistance. On the other hand, the third circuit
have a 220Ω source resistance and 2kΩ load resistance.

Below are the circuits constructed:

 Using a function generator, a 10Hz sinusoidal input was initially applied to the circuit. The voltage
peak was set to 5mV which was also used in the previous experiment. In order to obtain the time of phase
shift, the value of the input and output voltages were measured using an oscilloscope. The Channel A of
the oscilloscope was connected to the input while the Channel B of the oscilloscope was connected on its
output. In addition, probes were connected on the input and output network to measure the voltage peak –
peak of the input and output. The frequency input of the function generator was modified in every one
decade and the input and output voltage obtained from it was recorded. After that, the voltage gain was
calculated by the ratio of output voltage to input voltage. Aside from that, the phase shift was calculated
using the formula indicated in the experiment and the data gathered from the simulations.

In order to draw the frequency and phase plot, the AC Sweep was utilized. The start frequency was
set to 10 Hz while the stop frequency was set to 100MHz. Its sweep type was set to decade with 10 number
of points per decade and its vertical scale was in decibels. The output selected was the net name of the wire
on the circuit’s output. When the simulation was run, the plot for frequency and phase was shown. To
specify the values in each decade, the cursor was move to locate the frequency per decade and the label was
added along with it.

To show the bandwidth, the bode plot was generated was utilized. Using the cursor, the Ymax was
located and to determine the high cutoff and low cutoff frequency, the value of Y was subtracted to 3. As
the cut off frequency was located, the label was added to it. Using the values for low and high cutoff
frequency the bandwidth of the circuits was determined.
RESULTS AND DISCUSSIONS

Figure 10: JFET Amplifier 1

Figure 11: Frequency and Phase Plot of JFET Amplifier 1

Using the AC Sweep, the bode and phase plot on the first JFET circuit was obtained. Based on the
bode plot, the gain rises from -37.15dB to -32.54dB at points between 10Hz to 100 Hz. Between the points
100 Hz to 10 MHz, the gain seems to be constant with approximately -32.50dB. The gain started to decrease
from -32.80dB to -41.19dB from 10MHz to 100MHz. The lower graph shows how the phase shifts and
decreases. The phase went down as the frequency increases from 10Hz – 100MHz. However, between
frequency 100Hz to 1MHz the phase shift change seems to be constant at 180 degrees. This means that the
output of the amplifier shifted and the graph may have looked like as if the output was inverted.
 Figure 12: Bandwidth of JFET Amplifier 2

The critical points from the figure above has less than 3dB of the maximum gain obtained from the
plot. Low cutoff frequency obtained was 15.7336Hz while the high cutoff frequency was 33.4101MHz.
The bandwith was between the points of low and high cutoff frequency so the difference between the
frequencies would be the bandwidth of this plot.

𝐵𝑊 = 𝑓𝐶𝐻 − 𝑓𝐶𝐿

𝐵𝑊 = 33.4101𝑀𝐻𝑧 − 15.7336𝐻𝑧

𝐵𝑊 = 33.41008𝑀𝐻𝑧
 Table 4: JFET Amplifier 1
Bode Plot Phase Plot
Gain Phase
Frequency Vin Vout Gain (dB) Δt Period Shift
10Hz 4.99mV 13.9mV 2.775551 8.866985 42.8ms 0.1 154.0908
100Hz 4.99mV 23.6mV 4.719439 13.47781 4.77ms 0.01 171.828
1kHz 4.99mV 23.9mV 4.789579 13.60595 496us 0.001 178.63632
10kHz 4.99mV 23.9mV 4.789579 13.60595 50.0us 0.0001 180
100kHz 4.99mV 23.9mV 4.789579 13.60595 5.00us 0.00001 180
1MHz 4.99mV 24.0mV 4.799599 13.6241 508ns 0.000001 182.72736
10MHz 4.99mV 22.9mV 4.579158 13.21571 56.1ns 0.0000001 201.8196
100MHz 4.99mV 87.0mV 1.743487 4.828374 7.99ns 0.00000001 287.712

The table above shows the data collected from the simulation made in Multisim and the calculated
measurement using the generated results. The highlighted columns were the measurements obtained from
the Multisim. In order to observe the change within the bode plot, the gain was calculated from the ratio of
voltage output and input while the gain in decibels was calculated using the formula Av=20log(vout/vin).
It could be seen that the gain in decibels from 1kHz to 100KHz were the same because it has similar voltage
amplified within this range of frequency are similar. However, only 10kHz and 100kHz obtain a 180
degrees phase shift.

From 10 Hz to 100Hz, the gain started to rise until it reached its constant state. On the other hand,
the gain started to decrease from 1MHz to 100MHz. It could also be observed that the phase shift has
increased as frequency varies in each decade. Since higher frequencies has lower period it gives higher
time-period ratio which is why the phase shift is bound to increase. Based on the calculated results, the
behavior of the gain is particularly similar to the simulated result. On the other hand, the phase plot
simulated produces negative magnitude. However, the magnitude of the phase in the simulated result shows
an increase which is also the same for the magnitude of the phase shift for the calculated results.
 Figure 13: JFET Amplifier 2

Figure 14: Frequency and Phase Plot of JFET Amplifier 2

Using the AC Sweep, the bode and phase plot on the first JFET circuit was obtained. Based on the
bode plot, the gain rises from -50.94dB to -45.21dB at points between 10Hz to 100 Hz. Between the points
100 Hz to 10 MHz, the gain seems to be constant with approximately -45.1dB. The gain started to decrease
from -46.65dB to -48.08dB from 10MHz to 100MHz. The lower graph shows how the phase shifts and
decreases. The phase went down as the frequency increases from 10Hz – 100MHz. However, between
frequency 100Hz to 1MHz the phase shift change seems to be constant at 180 degrees. This means that the
output of the amplifier shifted and the graph may have looked like as if the output was inverted.
 Figure 15: Bandwidth of JFET Amplifier 2

The critical points from the figure above has less than 3dB of the maximum gain obtained from the
plot. Low cutoff frequency obtained was 17.9461Hz while the high cutoff frequency was 188.6022MHz.
The bandwith was between the points of low and high cutoff frequency so the difference between the
frequencies would be the bandwidth of this plot.

𝐵𝑊 = 𝑓𝐶𝐻 − 𝑓𝐶𝐿

𝐵𝑊 = 188.6022𝑀𝐻𝑧 − 17.9461𝐻𝑧

𝐵𝑊 = 188.6022𝑀𝐻𝑧

As seen in the bode plot, the high cutoff exceeds the 100MHz frequency applied to it which means
that the JFET amplifier can still operate at more than 100MHz and less than 190MHz with acceptable gain.
 Table 5: JFET Amplifier 2
Bode Plot Phase Plot
Gain
Frequency Vin Vout Gain (dB) Δt Period Phase Shift
10Hz 4.99mV 2.84mV 0.569138 -4.89564 34.8ms 0.1 125.1468
100Hz 4.99mV 5.50mV 1.102204 0.845243 46.8ms 0.01 168.408
1kHz 4.99mV 5.55mV 1.112224 0.923849 495us 0.001 178.1838
10kHz 4.99mV 5.60mV 1.122244 1.00175 50.0us 0.0001 180
100kHz 4.99mV 5.60mV 1.122244 1.00175 5.00us 0.00001 180.072
1MHz 4.99mV 5.55mV 1.112224 0.923849 503ns 0.000001 181.05336
10MHz 4.99mV 5.55mV 1.112224 0.923849 52.9ns 0.0000001 190.5048
100MHz 4.99mV 4.64mV 0.92986 -0.63165 7.46ns 0.00000001 268.956

The table above shows the data collected from the simulation made in Multisim and the calculated
measurement using the generated results for the second JFET amplifier circuit. The highlighted columns
were the measurements obtained from the Multisim. In order to observe the change within the bode plot,
the gain was calculated similar to the initial circuit. It could be seen that the gain in decibels from 10kHz
to 100KHz were the same because it has similar voltage output. Its phase shift was almost the same which
is approximately 180 degrees.

The rise of the gain happens from 10 Hz to 1kHz before the gain remains constant. On the other
hand, the gain started to fall from 1MHz to 100MHz. It could also be observed that the phase shift has
increased as frequency varies in each decade. Similar to the initial circuit, higher frequencies provide higher
time-period ratio than lower frequencies resulting to higher phase shift. Comparing the simulated results to
calculated results, it was almost the same except that the gain and phase in simulated results were expressed
in negative values. The behavior of the gain in each frequency was the same and the increasing magnitude
on its phase was also similar.
 Figure 16: JFET Amplifier 3

Figure 16: Frequency and Phase Plot of JFET Amplifier 3

Using the AC Sweep, the bode and phase plot on the first JFET circuit was obtained. Based on the
bode plot, the gain rises from -46.3834dB to -41.0056dB at points between 10Hz to 100 Hz. Between the
points 100 Hz to 10 MHz, the gain seems to be constant with approximately -40.92dB. The gain started to
decrease from -41.02dB to -46.69dB from 10MHz to 100MHz. The lower graph shows how the phase shifts
and decreases. The phase went down as the frequency increases from 10Hz – 100MHz. However, between
frequency 100Hz to 1MHz the phase shift change seems to be constant at 180 degrees. This means that the
output of the amplifier shifted and the graph may have looked like as if the output was inverted.
 Figure 18: Bandwidth of JFET Amplifier 3

The critical points from the figure above has less than 3dB of the maximum gain obtained from the
plot. Low cutoff frequency obtained was 17.2137Hz while the high cutoff frequency was 54.8350MHz.
The bandwith was between the points of low and high cutoff frequency so the difference between the
frequencies would be the bandwidth of this plot.

𝐵𝑊 = 𝑓𝐶𝐻 − 𝑓𝐶𝐿

𝐵𝑊 = 54.8350𝑀𝐻𝑧 − 17.2137𝐻𝑧

𝐵𝑊 = 54.8350𝑀𝐻𝑧
 Table 6: JFET Amplifier 3
Bode Plot Phase Plot
Gain
Frequency Vin Vout Gain (dB) Δt Period Phase Shift
10Hz 4.99mV 4.79mV 0.95992 -0.3553 36.1ms 0.1 129.78
100Hz 4.99mV 8.90mV 1.783567 5.025789 4.70ms 0.01 169.092
1kHz 4.99mV 9.00mV 1.803607 5.122839 496us 0.001 178.63632
10kHz 4.99mV 9.05mV 1.813627 5.170961 50.0us 0.0001 180
100kHz 4.99mV 9.05mV 1.813627 5.170961 5.00us 0.00001 180
1MHz 4.99mV 9.05mV 0.001814 -54.829 500ns 0.000001 180
10MHz 4.99mV 4.62mV 0.925852 -0.66917 54.5ns 1E-07 196.362
100MHz 4.99mV 8.90mV 1.783567 5.025789 8.18ns 1E-08 294.552

The table above shows the data collected from the simulation made in Multisim and the calculated
measurement using the generated results for the third JFET amplifier circuit. The highlighted columns were
the measurements obtained from the Multisim. In order to observe the change within the bode plot, the gain
was calculated similar to the previous circuits. It could be seen that the gain in decibels from 10kHz to
100KHz were the same because it has similar voltage output. On the other hand, the phase shift from 10kHz
to 1MHz were the same.

Before the gain became constant at 10kHz to 100kHz, the gain rises from 10Hz – 1kHz. On the
other hand, the gain started to fall from 1MHz to 100MHz. It could also be observed that the phase shift
has increased as frequency varies in each decade. Similar to the previous circuits, higher frequencies
provide higher time-period ratio than lower frequencies resulting to higher phase shift. Comparing the
simulated results to calculated results, it was almost the same except that the gain and phase in simulated
results were expressed in negative values. The behavior of the gain in each frequency was the same and the
increasing magnitude on its phase was also similar.

Based on the results gathered from the three circuit, the phase shift of the third circuit is the highest.
On the other hand, the gain for the JFET circuit with no source and load resistance seems to be the highest
because of less impedance on the circuit. However, when the two circuit with source and load resistance is
compared, the circuit with higher value of source and load resistance contains higher gain.
CONCLUSION

One of the main objectives of this experiment is to measure the bandwidth given that the tool used
was a simulation software. Bandwidth measurement was obtained through the use of a simulation command
for AC sweep. From this experiment, we learned how to draw a bode plot using the AC sweep by
manipulating the start and stop input frequency. As the function of cursors and data labels were used in the
experiment, the critical low frequency and critical high frequency was obtained. The difference of this two
critical points helped in obtaining the bandwidth measurement. Through observation, the change in the
bandwidth based on the source and load resistance was learned. The circuit with higher source and load
resistance produces narrow bandwidth while the circuit without source and load resistance produces wide
bandwidth.

Aside from that, another objective was accomplished using the same simulation command. AC
sweep generated both bode and phase plot for each decade in every circuit that was utilized for this
experiment. Through the plots, the behavior of the gain of a transistor circuit as well as its phase shift were
observed given that the input frequency varies every decade.

Three circuits were made for each transistor and this helped in observing the gain ang phase shift
in circuits with and without source and load resistance. Two combination of source and load resistance was
made into a circuit to observe the change of gain and phase as the resistance increases. Based on the result,
the circuit with higher load resistance have higher gain and phase shift. This was also explained from the
previous experiment were the source resistance practically only drops the input voltage but the amplifier
circuit itself can amplify the signal. The load resistance of the circuit serves as the storage of voltage output
therefore the amount of voltage stored in higher load resistance is much higher than lower value of load
resistance. Through calculations made for the gain and phase shift, the result of the plot was better observed.
Since the ratio of time and period of the higher source and load resistance circuit was higher compared to
lower source and load resistance, the phase shift was expected to be larger.

Comparing the two different transistor amplifiers, it was also concluded that JFET Amplifiers gain
within the bandwidth does not vary as much as BJT’s. Therefore, with much better stability, JFETs are
much more efficient to use in designing amplifiers than BJT.
REFERENCE

FREQUENCY RESPONSE OF AMPLIFIERS (n.d.). Retrieved November 14, 2020, from

http://electriciantraining.tpub.com/14180/css/Frequency-Response-Of-Amplifiers-17.htm

Frequency Response Analysis of Amplifiers and Filters. (2018, June 16). Retrieved November 14,
2020, from https://www.electronics-tutorials.ws/amplifier/frequency-response.html