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Max 17528

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19-4723; Rev 0; 7/09

KIT
ATION
EVALU BL E
AVAILA
1-Phase Quick-PWM
Intel IMVP-6.5/GMCH Controllers
General Description Features

MAX17528
The MAX17528 comprises 1-phase Quick-PWM™ step- o 1-Phase Quick-PWM Controller
down VID power-supply controllers for Intel notebook o ±0.5% VOUT Accuracy Over Line, Load, and
CPUs. The Quick-PWM control provides instantaneous Temperature
response to fast-load current steps. Active voltage o 7-Bit IMVP-6.5 DAC
positioning reduces power dissipation and bulk output o IMVP-6.5 and GMCH Compliant
capacitance requirements and allows ideal positioning
compensation for tantalum, polymer, or ceramic bulk o Active Voltage Positioning with Adjustable Gain
output capacitors. o Accurate Droop and Current Limit
The MAX17528 is intended for two different notebook o Remote Output and Ground Sense
CPU/GPU core applications: either bucking down the bat- o Adjustable Output-Voltage Slew Rate
tery directly to create the core voltage, or bucking down o Power-Good Window Comparator
the +5V system supply. The single-stage conversion
o Current Monitor
method allows these devices to directly step down high-
voltage batteries for the highest possible efficiency. o Temperature Comparator
Alternatively, 2-stage conversion (stepping down the o Drives Large Synchronous Rectifier FETs
+5V system supply instead of the battery) at higher o 2V to 26V Battery Input Range
switching frequency provides the minimum possible o Adjustable Switching Frequency (600kHz max)
physical size.
o Undervoltage and Thermal-Fault Protection
A slew-rate controller allows controlled transitions o Soft-Startup and Soft-Shutdown
between VID codes. A thermistor-based temperature
sensor provides programmable thermal protection. A o Internal Boost Diode
current monitor provides an analog output current pro-
portional to the processor load current. Ordering Information
The MAX17528 implements both the Intel IMVP-6.5 PART TEMP RANGE PIN-PACKAGE
CPU core specifications (CLKEN pullup to 3.3V), as o o
MAX17528GTJ+ -40 C to +105 C 32 TQFN-EP*
well as the Intel GMCH graphics core specifications
(CLKEN = GND). The MAX17528 is available in a +Denotes a lead(Pb)-free/RoHS-compliant package.
32-pin, 5mm x 5mm TQFN package. *EP = Exposed pad.

Applications Pin Configuration


IMVP-6.5 Core Power Supply
PGND

TOP VIEW
BST

VDD

Intel GMCH 2009


DL

D6

D5

D4

D3

Intel Calpella Platforms 24 23 22 21 20 19 18 17


LX 25 16 D2
Graphics Core Power Supply
DH 26 15 D1
Voltage-Positioned Step-Down Converters
PGDIN 27 14 D0
1-to-4 Lithium-Ion (Li+)-Cell Battery-to-CPU Core
Supply Converters VRHOT 28 13 GND
MAX17528
TIME 29 12 CLKEN
Notebooks/Desktops/Servers
PAD SHDN
ILIM 30 11
GND
VCC 31 10 PWRGD

CCV 32 9 TON
1 2 3 4 5 6 7 8
IMON

GNDS

FB

CSN

CSP

SLOW

SKIP

THRM

THIN QFN
Quick-PWM is a trademark of Maxim Integrated Products, Inc. 5mm x 5mm

________________________________________________________________ Maxim Integrated Products 1

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
1-Phase Quick-PWM
Intel IMVP-6.5/GMCH Controllers
ABSOLUTE MAXIMUM RATINGS
MAX17528

VCC, VDD to GND .....................................................-0.3V to +6V BST to GND ............................................................-0.3V to +36V


D0–D6 to GND..........................................................-0.3V to +6V LX to BST..................................................................-6V to +0.3V
CSP, CSN to GND ....................................................-0.3V to +6V BST to VDD.............................................................-0.3V to +30V
ILIM, THRM, PGDIN, VRHOT, PWRGD to GND .......-0.3V to +6V DH to LX ....................................................-0.3V to (VBST + 0.3V)
CLKEN to GND.........................................................-0.3V to +6V Continuous Power Dissipation (32-pin, 5mm x 5mm TQFN)
SKIP, SLOW to GND.................................................-0.3V to +6V Up to +70°C ..............................................................1702mW
CCV, FB, IMON, TIME to GND ...................-0.3V to (VCC + 0.3V) Derating above +70°C ..........................................21.3mW/°C
SHDN to GND (Note 1)...........................................-0.3V to +30V Operating Temperature Range .........................-40°C to +105°C
TON to GND ...........................................................-0.3V to +30V Junction Temperature ......................................................+150°C
GNDS, PGND to GND ...........................................-0.3V to +0.3V Storage Temperature Range .............................-65°C to +165°C
DL to PGND................................................-0.3V to (VDD + 0.3V) Lead Temperature (soldering, 10s) .................................+300°C

Note 1: SHDN can be forced to 12V for the purpose of debugging prototype breadboards using the no-fault test mode, which dis-
ables fault protection.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1, VIN = 12V, VDD = VCC = 5V, CLKEN pullup to 3.3V with 1.9kΩ, SHDN = SLOW = ILIM = PGDIN = VCC, SKIP =
GNDS = PGND = GND, VFB = VCSP = VCSN = 1.200V, D0–D6 set for 1.20V (D0–D6 = 0001100). TA = 0°C to +85°C, unless otherwise
specified. Typical values are at TA = +25°C.) (Note 2)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS


PWM CONTROLLER
Input-Voltage Range VCC, VDD 4.5 5.5 V
DAC codes from
-0.5 +0.5 %
Measured at FB with 0.8125V to 1.5000V
respect to GNDS;
DAC codes from
DC Output-Voltage Accuracy includes load- -7 +7
0.3750V to 0.8000V
regulation error mV
(Note 3) DAC codes from 0V
-20 +20
to 0.3625V
Boot Voltage VBOOT IMVP-6.5 (CLKEN pullup to 3.3V with 1.9k) 1.094 1.100 1.106 V
Line Regulation Error VCC = 4.5V to 5.5V, VIN = 4.5V to 26V 0.1 %
GNDS Input Range -200 +200 mV
GNDS Gain A GNDS VOUT/VGNDS, -200mV  VGNDS  +200mV 0.97 1.00 1.03 V/V
GNDS Input Bias Current IGNDS TA = +25°C -2 +2 µA
VCC = 4.5V to 5.5V,
TIME Voltage VTIME 1.985 2.000 2.015 V
ITIME = 28µA (RTIME = 71.5k)
RTIME = 71.5k (12.5mV/µs nominal) -10 +10
RTIME = 35.7k (25mV/µs nominal) to
-15 +15
178k (5mV/µs nominal)
Soft-start and soft-shutdown;
TIME Slew-Rate Accuracy RTIME = 35.7k (3.125mV/µs nominal) to -20 +20 %
178k (0.625mV/µs nominal)
SLOW = GND,
RTIME = 35.7k (12.5mV/µs nominal) to -20 +20
178k (2.5mV/µs nominal)

2 _______________________________________________________________________________________
1-Phase Quick-PWM
Intel IMVP-6.5/GMCH Controllers
ELECTRICAL CHARACTERISTICS (continued)

MAX17528
(Circuit of Figure 1, VIN = 12V, VDD = VCC = 5V, CLKEN pullup to 3.3V with 1.9kΩ, SHDN = SLOW = ILIM = PGDIN = VCC, SKIP =
GNDS = PGND = GND, VFB = VCSP = VCSN = 1.200V, D0–D6 set for 1.20V (D0–D6 = 0001100). TA = 0°C to +85°C, unless otherwise
specified. Typical values are at TA = +25°C.) (Note 2)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS


VIN = 12V, RTON = 96.75k 142 167 192
On-Time t ON VFB = 1.2V RTON = 200k 300 333 366 ns
(Note 4) RTON = 303.25k 425 500 575
Minimum Off-Time t OFF(MIN) Measured at DH (Note 4) 300 375 ns
SHDN = GND, VIN = 26V, VCC = VDD = 0V or
TON Shutdown Input Current 0.01 1 µA
5V, TA = +25°C
BIAS CURRENTS
Measured at VCC, VSKIP = 5V, FB forced
Quiescent Supply Current (VCC) ICC 1.5 3 mA
above the regulation point
Measured at VDD, SKIP = GND,
Quiescent Supply Current (VDD) IDD FB forced above the regulation point, 0.02 1 µA
TA = +25°C
Shutdown Supply Current (VCC) Measured at VCC, SHDN = GND 15 30 µA
Shutdown Supply Current (VDD) Measured at VDD, SHDN = GND, TA = +25°C 0.01 1 µA
FAULT PROTECTION
Output Undervoltage-Protection Measured at FB with respect to unloaded
VUVP -450 -400 -350 mV
Threshold output voltage
Output Undervoltage
tUVP FB forced 25mV below trip threshold 10 µs
Propagation Delay
IMVP-6.5: CLKEN pullup to 3.3V with 1.9k;
IMVP-6.5 CLKEN Startup Delay measured from the time when FB reaches
(Boot Time Period, CLKEN Pullup tBOOT the boot target voltage (Note 3); the time 20 60 100 µs
to 3.3V with 1.9k) needed for FB to reach this target voltage is
based on the slew rate set by RTIME
IMVP-6.5: CLKEN pullup to 3.3V with 1.9k;
measured at startup from the time when 3 5 8
CLKEN goes low
PWRGD Startup Delay GMCH: CLKEN = GND; measured from the ms
time when FB reaches the target voltage (Note
3 5 8
3); the time needed for FB to reach this target
voltage is based on the slew rate set by RTIME

Measured at FB Lower threshold,


PWRGD and CLKEN (IMVP-6.5, with respect to falling edge -350 -300 -250
CLKEN Pullup to 3.3V with unloaded output (undervoltage) mV
1.9k) Threshold voltage, 15mV Upper threshold, rising
hysteresis (typ) +150 +200 +250
edge (overvoltage)
PWRGD and CLKEN (IMVP-6.5, Measured from the time when FB reaches
CLKEN Pullup to 3.3V with tBLANK the target voltage (Note 3) based on the 20 µs
1.9k) Transition Blanking Time slew rate set by RTIME
PWRGD and CLKEN (IMVP-6.5,
FB forced 25mV outside the PWRGD
CLKEN Pullup to 3.3V with 10 µs
trip thresholds
1.9k) Delay

_______________________________________________________________________________________ 3
1-Phase Quick-PWM
Intel IMVP-6.5/GMCH Controllers
ELECTRICAL CHARACTERISTICS (continued)
MAX17528

(Circuit of Figure 1, VIN = 12V, VDD = VCC = 5V, CLKEN pullup to 3.3V with 1.9kΩ, SHDN = SLOW = ILIM = PGDIN = VCC, SKIP =
GNDS = PGND = GND, VFB = VCSP = VCSN = 1.200V, D0–D6 set for 1.20V (D0–D6 = 0001100). TA = 0°C to +85°C, unless otherwise
specified. Typical values are at TA = +25°C.) (Note 2)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
IMVP-6.5 CLKEN Output IMVP-6.5: CLKEN pullup to 3.3V with 1.9k;
0.4 V
Low Voltage I SINK = 3mA
IMVP-6.5 CLKEN High
IMVP-6.5: VPGDIN = 5V, V CLKEN = 3.3V 2 4 µA
Leakage Current
IMVP-6.5 CLKEN Shutdown
IMVP-6.5: V SHDN = GND, V CLKEN = 3.3V 0.01 1 µA
Leakage Current
PWRGD Output Low Voltage I SINK = 3mA 0.4 V
PWRGD Leakage Current High state, PWRGD forced to 5V, TA = +25°C 1 µA
VCC Undervoltage Lockout Rising edge, 65mV typical hysteresis,
VUVLO(VCC) 4.05 4.27 4.48 V
Threshold controller disabled below this level
CSN Discharge Resistance in SHDN = GND and drivers disabled
8 
UVLO and Shutdown (not switching)
THERMAL PROTECTION
Measured at THRM with respect to VCC;
VRHOT Trip Threshold 29.2 30 30.8 %
falling edge; typical hysteresis = 100mV
THRM forced 25mV below the VRHOT trip
VRHOT Delay t VRHOT 10 µs
threshold; falling edge
VRHOT Output On-Resistance RVRHOT Low state 2 8 
VRHOT Leakage Current I VRHOT High state, VRHOT forced to 5V, TA = +25°C 1 µA
THRM Input Leakage ITHRM VTHRM = 0V to 5V, TA = +25°C -100 +100 nA
Thermal-Shutdown Threshold T SHDN Typical hysteresis = 15°C +160 °C
VALLEY CURRENT LIMIT AND DROOP
Current-Limit Threshold Voltage VTIME - VILIM = 100mV 7 10 13
VLIMIT VCSP - VCSN mV
(Positive Adjustable) VTIME - VILIM = 500mV 45 50 55
Current-Limit Threshold Voltage
VCSP - VCSN, ILIM = VCC 20 22.5 25 mV
(Positive Default) Preset
Current-Limit Threshold Voltage
VLIMIT(NEG) VCSP - VCSN, nominally -125% of VLIMIT -4 +4 mV
(Negative) Accuracy
Current-Limit Threshold Voltage
VZERO VPGND - VLX, SKIP = VCC 1 mV
(Zero Crossing)
CSP, CSN Common-Mode
0 2 V
Input Range
CSP, CSN Input Current TA = +25°C -0.2 +0.2 µA
ILIM Input Current TA = +25°C -100 +100 nA
DC Droop Amplifier (GMD) Offset (VCSP - VCSN) at IFB = 0 -0.75 +0.75 mV
DC Droop Amplifier (GMD) IFB/(VCSP - VCSN); VFB = VCSN = 0.45V to
592 600 608 µS
Transconductance 2.0V, and (VCSP - VCSN) = -15.0mV to +15.0mV

4 _______________________________________________________________________________________
1-Phase Quick-PWM
Intel IMVP-6.5/GMCH Controllers
ELECTRICAL CHARACTERISTICS (continued)

MAX17528
(Circuit of Figure 1, VIN = 12V, VDD = VCC = 5V, CLKEN pullup to 3.3V with 1.9kΩ, SHDN = SLOW = ILIM = PGDIN = VCC, SKIP =
GNDS = PGND = GND, VFB = VCSP = VCSN = 1.200V, D0–D6 set for 1.20V (D0–D6 = 0001100). TA = 0°C to +85°C, unless otherwise
specified. Typical values are at TA = +25°C.) (Note 2)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS


GATE DRIVERS
BST - LX forced High state (pullup) 0.9 2.5
DH Gate-Driver On-Resistance R ON(DH) 
to 5V Low state (pulldown) 0.7 2.0
High state (pullup) 0.7 2.0
DL Gate-Driver On-Resistance R ON(DL) 
Low state (pulldown) 0.25 0.7
DH Gate-Driver Source Current IDH(SOURCE) DH forced to 2.5V, BST - LX forced to 5V 2.2 A
DH Gate-Driver Sink Current IDH(SINK) DH forced to 2.5V, BST - LX forced to 5V 2.7 A
DL Gate-Driver Source Current IDL(SOURCE) DL forced to 2.5V 2.7 A
DL Gate-Driver Sink Current IDL(SINK) DL forced to 2.5V 8 A
DH low to DL high 20
Driver Propagation Delay ns
DL low to DH high 20
DL falling, CDL = 3nF 20
DL Transition Time ns
DL rising, CDL = 3nF 20
DH falling, CDH = 3nF 20
DH Transition Time ns
DH rising, CDH = 3nF 20
Internal BST Switch On-Resistance RBST IBST = 10mA, VDD = 5V (Note 6) 10 20 
CURRENT MONITOR
Current-Monitor I IMON/(VCSP - VCSN),
Gm(IMON) 4.9 5.0 5.1 mS
Transconductance VCSN = 0.45V to 2.0V
Current-Monitor Offset
I IMON = 0 -1.0 +1.0 mV
Referred to V(CSP, CSN)
IMON Clamp Voltage VIMON I IMON = -1mA 1.05 1.10 1.15 V
LOGIC AND I/O
Logic-Input High Voltage VIH PGDIN 2.3 V
Logic-Input Low Voltage VIL PGDIN 1.0 V
Low-Voltage Logic-
VIHLV SHDN, SKIP, SLOW, D0–D6 0.67 V
Input High Voltage
Low-Voltage Logic-
VILLV SHDN, SKIP, SLOW, D0–D6 0.33 V
Input Low Voltage
PGDIN, SHDN, SKIP, SLOW, D0–D6 = 0 or
Logic-Input Current -1 +1 µA
5V, TA = +25°C
CLKEN Logic-Input High Voltage
2.3 V
for IMVP-6.5 Startup
CLKEN Logic-Input Low Voltage
1.0 V
for GMCH

_______________________________________________________________________________________ 5
1-Phase Quick-PWM
Intel IMVP-6.5/GMCH Controllers
ELECTRICAL CHARACTERISTICS
MAX17528

(Circuit of Figure 1, VIN = 12V, VDD = VCC = 5V, CLKEN pullup to 3.3V with 1.9kΩ, SHDN = SLOW = ILIM = PGDIN = VCC, SKIP =
GNDS = PGND = GND, VFB = VCSP = VCSN = 1.200V, D0–D6 set for 1.20V (D0–D6 = 0001100). TA = -40°C to +105°C, unless other-
wise specified.) (Note 2)
PARAMETER SYMBOL CONDITIONS MIN MAX UNITS
PWM CONTROLLER
Input-Voltage Range VCC, VDD 4.5 5.5 V
DAC codes from
-0.75 +0.75 %
Measured at FB with 0.8125V to 1.5000V
respect to GNDS;
DAC codes from
DC Output-Voltage Accuracy includes load- -10 +10
0.3750V to 0.8000V
regulation error mV
(Note 3) DAC codes from 0V
-25 +25
to 0.3625V
Boot Voltage VBOOT IMVP-6.5 (CLKEN pullup to 3.3V with 1.9k) 1.085 1.115 V
GNDS Input Range -200 +200 mV
GNDS Gain A GNDS VOUT/VGNDS, -200mV  VGNDS  +200mV 0.95 1.05 V/V
VCC = 4.5V to 5.5V,
TIME Voltage VTIME 1.98 2.02 V
ITIME = 28µA (RTIME = 71.5k)
RTIME = 71.5k (12.5mV/µs nominal) -10 +10
RTIME = 35.7k (25mV/µs nominal) to
-15 +15
178k (5mV/µs nominal)
Soft-start and soft-shutdown;
TIME Slew-Rate Accuracy RTIME = 35.7k (3.125mV/µs nominal) to -20 +20 %
178k (0.625mV/µs nominal)
SLOW = GND,
RTIME = 35.7k (12.5mV/µs nominal) to -20 +20
178k (2.5mV/µs nominal)
RTON = 96.75k 142 192
VIN = 12V, VFB = 1.2V
On-Time t ON RTON = 200k 300 366 ns
(Note 4)
RTON = 303.25k 425 575
Minimum Off-Time t OFF(MIN) Measured at DH (Note 4) 400 ns
BIAS CURRENTS
Measured at VCC, VSKIP = 5V,
Quiescent Supply Current (VCC) ICC 3 mA
FB forced above the regulation point
FAULT PROTECTION
Output Undervoltage-Protection Measured at FB with respect to unloaded
VUVP -460 -340 mV
Threshold output voltage
IMVP-6.5, CLKEN pullup to 3.3V with
1.9k; measured from the time when FB
IMVP-6.5 CLKEN Startup Delay
reaches the boot target voltage (Note 3);
(Boot Time Period, CLKEN Pullup tBOOT 20 100 µs
the time needed for FB to reach this target
to 3.3V with 1.9k)
voltage is based on the slew rate set by
RTIME

6 _______________________________________________________________________________________
1-Phase Quick-PWM
Intel IMVP-6.5/GMCH Controllers
ELECTRICAL CHARACTERISTICS (continued)

MAX17528
(Circuit of Figure 1, VIN = 12V, VDD = VCC = 5V, CLKEN pullup to 3.3V with 1.9kΩ, SHDN = SLOW = ILIM = PGDIN = VCC, SKIP =
GNDS = PGND = GND, VFB = VCSP = VCSN = 1.200V, D0–D6 set for 1.20V (D0–D6 = 0001100). TA = -40°C to +105°C, unless other-
wise specified.) (Note 2)

PARAMETER SYMBOL CONDITIONS MIN MAX UNITS


IMVP-6.5, CLKEN pullup to 3.3V with 1.9k;
measured at startup from the time when 3 8 ms
CLKEN goes low

PWRGD Startup Delay GMCH, CLKEN = GND; measured from the


time when FB reaches the target voltage
(Note 3); the time needed for FB to reach 3 8 µs
this target voltage is based on the slew rate
set by RTIME
Measured at FB Lower threshold, falling
PWRGD and CLKEN (IMVP-6.5, with respect to -360 -240
edge (undervoltage)
CLKEN Pullup to 3.3V with unloaded output mV
1.9k) Threshold voltage, 15mV Upper threshold, rising
+140 +260
hysteresis (typ) edge (overvoltage)

IMVP-6.5 CLKEN Output IMVP-6.5: CLKEN pullup to 3.3V with


0.4 V
Low Voltage 1.9k, I SINK = 3mA
IMVP-6.5 CLKEN High
IMVP-6.5 = PGDIN = 5V, V CLKEN = 3.3V 4 µA
Leakage Current
PWRGD Output Low Voltage I SINK = 3mA 0.4 V
VCC Undervoltage Lockout Rising edge, 65mV typical hysteresis,
VUVLO(VCC) 4.0 4.5 V
(UVLO) Threshold controller disabled below this level
THERMAL PROTECTION
Measured at THRM with respect to VCC;
VRHOT Trip Threshold 29 31 %
falling edge; typical hysteresis = 100mV
VRHOT Output On-Resistance RVRHOT Low state 8 
VALLEY CURRENT LIMIT AND DROOP
Current-Limit Threshold Voltage VTIME - VILIM = 100mV 7 13
VLIMIT VCSP - VCSN mV
(Positive Adjustable) VTIME - VILIM = 500mV 45 55
Current-Limit Threshold Voltage
VCSP - VCSN, ILIM = VCC 20 25 mV
(Positive Default Preset)
Current-Limit Threshold Voltage
VLIMIT(NEG) VCSP - VCSN, nominally -125% of VLIMIT -5 +5 mV
(Negative) Accuracy
CSP, CSN Common-Mode
0 2 V
Input Range
DC Droop Amplifier (GMD) Offset (VCSP - VCSN) at IFB = 0 -1.0 +1.0 mV
IFB/(VCSP - VCSN); FB = VCSN = 0.45V to
DC Droop Amplifier (GMD)
2.0V, and (VCSP - VCSN) = -15.0mV to 588 612 µS
Transconductance
+15.0mV

_______________________________________________________________________________________ 7
1-Phase Quick-PWM
Intel IMVP-6.5/GMCH Controllers
MAX17528

ELECTRICAL CHARACTERISTICS (continued)


(Circuit of Figure 1, VIN = 12V, VDD = VCC = 5V, CLKEN pullup to 3.3V with 1.9kΩ, SHDN = SLOW = ILIM = PGDIN = VCC, SKIP =
GNDS = PGND = GND, VFB = VCSP = VCSN = 1.200V, D0–D6 set for 1.20V (D0–D6 = 0001100). TA = -40°C to +105°C, unless other-
wise specified.) (Note 2)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS


GATE DRIVERS
BST - LX forced High state (pullup) 2.5
DH Gate-Driver On-Resistance R ON(DH) 
to 5V Low state (pulldown) 2.0
High state (pullup) 2.0
DL Gate-Driver On-Resistance R ON(DL) 
Low state (pulldown) 0.7
Internal BST Switch
RBST IBST = 10mA, VDD = 5V 20 
On-Resistance
CURRENT MONITOR
Current-Monitor I IMON/(VCSP - VCSN),
Gm(IMON) 4.9 5.1 mS
Transconductance VCSN = 0.45V to 2.0V
Current-Monitor Offset
I IMON = 0 -1.5 +1.5 mV
Referred to V(CSP, CSN)
IMON Clamp Voltage VIMON I IMON = -1mA 1.05 1.15 V
LOGIC AND I/O
Logic-Input High Voltage VIH PGDIN 2.3 V
Logic-Input Low Voltage VIL PGDIN 1.0 V
Low-Voltage Logic-
VIHLV SHDN, SKIP, SLOW, D0–D6 0.67 V
Input High Voltage
Low-Voltage Logic-
VILLV SHDN, SKIP, SLOW, D0–D6 0.33 V
Input Low Voltage
CLKEN Logic-Input High Voltage
2.3 V
for IMVP-6.5 Startup
CLKEN Logic-Input Low Voltage
1.0 V
for GMCH
Note 2: Limits are 100% production tested at TA = +25°C. Maximum and minimum limits over temperature are guaranteed by design
and characterization.
Note 3: The equation for the target voltage VTARGET is:
VTARGET = the slew-rate-controlled version of VDAC, where VDAC = 0V for shutdown, VDAC = VBOOT (IMVP-6.5) or VVID
(GMCH) during startup, and VDAC = VVID otherwise (the VVID voltages for all possible VID codes are given in Table 2).
In pulse-skipping mode, the output rises by approximately 1.5% when transitioning from continuous conduction to no load.
Note 4: On-time and minimum off-time specifications are measured from 50% to 50% at the DH pin, with LX forced to 0V, BST forced
to 5V, and a 500pF capacitor from DH to LX to simulate external MOSFET gate capacitance. Actual in-circuit times can be
different due to MOSFET switching speeds.

8 _______________________________________________________________________________________
1-Phase Quick-PWM
Intel IMVP-6.5/GMCH Controllers

MAX17528
Typical Operating Characteristics
(TA = +25°C, unless otherwise noted. Circuit of Figure 1.)

0.9V OUTPUT EFFICIENCY 0.9V OUTPUT VOLTAGE 0.65V OUTPUT EFFICIENCY


vs. LOAD CURRENT vs. LOAD CURRENT vs. LOAD CURRENT
100 0.92 100
MAX17528 toc01

MAX17528 toc02

MAX17528 toc03
SKIP MODE
12V SKIP MODE PWM MODE
90 7V 90
0.90 12V
7V
OUTPUT VOLTAGE (V)
EFFICIENCY (%)

EFFICIENCY (%)
80 80
0.88
PWM MODE
70 70
20V
0.86 20V
60 60
SKIP MODE
PWM MODE
50 0.84 50
0.01 0.1 1 10 100 0 5 10 15 20 25 0.01 0.1 1 10
LOAD CURRENT (A) LOAD CURRENT (A) LOAD CURRENT (A)

0.65V OUTPUT VOLTAGE OUTPUT EFFICIENCY OUTPUT VOLTAGE


vs. LOAD CURRENT vs. LOAD CURRENT vs. LOAD CURRENT
0.67 100 1.12
MAX17528 toc04

MAX17528 toc05

MAX17528 toc06
SKIP MODE
PWM MODE 1.10
0.66 90 12V
7V SKIP MODE
SKIP MODE
OUTPUT VOLTAGE (V)

OUTPUT VOLTAGE (V)

1.08
EFFICIENCY (%)

0.65 80
1.06

1.04 PWM MODE


0.64 70
PWM MODE
20V 1.02
0.63 60
1.00

0.62 50 0.98
0 2 4 6 8 10 0.01 0.1 1 10 0 2 4 6 8 10
LOAD CURRENT (A) LOAD CURRENT (A) LOAD CURRENT (A)

SWITCHING FREQUENCY SWITCHING FREQUENCY VOUT = 0.9V NO-LOAD


vs. LOAD CURRENT vs. LOAD CURRENT SUPPLY CURRENT vs. INPUT VOLTAGE
500 300 100
MAX17528 toc07

MAX17528 toc08

MAX17528 toc09

SKIP MODE
450 IIN (PWM)
PWM MODE
250
SWITCHING FREQUENCY (kHz)

SWITCHING FREQUENCY (kHz)

400 PWM MODE ICC + IDD (PWM)


SUPPLY CURRENT (mA)

350
200 10
300
ICC + IDD (SKIP)
250 150
VOUT = 0.65V
200
100 1
150 IIN (SKIP)
VOUT = 0.9V
100 SKIP MODE
50
50 SKIP MODE
PWM MODE
0 0 0.1
0.01 0.1 1 10 100 0.01 0.1 1 10 6 9 12 15 18 21 24
LOAD CURRENT (A) INPUT VOLTAGE (V) INPUT VOLTAGE (V)

_______________________________________________________________________________________ 9
1-Phase Quick-PWM
Intel IMVP-6.5/GMCH Controllers
MAX17528

Typical Operating Characteristics (continued)


(TA = +25°C, unless otherwise noted. Circuit of Figure 1.)

VOUT = 0.65V NO-LOAD NO-LOAD SUPPLY CURRENT


SUPPLY CURRENT vs. INPUT VOLTAGE vs. INPUT VOLTAGE
100 100

MAX17528 toc10

MAX17528 toc11
IIN (PWM)
IIN (PWM)
ICC + IDD (PWM)
SUPPLY CURRENT (mA)

10 ICC + IDD (PWM) 10

IBIAS (mA)
ICC + IDD (SKIP) ICC + IDD (SKIP)

1 1
IIN (SKIP) IIN (SKIP)

SKIP MODE SKIP MODE


PWM MODE PWM MODE
0.1 0.1
6 9 12 15 18 21 24 6 9 12 15 18 21 24
INPUT VOLTAGE (V) INPUT VOLTAGE (V)

IMON CURRENT AND ERROR IMON TRANSCONDUCTANCE


vs. LOAD CURRENT DISTRIBUTION
MAX17528 toc12
20 75 90

MAX17528 toc13
+85°C SAMPLE SIZE = 100
80 +25°C
16 60
70
PERCENTAGE (%)

60
ERROR (%)

12 45
IMON (µA)

50

40
8 30
30

4 SKIP 15 20
PWM 10
0 0 0
4.90
4.92
4.94
4.96
4.98
5.00
5.02
5.04
5.06
5.08
5.10

0 2 4 6 8 10 12 14 16
VCSP-N (mV) IMON TRANSCONDUCTANCE (mS)

0.8125V OUTPUT VOLTAGE DISTRIBUTION Gm (FB) TRANSCONDUCTANCE DISTRIBUTION


70 60
MAX17528 toc14

MAX17528 toc15

+85°C SAMPLE SIZE = 100 +85°C SAMPLE SIZE = 100


+25°C +25°C
60 50
SAMPLE PERCENTAGE (%)

SAMPLE PERCENTAGE (%)

50
40
40
30
30
20
20

10 10

0 0
0.8075
0.8085
0.8095
0.8105
0.8115
0.8125
0.8135
0.8145
0.8155
0.8165
0.8175

590
592
594
596
598
600
602
604
606
608
610

TRANSCONDUCTANCE (µS)
OUTPUT VOLTAGE (V)

10 ______________________________________________________________________________________
1-Phase Quick-PWM
Intel IMVP-6.5/GMCH Controllers

MAX17528
Typical Operating Characteristics (continued)
(TA = +25°C, unless otherwise noted. Circuit of Figure 1.)

IMVP-6.5 SOFT-START IMVP-6.5 SOFT-START


WAVEFORM (UP TO CLKEN) WAVEFORM (UP TO PWRGD) IMVP-6.5 SHUTDOWN WAVEFORM
MAX17528 toc16 MAX17528 toc17 MAX17528 toc18

5V 5V A 5V
A A
0 0
0 5V B 3.3V
5V
B
0 0
0 B 5V 5V
C C
1V 0 0
1V
C 5V
D
D
0 0.9V
0 E
0 D 0
0 E
0 F

200µs/div 1ms/div 100µs/div


A. SHDN, 5V/div C. VOUT, 500mV/div A. SHDN, 5V/div D. VOUT, 500mV/div A. SHDN, 5V/div E. DL, 5V/div
B. CLKEN, 5V/div D. INDUCTOR CURRENT, B. PWRGD, 5V/div E. INDUCTOR CURRENT, B. CLKEN, 3.3V/div D. VOUT, 1V/div
10A/div C. CLKEN, 5V/div 10A/div C. PWRGD, 5V/div F. INDUCTOR CURRENT,
5A/div

LOAD-TRANSIENT RESPONSE
GMCH SOFT-START WAVEFORM GMCH SHUTDOWN WAVEFORM (IMVP-6.5 HFM MODE)
MAX17528 toc20 MAX17528 toc21
MAX17528 toc19

5V
5V A 23A
A 0 A
0 5V
B
5V 5.5A
B 0
0
5V
C 0.9V B
0.9V 0.863V
0
C 1.0815V
23A
0
C
D 0 D
0 0 E 5.5A

1ms/div 100µs/div 20µs/div

A. SHDN, 5V/div C. VOUT, 500mV/div A. SHDN, 5V/div D. VOUT, 500mV/div A. IOUT = 5.5A TO 23A, C. INDUCTOR CURRENT,
B. PWRGD, 5V/div D. INDUCTOR CURRENT, B. PWRGD, 5V/div E. INDUCTOR CURRENT, 10A/div 10A/div
10A/div C. DL, 5V/div 5A/div B. VOUT, 50mV/div

______________________________________________________________________________________ 11
1-Phase Quick-PWM
Intel IMVP-6.5/GMCH Controllers
MAX17528

Typical Operating Characteristics (continued)


(TA = +25°C, unless otherwise noted. Circuit of Figure 1.)

LOAD-TRANSIENT RESPONSE DPRSLPVR = HIGH, SLOW = LOW,


(IMVP-6.5 LFM MODE) LOAD-TRANSIENT RESPONSE VID5 TRANSITION
MAX17528 toc22 MAX17528 toc23 MAX17528 toc24

8A
9.5A 1V
A A A
1.5A 0
3.5A
1.0815V 1V
0.8375V
B B
0.825V B 1.03V
0.6V
8A
C
C
9.5A C
1.5A
3.5A 0

20µs/div 20µs/div 40µs/div

A. IOUT = 3.5A TO 9.5A, C. INDUCTOR CURRENT, A. IOUT = 1.5A TO 8A, C. INDUCTOR CURRENT, A. VID5, 1V/div C. INDUCTOR CURRENT,
5A/div 10A/div 5A/div 5A/div B. VOUT, 200mV/div 10A/div
B. VOUT, 20mV/div B. VOUT, 50mV/div IOUT = 1A

DPRSLPVR = HIGH, SLOW = HIGH, D0 12.5mV DYNAMIC VID D2 50mV DYNAMIC VID
VID5 TRANSITION CODE CHANGE CODE CHANGE
MAX17528 toc25 MAX17528 toc26 MAX17528 toc27

1V 5V 5V
A A A
0 0 0

1V
B 0.9V B 0.9V B
0.8875V
0.6V 0.85V

C C 0 C
0
0

40µs/div 10µs/div 10µs/div

A. VID5, 1V/div C. INDUCTOR CURRENT, A. D0, 5V/div C. INDUCTOR CURRENT, A. D2, 5V/div C. INDUCTOR CURRENT,
B. VOUT, 200mV/div 10A/div B. VOUT, 20mV/div 2A/div B. VOUT, 50mV/div 2A/div
IOUT = 1A

12 ______________________________________________________________________________________
1-Phase Quick-PWM
Intel IMVP-6.5/GMCH Controllers

MAX17528
Typical Operating Characteristics (continued)
(TA = +25°C, unless otherwise noted. Circuit of Figure 1.)

BIAS SUPPLY REMOVAL


OUTPUT OVERLOAD WAVEFORM (UVLO RESPONSE)
MAX17528 toc28 MAX17528 toc29

5V A
1V
0.9V
A
B
0
5V 0
B 5V
0 C
5V 0
C 5V
0 D
0
D 10A
E
0 0

100µs/div 200µs/div

A. VOUT, 500mV/div C. DL, 5V/div A. 5V BIAS SUPPLY, 5V/div D. PGOOD, 5V/div


B. PGOOD, 5V/div D. INDUCTOR CURRENT, B. VOUT, 500mV/div E. INDUCTOR CURRENT,
10A/div C. DL, 5V/div 10A/div

______________________________________________________________________________________ 13
1-Phase Quick-PWM
Intel IMVP-6.5/GMCH Controllers
Pin Description
MAX17528

PIN NAME FUNCTION


Current Monitor Output. The MAX17528 IMON output sources a current that is directly proportional
to the current-sense voltage as defined by:
I IMON = Gm(IMON) x (VCSP - VCSN)
where Gm(IMON) = 5mS (typ).
The IMON current is unidirectional (sources current out of IMON only) for positive current-sense
values. For negative current-sense voltages, the IMON current is zero.
Connect an external resistor between IMON and VSS_SENSE to create the desired IMON gain
based on the following equation:
1 IMON RIMON = 0.999V/(IMAX x R SENSE x Gm(IMON))
where IMAX is defined in the Current Monitor (IMON) section of the Intel IMVP-6.5 specification and
based on discrete increments (20A, 30A, 40A, etc.,), RSENSE is the typical effective value of the
current-sense element (sense resistor or inductor DCR) that is used to provide the current-sense
voltage, and Gm(IMON) is the typical transconductance amplifier gain as defined in the Electrical
Characteristics table.
The IMON voltage is internally clamped to a maximum of 1.1V (typ).
The transconductance amplifier and voltage clamp are internally compensated, so IMON cannot
directly drive large capacitance values. To filter the IMON signal, use an RC filter as shown in
Figure 1. IMON is pulled to ground when the MAX17528 is in shutdown.
Remote Ground-Sense Input. Connect directly to the CPU or GMCH VSS sense pin (ground sense)
or directly to the ground connection of the load. GNDS internally connects to a transconductance
2 GNDS
amplifier that adjusts the feedback voltage, compensating for voltage drops between the
regulator’s ground and the processor’s ground.
Output of the Voltage-Positioning Transconductance Amplifier. Connect a resistor, RFB, between
FB and the positive side of the feedback remote sense to set the steady-state droop based on the
voltage-positioning gain requirement.
RFB = RDROOP/(RSENSE x GMD)
where RDROOP is the desired voltage-positioning slope, GMD = 600µS typ and RSENSE is the
3 FB value of the current-sense resistor that is used to provide the (CSP, CSN), current-sense voltage. If
lossless sensing is used, R SENSE = RL. In this case, consider using a thermistor-resistor network
to minimize the temperature dependence of the voltage-positioning slope. Droop can be disabled
by shorting FB to the positive remote-sense point, but doing so increases the minimum ESR
requirement of the output capacitance for stability, and FB might therefore need to be driven by a
carefully designed feed-forward network. FB is high impedance in shutdown.
Negative Inductor Current-Sense Input. Connect CSN to the negative terminal of the inductor
current-sensing resistor or directly to the negative terminal of the inductor if the lossless DCR
4 CSN sensing method is used (see Figure 4).
Under VCC UVLO conditions and after soft-shutdown is completed, CSN is internally pulled to GND
through a 10 FET to discharge the output.
Positive Inductor Current-Sense Input. Connect CSP to the positive terminal of the inductor current-
5 CSP sensing resistor or directly to the positive terminal of the filtering capacitor used when the
lossless DCR sensing method is used (see Figure 4).
Active-Low Slew-Rate Select Input. This 1.0V logic input signal selects between the nominal and
slow (half of nominal rate) slew rates. When SLOW is forced high, the selected nominal slew rate is
set by the time resistance. When SLOW is forced low, the slew rate is reduced to half of the
6 SLOW nominal slew rate.
For IMVP-6.5 applications (CLKEN pullup to 3.3V with 1.9k), the fast slew rate is not needed.
Connect SLOW to GND.
For GMCH 2009 applications (CLKEN = GND), connect to the system GFXDPRSLPVR signal.

14 ______________________________________________________________________________________
1-Phase Quick-PWM
Intel IMVP-6.5/GMCH Controllers
Pin Description (continued)

MAX17528
PIN NAME FUNCTION
Pulse-Skipping Control Input. This 1.0V logic input signal indicates power usage and sets the
operating mode of the MAX17528. When SKIP is forced high, the controller is immediately set to
automatic pulse-skipping mode. The controller returns to forced-PWM mode when SKIP is forced low
and the output is in regulation. The PWRGD upper threshold is blanked during any downward output-
voltage transition that happens when the controller is in skip mode, and stays blanked until the
transition-related PWRGD blanking period is complete and the output reaches regulation.
7 SKIP
IMVP-6.5: The MAX17528 is in skip mode during startup and while in boot mode, but is in forced-PWM
mode during the transition from boot mode to VID mode plus 20µs, and during soft-shutdown,
irrespective of the skip logic level. Connect to the system DPRSLPVR signal.
GMCH 2009: The MAX17528 is in skip mode during startup, while in standby mode, and while exiting
standby mode, but is in forced-PWM mode during soft-shutdown, and while entering standby mode,
irrespective of the skip logic level. Connect to the system GFXDPRSLPVR signal.
Comparator Input for Thermal Protection. THRM connects to the positive input of an internal
comparator. The comparator’s negative input connects to an internal resistive voltage-divider that
8 THRM accurately sets the THRM threshold to 30% of the VCC voltage. Connect the output of a resistor
and thermistor-divider (between VCC and GND) to THRM with the values selected so the voltage at
THRM falls below 30% of VCC (1.5V when VCC = 5V) at the desired high temperature.
Switching Frequency Setting Input. An external resistor between the input power source and this
pin sets the switching period (tSW = 1/f SW) according to the following equation:
t SW = 16.3pF x (RTON + 6.5k)
9 TON
TON becomes high impedance in shutdown to reduce the input quiescent current. If the TON
current is less than 10µA, the MAX17528 disables the controller, sets the TON open fault latch,
and pulls DL and DH low.
Open-Drain Power-Good Output. PWRGD is high impedance after output-voltage transitions (except
during power-up and power-down) if FB is in regulation.
During startup, PWRGD is held low.
IMVP-6.5: PWRGD continues to be low while the output is at the boot voltage, and stays low until
5ms (typ) after CLKEN goes low.
GMCH 2009: PWRGD starts monitoring the FB voltage 5ms (typ) after startup (from shutdown or
standby mode) is complete. PWRGD is also held low while in standby mode, and while entering
10 PWRGD and exiting standby mode.
PWRGD is forced low during soft-shutdown and while in shutdown. PWRGD is forced high
impedance whenever the slew-rate controller is active (output-voltage transitions), and continues
to be forced high impedance for an additional 20µs after the transition is completed.
The PWRGD upper threshold is blanked during any downward output-voltage transition that
happens when the MAX17528 is in skip mode, and stays blanked until the transition-related
PWRGD blanking period is complete and the output reaches regulation.
A pullup resistor on PWRGD causes additional finite shutdown current.
Active-Low Shutdown Control Input. Connect to VCC for normal operation. Connect to ground to put
the controller into the low-power 1µA (max) shutdown state. During startup, the controller ramps up
the output voltage at 1/8 the slew rate set by the TIME resistor to the target voltage defined by the
application circuit:
11 SHDN For IMVP-6.5 (CLKEN pullup to 3.3V with 1.9k), the startup target is the 1.1V boot voltage.
For GMCH 2009 (CLKEN = GND), the startup target is the voltage set by the VID inputs.
During the shutdown transition, the MAX17528 softly ramps down the output voltage at 1/8 the
slew rate set by the TIME resistor. Forcing SHDN to 11V~13V disables UVP, thermal shutdown, and
clears the fault latches.

______________________________________________________________________________________ 15
1-Phase Quick-PWM
Intel IMVP-6.5/GMCH Controllers
Pin Description (continued)
MAX17528

PIN NAME FUNCTION


Dual-Function GMCH/IMVP-6.5 Select Input and Active-Low IMVP-6.5 CPU Clock Enable Open-
Drain Output. Connect to system 3.3V supply through pullup resistors for proper IMVP-6.5
operation. CLKEN voltage has to be higher than 2.3V before SHDN is pulled high. Connect to GND
to select the Intel GMCH feature set. This active-low logic output indicates when the feedback
voltage is in regulation. The MAX17528 forces CLKEN low during dynamic VID transitions and for
12 CLKEN
an additional 20µs after the VID transition is completed. CLKEN is the inverse of PWRGD, except
for the 5ms PWRGD startup delay period after CLKEN is pulled low. See the startup timing diagram
(Figure 9). The CLKEN upper threshold is blanked during any downward output-voltage transition
that happens when the MAX17528 are in skip mode, and stays blanked until the transition-related
PWRGD blanking period is complete and the output reaches regulation.
13 GND Analog Ground
Low-Voltage (1.0V Logic) VID DAC Code Inputs. The D0–D6 inputs do not have internal pullups.
These 1.0V logic inputs are designed to interface directly with the CPU. The output voltage is set
by the VID code indicated by the logic-level voltages on D0–D6 (see Table 2).
The 1111111 code corresponds to standby mode. When this code is detected, the MAX17528
enters standby mode while in forced-PWM mode, and slews to 0V at 1/8 the slew rate set by the
14–20 D0–D6 TIME resistor. After slewing to 0V, the IC enters skip mode (DH and DL low). If D6–D0 is changed
from 1111111 to a different code, the MAX17528 exits standby mode (while in skip mode) and
slews the output voltage to the target voltage set by the VID code at 1x the slew rate set by the
TIME resistor. Note that the standby supply current consumed by the MAX17528 is the same as its
quiescent supply current, because no analog blocks are turned off. This is necessary because of
the fast wake-up requirement.
Power Ground. Ground connection for the DL driver. Also used as an input to the MAX17528’s zero-
21 PGND
crossing comparator.
Low-Side Gate-Driver Output. DL swings from PGND to VDD. DL is forced low after shutdown. DL is
22 DL
forced low in skip mode after detecting an inductor current zero-crossing.
Supply Voltage Input for the DL Driver. VDD is also the supply voltage used to internally recharge
23 VDD the BST flying capacitor during the time DL is high. Connect VDD to the 4.5V to 5.5V system supply
voltage. Bypass VDD to PGND with a 1µF or greater ceramic capacitor.
Boost Flying Capacitor Connection. BST provides the upper supply rail for the DH high-side gate
24 BST driver. An internal switch between VDD and BST charges the flying capacitor while the low-side
MOSFET is on (DL pulled high and LX pulled to ground).
Inductor Connection. LX is the internal lower supply rail for the DH high-side gate driver. Also used
25 LX
as an input to the MAX17528’s zero-crossing comparator.
26 DH High-Side Gate-Driver Output. DH swings from LX to BST. The controller pulls DH low in shutdown.
IMVP-6.5 Power-Good Logic Input. PGDIN indicates the power status of other system rails used to
power the chipset and CPU VCCP supplies. For the IMVP-6.5 (CLKEN pullup to 3.3V with 1.9k), the
MAX17528 powers up and remains at the boot voltage (VBOOT) as long as PGDIN remains low.
When PGDIN is forced high, the MAX17528 transitions the output to the voltage set by the VID
27 PGDIN code, and CLKEN is allowed to go low.
If PGDIN is pulled low at any time, the MAX17528 immediately forces CLKEN high and PWRGD low
and sets the output to the boot voltage. The output remains at the boot voltage until the system
either disables the controller or until PGDIN goes high again.
For GMCH 2009 applications (CLKEN = GND), connect PGDIN to the 5V bias supply.

16 ______________________________________________________________________________________
1-Phase Quick-PWM
Intel IMVP-6.5/GMCH Controllers
Pin Description (continued)

MAX17528
PIN NAME FUNCTION
Active-Low Open-Drain Output of Internal Comparator. VRHOT is pulled low when the voltage at
28 VRHOT
THRM goes below 1.5V (30% of VCC). VRHOT is high-impedance in shutdown.
Slew-Rate Adjustment Pin. TIME regulates to 2.0V and the load current determines the slew rate of
the internal error-amplifier target. The sum of the resistance between TIME and GND (RTIME)
determines the nominal slew rate:
Slew rate = (12.5mV/µs) x (71.5k/RTIME)
29 TIME The guaranteed RTIME range is between 35.7k and 178k. This nominal slew rate applies to VID
transitions and to the transition from boot mode to VID. If the VID DAC inputs are clocked, the slew
rate for all other VID transitions is set by the rate at which they are clocked, up to a maximum slew
rate equal to the nominal slew rate defined above.
The startup and shutdown slew rates are always 1/8 of nominal slew rate to minimize surge currents.
If SLOW is high, the slew rate is reduced to 1/2 of nominal.
Valley Current-Limit Adjustment Input. The valley current-limit threshold voltage at CSP to CSN
equals precisely 1/10 the differential TIME to ILIM voltage over a 0.1V to 0.5V range (10mV to 50mV
30 ILIM current-sense range). The negative current-limit threshold is nominally -125% of the corresponding
valley current-limit threshold. Connect ILIM directly to VCC to set the default current-limit threshold
setting of 22.5mV (typ) nominal.
31 VCC Controller Supply Voltage. Connect to a 4.5V to 5.5V source. Bypass to GND with 1µF minimum.
Integrator Capacitor Connection. Connect a capacitor (CCCV) from CCV to GND to set the
integration time constant. Choose the capacitor value according to:
16 x (CCCV/Gm(CCV)) x f SW >> 1
where Gm(CCV) = 320µS (max) is the integrator’s transconductance and fSW is the switching
32 CCV
frequency set by the RTON value.
The integrator is internally disabled during any downward output-voltage transition that occurs in
pulse-skipping mode, and remains disabled until the transition blanking period expires and the
output reaches regulation (error amplifier transition detected).
Exposed Pad (Back Side) and Analog Ground. Internally connected to GND. Connect to the ground
— EP (GND)
plane through a thermally enhanced via.

______________________________________________________________________________________ 17
1-Phase Quick-PWM
Intel IMVP-6.5/GMCH Controllers
MAX17528

R1
10Ω
11 31 5V BIAS
ON OFF (VRON) SHDN VCC
C1 C2 INPUT
6
SLOW 1.0µF 1.0µF
AGND
7 AGND
SKIP
23 PWR
VDD
SYSTEM I/O 27
PGDIN SWITCHING FREQUENCY (fSW = 1/tSW):
POWER-GOOD RTON tSW = 16.3pF x (RTON + 6.5kΩ)
200kΩ
14 9 INPUT
D0 TON
15 7V TO 24V
D1
16 RBST CIN
D2
17 0Ω
D3 24
BST
18 PWR
D4 26
19 DH NHI
D5 L1
20 CBST 0.36µH
D6 0.1µF 0.8mΩ
25 CORE
LX
VALLEY CURRENT LIMIT SET BY TIME TO ILIM OUTPUT
D1
VLIMIT = 0.2V x R2/(R2 + R3) 22 COUT
DL R10 R12
SLEW RATE SET BY TIME BIAS CURRENT NLO 10kΩ
1.00kΩ
dV/dt = 12.5mV/µs x 71.5kΩ/(R2 + R3) 21
PGND PWR
30
ILIM PWR
R3 5 R11 NTC1
64.9kΩ CSP
29 CCSP 1.50kΩ 10kΩ
TIME OPEN B = 4500
CSENSE
R2 0.47µF
5.90kΩ
AGND AGND
4
CSN
CCSN
3.3V DCR THERMAL COMPENSATION
OPEN

RVRHOT 1.9kΩ RPWRGD MAX17528 AGND


10kΩ 10kΩ
LOAD-LINE ADJUSTMENT:
10 RFB = RDROOP/(RSENSE x 600µs)
PWRGD
12 RFB R15
CLKEN 4.53kΩ 10Ω
28 1%
VRHOT 3
FB VCC_SENSE
RTHRM C9 R13
7.87kΩ 1000pF 10Ω REMOTE-SENSE
8
VCC THRM INPUTS
NTC2 2 AGND
100kΩ GNDS VSS_SENSE
CCCV C10
B = 4700 R14
100pF 1000pF R16
32 10Ω
CCV 10Ω
R3
1kΩ AGND AGND
13
CPU 1 GND
IMON
IMON AGND REMOTE-SENSE FILTERS PWR
C8 R4 GND CATCH RESISTORS
AGND
0.022µF 13.0kΩ REQUIRED WHEN CPU
EP NOT POPULATED
VSS_SENSE
RGND
AGND 0Ω
PWR

Figure 1. IMVP-6.5 CPU Core Application Circuit

18 ______________________________________________________________________________________
1-Phase Quick-PWM
Intel IMVP-6.5/GMCH Controllers

MAX17528
Table 1. IMVP-6.5 Component Selection
DESIGN AUBURNDALE AUBURNDALE AUBURNDALE AUBURNDALE
PARAMETERS IMVP-6.5 ULV IMVP-6.5 ULV RENDER GMCH SV RENDER GMCH ULV
Circuit Figure 1 Figure 1 Figure 2 Figure 2
Input-Voltage Range 7V to 20V 5V 7V to 20V 7V to 20V
Maximum Load Current 20A 20A 15A 7A
(TDC Current) (15A) (15A) (10A) (5A)
14A 14A 12A 5A
Transient Load Current
(10A/µs) (10A/µs) (10A/µs) (10A/µs)
Load Line 3mV/A 3mV/A 7mV/A 7mV/A
POC Setting 20A 20A 20A 20A
COMPONENTS
200k 120k 200k 200k
TON Resistance (RTON)
(fSW = 300kHz) (fSW = 500kHz) (fSW = 300kHz) (fSW = 300kHz)
NEC/TOKIN NEC/TOKIN NEC/TOKIN NEC/TOKIN
Inductance (L) MPC1055LR36 MPC1055LR36 MPCG0740LR42 MPC1040LR88C
0.36µH, 32A, 0.8m 0.36µH, 32A, 0.8m 0.42µH, 20A, 1.55m 0.88µH, 24A, 2.3m
Siliconix Siliconix Siliconix Siliconix
High-Side MOSFET (NH) 1x Si4386DY 1x Si4386DY 1x Si4386DY 1x Si4386DY
7.8m/9.5m (typ/max) 7.8m/9.5m (typ/max) 7.8m/9.5m (typ/max) 7.8m/9.5m (typ/max)
Siliconix Siliconix Siliconix Siliconix
Low-Side MOSFET (NL) 2x Si4642DY 2x Si4642DY 1x Si4642DY 1x Si4642DY
3.9m/4.7m (typ/max) 3.9m/4.7m (typ/max) 3.9m/4.7m (typ/max) 3.9m/4.7m (typ/max)
4x 330µF, 6m, 2.5V 4x 330µF, 6m, 2.5V
1x 470µF, 6m, 2.5V 1x 220µF, 7m, 2V
Panasonic Panasonic
Output Capacitors SANYO 2R5TPD470M6L SANYO 2TPF220M7L
EEFSX0D0D331XR EEFSX0D0D331XR
(COUT) 10x 10µF, 6V ceramic 10x 10µF, 6V ceramic
32x 10µF, 6V ceramic 32x 10µF, 6V ceramic
(0805) (0805)
(0805) (0805)
4x 10µF, 25V ceramic 6x 10µF, 6V ceramic 2x 10µF, 25V ceramic 2x 10µF, 25V ceramic
Input Capacitors (CIN)
(1210) (0805) (1210) (1210)
TIME-ILIM Resistance
5.90k 5.90k 6.65k 6.65k
(R1)
ILIM-GND Resistance
64.9k 64.9k 64.9k 64.9k
(R2)
FB Resistance (RFB) 4.53k 4.53k 10.0k 5.62k
IMON Resistance (R4) 13.0k 13.0k 7.68k 4.42k
LX-CSP Resistance (R5) 1.00k 1.00k 1.50k 0.806k
CSP-CSN Series
1.50k 1.50k 1.50k 1.20k
Resistance (R6)
Parallel NTC
10.0k 10.0k 4.02k 15.0k
Resistance (R7)
10k NTC B = 3380 10k NTC B = 3380 10k NTC B = 3380 10k NTC B = 3380
DCR Sense NTC (NTC1)
TDK NTCG163JH103F TDK NTCG163JH103F TDK NTCG163JH103F TDK NTCG163JH103F
DCR Sense 0.47µF, 6V ceramic 0.47µF, 6V ceramic 0.22µF, 6V ceramic 0.47µF, 6V ceramic
Capacitance (CSENSE) (0805) (0805) (0805) (0805)

______________________________________________________________________________________ 19
1-Phase Quick-PWM
Intel IMVP-6.5/GMCH Controllers
MAX17528

R1
10Ω
11 31 5V BIAS
ON OFF (VRON) SHDN VCC
C1 C2 INPUT
6 1.0µF 1.0µF
SLOW
7 AGND
SKIP
23 PWR
VDD
27
PGDIN SWITCHING FREQUENCY (fSW = 1/tSW):
RTON tSW = 16.3pF x (RTON + 6.5kΩ)
14 200kΩ
D0 9 INPUT
15 TON
D1 7V TO 24V
16
D2 RBST CIN
17 0Ω
VID INPUTS D3 24
18 BST
D4
19 26 PWR
D5 DH NHI
20 L1
D6 CBST 0.42µH
0.1µF 1.55mΩ
VALLEY CURRENT LIMIT SET BY TIME TO ILIM 25 GFX
LX
VLIMIT = 0.2V x R2/(R2 + R3) OUTPUT
D1
SLEW RATE SET BY TIME BIAS CURRENT 22 COUT
dV/dt = 12.5mV/µs x 71.5kΩ/(R2 + R3) DL R10 R12
NLO 1.50kΩ 4.02kΩ
30 21
R3 ILIM PGND PWR
64.9kΩ
29 PWR
TIME 5 R11 NTC1
CSP
R2 CCSP 1.50kΩ 10kΩ
6.65kΩ OPEN CSENSE B = 4500
AGND
0.22µF

4 AGND
3.3V CSN
CCSN
RVRHOT RPWRGD OPEN DCR THERMAL COMPENSATION
10kΩ 10kΩ MAX17528
10 AGND
PWRGD
LOAD-LINE ADJUSTMENT:
12
CLKEN RFB = RDROOP/(RSENSE x 600µs)
RFB R15
10.0kΩ 10Ω
28 1%
VRHOT 3
FB VCCGFX_SENSE
RTHRM C9 R13
7.87kΩ 1000pF 10Ω REMOTE-SENSE
8
VCC THRM INPUTS
NTC2 2 AGND
100kΩ GNDS VSSGFX_SENSE
CCCV C10
B = 4700 R14
100pF 1000pF R16
32 10Ω
CCV 10Ω
R3
6.2kΩ AGND AGND
13
GFX 1 GND
IMON
IMON AGND REMOTE-SENSE FILTERS PWR
C8 R4 GND CATCH RESISTORS
AGND
0.022µF 7.68kΩ REQUIRED WHEN CPU
EP NOT POPULATED
VSSGFX_SENSE
RGND
AGND 0Ω
PWR

Figure 2. GMCH (Render Core) Application Circuit

20 ______________________________________________________________________________________
1-Phase Quick-PWM
Intel IMVP-6.5/GMCH Controllers
Detailed Description A 96.75kΩ to 303.25kΩ corresponds to switching peri-

MAX17528
ods of 1.67µs (600kHz) to 5µs (200kHz), respectively.
Free-Running, Constant On-Time High-frequency (over 500kHz) operation optimizes the
Controllers with Input Feed-Forward application for the smallest component size, trading off
The Quick-PWM control architecture is a pseudo-fixed- efficiency due to higher switching losses. This may be
frequency, constant-on-time, current-mode regulator acceptable in ultra-portable devices where the load
with voltage feed-forward (Figure 3). This architecture currents are lower and the controller is powered from a
relies on the output filter capacitor’s ESR and the load lower voltage supply. Low-frequency (under 300kHz)
regulation to provide the proper current-mode compen- operation offers the best overall efficiency at the
sation, so the resulting feedback ripple voltage provides expense of component size and board space.
the PWM ramp signal. The control algorithm is simple:
the high-side switch on-time is determined solely by a TON Open-Circuit Fault Protection
one-shot whose period is inversely proportional to input The TON input includes open-circuit protection to avoid
voltage, and directly proportional to the feedback volt- long, uncontrolled on-times that could result in an over-
age (see the On-Time One-Shot section). Another one- voltage condition on the output. The MAX17528 detects
shot sets a minimum off-time. The on-time one-shot an open-circuit fault if the TON current drops below
triggers when the error comparator goes low (the feed- 10µA for any reason—the TON resistor (R TON ) is
back voltage drops below the target voltage), the unpopulated, a high resistance value is used, the input
inductor current is below the valley current-limit thresh- voltage is low, etc. Under these conditions, the
old, and the minimum off-time one-shot times out. MAX17528 stops switching (DH and DL pulled low) and
immediately sets the fault latch. Toggle SHDN or cycle
+5V Bias Supply (VCC and VDD) the VCC power supply below 0.5V to clear the fault latch
The Quick-PWM controller requires an external +5V bias and reactivate the controller.
supply in addition to the battery. Typically, this +5V bias
supply is the notebook’s 95%-efficient, +5V system sup- On-Time One-Shot
ply. Keeping the bias supply external to the IC improves The core contains a fast, low-jitter, adjustable one-shot
efficiency and eliminates the cost associated with the that sets the high-side MOSFET’s on-time. The one-shot
+5V linear regulator that would otherwise be needed to varies the on-time in response to the input and feedback
supply the PWM circuit and gate drivers. If stand-alone voltages. The main high-side switch on-time is inversely
capability is needed, the +5V bias supply can be gen- proportional to the input voltage as measured by the RTON
erated with an external linear regulator. input, and proportional to the feedback voltage (VFB):
The +5V bias supply must provide V CC (PWM con- ⎛V ⎞
tON = tSW ⎜ FB ⎟
troller) and VDD (gate-drive power), so the maximum ⎝ VIN ⎠
current drawn is:
where the switching period (tSW = 1/fSW) is set by the
(
IBIAS = ICC + fSW QG(LOW) + QG(HIGH) ) resistor between VIN and TON.
where ICC is provided in the Electrical Characteristics This algorithm results in a nearly constant switching fre-
table, fSW is the switching frequency, and QG(LOW) and quency despite the lack of a fixed-frequency clock
Q G(HIGH) are the MOSFET data sheet’s total gate- generator. The benefits of a constant switching fre-
charge specification limits at VGS = 5V. quency are twofold: first, the frequency can be select-
ed to avoid noise-sensitive regions, such as the 455kHz
VIN and VDD can be connected if the input power source IF band; second, the inductor ripple-current operating
is a fixed +4.5V to +5.5V supply. If the +5V bias supply is point remains relatively constant, resulting in easy
powered up prior to the battery supply, the enable signal design methodology and predictable output voltage
(SHDN going from low to high) must be delayed until the ripple. The on-time one-shots have good accuracy at
battery voltage is present to ensure startup. the operating points specified in the Electrical
Switching Frequency (TON) Characteristics table. On-times at operating points far
Connect a resistor (RTON) between TON and VIN to set removed from the conditions specified in the Electrical
the switching period (tSW = 1/fSW): Characteristics table can vary over a wider range.
tSW = 16.3pF x (RTON + 6.5kΩ)

______________________________________________________________________________________ 21
1-Phase Quick-PWM
Intel IMVP-6.5/GMCH Controllers
MAX17528

CSP CURRENT IMON


10x MONITOR Gm(IMON)
CSN
5mS
ILIM MINIMUM
OFF-TIME
TIME
Q TRIG
MAX17528
ONE-SHOT ON-TIME TON
FB ONE-SHOT
Q TRIG
VCC

BST
REF R
(2.0V) Q
DH
S
GND LX
S
D0–D6
Q
CURRENT PGND
PGDIN DAC R
SCALING LX
1mV VDD
SHDN

DL
TARGET

PGND
FAULT
REF
SKIP

500kΩ MODE SKIP

CCV SLEW_RATE CONTROL


SLOW
Gm(CCV)
BLANK

TARGET
160µS
+ 200mV
R
CLKEN
60µs
REF STARTUP
FB TARGET DELAY
- 300mV 5ms
CSP STARTUP PWRGD
DELAY
TARGET
Gm(FB) + 300mV
600µS CSN
GNDS
FAULT
VRHOT
TARGET
Gm(GNDS) 0.3 x VCC
- 400mV

THRM

Figure 3. Functional Diagram

22 ______________________________________________________________________________________
1-Phase Quick-PWM
Intel IMVP-6.5/GMCH Controllers
On-times translate only roughly to switching frequen- requirements (RCS x IOUT(MAX) < 50mV), and the time

MAX17528
cies. The on-times guaranteed in the Electrical constant of the RC network should match the inductor’s
Characteristics table are influenced by switching time constant (L/RDCR):
delays in the external high-side MOSFET. Resistive
losses, including the inductor, both MOSFETs, and ⎛ R2 ⎞
RCS = ⎜ ⎟R
printed-circuit board (PCB) copper losses in the output ⎝ R1+ R2 ⎠ DCR
and ground tend to raise the switching frequency as
the load current increases. Under light-load conditions, and:
the dead-time effect increases the effective on-time,
reducing the switching frequency. It occurs only during L ⎡1 1⎤
forced-PWM operation and dynamic output-voltage RDCR = ⎢ R1 + R2 ⎥
transitions when the inductor current reverses at light- CEQ ⎣ ⎦
or negative-load currents. With reversed inductor cur-
rent, the inductor’s EMF causes LX to go high earlier where RCS is the required current-sense resistance, and
than normal, extending the on-time by a period equal to RDCR is the inductor’s series DC resistance. Use the
the DH-rising dead time. For loads above the critical worst-case inductance and RDCR values provided by
conduction point, where the dead-time effect is no the inductor manufacturer, adding some margin for the
longer a factor, the actual switching frequency is: inductance drop over temperature and load. To mini-
mize the current-sense error due to the current-sense
fSW =
(VOUT + VDIS ) inputs’ bias current (ICSP), choose R1 || R2 to be less
t ON (VIN + VDIS − VCHG ) than 2kΩ and use the above equation to determine the
sense capacitance (CEQ). Choose capacitors with 5%
where VDIS is the sum of the parasitic voltage drops in tolerance and resistors with 1% tolerance specifications.
the inductor discharge path, including synchronous rec- Temperature compensation is recommended for this
tifier, inductor, and PCB resistances; VCHG is the sum of current-sense method. See the Voltage Positioning and
the parasitic voltage drops in the inductor charge path, Loop Compensation section for detailed information.
including high-side switch, inductor, and PCB resis- When using a current-sense resistor for accurate output-
tances; and tON is the on-time as determined above. voltage positioning, the circuit requires a differential RC
Current Sense filter to eliminate the AC voltage step caused by the
The output current is differentially sensed by the high- equivalent series inductance (LESL) of the current-sense
impedance current-sense inputs (CSP and CSN). Low- resistor (see Figure 4). The ESL-induced voltage step
offset amplifiers are used for voltage-positioning gain, does not affect the average current-sense voltage, but
current-limit protection, and current monitoring. Sensing results in a significant peak current-sense voltage error
the current at the output offers advantages, including less that results in unwanted offsets in the regulation voltage
noise sensitivity and the flexibility to use either a current- and results in early current-limit detection. Similar to the
sense resistor or the DC resistance of the power inductor. inductor DCR sensing method, the RC filter’s time con-
stant should match the L/R time constant formed by the
Using the DC resistance (RDCR) of the inductor allows current-sense resistor’s parasitic inductance:
higher efficiency. In this configuration, the initial toler-
ance and temperature coefficient of the inductor’s DCR LESL
must be accounted for in the output-voltage droop- = CEQR1
RSENSE
error budget and current monitor. This current-sense
method uses an RC filtering network to extract the cur-
rent information from the inductor (see Figure 4). The where LESL is the equivalent series inductance of the
resistive divider used should provide a current-sense current-sense resistor, R SENSE is the current-sense
resistance (RCS) low enough to meet the current-limit resistance value, CEQ and R1 are the time-constant
matching components.

______________________________________________________________________________________ 23
1-Phase Quick-PWM
Intel IMVP-6.5/GMCH Controllers
MAX17528

INPUT (VIN)
CIN
NH SENSE RESISTOR
DH
L LESL RSENSE
LX
NL
DL DL COUT LSENSE
MAX17528 CEQR1 =
RSENSE
PGND
R1 CEQ

CSP
CSN

A) OUTPUT SERIES RESISTOR SENSING

INPUT (VIN)
CIN
NH INDUCTOR
DH
L DCR
LX
NL
DL COUT

MAX17528 PGND
DL R1 R2 RCS = (R1R2+ R2) RDCR

L 1 1
CSP CEQ
RDCR =
CEQ [ R1
+
R2 ]
CSN FOR THERMAL COMPENSATION:
R2 SHOULD CONSIST OF AN NTC RESISTOR IN
B) LOSSLESS INDUCTOR SENSING SERIES WITH A STANDARD THIN-FILM RESISTOR.

Figure 4. Current-Sense Methods

Current Limit The positive valley current-limit threshold voltage at


The current-limit circuit employs a “valley” current-sens- CSP to CSN equals precisely 1/10 of the differential
ing algorithm that uses a current-sense element (see TIME to ILIM voltage over a 0.1V to 0.5V range (10mV
Figure 4) between the current-sense inputs (CSP to to 50mV current-sense range). Connect ILIM directly to
CSN) to detect the inductor current. If the differential VCC to set the default current-limit threshold setting of
current-sense voltage exceeds the current-limit thresh- 22.5mV nominal.
old, the PWM controller does not initiate a new cycle The negative current-limit threshold (forced-PWM mode
until the inductor current drops below the valley current- only) is nominally -125% of the corresponding valley
limit threshold. Since only the valley current level is current-limit threshold. When the inductor current drops
actively limited, the actual peak inductor current below the negative current limit, the controller immedi-
exceeds the valley current-limit threshold by an amount ately activates an on-time pulse—DL turns off, and DH
equal to the inductor ripple current. Therefore, the exact turns on—allowing the inductor current to remain above
current-limit characteristic and maximum load capability the negative current threshold.
are a function of the current-sense impedance, inductor
value, and battery voltage. When combined with the Carefully observe the PCB layout guidelines to ensure
undervoltage protection circuit, this current-limit method that noise and DC errors do not corrupt the current-sense
is effective in almost every circumstance. signals seen by the current-sense inputs (CSP, CSN).

24 ______________________________________________________________________________________
1-Phase Quick-PWM
Intel IMVP-6.5/GMCH Controllers
Feedback connects to an amplifier that adds an offset directly to

MAX17528
The nominal no-load output voltage (V TARGET ) is the feedback voltage, effectively adjusting the output
defined by the VID-selected DAC voltage (see Table 2) voltage to counteract the voltage drop in the ground
plus the remote ground-sense adjustment (VGNDS) as path. Connect the voltage-positioning resistor (RFB) and
defined in the following equation: ground-sense (GNDS) input directly to the processor’s
remote-sense outputs as shown in Figures 1 and 2.
VTARGET = VFB = VDAC + VGNDS
Integrator Amplifier
where VDAC is the selected VID voltage. On startup, An integrator amplifier forces the DC average of the FB
IMVP-6.5 (CLKEN pullup to 3.3V with 1.9kΩ) applica- voltage to equal the target voltage. This transconduc-
tions slew the target voltage from ground to the preset tance amplifier integrates the feedback voltage and
1.1V boot voltage and GMCH (CLKEN = GND) applica- provides a fine adjustment to the regulation voltage
tions slew the target voltage directly to the VID-selected (Figure 3), allowing accurate DC output-voltage regula-
DAC target. tion regardless of the output ripple voltage. The integra-
tor amplifier has the ability to shift the output voltage by
Voltage-Positioning Amplifier ±50mV (typ). The integration time constant can be set
(Steady-State Droop) easily with an external compensation capacitor
The MAX17528 includes a transconductance amplifier between CCV and analog ground, with the minimum
for adding gain to the voltage-positioning sense path. recommended CCV capacitor value determined by:
The amplifier’s input is generated by the differential CCCV >> Gm(CCV)/(16π x fSW)
current-sense inputs that sense the inductor current by
measuring the voltage across either current-sense where G m(CCV) = 320µS (max) is the integrator’s
resistors or the inductor’s DCR. The amplifier’s output transconductance and fSW is the switching frequency
connects directly to the regulator’s voltage-positioned set by the RTON resistance.
feedback input (FB), so the resistance between FB and The MAX17528 disables the integrator by connecting
the output-voltage sense point determines the voltage- the amplifier inputs together at the beginning of all
positioning gain: downward VID transitions done in pulse-skipping mode
(SKIP = high). The integrator remains disabled until
VOUT = VTARGET − RFBIFB 20µs after the transition is completed (the internal tar-
get settles) and the output is in regulation (edge detect-
where the target voltage (VTARGET = VFB) is defined by ed on the error comparator).
the selected VID code (Table 3 for IMVP6 or Table 4 for
GMCH), and the FB amplifier’s output current (IFB) is DAC Inputs (D0–D6)
determined by the sum of the current-sense voltages: The digital-to-analog converter (DAC) programs the
output voltage using the D0–D6 inputs. D0–D6 are low-
IFB = Gm(FB) (VCSP − VCSN ) voltage (1.0V) logic inputs designed to interface direct-
ly with the CPU. Do not leave D0–D6 unconnected.
where G m(FB) is typically 600µS as defined in the Changing D0–D6 initiates a transition to a new output-
Electrical Characteristics table. voltage level. Change D0–D6 together, avoiding
greater than 20ns skew between bits. Otherwise, incor-
Differential Remote Sense rect DAC readings can cause a partial transition to the
The MAX17528 includes differential, remote-sense wrong voltage level followed by the intended transition
inputs to eliminate the effects of voltage drops along the to the correct voltage level, lengthening the overall tran-
PCB traces and through the processor’s power pins. sition time. The available DAC codes and resulting out-
The feedback-sense node connects to the voltage-posi- put voltages are compatible with the Intel IMVP-6.5/
tioning resistor (RFB). The ground-sense (GNDS) input GMCH specifications (Table 2).

______________________________________________________________________________________ 25
1-Phase Quick-PWM
Intel IMVP-6.5/GMCH Controllers
Table 2. IMVP-6.5 Output Voltage VID DAC Codes
MAX17528

IMVP-6.5 IMVP-6.5
OUTPUT OUTPUT
D6 D5 D4 D3 D2 D1 D0 D6 D5 D4 D3 D2 D1 D0
VOLTAGE VOLTAGE
(V) (V)
0 0 0 0 0 0 0 1.5000 1 0 0 0 0 0 0 0.7000
0 0 0 0 0 0 1 1.4875 1 0 0 0 0 0 1 0.6875
0 0 0 0 0 1 0 1.4750 1 0 0 0 0 1 0 0.6750
0 0 0 0 0 1 1 1.4625 1 0 0 0 0 1 1 0.6625
0 0 0 0 1 0 0 1.4500 1 0 0 0 1 0 0 0.6500
0 0 0 0 1 0 1 1.4375 1 0 0 0 1 0 1 0.6375
0 0 0 0 1 1 0 1.4250 1 0 0 0 1 1 0 0.6250
0 0 0 0 1 1 1 1.4125 1 0 0 0 1 1 1 0.6125
0 0 0 1 0 0 0 1.4000 1 0 0 1 0 0 0 0.6000
0 0 0 1 0 0 1 1.3875 1 0 0 1 0 0 1 0.5875
0 0 0 1 0 1 0 1.3750 1 0 0 1 0 1 0 0.5750
0 0 0 1 0 1 1 1.3625 1 0 0 1 0 1 1 0.5625
0 0 0 1 1 0 0 1.3500 1 0 0 1 1 0 0 0.5500
0 0 0 1 1 0 1 1.3375 1 0 0 1 1 0 1 0.5375
0 0 0 1 1 1 0 1.3250 1 0 0 1 1 1 0 0.5250
0 0 0 1 1 1 1 1.3125 1 0 0 1 1 1 1 0.5125
0 0 1 0 0 0 0 1.3000 1 0 1 0 0 0 0 0.5000
0 0 1 0 0 0 1 1.2875 1 0 1 0 0 0 1 0.4875
0 0 1 0 0 1 0 1.2750 1 0 1 0 0 1 0 0.4750
0 0 1 0 0 1 1 1.2625 1 0 1 0 0 1 1 0.4625
0 0 1 0 1 0 0 1.2500 1 0 1 0 1 0 0 0.4500
0 0 1 0 1 0 1 1.2375 1 0 1 0 1 0 1 0.4375
0 0 1 0 1 1 0 1.2250 1 0 1 0 1 1 0 0.4250
0 0 1 0 1 1 1 1.2125 1 0 1 0 1 1 1 0.4125
0 0 1 1 0 0 0 1.2000 1 0 1 1 0 0 0 0.4000
0 0 1 1 0 0 1 1.1875 1 0 1 1 0 0 1 0.3875
0 0 1 1 0 1 0 1.1750 1 0 1 1 0 1 0 0.3750
0 0 1 1 0 1 1 1.1625 1 0 1 1 0 1 1 0.3625
0 0 1 1 1 0 0 1.1500 1 0 1 1 1 0 0 0.3500
0 0 1 1 1 0 1 1.1375 1 0 1 1 1 0 1 0.3375
0 0 1 1 1 1 0 1.1250 1 0 1 1 1 1 0 0.3250
0 0 1 1 1 1 1 1.1125 1 0 1 1 1 1 1 0.3125
0 1 0 0 0 0 0 1.1000 1 1 0 0 0 0 0 0.3000
0 1 0 0 0 0 1 1.0875 1 1 0 0 0 0 1 0.2875
0 1 0 0 0 1 0 1.0750 1 1 0 0 0 1 0 0.2750
0 1 0 0 0 1 1 1.0625 1 1 0 0 0 1 1 0.2625
0 1 0 0 1 0 0 1.0500 1 1 0 0 1 0 0 0.2500
0 1 0 0 1 0 1 1.0375 1 1 0 0 1 0 1 0.2375

26 ______________________________________________________________________________________
1-Phase Quick-PWM
Intel IMVP-6.5/GMCH Controllers
Table 2. IMVP-6.5 Output Voltage VID DAC Codes (continued)

MAX17528
IMVP-6.5 IMVP-6.5
OUTPUT OUTPUT
D6 D5 D4 D3 D2 D1 D0 D6 D5 D4 D3 D2 D1 D0
VOLTAGE VOLTAGE
(V) (V)
0 1 0 0 1 1 0 1.0250 1 1 0 0 1 1 0 0.2250
0 1 0 0 1 1 1 1.0125 1 1 0 0 1 1 1 0.2125
0 1 0 1 0 0 0 1.0000 1 1 0 1 0 0 0 0.2000
0 1 0 1 0 0 1 0.9875 1 1 0 1 0 0 1 0.1875
0 1 0 1 0 1 0 0.9750 1 1 0 1 0 1 0 0.1750
0 1 0 1 0 1 1 0.9625 1 1 0 1 0 1 1 0.1625
0 1 0 1 1 0 0 0.9500 1 1 0 1 1 0 0 0.1500
0 1 0 1 1 0 1 0.9375 1 1 0 1 1 0 1 0.1375
0 1 0 1 1 1 0 0.9250 1 1 0 1 1 1 0 0.1250
0 1 0 1 1 1 1 0.9125 1 1 0 1 1 1 1 0.1125
0 1 1 0 0 0 0 0.9000 1 1 1 0 0 0 0 0.1000
0 1 1 0 0 0 1 0.8875 1 1 1 0 0 0 1 0.0875
0 1 1 0 0 1 0 0.8750 1 1 1 0 0 1 0 0.0750
0 1 1 0 0 1 1 0.8625 1 1 1 0 0 1 1 0.0625
0 1 1 0 1 0 0 0.8500 1 1 1 0 1 0 0 0.0500
0 1 1 0 1 0 1 0.8375 1 1 1 0 1 0 1 0.0375
0 1 1 0 1 1 0 0.8250 1 1 1 0 1 1 0 0.0250
0 1 1 0 1 1 1 0.8125 1 1 1 0 1 1 1 0.0125
0 1 1 1 0 0 0 0.8000 1 1 1 1 0 0 0 0
0 1 1 1 0 0 1 0.7875 1 1 1 1 0 0 1 0
0 1 1 1 0 1 0 0.7750 1 1 1 1 0 1 0 0
0 1 1 1 0 1 1 0.7625 1 1 1 1 0 1 1 0
0 1 1 1 1 0 0 0.7500 1 1 1 1 1 0 0 0
0 1 1 1 1 0 1 0.7375 1 1 1 1 1 0 1 0
0 1 1 1 1 1 0 0.7250 1 1 1 1 1 1 0 0
0 1 1 1 1 1 1 0.7125 1 1 1 1 1 1 1 0

Output-Voltage Transition Timing approximately 20µs after the slew-rate controller reach-
The MAX17528 perform mode transitions in a controlled es the target output voltage. The controllers reenable
manner, automatically minimizing input surge currents. the upper PWRGD threshold 20µs after the slew-rate
This feature allows the circuit designer to achieve nearly controllers reach the target output voltage only for
ideal transitions, guaranteeing just-in-time arrival at the upward VID transitions. For downward VID transitions,
new output voltage level with the lowest possible peak the MAX17528 must also detect an error amplifier tran-
currents for a given output capacitance. sition (feedback drops below the new target threshold)
At the beginning of an output-voltage transition, the before reenabling the upper PWRGD transition to avoid
MAX17528 blanks both PWRGD thresholds, preventing false PWRGD errors under pulse-skipping conditions.
the PWRGD open-drain output and the CLKEN open- The slew rate (set by resistor RTIME) must be set fast
drain output from changing states during the transition. enough to ensure that the transition can be completed
The controllers reenable the lower PWRGD threshold within the maximum allotted time.

______________________________________________________________________________________ 27
1-Phase Quick-PWM
Intel IMVP-6.5/GMCH Controllers
The MAX17528 automatically controls the current to the where dVTARGET/dt is the required slew rate and COUT
MAX17528

minimum level required to complete the transition in the is the total output capacitance.
calculated time. The slew-rate controller uses an inter-
nal capacitor and current-source programmed by IMVP-6.5 Low-Power Sleep Transition
RTIME to transition the output voltage. The total transi- The IMVP-6.5 CPU enters a low-power state to con-
tion time depends on RTIME, the voltage difference, serve power (Figure 5). The processor enters this state
and the accuracy of the slew-rate controller (CSLEW by initially setting the core voltage to the LFM voltage
accuracy). The slew rate is not dependent on the total level (no LSB stepping). Upon reaching the LFM volt-
output capacitance, as long as the surge current is less age level, the processor asserts DPRLPVR, which is
than the current limit. For all dynamic VID transitions, connected to SKIP as shown in Figure 1, signaling that
the transition time (tTRAN) is given by: a very low current state has been entered. However,
the processor can still lower the core voltage by LSB
VNEW − VOLD increments to further reduce power consumption under
t TRAN =
( dVTARGET / dt ) this very low-power sleep state. The processor exits the
sleep state by pulling DPRSLVPR low and ramping up
where dVTARGET/dt = 12.5mV/µs x 71.5kΩ/RTIME is the the core voltage by LSB increments. During all VID
slew rate, V OLD is the original output voltage, and transitions, the MAX17528 blanks PWRGD (forced high
VNEW is the new target voltage. See TIME Slew-Rate impedance) and CLKEN (forced low) until 20µs after
Accuracy in the Electrical Characteristics table for the internal target (which moves at the slew rate set by
slew-rate limits. For soft-start and shutdown, the con- RTIME) reaches the selected VID code.
troller automatically reduces the slew rate to 1/8.
The output voltage tracks the slewed target voltage,
making the transitions relatively smooth. Excluding the
load current, the average inductor current required to
make an output voltage transition is:
IL ≅ COUT × (dVTARGET / dt)

ACTIVE VID HFM VID


CPU CORE
VOLTAGE
LFM VID

VID (D0–D6) LFM VID POSSIBLE VID CHANGE HFM VID

DPRSLPVR

PULSE SKIPPING 1-PHASE FORCED PWM

PWRGD BLANK HIGH IMPEDANCE BLANK HIGH IMPEDANCE

CLKEN BLANK LOW BLANK LOW

DH

tBLANK tBLANK
20µs typ 20µs typ
NOTE: DPRSLPVR = SKIP.

Figure 5. IMVP-6.5 Sleep Transition

28 ______________________________________________________________________________________
1-Phase Quick-PWM
Intel IMVP-6.5/GMCH Controllers
GMCH Sleep Transition The exit transition begins by pulling GFXDPRSLPVR

MAX17528
For GMCH applications (CLKEN = GND), the system low, followed by LSB VID steps every 2.5µs until the
enters the sleep state by stepping the VID code down to active VID target is reached (Figure 6).
the deeper sleep VID code. During these VID transitions, Fast GMCH sleep exit: When quickly exiting from the
the MAX17528 blanks PWRGD (forced high impedance) sleep state, the system immediately changes the VID
until 20µs after the last VID transition is completed. Upon code to the active VID code (no LSB stepping) and
reaching the low-voltage code, the system asserts keeps GFXDPRSLPVR asserted to select the fast
GFXDPRSLPVR, which is connected to the MAX17528 10mV/µs slew rate. Upon completion of the transition,
SKIP and SLOW pins as shown in Figure 2, allowing the the system pulls GFXDPRSLPVR low to signal the
voltage regulator to enter a pulse-skipping mode (for beginning of active state operation.
best light-load efficiency).
During all VID transitions, the MAX17528 blanks
Slow GMCH sleep exit: To avoid audible noise, the sys- PWRGD (forced high impedance) until 20µs after the
tem reduces the exit slew rate to minimize surge cur- internal target (which moves at the slew rate set by
rents from the input capacitors to the output capacitors. RTIME) reaches the selected VID code.

ACTIVE VID ACTIVE VID


CPU CORE
VOLTAGE
DPRSLP VID

VID (D0–D6) DEEPER SLEEP VID

GFXDPRSLPVR

PULSE SKIPPING 1-PHASE FORCED PWM

PWRGD BLANK HIGH IMPEDANCE BLANK HIGH IMPEDANCE

DH

tBLANK tBLANK
20µs typ 20µs typ

NOTE: GFXDPRSLPVR = SKIP = SLOW.

Figure 6. Slow Render GMCH Sleep Transition

______________________________________________________________________________________ 29
1-Phase Quick-PWM
Intel IMVP-6.5/GMCH Controllers
Forced-PWM Operation (Normal Mode) Light-Load Pulse-Skipping Operation
MAX17528

During soft-shutdown and normal operation—when the During soft-start and sleep states—SKIP is pulled
CPU is actively running (SKIP = low, Table 3), the high—the MAX17528 operates in pulse-skipping mode.
MAX17528 operates with the low-noise, forced-PWM The pulse-skipping mode enables the driver’s zero-
control scheme. Forced-PWM operation disables the crossing comparator, so the controller pulls DL low
zero-crossing comparator, forcing the low-side gate- when the low-side MOSFET voltage drop (LX to GND
drive waveforms to constantly be the complement of voltage) detects “zero” inductor current. This keeps the
the high-side gate-drive waveforms. This keeps the inductor from sinking current and discharging the output
switching frequency constant and allows the inductor capacitors and forces the controller to skip pulses under
current to reverse under light loads, providing fast, light-load conditions to avoid overcharging the output.
accurate negative output-voltage transitions by quickly Upon entering pulse-skipping operation, the controller
discharging the output capacitors. temporarily blanks the upper PWRGD and CLKEN
Forced-PWM operation comes at a cost: the no-load thresholds, when the transition to pulse-skipping opera-
+5V bias supply current remains between 10mA to tion coincides with a VID code change. Once the error
50mA, depending on the external MOSFETs and switch- amplifier detects that the output voltage is in regulation,
ing frequency. To maintain high efficiency under light- the upper PWRGD and upper CLKEN, resume tracking
load conditions, the processor can switch the controller the selected VID DAC code. The MAX17528 automati-
to a low-power pulse-skipping control scheme after cally uses forced-PWM operation during soft-shutdown,
entering suspend mode. The MAX17528 automatically regardless of the SKIP configuration.
uses pulse-skipping operation during soft-start, regard-
less of the SKIP configuration.

10mV/µs
ACTIVE VID ACTIVE VID
CPU CORE
VOLTAGE
DPRSLP VID

VID (D0–D6) DEEPER SLEEP VID

GFXDPRSLPVR

PULSE SKIPPING 1-PHASE FORCED PWM

PWRGD BLANK HIGH IMPEDANCE BLANK HIGH IMPEDANCE

DH

tBLANK tBLANK
20µs typ 20µs typ

NOTE: GFXDPRSLPVR = SKIP = SLOW.

Figure 7. Fast Render GMCH Sleep Transition

30 ______________________________________________________________________________________
1-Phase Quick-PWM
Intel IMVP-6.5/GMCH Controllers
Automatic Pulse-Skipping Switchover inductor values include larger physical size and

MAX17528
In skip mode (SKIP = high), an inherent automatic degraded load-transient response, especially at low
switchover to PFM takes place at light loads (Figure 8). input-voltage levels.
This switchover is affected by a comparator that truncates
the low-side switch on-time at the inductor current’s zero Power-Up Sequence (POR, UVLO)
crossing. The zero-crossing comparator senses the The MAX17528 is enabled when SHDN is driven high
inductor current across the low-side MOSFETs. Once (Figures 9 and 10). The internal reference powers up
VLX drops below the zero-crossing comparator threshold first, followed by the analog control circuitry. Roughly
(see the Electrical Characteristics table), the comparator 50µs after the analog control circuitry powers up, the
forces DL low (Figure 3). This mechanism causes the PWM controller is enabled and begins the soft-start
threshold between pulse-skipping PFM and nonskipping sequence.
PWM operation to coincide with the boundary between Power-on reset (POR) occurs when VCC rises above
continuous and discontinuous inductor-current opera- approximately 2V, resetting the fault latch and prepar-
tion. The PFM/PWM crossover occurs when the load-cur- ing the controller for operation. The VCC UVLO circuitry
rent is equal to 1/2 the peak-to-peak ripple current, inhibits switching until VCC rises above 4.25V. The con-
which is a function of the inductor value (Figure 8). For a troller powers up the reference once the system
battery input range of 7V to 20V, this threshold is relative- enables the controller, VCC is above 4.25V, and SHDN
ly constant, with only a minor dependence on the input is driven high. The soft-start sequence ramps the out-
voltage due to the typically low duty cycles. The total put voltage up to the target voltage—either the 1.1V
load current at the PFM/PWM crossover threshold boot voltage for IMVP-6.5 (CLKEN pullup to 3.3V with
(ILOAD(SKIP)) is approximately: 1.9kΩ) or the selected VID voltage for GMCH (CLKEN
= GND)—at 1/8 the nominal slew rate set by RTIME:
⎛t V ⎞ ⎛ V − VOUT ⎞
ILOAD(SKIP) = ⎜ SW OUT ⎟ ⎜ IN ⎟⎠ 8VSTART
⎝ L ⎠⎝ VIN t TRAN(START) =
(dVTARGET / dt)
The switching waveforms might appear noisy and asyn-
chronous when light loading activates pulse-skipping where dVTARGET/dt = 12.5mV/µs x 71.5kΩ/RTIME is the
operation, but this is a normal operating condition that nominal slew rate. The soft-start circuitry does not use a
results in high light-load efficiency. Trade-offs between variable current limit, so full output current is available
PFM noise and light-load efficiency are made by immediately. The MAX17528 automatically uses pulse-
varying the inductor value. Generally, low inductor val- skipping mode during soft-start and uses forced-PWM
ues produce a broader efficiency vs. load curve, while mode during soft-shutdown, regardless of the SKIP
higher values result in higher full-load efficiency configuration.
(assuming that the coil resistance remains fixed) and For IMVP-6.5 applications (CLKEN pullup to 3.3V with
less output voltage ripple. Penalties for using higher 1.9kΩ), the MAX17528 pulls CLKEN low approximately
60µs after reaching PGDIN is pulled high and the con-
troller reaches the 1.1V boot voltage. At the same time,
the MAX17528 slews the output to the selected VID
voltage at the programmed nominal slew rate. PWRGD
becomes high impedance approximately 5ms after
CLKEN is pulled low.
∆i VBATT - VOUT
= For GMCH applications (CLKEN = GND), PWRGD
∆t L
becomes high impedance approximately 60µs after
INDUCTOR CURRENT

IPEAK
reaching the selected VID voltage.
For automatic startup, the battery voltage should be
present before VCC rises above its UVLO threshold. If
ILOAD = IPEAK/2 the controller attempts to bring the output into regula-
tion without the battery voltage present, the output
undervoltage fault latch disables the controller. The
MAX17528 remains shut down until the fault latch is
0 ON-TIME TIME cleared by toggling SHDN or cycling the VCC power
supply below 0.5V.
Figure 8. Pulse-Skipping/Discontinuous Crossover Point

______________________________________________________________________________________ 31
1-Phase Quick-PWM
Intel IMVP-6.5/GMCH Controllers
If the VCC voltage drops below 4.25V, the controller faults, the controller shuts down immediately and forces
MAX17528

assumes that there is not enough supply voltage to make a high-impedance output (DL and DH pulled low) and
valid decisions. To protect the output from overvoltage pulls CSN low through a 10Ω discharge MOSFET.

VCC

SHDN

VID (D0–D6) INVALID VID VALID VID INVALID VID

SOFT-START
1/8 RTIME SLEW RATE SOFT-SHUTDOWN
1.1V BOOT 1/8 RTIME SLEW RATE
CPU CORE
VOLTAGE
INTERNAL
PWM MODE PULSE SKIPPING FORCED-PWM MODE

CLKEN

PWRGD
tBLANK tBLANK
60µs typ 5ms typ tBLANK
tBLANK 60µs typ
NOTE: PGDIN = VCC. 20µs typ

Figure 9. IMVP-6.5 Power-Up and Shutdown Sequence Timing Diagram

VCC

SHDN

VID (D0–D6) VALID VID INVALID VID

SOFT-START
1/8 RTIME SLEW RATE SOFT-SHUTDOWN
1/8 RTIME SLEW RATE
GMCH CORE
VOLTAGE
INTERNAL
PWM MODE PULSE SKIPPING FORCED-PWM

PWRGD

tBLANK
5ms typ tBLANK
60µs typ

Figure 10. GMCH Power-Up and Shutdown Sequence Timing Diagram

32 ______________________________________________________________________________________
1-Phase Quick-PWM
Intel IMVP-6.5/GMCH Controllers
Table 3. Operating Mode Truth Table

MAX17528
SHDN SLOW SKIP OPERATING MODE
LOW-POWER SHUTDOWN. DL forced low, and the controller is disabled. The
GND X X DISABLED
supply current drops below 30µA.
STARTUP. When SHDN is pulled high, the MAX17528 begins the startup
Pulse skipping
sequence after the internal circuitry powers up. The MAX17528 enables the
Rising X X 1/8 RTIME slew
PWM controller and ramps the output voltage up to the startup voltage. See
rate
Figures 9 and 10.
Forced-PWM
FULL POWER. The no-load output voltage is determined by the selected VID
High X Low nominal RTIME
DAC code (Table 2).
slew rate
LOW-POWER MODE (NOMINAL TRANSITION). The no-load output voltage is
Pulse-skipping determined by the selected VID DAC code (Table 2). When SKIP is pulled high,
High High High nominal RTIME the controller immediately enters pulse-skipping operation, allowing automatic
slew rate PWM/PFM switchover under light loads. The PWRGD and CLKEN upper
thresholds are blanked during the transition.
LOW-POWER MODE (SLOW TRANSITION). The no-load output voltage is
Pulse-skipping determined by the selected VID DAC code (Table 2). When SKIP is pulled high,
High Low High 1/2 RTIME slew the MAX17528 enters pulse-skipping operation, allowing automatic PWM/PFM
rate switchover under light loads. The PWRGD and CLKEN thresholds are blanked
during the transition.
SHUTDOWN. When SHDN is pulled low, the MAX17528 immediately pulls
Forced-PWM
PWRGD low, CLKEN becomes high impedance, and the output voltage is
Falling X X 1/8 RTIME slew
ramped down to ground. Once the output reaches zero, the controller enters the
rate
low-power shutdown state. See Figures 9 and 10.

FAULT MODE. The fault latch has been set by the MAX17528 UVP fault, RTON
High X X DISABLED open fault, or thermal-shutdown protection. The controller remains in FAULT
mode until VCC power is cycled or SHDN toggled.

Shutdown the drivers are disabled (DL and DH are pulled low)—
When SHDN goes low, the MAX17528 enters low- the internal reference turns off, and the supply currents
power shutdown mode. PWRGD is pulled low immedi- drop to about 30µA (max).
ately, and the output voltage ramps down at 1/8 the When an output undervoltage fault condition activates
slew rate set by RTIME: the shutdown sequence, the protection circuitry sets the
8VOUT UVP fault latch to prevent the controller from restarting.
t TRAN(SHDN) =
(dVTARGET / dt) To clear the fault latch and reactivate the controller,
toggle SHDN or cycle VCC power below 0.5V.
where dVTARGET/dt = 12.5mV/µs x 71.5kΩ/RTIME is the
nominal slew rate. Slowly discharging the output capaci- Current Monitor (IMON)
tors by slewing the output over a long period of time The MAX17528 includes a unidirectional transconduc-
keeps the average negative inductor current low tance amplifier that sources current proportional to the
(damped response), thereby eliminating the negative positive current-sense voltage. The IMON output cur-
output-voltage excursion that occurs when the controller rent is defined by:
discharges the output quickly by permanently turning on IIMON = Gm(IMON) x (VCSP - VCSN)
the low-side MOSFET (underdamped response). This where Gm(IMON) = 5mS (typ) and the IMON current is
eliminates the need for the Schottky diode connected unidirectional (sources current out of IMON only) for
between the output and ground to clamp the negative positive current-sense values. For negative current-
output-voltage excursion. After the controller reaches sense voltages, the IMON current is zero.
the zero target, the MAX17528 shuts down completely—

______________________________________________________________________________________ 33
1-Phase Quick-PWM
Intel IMVP-6.5/GMCH Controllers
The current monitor allows the processor to accurately Thermal Fault Protection
MAX17528

monitor the CPU load and quickly calculate the power The MAX17528 features a thermal-fault-protection cir-
dissipation to determine if the system is about to over- cuit. When the junction temperature rises above
heat before the significantly slower temperature sensor +160°C, a thermal sensor sets the fault latch, forces DL
signals an overtemperature alert. low, and pulls DH low. Toggle SHDN or cycle the VCC
Connect an external resistor between IMON and power supply below 0.5V to clear the fault latch and
VSS_SENSE to create the desired IMON gain based on reactivate the controller after the junction temperature
the following equation: cools by 15°C. Thermal shutdown can be disabled
through the no-fault test mode (see the No-Fault Test
RIMON = 0.999V/(IMAX x RSENSE x Gm(IMON)) Mode section).
where IMAX is defined in the Current Monitor section of
the Intel IMVP-6.5 specification and based on discrete No-Fault Test Mode
increments (10A, 20A, 30A, 40A, etc.,), RSENSE is the The latched fault-protection feature can complicate the
typical effective value of the current-sense element process of debugging prototype breadboards since
(sense resistor or inductor DCR) that is used to provide there are (at most) a few milliseconds in which to deter-
the current-sense voltage, and Gm(IMON) is the typical mine what went wrong. Therefore, a “no-fault” test
transconductance amplifier gain as defined in the mode is provided to disable the fault protection—UVP,
Electrical Characteristics table. thermal shutdown, and TON open-circuit fault protec-
tion. The “no-fault” test mode also disables the BST
The IMON voltage is internally clamped to a maximum switch, although the switch’s body diode provides suffi-
of 1.1V (typ), preventing the IMON output from exceed- cient power for the high-side driver to function properly.
ing the IMON voltage rating even under overload or Additionally, the test mode clears the fault latch if it has
short-circuit conditions. When the controller is disabled, been set. The no-fault test mode is entered by forcing
IMON is pulled to ground. 11V to 13V on SHDN.
The transconductance amplifier and voltage clamp are
internally compensated, so IMON cannot directly drive MOSFET Gate Drivers
large capacitance values. To filter the IMON signal, use The DH and DL drivers are optimized for driving mod-
an RC filter as shown in Figure 1. erate-sized high-side and larger low-side power
MOSFETs. This is consistent with the low duty factor
Temperature Comparator (VRHOT) seen in notebook applications, where a large V IN -
The MAX17528 also features an independent compara- VOUT differential exists. The high-side gate drivers (DH)
tor with an accurate threshold that tracks the analog source and sink 2.2A, and the low-side gate drivers
supply voltage (VHOT = 0.3 x VCC). This makes the ther- (DL) source 2.7A and sink 8A. This ensures robust gate
mal trip threshold independent of the VCC supply volt- drive for high-current applications. The DH high-side
age tolerance. Use a resistor- and thermistor-divider MOSFET driver is powered by an internal charge-pump
between VCC and GND to generate a voltage-regulator boost switch at BST, while the DL synchronous-rectifier
overtemperature monitor. Place the thermistor as close driver is powered directly by the 5V bias supply (VDD).
as possible to the MOSFETs and inductors. Adaptive dead-time circuits monitor the DL and DH dri-
Output Undervoltage (UVP) Protection vers and prevent either FET from turning on until the
The output UVP function limits the power loss by dis- other is fully off. The adaptive driver dead time allows
abling the regulator if the MAX17528 output voltage operation without shoot-through with a wide range of
drops 400mV below the target voltage; the controller MOSFETs, minimizing delays and maintaining efficiency.
activates the shutdown sequence and sets the fault There must be a low-resistance, low-inductance path
latch. Once the controller ramps down to zero, it forces from the DL and DH drivers to the MOSFET gates for
DL high and DH low. Toggle SHDN or cycle the VCC the adaptive dead-time circuits to work properly; other-
power supply below 0.5V to clear the fault latch and wise, the sense circuitry in the MAX17528 interprets the
reactivate the controller. MOSFET gates as “off” while charge actually remains.
UVP protection can be disabled through the no-fault Use very short, wide traces (50 mils to 100 mils wide if
test mode (see the No-Fault Test Mode section). the MOSFET is 1in from the driver).

34 ______________________________________________________________________________________
1-Phase Quick-PWM
Intel IMVP-6.5/GMCH Controllers
The internal pulldown transistor that drives DL low is

MAX17528
robust, with a 0.25Ω (typ) on-resistance. This helps pre-
vent DL from being pulled up due to capacitive coupling MAX17528
(RBST)*
from the drain to the gate of the low-side MOSFETs BST
INPUT (VIN)
when the inductor node (LX) quickly switches from
ground to VIN. Applications with high input voltages and CBST
DH
long inductive driver traces must guarantee rising LX NH
edges do not pull up the low-side MOSFET’s gate, caus- L
LX
ing shoot-through currents. The capacitive coupling
between LX and DL created by the MOSFET’s gate-to-
drain capacitance (CRSS), gate-to-source capacitance
(CISS - CRSS), and additional board parasitics should CBYP
VDD
not exceed the following minimum threshold:
⎛C ⎞
VGS(TH) < VIN ⎜ RSS ⎟
⎝ CISS ⎠
DL
Typically, adding a 4700pF between DL and power NL
ground (C NL in Figure 11), close to the low-side (CNL)*
MOSFETs, greatly reduces coupling. Do not exceed
22nF of total gate capacitance to prevent excessive PGND
turn-off delays.
Alternatively, shoot-through currents can be caused by (RBST)* OPTIONAL—THE RESISTOR LOWERS EMI BY DECREASING
a combination of fast high-side MOSFETs and slow low- THE SWITCHING NODE RISE TIME.
side MOSFETs. If the turn-off delay time of the low-side (CNL)* OPTIONAL—THE CAPACITOR REDUCES LX TO DL CAPACITIVE
MOSFET is too long, the high-side MOSFETs can turn COUPLING THAT CAN CAUSE SHOOT-THROUGH CURRENTS.
on before the low-side MOSFETs have actually turned
off. Adding a resistor less than 5Ω in series with BST Figure 11. Gate-Drive Circuit
slows down the high-side MOSFET turn-on time, elimi-
nating the shoot-through currents without degrading
the turn-off time (RBST in Figure 11). Slowing down the • Maximum load current: There are two values to
high-side MOSFET also reduces the LX node rise time, consider. The peak load current (I LOAD(MAX) )
thereby reducing EMI and high-frequency coupling determines the instantaneous component stresses
responsible for switching noise. and filtering requirements, and thus, drives output
capacitor selection, inductor saturation rating, and
Quick-PWM the design of the current-limit circuit. The continu-
Design Procedure ous load current (ILOAD) determines the thermal
stresses, and thus, drives the selection of input
Firmly establish the input voltage range and maximum capacitors, MOSFETs, and other critical heat-con-
load current before choosing a switching frequency tributing components. Modern notebook CPUs gen-
and inductor operating point (ripple-current ratio). The erally exhibit ILOAD = ILOAD(MAX) x 80%.
primary design trade-off lies in choosing a good switch-
ing frequency and inductor operating point, and the fol- • Load line (voltage positioning): The load line (out-
lowing five factors dictate the rest of the design: put voltage vs. load slope) dynamically lowers the
output voltage in response to the load current, reduc-
• Input voltage range: The maximum value ing the output capacitance requirement and the
(VIN(MAX)) must accommodate the worst-case high processor’s power dissipation. The Intel specification
AC adapter voltage. The minimum value (VIN(MIN)) clearly defines the load-line requirement in the power-
must account for the lowest input voltage after supply specifications for each processor family.
drops due to connectors, fuses, and battery selec-
tor switches. If there is a choice at all, lower input
voltages result in better efficiency.

______________________________________________________________________________________ 35
1-Phase Quick-PWM
Intel IMVP-6.5/GMCH Controllers
• Switching frequency: This choice determines the
MAX17528

⎡⎛ VOUT tSW ⎞ ⎤
basic trade-off between size and efficiency. The (
L ∆ILOAD(MAX) )2
⎢⎜ ⎟ + tOFF(M
MIN) ⎥
optimal frequency is largely a function of maximum
VSAG = ⎣⎝ VIN ⎠ ⎦
input voltage due to MOSFET switching losses that ⎡⎛ ( VIN − VOUT ) tSW ⎞ ⎤
are proportional to frequency and VIN2. The opti- 2COUT VOUT ⎢⎜ ⎟ − tOFF(MIN) ⎥
mum frequency is also a moving target due to rapid ⎢⎣⎝ VIN ⎠ ⎥⎦
improvements in MOSFET technology that are mak-
where t OFF(MIN) is the minimum off-time (see the
ing higher frequencies more practical.
Electrical Characteristics table).
• Inductor operating point: This choice provides The amount of overshoot due to stored inductor energy
trade-offs between size vs. efficiency and transient can be calculated as:
response vs. output noise. Low inductor values pro-
vide better transient response and smaller physical
size, but also result in lower efficiency and higher VSOAR ≈
( ∆ILOAD(MAX) ) L
2

output noise due to increased ripple current. The 2COUT VOUT


minimum practical inductor value is one that causes
the circuit to operate at the edge of critical conduc- Current-Limit and Slew-Rate Control
tion (where the inductor current just touches zero (TIME and ILIM)
with every cycle at maximum load). Inductor values TIME and ILIM are used to control the slew rate and
lower than this grant no further size-reduction bene- current limit. TIME regulates to a fixed 2.0V. The
fit. The optimum operating point is usually found MAX17528 uses the TIME source current to set the
between 20% and 50% ripple current. slew rate (dVTARGET/dt). The higher the source current,
the faster the nominal output-voltage slew rate:
Inductor Selection
The switching frequency and operating point (% ripple ⎛ 71.5kΩ ⎞
dVTARGET / dt = 12.5mV / µs × ⎜
current or LIR) determine the inductor value as follows: ⎝ RTIME ⎟⎠
⎛ ⎞⎛ V
L=⎜
VIN − VOUT OUT ⎞ where RTIME is the sum of resistance values between
⎟⎜ ⎟
f I
⎝ SW LOAD(MAX) LIR ⎠ ⎝ IN ⎠
V TIME and ground.
The ILIM voltage determines the valley current-sense
Find a low-loss inductor having the lowest possible DC
threshold. When ILIM = VCC, the controller uses the
resistance that fits in the allotted dimensions. Molded
preset 22.5mV (typ) current-limit threshold. In an
cores are often the best choice, although powdered
adjustable design, ILIM is connected to a resistive volt-
iron and ferrite cores are inexpensive and can work
age-divider connected between TIME and ground. The
well at 300kHz. The core must be large enough not to
differential voltage between TIME and ILIM sets the
saturate at the peak inductor current (IPEAK):
current-limit threshold (VLIMIT), so the valley current-
⎛ LIR ⎞ sense threshold is:
IPEAK = ILOAD(MAX) ⎜1 + ⎟
⎝ 2 ⎠
V −V
VLIMIT = TIME ILIM
10
Transient Response
The inductor ripple current impacts transient-response where the VLIMIT tolerances are defined in the Electrical
performance, especially at low VIN - VOUT differentials. Characteristics table.
Low inductor values allow the inductor current to slew
This allows design flexibility since the DCR sense cir-
faster, replenishing charge removed from the output fil-
cuit or sense resistor does not have to be adjusted to
ter capacitors by a sudden load step. The amount of
meet the current limit as long as the current-sense volt-
output sag is also a function of the maximum duty fac-
age never exceeds 50mV. Keeping VLIMIT between
tor, which can be calculated from the on-time and mini-
20mV to 40mV leaves room for future current-limit
mum off-time. The worst-case output sag voltage can
adjustment.
be determined by:

36 ______________________________________________________________________________________
1-Phase Quick-PWM
Intel IMVP-6.5/GMCH Controllers
The minimum current-limit threshold must be high In CPU VCORE converters and other applications where

MAX17528
enough to support the maximum load current when the the output is subject to large-load transients, the output
current limit is at the minimum tolerance value. The val- capacitor’s size typically depends on how much ESR is
ley of the inductor current occurs at ILOAD(MAX) minus needed to prevent the output from dipping too low
half the ripple current; therefore: under a load transient. Ignoring the sag due to finite
capacitance:
⎛ LIR ⎞
IVALLEY > ILOAD(MAX) ⎜1 − ⎟ VSTEP
⎝ 2 ⎠ (RESR + RPCB ) ≤ ∆I
LOAD(MAX)
where:
VLIMIT VLIMIT In non-CPU applications, the output capacitor’s size
IVALLEY = =
RSENSE DCR × RCSP−CSN often depends on how much ESR is needed to maintain
RLX −CSN an acceptable level of output ripple voltage. The output
ripple voltage of a step-down controller equals the total
where RSENSE is the sensing resistor and RCSP-CSN/ inductor ripple current multiplied by the output capaci-
R LX-CSN is the ratio of resistor-divider with DCR- tor’s ESR. The maximum ESR to meet ripple require-
sensing approach. ments is:
Voltage Positioning and ⎡ VINfSWL ⎤
RESR ≤ ⎢ ⎥VRIPPLE
Loop Compensation ⎢⎣ (VIN − VOUT )VOUT ⎥⎦
Voltage positioning dynamically lowers the output volt-
age in response to the load current, reducing the out- where f SW is the switching frequency. The actual
put capacitance and processor’s power dissipation capacitance value required relates to the physical size
requirements. The controller uses a transconductance needed to achieve low ESR, as well as to the chemistry
amplifier to set the transient and DC output voltage of the capacitor technology. Thus, the capacitor is usu-
droop (Figure 3) as a function of the load. This adjusta- ally selected by ESR and voltage rating rather than by
bility allows flexibility in the selected current-sense capacitance value (this is true of polymer types).
resistor value or inductor DCR, and allows smaller cur-
rent-sense resistance to be used, reducing the overall When using low-capacity ceramic filter capacitors,
power dissipated. capacitor size is usually determined by the capacity
needed to prevent V SAG and V SOAR from causing
Steady-State Voltage Positioning problems during load transients. Generally, once
Connect a resistor (RFB) between FB and VOUT to set enough capacitance is added to meet the overshoot
the DC steady-state droop (load line) based on the requirement, undershoot at the rising load edge is no
required voltage-positioning slope (RDROOP): longer a problem (see the VSAG and VSOAR equations
in the Transient Response section).
RDROOP
RFB =
RSENSEGm(FB) Output Capacitor Stability Considerations
For Quick-PWM controllers, stability is determined by
where the effective current-sense resistance (RSENSE) the value of the ESR zero relative to the switching fre-
depends on the current-sense method (see the Current quency. The boundary of instability is given by the fol-
Sense section), and the voltage-positioning amplifier’s lowing equation:
transconductance (G m(FB) ) is typically 600µS as f
defined in the Electrical Characteristics table. When the fESR ≤ SW
π
inductors’ DCR is used as the current-sense element
(R SENSE = R DCR), the current-sense design should where:
include a thermistor to minimize the temperature 1
dependence of the voltage-positioning slope as shown fESR =
2πREFFCOUT
in Figure 1.
Output Capacitor Selection and:
The output filter capacitor must have low enough effec- REFF = RESR + RDROOP + RPCB
tive series resistance (ESR) to meet output ripple and
load-transient requirements, yet have high enough ESR where COUT is the total output capacitance, RESR is the
to satisfy stability requirements. total ESR, RDROOP is the voltage-positioning slope, and

______________________________________________________________________________________ 37
1-Phase Quick-PWM
Intel IMVP-6.5/GMCH Controllers
RPCB is the parasitic board resistance between the out- Input Capacitor Selection
MAX17528

put capacitors and sense resistors. The input capacitor must meet the ripple current
For a standard 300kHz application, the ESR zero fre- requirement (IRMS) imposed by the switching currents.
quency must be well below 95kHz, preferably below The IRMS requirements can be determined by the fol-
50kHz. Tantalum, SANYO POSCAP, and Panasonic SP lowing equation:
capacitors in widespread use at the time of publication ⎛I ⎞
IRMS = ⎜ LOAD ⎟ VOUT (VIN − VOUT )
have typical ESR zero frequencies below 50kHz. In the ⎝ IN ⎠
V
standard GMCH application circuit, the ESR needed to
support a 10mVP-P ripple is 10mV/(10A x 0.3) = 3.3mΩ. The worst-case RMS current requirement occurs when
Two 330µF/2.5V Panasonic SP (type SX) capacitors in operating with VIN = 2 x VOUT. At this point, the above
parallel provide 3.0mΩ (max) ESR. With a 5mΩ droop equation simplifies to IRMS = 0.5 x ILOAD.
and 0.5mΩ PCB resistance, the typical combined ESR For most applications, nontantalum chemistries (ceramic,
results in a zero at 28kHz. aluminum, or OS-CON) are preferred due to their resis-
Ceramic capacitors have a high-ESR zero frequency, tance to inrush surge currents typical of systems with a
but applications with significant voltage positioning can mechanical switch or connector in series with the input.
take advantage of their size and low ESR. Do not put If the Quick-PWM controller is operated as the second
high-value ceramic capacitors directly across the out- stage of a two-stage power-conversion system, tanta-
put without verifying that the circuit contains enough lum input capacitors are acceptable. In either configu-
voltage positioning and series PCB resistance to ration, choose an input capacitor that exhibits less than
ensure stability. When only using ceramic output +10°C temperature rise at the RMS input current for
capacitors, output overshoot (VSOAR) typically deter- optimal circuit longevity.
mines the minimum output capacitance requirement.
Their relatively low capacitance value can cause output Power-MOSFET Selection
overshoot when stepping from full-load to no-load con- Most of the following MOSFET guidelines focus on the
ditions, unless a small inductor value is used (high challenge of obtaining high load-current capability
switching frequency) to minimize the energy transferred when using high-voltage (> 20V) AC adapters. Low-
from inductor to capacitor during load-step recovery. current applications usually require less attention.
Unstable operation manifests itself in two related, but The high-side MOSFET (NH) must be able to dissipate
distinctly different ways: double pulsing and feedback the resistive losses plus the switching losses at both
loop instability. Double pulsing occurs due to noise on VIN(MIN) and VIN(MAX). Calculate both of these sums.
the output or because the ESR is so low that there is Ideally, the losses at VIN(MIN) should be roughly equal
not enough voltage ramp in the output voltage signal. to losses at VIN(MAX), with lower losses in between. If
This “fools” the error comparator into triggering a new the losses at VIN(MIN) are significantly higher than the
cycle immediately after the minimum off-time period losses at VIN(MAX), consider increasing the size of NH
has expired. Double pulsing is more annoying than (reducing RDS(ON) but with higher CGATE). Conversely,
harmful, resulting in nothing worse than increased out- if the losses at VIN(MAX) are significantly higher than the
put ripple. However, it can indicate the possible pres- losses at VIN(MIN), consider reducing the size of NH
ence of loop instability due to insufficient ESR. Loop (increasing RDS(ON) to lower CGATE). If VIN does not vary
instability can result in oscillations at the output after over a wide range, the minimum power dissipation occurs
line or load steps. Such perturbations are usually where the resistive losses equal the switching losses.
damped, but can cause the output voltage to rise Choose a low-side MOSFET that has the lowest possi-
above or fall below the tolerance limits. ble on-resistance (R DS(ON)), comes in a moderate-
The easiest method for checking stability is to apply a sized package (i.e., one or two 8-pin SOs, DPAK, or
very fast zero-to-max load transient and carefully D2PAK), and is reasonably priced. Make sure that the
observe the output voltage ripple envelope for over- DL gate driver can supply sufficient current to support
shoot and ringing. It can help to simultaneously monitor the gate charge and the current injected into the para-
the inductor current with an AC current probe. Do not sitic gate-to-drain capacitor caused by the high-side
allow more than one cycle of ringing after the initial MOSFET turning on; otherwise, cross-conduction prob-
step-response under/overshoot. lems can occur (see the MOSFET Gate Drivers section).

38 ______________________________________________________________________________________
1-Phase Quick-PWM
Intel IMVP-6.5/GMCH Controllers
MOSFET Power Dissipation ILOAD(MAX), but are not quite high enough to exceed

MAX17528
Worst-case conduction losses occur at the duty factor the current limit and cause the fault latch to trip. To pro-
extremes. For the high-side MOSFET (NH), the worst- tect against this possibility, you can “over design” the
case power dissipation due to resistance occurs at the circuit to tolerate:
minimum input voltage:
⎛ ∆I ⎞
⎛V ⎞ ILOAD = ⎜ IVALLEY(MAX) + INDUCTOR ⎟ = IVALLEY(MAX)
PD(NHRe sistive) = ⎜ OUT ⎟ (ILOAD ) RDS(ON)
2 ⎝ 2 ⎠
⎝ VIN ⎠
where I VALLEY(MAX) is the maximum valley current
Generally, a small high-side MOSFET is desired to allowed by the current-limit circuit, including threshold
reduce switching losses at high input voltages. tolerance and on-resistance variation. The MOSFETs
However, the RDS(ON) required to stay within package must have a good-size heatsink to handle the overload
power dissipation often limits how small the MOSFET power dissipation.
can be. Again, the optimum occurs when the switching Choose a Schottky diode (DL) with a forward voltage
losses equal the conduction (RDS(ON)) losses. High- low enough to prevent the low-side MOSFET body
side switching losses do not usually become an issue diode from turning on during the dead time. Select a
until the input is greater than approximately 15V. diode that can handle the load current during the dead
Calculating the power dissipation in high-side MOSFET times. This diode is optional and can be removed if effi-
(NH) due to switching losses is complicated since it ciency is not critical.
must allow for difficult quantifying factors that influence
the turn-on and turn-off times. These factors include the Boost Capacitors
internal gate resistance, gate charge, threshold volt- The boost capacitors (CBST) must be selected large
age, source inductance, and PCB layout characteris- enough to handle the gate-charging requirements of
tics. The following switching-loss calculation provides the high-side MOSFETs. Typically, 0.1µF ceramic
only a very rough estimate and is no substitute for capacitors work well for low-power applications driving
breadboard evaluation, preferably including verification medium-sized MOSFETs. However, high-current appli-
using a thermocouple mounted on NH: cations driving large, high-side MOSFETs require boost
capacitors larger than 0.1µF. For these applications,
⎛ QG(SW) ⎞ COSSVIN2fSW
PD(NHSwitching) = VIN(MAX)ILOADfSW ⎜ ⎟+ select the boost capacitors to avoid discharging the
⎝ IGATE ⎠ 2 capacitor more than 200mV while charging the high-
where COSS is the NH MOSFET’s output capacitance, side MOSFETs’ gates:
QG(SW) is the charge needed to turn on the NH MOSFET, N × QGATE
and IGATE is the peak gate-drive source/sink current CBST =
200mV
(2.2A typ).
Switching losses in the high-side MOSFET can become where N is the number of high-side MOSFETs used for
an insidious heat problem when maximum AC adapter one regulator, and QGATE is the gate charge specified
voltages are applied, due to the squared term in the in the MOSFET’s data sheet. For example, assume (2)
C x VIN2 x fSW switching-loss equation. If the high-side IRF7811W n-channel MOSFETs are used on the high
MOSFET chosen for adequate RDS(ON) at low battery side. According to the manufacturer’s data sheet, a sin-
voltages becomes extraordinarily hot when biased from gle IRF7811W has a maximum gate charge of 24nC
V IN(MAX) , consider choosing another MOSFET with (VGS = 5V). Using the above equation, the required
lower parasitic capacitance. boost capacitance would be:
For the low-side MOSFET (NL), the worst-case power
2 × 24nC
dissipation always occurs at maximum input voltage: CBST = = 0.24µF
⎡ ⎛ V
200mV
⎞⎤
PD(NL Re sistive) = ⎢1 − ⎜ OUT ⎟ ⎥(ILOAD ) RDS(ON)
2
Selecting the closest standard value, this example
⎢⎣ ⎝ VIN(MAX) ⎠ ⎥⎦
requires a 0.22µF ceramic capacitor.
The worst case for MOSFET power dissipation occurs
under heavy overloads that are greater than

______________________________________________________________________________________ 39
1-Phase Quick-PWM
Intel IMVP-6.5/GMCH Controllers
Applications Information • CSP and CSN connections for current limiting and
MAX17528

voltage positioning must be made using Kelvin-


PCB Layout Guidelines sense connections to guarantee the current-sense
Careful PCB layout is critical to achieve low switching accuracy.
losses and clean, stable operation. The switching • Route high-speed switching nodes (LX, DH, BST,
power stage requires particular attention. If possible, and DL) away from sensitive analog areas (FB,
mount all the power components on the top side of the CSP, CSN, CCV, etc.).
board with their ground terminals flush against one
another. Follow the MAX17528 Evaluation Kit layout and Layout Procedure
use the following guidelines for good PCB layout: 1) Place the power components first, with ground ter-
• High-current path/components: Keep the high-cur- minals adjacent (low-side MOSFET source, CIN,
rent paths short, especially at the ground terminals. COUT, and D1 anode). If possible, make all these
This is essential for stable, jitter-free operation. connections on the top layer with wide, copper-
filled areas.
• Keep the power traces and load connections short.
This is essential for high efficiency. The use of thick 2) Mount the controller IC adjacent to the low-side
copper PCBs (2oz vs. 1oz) can enhance full-load MOSFET. The DL gate traces must be short and
efficiency by 1% or more. Correctly routing PCB wide (50 mils to 100 mils wide if the MOSFET is 1in
traces is a difficult task that must be approached in from the controller IC).
terms of fractions of centimeters, where a single 3) Group the gate-drive components (BST capacitor,
mΩ of excess trace resistance causes a measur- VDD bypass capacitor) together near the controller IC.
able efficiency penalty.
4) Make the DC-DC controller ground connections as
• When trade-offs in trace lengths must be made, it is shown in the standard application circuits. This dia-
preferable to allow the inductor charging path to be gram can be viewed as having three separate
made longer than the discharge path. For example, ground planes: input/output system ground, where
it is better to allow some extra distance between the all the high-power components go; the power
input capacitors and the high-side MOSFET than to ground plane, where the PGND pin and V DD
allow distance between the inductor and the low- bypass capacitor go; and the controller’s analog
side MOSFET or between the inductor and the out- ground plane where sensitive analog components,
put filter capacitor. the analog GND pin, and VCC bypass capacitor go.
• MOSFET drivers: Keep the high-current, gate-dri- The analog GND plane must meet the PGND plane
ver traces (DL, DH, LX, and BST) short and wide only at a single point directly beneath the controller.
to minimize trace resistance and inductance. This This star ground point (where the power and analog
is essential for high-power MOSFETs that require grounds are connected) should connect to the
low-impedance gate drivers to avoid shoot- high-power system ground with a low-impedance
through currents. connection (short trace or multiple vias) from PGND
to the source of the low-side MOSFET.
• Analog control signals: Connect all analog grounds
to a separate solid copper plane, which connects to 5) Connect the output power planes (VCORE and sys-
the GND pin of the Quick-PWM controller as shown tem ground planes) directly to the output filter
in Figures 1 and 2. This includes the VCC bypass capacitor positive and negative terminals with multi-
capacitor, remote-sense bypass capacitors, and ple vias. Place the entire DC-DC converter circuit
the compensation (CCV) components. as close as is practical to the CPU.

40 ______________________________________________________________________________________
1-Phase Quick-PWM
Intel IMVP-6.5/GMCH Controllers
Chip Information Package Information

MAX17528
PROCESS: BiCMOS For the latest package outline information and land patterns, go
to www.maxim-ic.com/packages.

PACKAGE TYPE PACKAGE CODE DOCUMENT NO.


32 TQFN T3255-3 21-0140

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 41
© 2009 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.

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