MCP1825/MCP1825S: 500 Ma, Low Voltage, Low Quiescent Current LDO Regulator

MCP1825/MCP1825S
500 mA, Low Voltage, Low Quiescent Current LDO Regulator
Features Description
• 500 mA Output Current Capability The MCP1825/MCP1825S is a 500 mA Low Dropout
• Input Operating Voltage Range: 2.1V to 6.0V (LDO) linear regulator that provides high current and
• Adjustable Output Voltage Range: 0.8V to 5.0V low output voltages. The MCP1825 comes in a fixed or
(MCP1825 only) adjustable output voltage version, with an output
voltage range of 0.8V to 5.0V. The 500 mA output
• Standard Fixed Output Voltages:
current capability, combined with the low output voltage
- 0.8V, 1.2V, 1.8V, 2.5V, 3.0V, 3.3V, 5.0V capability, make the MCP1825 a good choice for new
• Other Fixed Output Voltage Options Available sub-1.8V output voltage LDO applications that have
Upon Request high current demands. The MCP1825S is a 3-pin fixed
• Low Dropout Voltage: 210 mV Typical at 500 mA voltage version.
• Typical Output Voltage Tolerance: 0.5% The MCP1825/MCP1825S is stable using ceramic
• Stable with 1.0 µF Ceramic Output Capacitor output capacitors that inherently provide lower output
• Fast response to Load Transients noise and reduce the size and cost of the entire
regulator solution. Only 1 µF of output capacitance is
• Low Supply Current: 120 µA (typical)
needed to stabilize the LDO.
• Low Shutdown Supply Current: 0.1 µA (typical)
(MCP1825 only) Using CMOS construction, the quiescent current
consumed by the MCP1825/MCP1825S is typically
• Fixed Delay on Power Good Output
less than 120 µA over the entire input voltage range,
(MCP1825 only)
making it attractive for portable computing applications
• Short Circuit Current Limiting and that demand high output current. The MCP1825
Overtemperature Protection versions have a Shutdown (SHDN) pin. When shut
• TO-263-5 (DDPAK-5), TO-220-5, SOT-223-5 down, the quiescent current is reduced to less than
Package Options (MCP1825). 0.1 µA.
• TO-263-3 (DDPAK-3), TO-220-3, SOT-223-3 On the MCP1825 fixed output versions, the scaled-
Package Options (MCP1825S). down output voltage is internally monitored and a
power good (PWRGD) output is provided when the
Applications output is within 92% of regulation (typical). The
PWRGD delay is internally fixed at 110 µs (typical).
• High-Speed Driver Chipset Power
• Networking Backplane Cards The overtemperature and short circuit current-limiting
provide additional protection for the LDO during system
• Notebook Computers
fault conditions.
• Network Interface Cards
• Palmtop Computers
• 2.5V to 1.XV Regulators
© 2008 Microchip Technology Inc. DS22056B-page 1

MCP1825/MCP1825S
Package Types
MCP1825 MCP1825S
DDPAK-5 TO-220-5 DDPAK-3 TO-220-3
Fixed/Adjustable
1 2 3
1 2 3
1 2 3 4 5
1 2 3 4 5
SOT-223-5 SOT-223-3
6 4
1 2 3 4 5 1 2 3
Pin Fixed Adjustable Pin
1 SHDN SHDN 1 VIN

2 VIN VIN 2 GND (TAB)
3 GND (TAB) GND (TAB) 3 VOUT

4 GND (TAB)
4 VOUT VOUT
5 PWRGD ADJ
6 GND (TAB) GND (TAB)
DS22056B-page 2 © 2008 Microchip Technology Inc.

MCP1825/MCP1825S
Typical Applications
MCP1825 Fixed Output Voltage
PWRGD
R1
On 100 kΩ
Off SHDN
1 VOUT = 1.8V @ 500 mA
VIN = 2.3V to 2.8V VIN VOUT
GND
C1
C2
4.7 µF 1 µF
MCP1825 Adjustable Output Voltage
VADJ
R2
R1 20 kΩ
On 40 kΩ
Off SHDN
1 VOUT = 1.2V @ 500 mA
VIN = 2.1V to 2.8V VIN VOUT
C1
C2
4.7 µF 1 µF
GND

MCP1825/MCP1825S
Functional Block Diagram - Adjustable Output
PMOS
VIN VOUT
Undervoltage
Lock Out
(UVLO)
ISNS Cf Rf
SHDN ADJ/SENSE
+
Driver w/limit
and SHDN EA
Overtemperature
Sensing –
SHDN
VREF
V IN
SHDN Reference
Soft-Start
Comp TDELAY
GND
92% of VREF

MCP1825/MCP1825S
Functional Block Diagram - Fixed Output (3-Pin)
PMOS
VIN VOUT
Undervoltage Sense
Lock Out
(UVLO)
ISNS Cf Rf
SHDN
+
Driver w/limit
and SHDN EA
Overtemperature
Sensing –
SHDN
VREF
V IN
SHDN Reference
Soft-Start
Comp TDELAY
GND
92% of VREF

MCP1825/MCP1825S
Functional Block Diagram - Fixed Output (5-Pin)
PMOS
VIN VOUT
Undervoltage Sense
Lock Out
(UVLO)
ISNS Cf Rf
SHDN
+
Driver w/limit
and SHDN EA
Overtemperature
Sensing –
SHDN
VREF
V IN
SHDN Reference
Soft-Start
PWRGD
Comp TDELAY
GND
92% of VREF

MCP1825/MCP1825S
1.0 ELECTRICAL † Notice: Stresses above those listed under “Maximum Rat-
ings” may cause permanent damage to the device. This is a
CHARACTERISTICS stress rating only and functional operation of the device at
those or any other conditions above those indicated in the
Absolute Maximum Ratings † operational listings of this specification is not implied. Expo-
sure to maximum rating conditions for extended periods may
VIN ....................................................................................6.5V affect device reliability.
Maximum Voltage on Any Pin .. (GND – 0.3V) to (VDD + 0.3)V
Maximum Power Dissipation......... Internally-Limited (Note 6)
Output Short Circuit Duration ................................ Continuous
Storage temperature .....................................-65°C to +150°C
Maximum Junction Temperature, TJ ........................... +150°C
ESD protection on all pins (HBM/MM) ........... ≥ 4 kV; ≥ 300V
AC/DC CHARACTERISTICS
Electrical Specifications: Unless otherwise noted, VIN = VOUT(MAX) + VDROPOUT(MAX), Note 1, VR = 1.8V for Adjustable Output,
IOUT = 1 mA, CIN = COUT = 4.7 µF (X7R Ceramic), TA = +25°C.
Boldface type applies for junction temperatures, TJ (Note 7) of -40°C to +125°C
Parameters Sym Min Typ Max Units Conditions

Input Operating Voltage VIN 2.1 6.0 V Note 1
Input Quiescent Current Iq — 120 220 µA IL = 0 mA, VOUT = 0.8V to
5.0V
Input Quiescent Current for ISHDN — 0.1 3 µA SHDN = GND
SHDN Mode
Maximum Output Current IOUT 500 — — mA VIN = 2.1V to 6.0V
VR = 0.8V to 5.0V, Note 1
Line Regulation ΔVOUT/ — ±0.05 ±0.16 %/V (Note 1) ≤ VIN ≤ 6V
(VOUT x ΔVIN)
Load Regulation ΔVOUT/VOUT -1.0 ±0.5 1.0 % IOUT = 1 mA to 500 mA,
(Note 4)
Output Short Circuit Current IOUT_SC — 1.2 — A RLOAD < 0.1Ω, Peak Current
Adjust Pin Characteristics (Adjustable Output Only)
Adjust Pin Reference Voltage VADJ 0.402 0.410 0.418 V VIN = 2.1V to VIN = 6.0V,
IOUT = 1 mA
Adjust Pin Leakage Current IADJ -10 ±0.01 +10 nA VIN = 6.0V, VADJ = 0V to 6V
Adjust Temperature Coefficient TCVOUT — 40 — ppm/°C Note 3
Fixed-Output Characteristics (Fixed Output Only)
Voltage Regulation VOUT VR - 2.5% VR ±0.5% VR + 2.5% V Note 2
Note 1: The minimum VIN must meet two conditions: VIN ≥ 2.1V and VIN ≥ VOUT(MAX) + VDROPOUT(MAX).
2: VR is the nominal regulator output voltage for the fixed cases. VR = 1.2V, 1.8V, etc. VR is the desired set point output
voltage for the adjustable cases. VR = VADJ * ((R1/R2)+1). Figure 4-1.
3: TCVOUT = (VOUT-HIGH – VOUT-LOW) *106 / (VR * ΔTemperature). VOUT-HIGH is the highest voltage measured over the
temperature range. VOUT-LOW is the lowest voltage measured over the temperature range.
4: Load regulation is measured at a constant junction temperature using low duty-cycle pulse testing. Load regulation is
tested over a load range from 1 mA to the maximum specified output current.
5: Dropout voltage is defined as the input-to-output voltage differential at which the output voltage drops 2% below its
nominal value that was measured with an input voltage of VIN = VOUT(MAX) + VDROPOUT(MAX).
6: The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junction
temperature and the thermal resistance from junction to air. (i.e., TA, TJ, θJA). Exceeding the maximum allowable power
dissipation will cause the device operating junction temperature to exceed the maximum +150°C rating. Sustained
junction temperatures above 150°C can impact device reliability.
7: The junction temperature is approximated by soaking the device under test at an ambient temperature equal to the
desired junction temperature. The test time is small enough such that the rise in the junction temperature over the
ambient temperature is not significant.

MCP1825/MCP1825S
AC/DC CHARACTERISTICS (CONTINUED)
Dropout Characteristics
Dropout Voltage VDROPOUT — 210 350 mV Note 5, IOUT = 500 mA,
VIN(MIN) = 2.1V
Power Good Characteristics
PWRGD Input Voltage Operat- VPWRGD_VIN 1.0 — 6.0 V TA = +25°C
ing Range 1.2 — 6.0 TA = -40°C to +125°C
For VIN < 2.1V, ISINK = 100 µA
PWRGD Threshold Voltage VPWRGD_TH %VOUT Falling Edge
(Referenced to VOUT) 89 92 95 VOUT < 2.5V Fixed,
VOUT = Adj.
90 92 94 VOUT >= 2.5V Fixed
PWRGD Threshold Hysteresis VPWRGD_HYS 1.0 2.0 3.0 %VOUT
PWRGD Output Voltage Low VPWRGD_L — 0.2 0.4 V IPWRGD SINK = 1.2 mA,
ADJ = 0V
PWRGD Leakage PWRGD_LK — 1 — nA VPWRGD = VIN = 6.0V
PWRGD Time Delay TPG — 110 — µs Rising Edge
RPULLUP = 10 kΩ
Detect Threshold to PWRGD TVDET-PWRGD — 200 — µs VOUT = VPWRGD_TH + 20 mV
Active Time Delay to VPWRGD_TH - 20 mV
Shutdown Input
Logic High Input VSHDN-HIGH 45 — — %VIN VIN = 2.1V to 6.0V
Logic Low Input VSHDN-LOW — — 15 %VIN VIN = 2.1V to 6.0V
SHDN Input Leakage Current SHDNILK -0.1 ±0.001 +0.1 µA VIN = 6V, SHDN =VIN,
SHDN = GND
AC Performance
Output Delay From SHDN TOR — 100 — µs SHDN = GND to VIN,
VOUT = GND to 95% VR
Output Noise eN — 2.0 — µV/√Hz IOUT = 200 mA, f = 1 kHz,
COUT = 10 µF (X7R Ceramic),
VOUT = 2.5V

MCP1825/MCP1825S
AC/DC CHARACTERISTICS (CONTINUED)
Power Supply Ripple Rejection PSRR — 60 — dB f = 100 Hz, COUT = 4.7 µF,
Ratio IOUT = 100 µA,
VINAC = 100 mV pk-pk,
CIN = 0 µF
Thermal Shutdown Temperature TSD — 150 — °C IOUT = 100 µA, VOUT = 1.8V,
VIN = 2.8V
Thermal Shutdown Hysteresis ΔTSD — 10 — °C IOUT = 100 µA, VOUT = 1.8V,
VIN = 2.8V

MCP1825/MCP1825S
TEMPERATURE SPECIFICATIONS

Temperature Ranges
Operating Junction Temperature Range TJ -40 — +125 °C Steady State
Maximum Junction Temperature TJ — — +150 °C Transient
Storage Temperature Range TA -65 — +150 °C
Thermal Package Resistances
Thermal Resistance, 3LD DDPAK θJA — 31.4 — °C/W 4-Layer JC51 Standard
θJC — 3.0 — Board
Thermal Resistance, 3LD TO-220 θJA — 29.4 — °C/W 4-Layer JC51 Standard
Thermal Resistance, 3LD SOT-223 θJA — 62 — °C/W EIA/JEDEC JESD51-751-7
θJC — 15.0 — 4 Layer Board
Thermal Resistance, 5LD DDPAK θJA — 31.2 — °C/W 4-Layer JC51 Standard
Thermal Resistance, 5LD TO-220 θJA — 29.3 — °C/W 4-Layer JC51 Standard
Thermal Resistance, 5LD SOT-223 θJA — 62 — °C/W EIA/JEDEC JESD51-751-7
θJC — 15.0 — 4 Layer Board

MCP1825/MCP1825S
2.0 TYPICAL PERFORMANCE CURVES
Note: The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note: Unless otherwise indicated, COUT = 4.7 µF Ceramic (X7R), CIN = 4.7 µF Ceramic (X7R), IOUT = 1 mA,
Temperature = +25°C, VIN = VOUT + 0.5V, Fixed output.
140 0.10
VOUT = 1.2V adj
VOUT = 1.2V Adj 0.09 IOUT = 1 mA
VIN = 2.1V to 6.0V
Line Regulation (%/V)

Quiescent Current (μA)
IOUT = 0 mA 0.08
130
0.07
130°C
120 0.06 IOUT = 50 mA
90°C
0.05
110 0.04
25°C
0°C 0.03 IOUT=100 mA IOUT=500 mA
100 -45°C 0.02 IOUT=250 mA
0.01
90 0.00
2 3 4 5 6 -45 -20 5 30 55 80 105 130
Input Voltage (V) Temperature (°C)
FIGURE 2-1: Quiescent Current vs. Input FIGURE 2-4: Line Regulation vs.
Voltage (Adjustable Version). Temperature (Adjustable Version).
200 0.20
VOUT = 1.2V Adj IOUT = 1.0 mA to 500 mA
190 0.15
Load Regulation (%)
Ground Current (μA)
180
VOUT = 3.3V
170 0.10
160 VIN=5.0V
0.05
150 VIN=3.3V
0.00 VOUT = 1.8V
140
VOUT = 0.8V
130 -0.05
VOUT = 5.0V
120
110
-0.10
VIN=2.5V
100 -0.15
0 100 200 300 400 500 600 -45 -20 5 30 55 80 105 130
Load Current (mA) Temperature (°C)
FIGURE 2-2: Ground Current vs. Load FIGURE 2-5: Load Regulation vs.
Current (Adjustable Version). Temperature (Adjustable Version).
170 0.4110
VOUT = 1.2V Adj VOUT = 1.8V
160 IOUT = 0 mA 0.4105
IOUT = 1.0 mA
Adjust Pin Voltage (V)
150 0.4100
140 0.4095 VIN = 6.0V
VIN=6.0V
130 VIN=5.0V 0.4090
120 0.4085 VIN = 4.0V
110 VIN=4.0V 0.4080
100 0.4075
VIN=2.1V VIN=3.0V VIN = 2.3V
90 0.4070
-45 -20 5 30 55 80 105 130 -45 -20 5 30 55 80 105 130
Temperature (°C) Temperature (°C)
FIGURE 2-3: Quiescent Current vs. FIGURE 2-6: Adjust Pin Voltage vs.
Junction Temperature (Adjustable Version). Temperature (Adjustable Version).

MCP1825/MCP1825S
0.30 160
VOUT = 0.8V
150 IOUT = 0 mA

0.25
Dropout Voltage (V)
VOUT = 5.0V Adj 140

0.20 +130°C
130 +90°C
0.15 +25°C
VOUT = 2.5V Adj 120
0°C
0.10
110 -45°C
0.05 100
0.00 90
0 50 100 150 200 250 300 350 400 450 500 2 3 4 5 6
Load Current (mA) Input Voltage (V)
FIGURE 2-7: Dropout Voltage vs. Load FIGURE 2-10: Quiescent Current vs. Input
Current (Adjustable Version). Voltage.
0.30 150
IOUT = 500 mA VOUT = 2.5V

140 IOUT = 0 mA
0.28
Dropout Voltage (V)
VOUT = 5.0V Adj

130 +130°C
0.26
120 +90°C
VOUT = 3.3V Adj
0.24 +25°C
110 +0°C
VOUT = 2.5V Adj
0.22 100
-45°C
0.20 90
-45 -20 5 30 55 80 105 130 3 3.5 4 4.5 5 5.5 6
Temperature (°C) Input Voltage (V)
FIGURE 2-8: Dropout Voltage vs. FIGURE 2-11: Quiescent Current vs. Input
Temperature (Adjustable Version). Voltage.
170 250
Power Good Time Delay (µS)
VOUT = 2.5V Fixed VIN = 2.3V for VR=0.8V

160 VIN = 3.0V for VR=2.5V
Ground Current (μA)
200
150
VIN = 6.0V
150 VOUT=2.5V
140
VIN = 5.0V
130 100
VOUT=0.8V
120
VIN = 3.0V VIN = 4.0V 50
110
100 0
-45 -20 5 30 55 80 105 130 0 100 200 300 400 500 600
Temperature (°C) Load Current (mA)
FIGURE 2-9: Power Good (PWRGD) FIGURE 2-12: Ground Current vs. Load
Time Delay vs. Temperature. Current.

MCP1825/MCP1825S
140 0.045
IOUT = 0 mA VR = 2.5V
135 VIN = 3.1V to 6.0V

IOUT = 1 mA
0.040
130
125 VOUT = 5V
0.035
120 IOUT = 50 mA
0.030 IOUT = 100 mA
115
110 VOUT = 2.5V
0.025
105
VOUT = 0.8V
0.020
100 IOUT = 250 mA IOUT = 500 mA
95 0.015
-45 -20 5 30 55 80 105 130 -45 -20 5 30 55 80 105 130
FIGURE 2-13: Quiescent Current vs. FIGURE 2-16: Line Regulation vs.
Temperature. Temperature.
0.30
VR = 0.8V 0.25
VOUT = 0.8V
0.25 IOUT = 1 mA to 500 mA
0.15
Load Regulation (%)

VIN = 4.0V
VIN = 5.0V
0.20
Ishdn (μA)
VIN = 6.0V
0.05
0.15 VIN = 2.1V
VIN = 5.0V VIN = 4.0V
VIN = 2.3V
-0.05
0.10
VIN = 6.0V
0.05 -0.15
0.00 -0.25
-45 -20 5 30 55 80 105 130 -45 -20 5 30 55 80 105 130
FIGURE 2-14: ISHDN vs. Temperature. FIGURE 2-17: Load Regulation vs.
Temperature (VOUT < 2.5V Fixed).
0.09 0.00
VOUT = 0.8V IOUT = 1 mA to 500 mA
0.08 IOUT = 1 mA -0.05
VIN = 2.1V to 6.0V

Load Regulation (%)
VOUT = 2.5V
0.07 -0.10
IOUT = 50 mA
0.06 -0.15
IOUT = 100 mA
0.05 -0.20 VOUT = 5.0V
0.04 IOUT = 250 mA -0.25
0.03 -0.30
IOUT = 500 mA
0.02 -0.35
-45 -20 5 30 55 80 105 130 -45 -20 5 30 55 80 105 130
FIGURE 2-15: Line Regulation vs. FIGURE 2-18: Load Regulation vs.
Temperature. Temperature (VOUT ≥ 2.5V Fixed).

MCP1825/MCP1825S
0.30
10
VR=2.5V, VIN=3.3V COUT=1 μF cer
0.25 CIN=10 μF cer
Dropout Voltage (V)
Noise (mV/ √Hz)

0.20 VOUT = 5.0V
1
IOUT=200 mA
0.15 VOUT = 2.5V VR=0.8V, VIN=2.3V
0.10 0.1
0.05
0.00 0.01
0 100 200 300 400 500 0.01 0.1 1 10 100 1000
Load Current (mA) Frequency (kHz)
FIGURE 2-19: Dropout Voltage vs. Load FIGURE 2-22: Output Noise Voltage
Current. Density vs. Frequency.
0.30 0.0
IOUT = 500 mA
0.28 -10.0
Dropout Voltage (V)
-20.0
0.26 PSRR (dB)
VOUT = 5.0V -30.0
0.24 -40.0 VR=1.2V Adj
0.22 -50.0 COUT=10 μF ceramic X7R
VIN=2.5V
-60.0 CIN=0 μF
0.20
VOUT = 2.5V -70.0 IOUT=10 mA
0.18
-80.0
-45 -20 5 30 55 80 105 130
0.01 0.1 1 10 100 1000
Temperature (°C) Frequency (kHz)
FIGURE 2-20: Dropout Voltage vs. FIGURE 2-23: Power Supply Ripple
Temperature. Rejection (PSRR) vs. Frequency (Adj.).
0.0
0.80
VOUT = 2.5V -10.0
Short Circuit Current (A)
0.70
-20.0
0.60
-30.0
PSRR (dB)
0.50
-40.0
0.40 VR=2.5V (Fixed)
-50.0
0.30 COUT=22 μF ceramic X7R
-60.0 VIN=3.3V
0.20 -70.0 CIN=0 μF
0.10 -80.0 IOUT=10 mA
0.00 -90.0
0.00 1.00 2.00 3.00 4.00 5.00 6.00 0.01 0.1 1 10 100 1000
Input Voltage (V) Frequency (kHz)
FIGURE 2-21: Short Circuit Current vs. FIGURE 2-24: Power Supply Ripple
Input Voltage. Rejection (PSRR) vs. Frequency.

MCP1825/MCP1825S
FIGURE 2-25: 2.5V (Adj.) Startup from VIN. FIGURE 2-28: Dynamic Line Response.
FIGURE 2-26: 2.5V (Adj.) Startup from FIGURE 2-29: Dynamic Load Response
Shutdown. (1 mA to 500 mA).
FIGURE 2-27: Power Good (PWRGD) FIGURE 2-30: Dynamic Load Response
Timing. (10 mA to 500 mA).

MCP1825/MCP1825S
3.0 PIN DESCRIPTION
The descriptions of the pins are listed in Table 3-1.
TABLE 3-1: PIN FUNCTION TABLE
3-Pin Fixed 5-Pin Fixed Adjustable
Name Description
Output Output Output
— 1 1 SHDN Shutdown Control Input (active-low)
1 2 2 VIN Input Voltage Supply
2 3 3 GND Ground
3 4 4 VOUT Regulated Output Voltage
— 5 — PWRGD Power Good Output
— — 5 ADJ Voltage Adjust/Sense Input
Exposed Pad Exposed Pad Exposed Pad EP Exposed Pad of the Package (ground potential)
3.1 Shutdown Control Input (SHDN) 3.5 Power Good Output (PWRGD)
The SHDN input is used to turn the LDO output voltage The PWRGD output is an open-drain output used to
on and off. When the SHDN input is at a logic-high indicate when the LDO output voltage is within 92%
level, the LDO output voltage is enabled. When the (typically) of its nominal regulation value. The PWRGD
SHDN input is pulled to a logic-low level, the LDO threshold has a typical hysteresis value of 2%. The
output voltage is disabled. When the SHDN input is PWRGD output is delayed by 110 µs (typical) from the
pulled low, the PWRGD output also goes low and the time the LDO output is within 92% + 3% (maximum
LDO enters a low quiescent current shutdown state hysteresis) of the regulated output value on power-up.
where the typical quiescent current is 0.1 µA. This delay time is internally fixed.
3.2 Input Voltage Supply (VIN) 3.6 Output Voltage Adjust Input (ADJ)
Connect the unregulated or regulated input voltage For adjustable applications, the output voltage is
source to VIN. If the input voltage source is located connected to the ADJ input through a resistor divider
several inches away from the LDO, or the input source that sets the output voltage regulation value. This
is a battery, it is recommended that an input capacitor provides the user the capability to set the output
be used. A typical input capacitance value of 1 µF to voltage to any value they desire within the 0.8V to 5.0V
10 µF should be sufficient for most applications. range of the device.
3.3 Ground (GND) 3.7 Exposed Pad (EP)

Connect the GND pin of the LDO to a quiet circuit The DDPAK and TO-220 package have an exposed
ground. This will help the LDO power supply rejection tab on the package. A heat sink may may be mount to
ratio and noise performance. The ground pin of the the tab to aid in the removal of heat from the package
LDO only conducts the quiescent current of the LDO during operation. The exposed tab is at the ground
(typically 120 µA), so a heavy trace is not required. potential of the LDO.
For applications that have switching or noisy inputs, tie
the GND pin to the return of the output capacitor.
Ground planes help lower inductance and voltage
spikes caused by fast transient load currents and are
recommended for applications that are subjected to
fast load transients.
3.4 Regulated Output Voltage (VOUT)

The VOUT pin is the regulated output voltage of the
LDO. A minimum output capacitance of 1.0 µF is
required for LDO stability. The MCP1825/MCP1825S
is stable with ceramic, tantalum and aluminum-electro-
lytic capacitors. See Section 4.3 “Output Capacitor”
for output capacitor selection guidance.

MCP1825/MCP1825S
4.0 DEVICE OVERVIEW EQUATION 4-2:
V OUT – V ADJ
The MCP1825/MCP1825S is a high output current, R 1 = R 2 ⎛ --------------------------------⎞
⎝ V ADJ ⎠
Low Dropout (LDO) voltage regulator. The low dropout
Where:
voltage of 210 mV typical at 500 mA of current makes
it ideal for battery-powered applications. Unlike other VOUT = LDO Output Voltage
high output current LDOs, the MCP1825/MCP1825S VADJ = ADJ Pin Voltage
only draws a maximum of 220 µA of quiescent current. (typically 0.41V)
The MCP1825 has a shutdown control input and a
power good output.
4.2 Output Current and Current
4.1 LDO Output Voltage Limiting
The 5-pin MCP1825 LDO is available with either a fixed The MCP1825/MCP1825S LDO is tested and ensured
output voltage or an adjustable output voltage. The to supply a minimum of 500 mA of output current. The
output voltage range is 0.8V to 5.0V for both versions. MCP1825/MCP1825S has no minimum output load, so
The 3-pin MCP1825S LDO is available as a fixed the output load current can go to 0 mA and the LDO will
voltage device. continue to regulate the output voltage to within
tolerance.
4.1.1 ADJUST INPUT
The MCP1825/MCP1825S also incorporates an output
The adjustable version of the MCP1825 uses the ADJ current limit. If the output voltage falls below 0.7V due
pin (pin 5) to get the output voltage feedback for output to an overload condition (usually represents a shorted
voltage regulation. This allows the user to set the load condition), the output current is limited to 1.2A
output voltage of the device with two external resistors. (typical). If the overload condition is a soft overload, the
The nominal voltage for ADJ is 0.41V. MCP1825/MCP1825S will supply higher load currents
Figure 4-1 shows the adjustable version of the of up to 1.5A. The MCP1825/MCP1825S should not be
MCP1825. Resistors R1 and R2 form the resistor operated in this condition continuously as it may result
divider network necessary to set the output voltage. in failure of the device. However, this does allow for
With this configuration, the equation for setting VOUT is: device usage in applications that have higher pulsed
load currents having an average output current value of
EQUATION 4-1: 500 mA or less.
R1 + R2 Output overload conditions may also result in an over-
V OUT = V ADJ ⎛ ------------------⎞
⎝ R2 ⎠ temperature shutdown of the device. If the junction
Where: temperature rises above 150°C, the LDO will shut
down the output voltage. See Section 4.8 “Overtem-
VOUT = LDO Output Voltage perature Protection” for more information on
VADJ = ADJ Pin Voltage overtemperature shutdown.
(typically 0.41V)
4.3 Output Capacitor
MCP1825-ADJ
The MCP1825/MCP1825S requires a minimum output
capacitance of 1 µF for output voltage stability.
VOUT
Ceramic capacitors are recommended because of their
On R1
size, cost and environmental robustness qualities.
Off 1 2 3 4 5 C2
SHDN ADJ 1 µF Aluminum-electrolytic and tantalum capacitors can be
VIN
used on the LDO output as well. The Equivalent Series
Resistance (ESR) of the electrolytic output capacitor
C1 R2
4.7 µF GND must be no greater than 1 ohm. The output capacitor
should be located as close to the LDO output as is
practical. Ceramic materials X7R and X5R have low
temperature coefficients and are well within the
FIGURE 4-1: Typical adjustable output acceptable ESR range required. A typical 1 µF X7R
voltage application circuit. 0805 capacitor has an ESR of 50 milli-ohms.
The allowable resistance value range for resistor R2 is Larger LDO output capacitors can be used with the
from 10 kΩ to 200 kΩ. Solving the equation for R1 MCP1825/MCP1825S to improve dynamic
yields the following equation: performance and power supply ripple rejection
performance. A maximum of 22 µF is recommended.
Aluminum-electrolytic capacitors are not recom-
mended for low temperature applications of < -25°C.

MCP1825/MCP1825S
4.4 Input Capacitor The power good output is an open-drain output that can
be pulled up to any voltage that is equal to or less than
Low input source impedance is necessary for the LDO the LDO input voltage. This output is capable of sinking
output to operate properly. When operating from 1.2 mA (VPWRGD < 0.4V maximum).
batteries, or in applications with long lead length
(> 10 inches) between the input source and the LDO,
some input capacitance is recommended. A minimum
of 1.0 µF to 4.7 µF is recommended for most VPWRGD_TH
applications.
VOUT
For applications that have output step load
TPG
requirements, the input capacitance of the LDO is very
important. The input capacitance provides the LDO
with a good local low-impedance source to pull the VOH
transient currents from in order to respond quickly to TVDET_PWRG
the output load step. For good step response

performance, the input capacitor should be of PWRGD
equivalent (or higher) value than the output capacitor.
The capacitor should be placed as close to the input of VOL
the LDO as is practical. Larger input capacitors will also
help reduce any high-frequency noise on the input and
output of the LDO and reduce the effects of any FIGURE 4-2: Power Good Timing.
inductance that exists between the input source
voltage and the input capacitance of the LDO.
4.5 Power Good Output (PWRGD) VIN

TOR
The PWRGD output is used to indicate when the output
voltage of the LDO is within 92% (typical value, see 70 µs
30 µs
Section 1.0 “Electrical Characteristics” for Minimum
and Maximum specifications) of its nominal regulation
SHDN TPG
value.
As the output voltage of the LDO rises, the PWRGD
output will be held low until the output voltage has
exceeded the power good threshold plus the hysteresis
value. Once this threshold has been exceeded, the VOUT
power good time delay is started (shown as TPG in the
Electrical Characteristics table). The power good time
delay is fixed at 110 µs (typical). After the time delay
period, the PWRGD output will go high, indicating that
PWRGD
the output voltage is stable and within regulation limits.
If the output voltage of the LDO falls below the power
good threshold, the power good output will transition
low. The power good circuitry has a 170 µs delay when FIGURE 4-3: Power Good Timing from
detecting a falling output voltage, which helps to Shutdown.
increase noise immunity of the power good output and
avoid false triggering of the power good output during 4.6 Shutdown Input (SHDN)
fast output transients. See Figure 4-2 for power good
timing characteristics. The SHDN input is an active-low input signal that turns
the LDO on and off. The SHDN threshold is a
When the LDO is put into Shutdown mode using the percentage of the input voltage. The typical value of
SHDN input, the power good output is pulled low this shutdown threshold is 30% of VIN, with minimum
immediately, indicating that the output voltage will be and maximum limits over the entire operating
out of regulation. The timing diagram for the power temperature range of 45% and 15%, respectively.
good output when using the shutdown input is shown in
Figure 4-3. The SHDN input will ignore low-going pulses (pulses
meant to shut down the LDO) that are up to 400 ns in
pulse width. If the shutdown input is pulled low for more
than 400 ns, the LDO will enter Shutdown mode. This
small bit of filtering helps to reject any system noise
spikes on the shutdown input signal.

MCP1825/MCP1825S
On the rising edge of the SHDN input, the shutdown 4.7 Dropout Voltage and
circuitry has a 30 µs delay before allowing the LDO Undervoltage Lockout
output to turn on. This delay helps to reject any false
turn-on signals or noise on the SHDN input signal. After Dropout voltage is defined as the input-to-output
the 30 µs delay, the LDO output enters its soft-start voltage differential at which the output voltage drops
period as it rises from 0V to its final regulation value. If 2% below the nominal value that was measured with a
the SHDN input signal is pulled low during the 30 µs VR + 0.5V differential applied. The MCP1825/
delay period, the timer will be reset and the delay time MCP1825S LDO has a very low dropout voltage
will start over again on the next rising edge of the specification of 210 mV (typical) at 500 mA of output
SHDN input. The total time from the SHDN input going current. See Section 1.0 “Electrical Characteristics”
high (turn-on) to the LDO output being in regulation is for maximum dropout voltage specifications.
typically 100 µs. See Figure 4-4 for a timing diagram of The MCP1825/MCP1825S LDO operates across an
the SHDN input. input voltage range of 2.1V to 6.0V and incorporates
input Undervoltage Lockout (UVLO) circuitry that
TOR keeps the LDO output voltage off until the input voltage
400 ns (typ) reaches a minimum of 2.00V (typical) on the rising
70 µs edge of the input voltage. As the input voltage falls, the
30 µs
LDO output will remain on until the input voltage level
reaches 1.82V (typical).
SHDN
Since the MCP1825/MCP1825S LDO undervoltage
lockout activates at 1.82V as the input voltage is falling,
the dropout voltage specification does not apply for
output voltages that are less than 1.8V.
VOUT For high-current applications, voltage drops across the
PCB traces must be taken into account. The trace
resistances can cause significant voltage drops
FIGURE 4-4: Shutdown Input Timing between the input voltage source and the LDO. For
Diagram. applications with input voltages near 2.1V, these PCB
trace voltage drops can sometimes lower the input
voltage enough to trigger a shutdown due to
undervoltage lockout.
4.8 Overtemperature Protection

The MCP1825/MCP1825S LDO has temperature-
sensing circuitry to prevent the junction temperature
from exceeding approximately 150°C. If the LDO
junction temperature does reach 150°C, the LDO
output will be turned off until the junction temperature
cools to approximately 140°C, at which point the LDO
output will automatically resume normal operation. If
the internal power dissipation continues to be
excessive, the device will again shut off. The junction
temperature of the die is a function of power
dissipation, ambient temperature and package thermal
resistance. See Section 5.0 “Application Circuits/
Issues” for more information on LDO power
dissipation and junction temperature.

MCP1825/MCP1825S
5.0 APPLICATION CIRCUITS/ In addition to the LDO pass element power dissipation,
there is power dissipation within the MCP1825/
ISSUES MCP1825S as a result of quiescent or ground current.
The power dissipation as a result of the ground current
5.1 Typical Application can be calculated using the following equation:
The MCP1825/MCP1825S is used for applications that
require high LDO output current and a power good EQUATION 5-2:
output. P I ( GND ) = V IN ( MAX ) × I VIN
Where:
VOUT = 2.5V @ 500 mA
PI(GND = Power dissipation due to the
MCP1825-2.5 quiescent current of the LDO
On R1
Off 1 2 3 4 5 10 kΩ C2 VIN(MAX) = Maximum input voltage
SHDN 10 µF
IVIN = Current flowing in the VIN pin
VIN
3.3V with no LDO output current
C1 (LDO quiescent current)
4.7 µF
GND PWRGD
The total power dissipated within the MCP1825/
MCP1825S is the sum of the power dissipated in the
FIGURE 5-1: Typical Application Circuit. LDO pass device and the P(IGND) term. Because of the
CMOS construction, the typical IGND for the MCP1825/
5.1.1 APPLICATION CONDITIONS MCP1825S is 120 µA. Operating at a maximum VIN of
Package Type = TO-220-5 3.465V results in a power dissipation of 0.12 milli-Watts
for a 2.5V output. For most applications, this is small
Input Voltage Range = 3.3V ± 5% compared to the LDO pass device power dissipation
VIN maximum = 3.465V and can be neglected.
VIN minimum = 3.135V The maximum continuous operating junction
VDROPOUT (max) = 0.350V temperature specified for the MCP1825/MCP1825S is
VOUT (typical) = 2.5V +125°C. To estimate the internal junction temperature
of the MCP1825/MCP1825S, the total internal power
IOUT = 500 mA maximum dissipation is multiplied by the thermal resistance from
PDISS (typical) = 0.483W junction to ambient (RθJA) of the device. The thermal
Temperature Rise = 14.2°C resistance from junction to ambient for the TO-220-5
package is estimated at 29.3°C/W.
5.2 Power Calculations
EQUATION 5-3:
5.2.1 POWER DISSIPATION T J ( MAX ) = P TOTAL × Rθ JA + T AMAX
The internal power dissipation within the MCP1825/
TJ(MAX) = Maximum continuous junction
MCP1825S is a function of input voltage, output
temperature
voltage, output current and quiescent current.
Equation 5-1 can be used to calculate the internal PTOTAL = Total device power dissipation
power dissipation for the LDO. RθJA = Thermal resistance from junction to
ambient
EQUATION 5-1: TAMAX = Maximum ambient temperature
P LDO = ( V IN ( MAX ) ) – V OUT ( MIN ) ) × I OUT ( MAX ) )
Where:
PLDO = LDO Pass device internal
power dissipation
VIN(MAX) = Maximum input voltage
VOUT(MIN) = LDO minimum output voltage

MCP1825/MCP1825S
The maximum power dissipation capability for a 5.3 Typical Application
package can be calculated given the junction-to-
ambient thermal resistance and the maximum ambient Internal power dissipation, junction temperature rise,
temperature for the application. Equation 5-4 can be junction temperature and maximum power dissipation
used to determine the package maximum internal is calculated in the following example. The power
power dissipation. dissipation as a result of ground current is small
enough to be neglected.
EQUATION 5-4:
5.3.1 POWER DISSIPATION EXAMPLE
( T J ( MAX ) – T A ( MAX ) )
P D ( MAX ) = ---------------------------------------------------
Rθ JA Package
Package Type = TO-220-5
PD(MAX) = Maximum device power dissipation
Input Voltage
TJ(MAX) = maximum continuous junction
VIN = 3.3V ± 5%
temperature
LDO Output Voltage and Current
TA(MAX) = maximum ambient temperature
VOUT = 2.5V
RθJA = Thermal resistance from junction-to-
ambient IOUT = 500 mA
Maximum Ambient Temperature
TA(MAX) = 60°C
EQUATION 5-5:
T J ( RISE ) = P D ( MAX ) × Rθ JA Internal Power Dissipation
PLDO(MAX) = (VIN(MAX) – VOUT(MIN)) x IOUT(MAX)
TJ(RISE) = Rise in device junction temperature PLDO = ((3.3V x 1.05) – (2.5V x 0.975))
over the ambient temperature x 500 mA
PD(MAX) = Maximum device power dissipation PLDO = 0.514 Watts
RθJA = Thermal resistance from junction-to- 5.3.1.1 Device Junction Temperature Rise
ambient
The internal junction temperature rise is a function of
internal power dissipation and the thermal resistance
EQUATION 5-6: from junction-to-ambient for the application. The
thermal resistance from junction-to-ambient (RθJA) is
T J = T J ( RISE ) + T A
derived from EIA/JEDEC standards for measuring
thermal resistance. The EIA/JEDEC specification is
TJ = Junction temperature
JESD51. The standard describes the test method and
TJ(RISE) = Rise in device junction temperature board specifications for measuring the thermal
over the ambient temperature resistance from junction to ambient. The actual thermal
TA = Ambient temperature resistance for a particular application can vary
depending on many factors such as copper area and
thickness. Refer to AN792, “A Method to Determine
How Much Power a SOT23 Can Dissipate in an
Application” (DS00792), for more information regarding
this subject.
TJ(RISE) = PTOTAL x RθJA

TJRISE = 0.514 W x 29.3° C/W
TJRISE = 15.06°C

MCP1825/MCP1825S
5.3.1.2 Junction Temperature Estimate
To estimate the internal junction temperature, the
calculated temperature rise is added to the ambient or
offset temperature. For this example, the worst-case
junction temperature is estimated below:
TJ = TJRISE + TA(MAX)
TJ = 15.06°C + 60.0°C
TJ = 75.06°C
5.3.1.3 Maximum Package Power

Dissipation at 60°C Ambient
Temperature
TO-220-5 (29.3°C/W RθJA):
PD(MAX) = (125°C – 60°C) / 29.3°C/W
PD(MAX) = 2.218W
DDPAK-5 (31.2°C/Watt RθJA):
PD(MAX) = (125°C – 60°C)/ 31.2°C/W
PD(MAX) = 2.083W
From this table, you can see the difference in maximum
allowable power dissipation between the TO-220-5
package and the DDPAK-5 package.

MCP1825/MCP1825S
6.0 PACKAGING INFORMATION
6.1 Package Marking Information

3-Lead DDPAK (MCP1825S) Example:
XXXXXXXXX MCP1825S
XXXXXXXXX 08EEB e3
YYWWNNN 0710256
1 2 3 1 2 3
3-Lead SOT-223 (MCP1825S) Example:
XXXXXXX 1825S08
XXXYYWW EDB0710
NNN 256
3-Lead TO-220 (MCP1825S) Example:
XXXXXXXXX MCP1825S
XXXXXXXXX 12EAB e3
YYWWNNN 0710256
1 2 3 1 2 3
Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
e3 Pb-free JEDEC designator for Matte Tin (Sn)
* This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.

MCP1825/MCP1825S
Package Marking Information (Continued)
5-Lead DDPAK (MCP1825) Example:
XXXXXXXXX MCP1825
XXXXXXXXX 12EET e3
YYWWNNN 0710256
1 2 3 4 5 1 2 3 4 5
5-Lead SOT-223 (MCP1825) Example:
XXXXXXX 1825-08
XXXYYWW EDC0710
NNN 256
5-Lead TO-220 (MCP1825) Example:
XXXXXXXXX MCP1825
XXXXXXXXX e3
08EAT^^
YYWWNNN 0710256
1 2 3 4 5 1 2 3 4 5
Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
e3 Pb-free JEDEC designator for Matte Tin (Sn)
* This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.

MCP1825/MCP1825S
3-Lead Plastic (EB) [DDPAK]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
E E1
L1
D1
D
H
1 N
b
e BOTTOM VIEW
TOP VIEW
b1 CHAMFER
OPTIONAL
A C2
φ
A1 c L
Units INCHES
Dimension Limits MIN NOM MAX
Number of Pins N 3
Pitch e .100 BSC
Overall Height A .160 – .190
Standoff § A1 .000 – .010
Overall Width E .380 – .420
Exposed Pad Width E1 .245 – –
Molded Package Length D .330 – .380
Overall Length H .549 – .625
Exposed Pad Length D1 .270 – –
Lead Thickness c .014 – .029
Pad Thickness C2 .045 – .065
Lower Lead Width b .020 – .039
Upper Lead Width b1 .045 – .070
Foot Length L .068 – .110
Pad Length L1 – – .067
Foot Angle φ 0° – 8°
Notes:
1. § Significant Characteristic.
2. Dimensions D and E do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005" per side.
3. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing C04-011B

MCP1825/MCP1825S
3-Lead Plastic Small Outline Transistor (DB) [SOT-223]

D
b2
E1 E
1 2 3
e1
A A2 c
φ
b A1 L
Units MILLIMETERS
Number of Leads N 3
Lead Pitch e 2.30 BSC
Outside Lead Pitch e1 4.60 BSC
Overall Height A – – 1.80
Standoff A1 0.02 – 0.10
Molded Package Height A2 1.50 1.60 1.70
Overall Width E 6.70 7.00 7.30
Molded Package Width E1 3.30 3.50 3.70
Overall Length D 6.30 6.50 6.70
Lead Thickness c 0.23 0.30 0.35
Lead Width b 0.60 0.76 0.84
Tab Lead Width b2 2.90 3.00 3.10
Foot Length L 0.75 – –
Lead Angle φ 0° – 10°
Notes:
1. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.127 mm per side.

MCP1825/MCP1825S
/HDG3ODVWLF6PDOO2XWOLQH7UDQVLVWRU'%>627@

1RWH )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW
KWWSZZZPLFURFKLSFRPSDFNDJLQJ

MCP1825/MCP1825S
3-Lead Plastic Transistor Outline (AB) [TO-220]

E CHAMFER A
OPTIONAL
φP A1
Q
H1
D1
L1
L
b2
1 2 N
b c
e A2
e1
Units INCHES
Number of Pins N 3
Pitch e .100 BSC
Overall Pin Pitch e1 .200 BSC
Tab Thickness A1 .020 – .055
Base to Lead A2 .080 – .115
Mounting Hole Center Q .100 – .120
Overall Length D .560 – .650
Molded Package Length D1 .330 – .355
Tab Length H1 .230 – .270
Mounting Hole Diameter φP .139 – .156
Lead Length L .500 – .580
Lead Shoulder L1 – – .250
Lead Width b .015 .027 .040
Shoulder Width b2 .045 .057 .070
Notes:

MCP1825/MCP1825S
5-Lead Plastic (ET) [DDPAK]

E E1
L1
D1
1 N
b e BOTTOM VIEW
TOP VIEW
CHAMFER
OPTIONAL
A C2
φ
A1 c L
Units INCHES
Number of Pins N 5
Pitch e .067 BSC
Standoff § A1 .000 – .010
Exposed Pad Width E1 .245 – –
Molded Package Length D .330 – .380
Overall Length H .549 – .625
Exposed Pad Length D1 .270 – –
Pad Thickness C2 .045 – .065
Lead Width b .020 – .039
Foot Length L .068 – .110
Pad Length L1 – – .067
Foot Angle φ 0° – 8°
Notes:
1. § Significant Characteristic.

MCP1825/MCP1825S
/HDG3ODVWLF6PDOO2XWOLQH7UDQVLVWRU'&>627@

D
b2
E1 E
1 2 3 4 N
e
e1
A A2 c
φ
b A1 L
8QLWV 0,//,0(7(56
'LPHQVLRQ/LPLWV 0,1 120 0$;
1XPEHURI/HDGV 1
/HDG3LWFK H %6&
2XWVLGH/HDG3LWFK H %6&
2YHUDOO+HLJKW $ ± ±
6WDQGRII $
0ROGHG3DFNDJH+HLJKW $
2YHUDOO:LGWK (
0ROGHG3DFNDJH:LGWK (
2YHUDOO/HQJWK '
/HDG7KLFNQHVV F
/HDG:LGWK E
7DE/HDG:LGWK E
)RRW/HQJWK / ±
/HDG$QJOH
1RWHV
'LPHQVLRQV'DQG(GRQRWLQFOXGHPROGIODVKRUSURWUXVLRQV0ROGIODVKRUSURWUXVLRQVVKDOOQRWH[FHHGPPSHUVLGH
'LPHQVLRQLQJDQGWROHUDQFLQJSHU$60(<0
%6& %DVLF'LPHQVLRQ7KHRUHWLFDOO\H[DFWYDOXHVKRZQZLWKRXWWROHUDQFHV
0LFURFKLS 7HFKQRORJ\ 'UDZLQJ &%

MCP1825/MCP1825S
/HDG3ODVWLF6PDOO2XWOLQH7UDQVLVWRU'&>627@


MCP1825/MCP1825S
5-Lead Plastic Transistor Outline (AT) [TO-220]

E A
φP
CHAMFER A1
OPTIONAL
Q
H1
D1
1 2 3 N
b e c
e1 A2
Units INCHES
Number of Pins N 5
Pitch e .067 BSC
Overall Pin Pitch e1 .268 BSC
Overall Length D .560 – .650
Molded Package Length D1 .330 – .355
Tab Length H1 .204 – .293
Tab Thickness A1 .020 – .055
Mounting Hole Center Q .100 – .120
Mounting Hole Diameter φP .139 – .156
Lead Length L .482 – .590
Base to Bottom of Lead A2 .080 – .115
Lead Width b .015 .027 .040
Notes:

MCP1825/MCP1825S
APPENDIX A: REVISION HISTORY
Revision B (February 2008)

The following is the list of modifications
1. Updated Figure 2-4, Figure 2-5, Figure 2-16,
Figure 2-29, and Figure 2-30.
2. Updated package outline drawings and landing
pattern drawings to Section 6.0 “Packaging
Information”.
3. Updated Appendix A: “Revision History”.
Revision A (August 2007)

• Original Release of this Document.

MCP1825/MCP1825S
NOTES:

MCP1825/MCP1825S
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO. XX X X X/ XX Examples:

a) MCP1825-0802E/XX: 0.8V LDO Regulator
Device Output Feature Tolerance Temp. Package
b) MCP1825-1202E/XX: 1.2V LDO Regulator
Voltage Code
c) MCP1825-1802E/XX: 1.8V LDO Regulator
d) MCP1825-2502E/XX: 2.5V LDO Regulator
Device: MCP1825: 500 mA Low Dropout Regulator e) MCP1825-3002E/XX: 3.0V LDO Regulator
MCP1825T: 500 mA Low Dropout Regulator f) MCP1825-3302E/XX: 3.3V LDO Regulator
Tape and Reel g) MCP1825-5002E/XX: 5.0V LDO Regulator
MCP1825S: 500 mA Low Dropout Regulator
MCP1825ST: 500 mA Low Dropout Regulator h) MCP1825-ADJE/XX: ADJ LDO Regulator
Tape and Reel
a) MCP1825S-0802E/YY:0.8V LDO Regulator
b) MCP1825S-1202E/YY:1.2V LDO Regulator
Output Voltage *: 08 = 0.8V “Standard”
12 = 1.2V “Standard” c) MCP1825S-1802E/YY:1.8V LDO Regulator
18 = 1.8V “Standard” d) MCP1825S-2502E/YY:2.5V LDO Regulator
25 = 2.5V “Standard”
e) MCP1825S-2502E/YY:3.0V LDO Regulator
30 = 3.0V “Standard”
33 = 3.3V “Standard” f) MCP1825S-3302E/YY:3.3V LDO Regulator
50 = 5.0V “Standard” g) MCP1825S-5002E/YY:5.0V LDO Regulator
ADJ = Adjustable Output Voltage ** (MCP1825 Only)
*Contact factory for other output voltage options
** When ADJ is used, the “extra feature code” and XX = AT for 5LD TO-220 package
“tolerance” columns do not apply. Refer to examples. = DC for 5LD SOT-223 package
Extra Feature Code: 0 = Fixed = ET for 5LD DDPAK package
Tolerance: 2 = 2.5% (Standard) YY = AB for 3LD TO-220 package

= DB for 3LD SOT-223 package
Temperature: E = -40°C to +125°C
= EB for 3LD DDPAK package
Package Type: AB = Plastic Transistor Outline, TO-220, 3-lead

AT = Plastic Transistor Outline, TO-220, 5-lead
EB = Plastic, DDPAK, 3-lead
ET = Plastic, DDPAK, 5-lead
DB = Plastic Small Transistor Outline, SOT-223, 3-lead
DC = Plastic Small Transistor Outline, SOT-223, 5-lead
Note: ADJ (Adjustable) only available in 5-lead version.

MCP1825/MCP1825S
NOTES:

Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device Trademarks

applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, Accuron,
and may be superseded by updates. It is your responsibility to
dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,
ensure that your application meets with your specifications.
PICSTART, PRO MATE, rfPIC and SmartShunt are registered
MICROCHIP MAKES NO REPRESENTATIONS OR trademarks of Microchip Technology Incorporated in the
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
U.S.A. and other countries.
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION, FilterLab, Linear Active Thermistor, MXDEV, MXLAB,
INCLUDING BUT NOT LIMITED TO ITS CONDITION, SEEVAL, SmartSensor and The Embedded Control Solutions
QUALITY, PERFORMANCE, MERCHANTABILITY OR Company are registered trademarks of Microchip Technology
FITNESS FOR PURPOSE. Microchip disclaims all liability Incorporated in the U.S.A.
arising from this information and its use. Use of Microchip Analog-for-the-Digital Age, Application Maestro, CodeGuard,
devices in life support and/or safety applications is entirely at dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
the buyer’s risk, and the buyer agrees to defend, indemnify and ECONOMONITOR, FanSense, In-Circuit Serial
hold harmless Microchip from any and all damages, claims, Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB
suits, or expenses resulting from such use. No licenses are Certified logo, MPLIB, MPLINK, mTouch, PICkit, PICDEM,
conveyed, implicitly or otherwise, under any Microchip PICDEM.net, PICtail, PIC32 logo, PowerCal, PowerInfo,
intellectual property rights. PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total
Endurance, UNI/O, WiperLock and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2008, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.

WORLDWIDE SALES AND SERVICE
AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE
Corporate Office Asia Pacific Office India - Bangalore Austria - Wels
2355 West Chandler Blvd. Suites 3707-14, 37th Floor Tel: 91-80-4182-8400 Tel: 43-7242-2244-39
Chandler, AZ 85224-6199 Tower 6, The Gateway Fax: 91-80-4182-8422 Fax: 43-7242-2244-393
Tel: 480-792-7200 Harbour City, Kowloon India - New Delhi Denmark - Copenhagen
Fax: 480-792-7277 Hong Kong Tel: 45-4450-2828
Tel: 91-11-4160-8631
Technical Support: Tel: 852-2401-1200 Fax: 45-4485-2829
Fax: 91-11-4160-8632
http://support.microchip.com
Fax: 852-2401-3431 France - Paris
Web Address: India - Pune
Australia - Sydney Tel: 91-20-2566-1512 Tel: 33-1-69-53-63-20
www.microchip.com
Tel: 61-2-9868-6733 Fax: 91-20-2566-1513 Fax: 33-1-69-30-90-79
Atlanta Fax: 61-2-9868-6755
Duluth, GA Japan - Yokohama Germany - Munich
China - Beijing Tel: 81-45-471- 6166 Tel: 49-89-627-144-0
Tel: 678-957-9614
Tel: 86-10-8528-2100 Fax: 49-89-627-144-44
Fax: 678-957-1455 Fax: 81-45-471-6122
Fax: 86-10-8528-2104 Italy - Milan
Boston Korea - Daegu
Westborough, MA China - Chengdu Tel: 82-53-744-4301
Tel: 39-0331-742611
Tel: 86-28-8665-5511 Fax: 82-53-744-4302 Fax: 39-0331-466781
Tel: 774-760-0087
Fax: 86-28-8665-7889 Netherlands - Drunen
Fax: 774-760-0088 Korea - Seoul
Chicago China - Hong Kong SAR Tel: 82-2-554-7200 Tel: 31-416-690399
Itasca, IL Tel: 852-2401-1200 Fax: 82-2-558-5932 or Fax: 31-416-690340
Tel: 630-285-0071 Fax: 852-2401-3431 82-2-558-5934 Spain - Madrid
Fax: 630-285-0075 China - Nanjing Tel: 34-91-708-08-90
Malaysia - Kuala Lumpur
Tel: 86-25-8473-2460 Fax: 34-91-708-08-91
Dallas Tel: 60-3-6201-9857
Addison, TX Fax: 86-25-8473-2470 Fax: 60-3-6201-9859 UK - Wokingham
Tel: 972-818-7423 China - Qingdao Tel: 44-118-921-5869
Malaysia - Penang
Fax: 972-818-2924 Tel: 86-532-8502-7355 Fax: 44-118-921-5820
Tel: 60-4-227-8870
Detroit Fax: 86-532-8502-7205 Fax: 60-4-227-4068
Farmington Hills, MI China - Shanghai Philippines - Manila
Tel: 248-538-2250 Tel: 86-21-5407-5533 Tel: 63-2-634-9065
Fax: 248-538-2260 Fax: 86-21-5407-5066 Fax: 63-2-634-9069
Kokomo China - Shenyang Singapore
Kokomo, IN Tel: 86-24-2334-2829 Tel: 65-6334-8870
Tel: 765-864-8360 Fax: 86-24-2334-2393 Fax: 65-6334-8850
Fax: 765-864-8387
China - Shenzhen Taiwan - Hsin Chu
Los Angeles Tel: 86-755-8203-2660 Tel: 886-3-572-9526
Mission Viejo, CA Fax: 86-755-8203-1760 Fax: 886-3-572-6459
Tel: 949-462-9523
China - Wuhan Taiwan - Kaohsiung
Fax: 949-462-9608
Tel: 86-27-5980-5300 Tel: 886-7-536-4818
Santa Clara Fax: 86-27-5980-5118 Fax: 886-7-536-4803
Santa Clara, CA
China - Xiamen Taiwan - Taipei
Tel: 408-961-6444
Tel: 86-592-2388138 Tel: 886-2-2500-6610
Fax: 408-961-6445
Fax: 86-592-2388130 Fax: 886-2-2508-0102
Toronto
China - Xian Thailand - Bangkok
Mississauga, Ontario,
Tel: 86-29-8833-7252 Tel: 66-2-694-1351
Canada
Tel: 905-673-0699 Fax: 86-29-8833-7256 Fax: 66-2-694-1350
Fax: 905-673-6509 China - Zhuhai
Tel: 86-756-3210040
Fax: 86-756-3210049
01/02/08

Mouser Electronics
Authorized Distributor
Click to View Pricing, Inventory, Delivery & Lifecycle Information:
Microchip:
MCP1825-0802E/AT MCP1825-0802E/ET MCP1825-1202E/AT MCP1825-1202E/ET MCP1825-1802E/AT
MCP1825-1802E/ET MCP1825-2502E/AT MCP1825-2502E/ET MCP1825-3002E/AT MCP1825-3002E/ET
MCP1825-3302E/AT MCP1825-3302E/ET MCP1825-5002E/AT MCP1825-5002E/ET MCP1825-ADJE/AT MCP1825-
ADJE/ET MCP1825S-0802E/AB MCP1825S-0802E/DB MCP1825S-0802E/EB MCP1825S-1202E/AB MCP1825S-
1202E/DB MCP1825S-1202E/EB MCP1825S-1802E/AB MCP1825S-1802E/DB MCP1825S-1802E/EB MCP1825S-
2502E/AB MCP1825S-2502E/DB MCP1825S-2502E/EB MCP1825S-3002E/AB MCP1825S-3002E/DB MCP1825S-
3002E/EB MCP1825S-3302E/AB MCP1825S-3302E/DB MCP1825S-3302E/EB MCP1825S-5002E/AB MCP1825S-
5002E/DB MCP1825S-5002E/EB MCP1825ST-0802E/DB MCP1825ST-0802E/EB MCP1825ST-1202E/DB
MCP1825ST-1202E/EB MCP1825ST-1802E/DB MCP1825ST-1802E/EB MCP1825ST-2502E/DB MCP1825ST-
2502E/EB MCP1825ST-3002E/DB MCP1825ST-3002E/EB MCP1825ST-3302E/DB MCP1825ST-3302E/EB
MCP1825ST-5002E/DB MCP1825ST-5002E/EB MCP1825T-0802E/DC MCP1825T-0802E/ET MCP1825T-1202E/DC
MCP1825T-1202E/ET MCP1825T-1802E/DC MCP1825T-1802E/ET MCP1825T-2502E/DC MCP1825T-2502E/ET
MCP1825T-3002E/DC MCP1825T-3002E/ET MCP1825T-3302E/DC MCP1825T-3302E/ET MCP1825T-5002E/DC
MCP1825T-5002E/ET MCP1825T-ADJE/DC MCP1825T-ADJE/ET

MCP1825/MCP1825S: 500 Ma, Low Voltage, Low Quiescent Current LDO Regulator

Uploaded by

Copyright:

Available Formats

MCP1825/MCP1825S: 500 Ma, Low Voltage, Low Quiescent Current LDO Regulator

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

MCP1825/MCP1825S: 500 Ma, Low Voltage, Low Quiescent Current LDO Regulator

Uploaded by

Copyright:

Available Formats

MCP1825/MCP1825S

500 mA, Low Voltage, Low Quiescent Current LDO Regulator

© 2008 Microchip Technology Inc. DS22056B-page 1

Pin Fixed Adjustable Pin

1 SHDN SHDN 1 VIN

3 GND (TAB) GND (TAB) 3 VOUT

DS22056B-page 2 © 2008 Microchip Technology Inc.

MCP1825 Fixed Output Voltage

MCP1825 Adjustable Output Voltage

© 2008 Microchip Technology Inc. DS22056B-page 3

DS22056B-page 4 © 2008 Microchip Technology Inc.

© 2008 Microchip Technology Inc. DS22056B-page 5

DS22056B-page 6 © 2008 Microchip Technology Inc.

Parameters Sym Min Typ Max Units Conditions

© 2008 Microchip Technology Inc. DS22056B-page 7

Parameters Sym Min Typ Max Units Conditions

DS22056B-page 8 © 2008 Microchip Technology Inc.

Parameters Sym Min Typ Max Units Conditions

© 2008 Microchip Technology Inc. DS22056B-page 9

Parameters Sym Min Typ Max Units Conditions

DS22056B-page 10 © 2008 Microchip Technology Inc.

Line Regulation (%/V)

© 2008 Microchip Technology Inc. DS22056B-page 11

Quiescent Current (μA)

VOUT = 5.0V Adj 140

Quiescent Current (μA)

VOUT = 5.0V Adj

VOUT = 2.5V Fixed VIN = 2.3V for VR=0.8V

DS22056B-page 12 © 2008 Microchip Technology Inc.

Line Regulation (%/V)

Load Regulation (%)

VIN = 2.1V to 6.0V

© 2008 Microchip Technology Inc. DS22056B-page 13

Noise (mV/ √Hz)

DS22056B-page 14 © 2008 Microchip Technology Inc.

© 2008 Microchip Technology Inc. DS22056B-page 15

3.3 Ground (GND) 3.7 Exposed Pad (EP)

3.4 Regulated Output Voltage (VOUT)

DS22056B-page 16 © 2008 Microchip Technology Inc.

© 2008 Microchip Technology Inc. DS22056B-page 17

the output load step. For good step response

4.5 Power Good Output (PWRGD) VIN

DS22056B-page 18 © 2008 Microchip Technology Inc.

4.8 Overtemperature Protection

© 2008 Microchip Technology Inc. DS22056B-page 19

DS22056B-page 20 © 2008 Microchip Technology Inc.

TJ(RISE) = PTOTAL x RθJA

© 2008 Microchip Technology Inc. DS22056B-page 21

5.3.1.3 Maximum Package Power

DS22056B-page 22 © 2008 Microchip Technology Inc.

6.1 Package Marking Information

3-Lead SOT-223 (MCP1825S) Example:

3-Lead TO-220 (MCP1825S) Example:

Legend: XX...X Customer-specific information

© 2008 Microchip Technology Inc. DS22056B-page 23

5-Lead DDPAK (MCP1825) Example:

5-Lead SOT-223 (MCP1825) Example:

5-Lead TO-220 (MCP1825) Example:

Legend: XX...X Customer-specific information

/HDG3ODVWLF6PDOO2XWOLQH7UDQVLVWRU'%>627@

/HDG3ODVWLF6PDOO2XWOLQH7UDQVLVWRU'&>627@

/HDG3ODVWLF6PDOO2XWOLQH7UDQVLVWRU'&>627@