Supercapacitor Supported DSTATCOM For Harmonic Reduction and Power Factor Correction
Supercapacitor Supported DSTATCOM For Harmonic Reduction and Power Factor Correction
Supercapacitor Supported DSTATCOM For Harmonic Reduction and Power Factor Correction
T1 T3 T5
Supercapacitor zc
with vdc C
switching
circuit
T2 T4 T6
Compensator
Switching signals
Hysteresis current
isa
controller
isb
isc
i*sa i*sb i*sc
vs Instantaneous Symmetrical vdc(ref)
Component Theory
vl vdc
ila ilb ilc
Fig.1: Proposed Topology based DSTATCOM for distribution system
Supercapacitor:
A supercapacitor is connected to a DSTATCOM through a
bi-directional chopper. The chopper plays an important role
in charging/discharging of energy to/from the supercapacitor. S1
Stored energy in the supercapacitor is used to maintain the
voltage across dc bus capacitor during compensation of Vdc RS
different power quality problems. An equivalent circuit Icell Ip Isc
diagram of the chopper with a supercapacitor is given in RP Csc
Fig.2. Mainly, the supercapacitor involves two operation; one
S2
is charging operation and another is discharging operation as
follows;
Fig.2: Equivalent circuit of bi-directional chopper with a supercapacitor
Let us consider, S1 and S2 are two switches (IGBTs) of
the bi-directional chopper to perform the charging and
discharging operation of the supercapacitor. Charging:
In Fig.2, Current relation during charging period of the super
capacitor( C sc )is given by
I cell=I p + I sc (1)
Where, I p , I sc , I cell are the current through R p , C sc and R s
respectively.
Applying KCL,
d V sc V sc
C sc + −I sc =0(2)
dt Rp
Equivalent voltage appeared across supercapacitor circuit is ¿ v +¿
a1
given by; i = +¿
sa ¿
∆1 ( p lavg + ploss ) (10) ¿
[ ( )]
V cell =I sc Rs + I sc R p 1−exp
−t
R p C sc
(3)
¿
i = +¿
sb
v +¿
b1
[ ( )]
V sc =V rsc−( V rsc + I sc R p ) 1−exp
−t
R p C sc
(7) Wherek p and k iare the proportional gain and integral gain of
the PI controller respectively. Theactual source currents are
subtracted from the referencesource which causessource
Discharging power from the supercapacitor to load is given currents error are regulated around a predefined hysteresis
by current controller (HCC) and IGBT switching pulses (
E max T 1 , T 2 , T 3 , T 4 ,T 5∧T 6)are generated, as shown in Fig.3.
Pd = −I cell2 R s−I sc 2 R p (9) vdc
t fc vdc(ref) - Ploss
+ PI Controller
isa T2
B. Control Strategy i*sa -
HCC1
il Moving Plavg + T1
Theblock diagram for controlling of VSC is shown in Fig.3. vl Average Filter Generation of isb
T4
i*sb -
HCC2
TheDSTATCOM is controlled in such a way that the source reference + T3
Extraction of source currents
currentsare balanced, sinusoidal and in phase with the + + + isc
vs fundamental +ve (va1 ,vb1 ,vc1 ) i*sc -
HCC3 T6
respectivevoltages.In addition, average load power and losses sequence + T5
in the VSC are supplied by the source are used directly to components
calculate reference filter currents for satisfactory Fig.3: Block diagram for switching pulses generation
compensation.
III. SIMULATION RESULTS AND DISCUSSION
Therefore, the fundamental positive sequence componentsof
three-phase voltages are extracted to generate The simulation of the proposed described systemis carried
¿ ¿ ¿
referencesource currents (i sa ,i sb∧i sc ) based on the out in MATLAB Simulink to observe the performance
instantaneoussymmetrical component theory [17-18]. These under the various situations such as without DSTATCOM,
currents are givenas follows: with DSTATCOM and supercapacitor supported
DSTATCOM. These different cases are described separately
in below.
a. Without DSTATCOM 500
v s (V)
The Fig.4showsthe source voltage ( v s) and source current ( 0
-500
i s), load voltage ( vl ) and load current (i l) [from top to 100
is (A)
0
bottom] of the distribution system without DSTATCOM
-100
under balanced load. %THD of both source current and load 100
current is observed 20.66%, as shown in Fig.5.
il (A)
0
-100
50
0 -50
50
-500
50 0
is (A)
0 -50
50
v dc (V) i (A)
-50 0
cc
500
-50
v l (V)
0 800
600
-500
400
50
0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9 0.95 1
il (A)
0
Time (Sec)
-50
0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9 0.95 1
Time (Sec) Fig.6: simulation results with DSTATCOM
Fig.4:simulation results without DSTATCOM
M a g (% o f F u n d a m e n t a l)
Fundamental (50Hz) = 53.41 , THD= 2.76%
1.2
1
0.8
M a g (% o f F u n d a m e n t a l)
0.6
Fundamental (50Hz) = 51.25 , THD= 20.66% 0.4
0.2
15 0
0 200 400 600 800 1000
Frequency (Hz)
10
0
0 200 400 600 800 1000
Frequency (Hz)
10
0 400
A
( )sc
-500 voltage
100 300
current
,i
is (A)
V )
200
Vsc (
-100
100 100
0
il(A)
-100 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
50
ica (A)
0 Time (Sec)
-50
50
icb (A)
600
400 table-I. From the table-I, it is observed that power quality of
0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9 0.95 1 the distribution system is improved pretty more as compare
Time (Sec) to the traditional DSTATCOM.
Fig.9: simulation results with Super capacitor supported DSTATCOM Table-I: Performance parameters for different compensators condition
With Super
Performance Without With
capacitor based
M a g (% o f F u n d a m e n t a l)
0.4
Source current
51.25, 20.66 53.41, 2.76 53.20, 2.02
0.2
(A),%THD
0
0 200 400 600 800 1000
Load current
Frequency (Hz)
Fig.10: THD of source currentfor Super capacitor supported DSTATCOM N:B:- System parameters considered for the simulation are
summarized in table-II.
%THD of source current and load current are found 2.02%
and 20.78% respectively, as shown in Fig. 10 and Fig.11. IV. CONCLUSION
In this paper, modelling and operation of an ISCT based
From Fig.6 and Fig.9, it is observed that the dc bus voltage super capacitor supported DSTATCOM topology is proposed
regulation and harmonic reduction of source are achieved to compensate harmonics of source current and to improve
effectively in case of supercapacitor-DSTATCOM as input power factor of the system also provides reduced dc
compare to the traditional DSTATCOM. bus voltage. Moreover, dc busvoltage of theDSTATCOM is
regulated by the super capacitor at a fast rate than that of a
traditional DSTATCOM topology. This unique feature of the
proposed topology contributes significant reduction in cost,
M a g (% o f F u n d a m e n t a l)
2
Appendix
0
0 200 400 600 800 1000 Table-II:System parameter for simulation studies
Frequency (Hz)
Source voltage
(V s )=230V,50Hz
Source resistance
Grid parameters ( R s)=0.04Ω
Source inductance
Fig.11: THD of load current With Super capacitor supported DSTATCOM ( Ls )=2mH
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