CH 06

C H A P T E R
6
Basic FET Ampli®ers
6.0 PREVIEW
In the last chapter, we described the operation of the FET, in particular the
MOSFET, and analyzed and designed the dc response of circuits containing
these devices. In this chapter, we emphasize the use of FETs in linear ampli®er
applications. Although a major use of MOSFETs is in digital applications, they
are also used in linear ampli®er circuits.
There are three basic con®gurations of single-stage or single-transistor
FET ampli®ers. These are the common-source, source-follower, and com-
mon-gate con®gurations. We investigate the characteristics of each con®gura-
tion and show how these properties are used in various applications. Since
MOSFET integrated circuit ampli®ers normally use MOSFETs as load devices
instead of resistors because of their small size, we introduce the technique of
using MOSFET enhancement or depletion devices as loads. These three con-
®gurations form the building blocks for more complex ampli®ers, so gaining a
good understanding of these three ampli®er circuits is an important goal of this
chapter.
In integrated circuit systems, ampli®ers are usually connected in series or
cascade, forming a multistage con®guration, to increase the overall voltage
gain, or to provide a particular combination of voltage gain and output resis-
tance. We consider a few of the many possible multistage con®gurations, to
introduce the analysis methods required for such circuits, as well as their
properties.
JFET ampli®ers are also considered. These circuits, again, tend to be
specialized, so the JFET discussion is brief.
6.1 THE MOSFET AMPLIFIER

In Chapter 4, we discussed the reasons linear ampli®ers are necessary in analog
electronic systems. In this chapter, we continue the analysis and design of linear
ampli®ers that use ®eld-effect transistors as the amplifying device. The term
small signal means that we can linearize the ac equivalent circuit. We will de®ne
what is meant by small signal in the case of MOSFET circuits. The term linear
ampli®ers means that we can use superposition so that the dc analysis and ac
313
314 Part I Semiconductor Devices and Basic Applications
analysis of the circuits can be performed separately and the total response is the
sum of the two individual responses.
The mechanism with which MOSFET circuits amplify small time-varying
signals was introduced in the last chapter. In this section, we will expand that
discussion using the graphical technique, dc load line, and ac load line. In the
process, we will develop the various small-signal parameters of linear circuits
and the corresponding equivalent circuits.
There are four possible equivalent circuits that can be used. These are
listed in Table 4.3 of Chapter 4. The most common equivalent circuit that is
used for the FET ampli®ers is the transconductance ampli®er, in which the
input signal is a voltage and the output signal is a current. The small-signal
parameters associated with this equivalent circuit are developed in the follow-
ing section.
6.1.1 Graphical Analysis, Load Lines, and Small-Signal

Parameters
Figure 6.1 shows an NMOS common-source circuit with a time-varying vol-
tage source in series with the dc source. We assume the time-varying input
signal is sinusoidal. Figure 6.2 shows the transistor characteristics, dc load line,
and Q-point, where the dc load line and Q-point are functions of vGS , VDD , RD ,
and the transistor parameters. For the output voltage to be a linear function of
the input voltage, the transistor must be biased in the saturation region. (Note
that, although we primarily use n-channel, enhancement-mode MOSFETs in
our discussions, the same results apply to the other MOSFETs.)
VDD
iD
iD RD
vDS (sat)
vO
+ Time Q-point
vDS
+ vi Time
– IDQ VGSQ
vi + vGS
– –
+
VGSQ
–
VDSQ VDD vDS

Figure 6.31 Equivalent
circuit NMOS source-
follower, for determining Time
output resistanceFigure 6.1
NMOS common-source
circuit with time-varying Figure 6.2 Common-source transistor characteristics, dc load
signal source in series with line, and sinusoidal variation in gate-to-source voltage, drain
gate dc source current, and drain-to-source voltage
Also shown in Figure 6.2 are the sinusoidal variations in the gate-to-source
voltage, drain current, and drain-to-source voltage, as a result of the sinusoidal
source vi . The total gate-to-source voltage is the sum of VGSQ and vi . As vi
increases, the instantaneous value of vGS increases, and the bias point moves up
Chapter 6 Basic FET Amplifiers 315
the load line. A larger value of vGS means a larger drain current and a smaller
value of vDS . For a negative vI (the negative portion of the sine wave), the
instantaneous value of vGS decreases below the quiescent value, and the bias
point moves down the load line. A smaller vGS value means a smaller drain
current and increased value of vDS . Once the Q-point is established, we can
develop a mathematical model for the sinusoidal, or small-signal, variations in
gate-to-source voltage, drain-to-source voltage, and drain current.
The time-varying signal source vi in Figure 6.1 generates a time-varying
component of the gate-to-source voltage. In this case, vgs vi , where vgs is the
time-varying component of the gate-to-source voltage. For the FET to operate
as a linear ampli®er, the transistor must be biased in the saturation region, and
the instantaneous drain current and drain-to-source voltage must also be con-
®ned to the saturation region.
Transistor Parameters
The instantaneous gate-to-source voltage is
vGS VGSQ vi VGSQ vgs 6:1
where VGSQ is the dc component and vgs is the ac component. The instanta-
neous drain current is
iD Kn vGS VTN 2 6:2
Substituting Equation (6.1) into (6.2) produces
iD Kn VGSQ vgs VTN 2 Kn VGSQ VTN vgs 2 6:3a
or
iD Kn VGSQ VTN 2 2Kn VGSQ VTN vgs Kn v2gs 6:3b
The ®rst term in Equation (6.3(b)) is the dc or quiescent drain current IDQ ,
the second term is the time-varying drain current component that is linearly
related to the signal vgs , and the third term is proportional to the square of the
signal voltage. For a sinusoidal input signal, the squared term produces unde-
sirable harmonics, or nonlinear distortion, in the output voltage. To minimize
these harmonics, we require
vgs 2VGSQ VTN 6:4
which means that the third term in Equation (6.3(b)) will be much smaller than
the second term. Equation (6.4) represents the small-signal condition that must
be satis®ed for linear ampli®ers.
Neglecting the v2gs term, we can write Equation (6.3(b))
iD IDQ id 6:5
Again, small-signal implies linearity so that the total current can be separated
into a dc component and an ac component. The ac component of the drain
current is given by
id 2Kn VGSQ VTN vgs 6:6
The small-signal drain current is related to the small-signal gate-to-source
voltage by the transconductance gm . The relationship is
id
gm 2Kn VGSQ VTN 6:7
vgs
The transconductance is a transfer coef®cient relating output current to input
voltage and can be thought of as representing the gain of the transistor.
The transconductance can also be obtained from the derivative

@iD
gm 2Kn VGSQ VTN 6:8a
@vGS vGS VGSQ const:
which can be written

p
gm 2 Kn IDQ 6:8b
The drain current versus gate-to-source voltage for the transistor biased in
the saturation region is given in Equation (6.2) and is shown in Figure 6.3. The
transconductance gm is the slope of the curve. If the time-varying signal vgs is
suf®ciently small, the transconductance gm is a constant. With the Q-point in
the saturation region, the transistor operates as a current source that is linearly
controlled by vgs . If the Q-point moves into the nonsaturation region, the
transistor no longer operates as a linearly controlled current source.
iD
Time
IDQ Slope = gm
Time
VTh VGS vGS
Figure 6.3 Drain current versus gate-to-source voltage characteristics, with superimposed
sinusoidal signals
As shown in Equation (6.8(a)), the transconductance is directly propor-

tional to the conduction parameter Kn , which in turn is a function of the width-
to-length ratio. Therefore, increasing the width of the transistor increases the
transconductance, or gain, of the transistor.
Example 6.1 Objective: Calculate the transconductance of an n-channel

MOSFET.
Consider an n-channel MOSFET with parameters VTN 1 V, 12n Cox
20 mA=V2 , and W=L 40. Assume the drain current is ID 1 mA.
Solution: The conduction parameter is

1 W
Kn n Cox 2040 mA=V2 ) 0:80 mA=V2
2 L
Assuming the transistor is biased in the saturation region, the transconductance is

determined from Equation (6.8(b)),
p p
gm 2 Kn IDQ 2 0:81 1:79 mA=V
Comment: The transconductance of a bipolar transistor is gm ICQ =VT , which is

38.5 mA/V for a collector current of 1 mA. The transconductance values of MOSFETs
tend to be small compared to those of BJTs. However, the advantages of MOSFETs
include high input impedance, small size, and low power dissipation.
AC Equivalent Circuit
From Figure 6.1, we see that the output voltage is
vDS vO VDD iD RD 6:9
Using Equation (6.5), we obtain
vO VDD IDQ id RD VDD IDQ RD id RD 6:10
The output voltage is also a combination of dc and ac values. The time-
varying output signal is the time-varying drain-to-source voltage, or
vo vds id R D 6:11
Also, from Equations (6.6) and (6.7), we have
id gm vgs 6:12
In summary, the following relationships exist between the time-varying
signals for the circuit in Figure 6.1. The equations are given in terms of the
instantaneous ac values, as well as the phasors. We have
vgs vi 6:13a
or
Vgs Vi 6:13b
and
id gm vgs 6:14a
or
Id gm Vgs 6:14b
Also,
vo
vds id RD 6:15a id
or +
RD
vgs
Vds Id R D 6:15b vi +
– –
The ac equivalent circuit in Figure 6.4 is developed by setting the dc

sources in Figure 6.1 equal to zero. The small-signal relationships are given
in Equations (6.13), (6.14), and (6.15). As shown in Figure 6.1, the drain
Figure 6.4 AC equivalent
current, which is composed of ac signals superimposed on the quiescent circuit of common-source
value, ¯ows through the voltage source VDD . Since the voltage across this ampli®er with NMOS transistor
source is assumed to be constant, the sinusoidal current produces no sinusoidal

voltage component across this element. The equivalent ac impedance is there-
fore zero, or a short circuit. Consequently, in the ac equivalent circuit, the dc
voltage sources are equal to zero. We say that the node connecting RD and VDD
is at signal ground.
6.1.2 Small-Signal Equivalent Circuit

Now that we have the ac equivalent circuit for the NMOS ampli®er circuit,
(Figure 6.4), we must develop a small-signal equivalent circuit for the transis-
tor.
Initially, we assume that the signal frequency is suf®ciently low so that any
capacitance at the gate terminal can be neglected. The input to the gate thus
appears as an open circuit, or an in®nite resistance. Equation (6.14) relates the
small-signal drain current to the small-signal input voltage, and Equation (6.7)
shows that the transconductance gm is a function of the Q-point. The resulting
simpli®ed small-signal equivalent circuit for the NMOS device is shown in
Figure 6.5. (The phasor components are in parentheses.)
D
+
id (Id ) G D
G
+ +
+ vds (Vds) id (Id)
gmvgs vds (Vds)
vgs (Vgs) vgs (Vgs)
(gmVgs)
– – – –
S S
(a) (b)
Figure 6.5 (a) Common-source NMOS transistor with small-signal parameters and
(b) simpli®ed small-signal equivalent circuit for NMOS transistor
This small-signal equivalent circuit can also be expanded to take into

account the ®nite output resistance of a MOSFET biased in the saturation
region. This effect, discussed in the last chapter, is a result of the nonzero
slope in the iD versus vDS curve.
We know that
iD Kn vGS VTN 2 1 vDS 6:16
where is the channel-length modulation parameter and is a positive quantity.

The small-signal output resistance, as previously de®ned, is
1
@iD
ro 6:17
@vDS
vGS VGSQ const:
or
ro Kn VGSQ VTN 2 1

IDQ 1
6:18
This small-signal output resistance is also a function of the Q-point parameters.

The expanded small-signal equivalent cicuit of the n-channel MOSFET is

shown in Figure 6.6 in phasor notation. Note that this equivalent circuit is a
transconductance ampli®er (see Table 4.3) in that the input signal is a voltage
and the output signal is a current. This equivalent circuit can now be inserted
into the ampli®er ac equivalent circuit in Figure 6.4 to produce the circuit in
Figure 6.7. We may note that the small-signal equivalent circuit for the
MOSFET circuit is very similar to that of the BJT circuits considered in
Chapter 4.
G D
+ +
Id
Vo
Vgs gmVgs ro Vds + +
Vi + Vgs gmVgs ro RD Vds

– – –
S – –
Figure 6.6 Expanded small-
signal equivalent circuit, Figure 6.7 Small-signal equivalent circuit of
including output resistance, for common-source circuit with NMOS transistor
NMOS transistor model
Example 6.2 Objective: Determine the small-signal voltage gain of a MOSFET

circuit.
For the circuit in Figure 6.1, assume parameters are: VGSQ 2:12 V, VDD 5 V,
and RD 2:5 k
. Assume transistor parameters are: VTN 1 V, Kn 0:80 mA=V2 , and
0:02 V 1 . Assume the transistor is biased in the saturation region.
Solution: The quiescent values are
IDQ Kn VGSQ VTN 2 0:82:12 12 1:0 mA
and
VDSQ VDD IDQ RD 5 12:5 2:5 V
Therefore,
VDSQ 2:5 V > VDS sat VGS VTN 1:82 1 0:82 V
which means that the transistor is biased in the saturation region, as initially assumed,
and as required for a linear ampli®er. The transconductance is
gm 2Kn VGSQ VTN 20:82:12 1 1:79 mA=V
and the output resistance is

1 1
ro IDQ 0:021 50 k
From Figure 6.7, the output voltage is

Vo gm Vgs ro kRD
Since Vgs Vi , the small-signal voltage gain is

Vo
Av gm ro kRd 1:7950k2:5 4:26
Vi
Comment: Because of the relatively low value of transconductance, MOSFET circuits

tend to have a lower small-signal voltage gain than comparable bipolar circuits. Also,
the small-signal voltage gain contains a minus sign, which means that the sinusoidal
output voltage is 180 degrees out of phase with respect to the input sinusoidal signal.
Problem Solving Method: MOSFET AC Analysis

Since we are dealing with linear ampli®ers, superposition applies, which means
that we can perform the dc and ac analyses separately. The analysis of the
MOSFET ampli®er proceeds as follows:
1. Analyze the circuit with only the dc sources present. This solution is the dc
or quiescent solution. The transistor must be biased in the saturation
region in order to produce a linear ampli®er.
2. Replace each element in the circuit with its small-signal model, which
means replacing the transistor by its small-signal equivalent cicuit.
3. Analyze the small-signal equivalent circuit, setting the dc source compo-
nents equal to zero, to produce the response of the circuit to the time-
varying input signals only.
Test Your Understanding

6.1 For an n-channel MOSFET biased in the saturation region, the parameters are
Kn 0:5 mA=V2 , VTN 0:8 V, and 0:01 V 1 , and IDQ 0:75 mA. Determine gm
and ro . (Ans. gm 1:22 mA=V, ro 1:33 k
)
6.2 The parameters of an n-channel MOSFET are: VTN 1 V, 12 n Cox 18 mA=V2 ,
and 0:015 V 1 . The transistor is to be biased in the saturation region with
IDQ 2 mA. Design the width-to-length ratio such that the transconductance is
gm 3:4 mA/V. Calculate ro for this condition. (Ans. W=L 80:6, ro 33:3 k
)
6.3 For the circuit shown in Figure 6.1, VDD 10 V and RD 10 k
. The transistor
parameters are: VTN 2 V, Kn 0:5 mA=V2 , and 0. (a) Determine VGSQ such that
IDQ 0:4 mA. Calculate VDSQ . (b) Calculate gm and ro , and determine the small-signal
voltage gain. (c) If vi 0:4 sin !t, ®nd vds . Does the transistor remain in the saturation
region? (Ans. (a) VGSQ 2:89 V, VDSQ 6 V; (b) gm 0:89 mA/V, ro 1, Av 8:9;
(c) vds 3:56 sin !t, yes)
The previous discussion was for an n-channel MOSFET ampli®er. The

same basic analysis and equivalent circuit also applies to the p-channel tran-
sistor. Figure 6.8(a) shows a circuit containing a p-channel MOSFET. Note
that the power supply voltage VDD is connected to the source. (The subscript
DD can be used to indicate that the supply is connected to the drain terminal.
Here, however, VDD is simply the usual notation for the power supply voltage
in MOSFET circuits.) Also note the change in current directions and voltage
polarities compared to the circuit containing the NMOS transistor. Figure
6.8(b) shows the ac equivalent circuit, with the dc voltage sources replaced
VDD
vSG +
+ vsg +
– +
vSD –
vsd
–
+ vO –
vi – vo
vi +
+ –
iD RD id RD
VGG
–
(a) (b)
Figure 6.8 (a) Common-source circuit with PMOS transistor and (b) corresponding ac
equivalent circuit
by ac short circuits, and all currents and voltages shown are the time-varying
components.
In the circuit of Figure 6.8(b), the transistor can be replaced by the equiva-
lent circuit in Figure 6.9. The equivalent circuit of the p-channel MOSFET is
the same as that of the n-channel device, except that all current directions and
voltage polarities are reversed.
The ®nal small-signal equivalent circuit of the p-channel MOSFET ampli-
®er is shown in Figure 6.10. The output voltage is
Vo gm Vsg Ro kRD 6:19
Id
G D G D
Vo
– – –
Vsg gmVsg ro Vsd Vi + Vsg gmVsg ro RD

–
+ + +
S S
Figure 6.9 Small-signal Figure 6.10 Small-signal equivalent circuit

equivalent circuit of PMOS of common-source ampli®er with PMOS
transistor transistor model
The control voltage Vsg , given in terms of the input signal voltage, is
Vsg Vi 6:20
and the small-signal voltage gain is

Vo
Av gm ro kRD 6:21
Vi
This expression for the small-signal voltage gain of the p-channel
MOSFET ampli®er is exactly the same as that for the n-channel MOSFET
ampli®er. The negative sign indicates that a 180-degree phase reversal exists
between the ouput and input signals, for both the PMOS and the NMOS
circuit.
We may again note that if the polarity of the small-signal gate-to-source

voltage is reversed, then the small-signal drain current direction is reversed and
the small-signal equivalent cicuit of the PMOS device is exactly identical to that
of the NMOS device. However, the author prefers to use the small-signal
equivalent circuit in Figure 6.9 to be consistent with the voltage polarities
and current directions of the PMOS transistor.
6.1.3 Modeling the Body Effect

As mentioned in Section 5.1.7, Chapter 5, the body effect occurs in a MOSFET
in which the substrate, or body, is not connected to the source. For an NMOS
device, the body is connected to the most negative potential in the circuit and
will be at signal ground. Figure 6.11(a) shows the four-terminal MOSFET with
dc voltages and Figure 6.11(b) shows the device with ac voltages. Keep in mind
that vSB must be greater or equal to zero. The simpli®ed current-voltage
relation is
iD Kn vGS VTN 2 6:22
and the threshold voltage is given by

hq q i
VTN VTNO 2f vSB 2f 6:23
Figure 6.11 The four-terminal NMOS device with (a) dc voltages and (b) ac voltages
If an ac component exists in the source-to-body voltage, vSB , there will be

an ac component induced in the threshold voltage, which causes an ac compo-
nent in the drain current. Thus, a back-gate transconductance can be de®ned as

@iD @iD @iD @VTN
gmb 6:24
@vBS Q-pt @vSB Q-pt @VTN @vSB Q-pt
Using Equation (6.22), we ®nd

@iD
2Kn vGS VTN gm 6:25a
@VTN
and using Equation (6.23), we ®nd
@VTN
p 6:25b
@vSB 2 2f vSB
The back gate transconductance is then

gmb gm gm 6:26
Including the body effect, the small-signal equivalent circuit of the MOSFET is
shown in Figure 6.12. We note the direction of the current and the polarity of
the small-signal source-to-body voltage. If vbs > 0, then vSB decreases, VTN
decreases, and iD increases. The current direction and voltage polarity are
thus consistent.
Figure 6.12 Small-signal equivalent circuit of NMOS device including body effect
For f 0:35 V and 0:35 V1=2 , the value of from Equation (6.25(b))
is 0:23. Therefore, will be in the range 0 0:23. The value of vbs will
depend on the particular circuit.
In general, we will neglect gmb in our hand analyses and designs, but will
investigate the body effect in PSpice analyses.

6.4 The parameters for the circuit in Figure 6.8 are VDD 12 V and RD 6 k
. The
transistor parameters are: VTP 1 V, Kp 2 mA=V2 , and 0. (a) Determine VSG
such that VSDQ 7 V. (b) Determine gm and ro , and calculate the small-signal voltage
gain. (Ans. (a) VSG 1:65 V; (b) gm 2:6 mA/V, ro 1, Av 15:6)
6.5 Show that, for an NMOS transistor biased in the saturation region, with a drain
current of IDQ , the transconductance can be expressed as given in Equation (6.8(b)), that
is
p
gm 2 Kn IDQ
6.6 A transistor has the same parameters as those given in Exercise 6.1. In addition,
the body effect coef®cient is 0:40 V1=2 and f 0:35 V. Determine the value of
and the back gate transconductance gmb for (a) vSB 1 V and (b) vSB 3 V.
6.2 BASIC TRANSISTOR AMPLIFIER CONFIGURATIONS

As we have seen, the MOSFET is a three-terminal device. Three basic single-
transistor ampli®er con®gurations can be formed, depending on which of the
three transistor terminals is used as signal ground. These three basic con®g-
urations are appropriately called common source, common drain (source fol-
lower), and common gate. These three circuit con®gurations correspond to
the common-emitter, emitter-follower, and common-base con®gurations
using BJTs. The similarities and differences between the FET and BJT circuits
will be discussed.
The input and output resistance characteristics of ampli®ers are important
in determining loading effects. These parameters, as well as voltage gain, for
the three basic MOSFET circuit con®gurations will be determined in the fol-
lowing sections. The characteristics of the three types of ampli®ers will then
allow us to understand under what condition each ampli®er is most useful.
Initially, we will consider MOSFET ampli®er circuits that emphasize dis-
crete designs, in that resistor biasing will be used. The purpose is to become
familiar with basic MOSFET ampli®er designs and their characteristics, using
biasing techniques similar to those used in BJT ampli®ers in previous chapters.
In Section 6.7, we will begin to consider integrated circuit MOSFET designs
that involve all-transistor circuits and current source biasing. These initial
designs provide an introduction to more advanced MOS ampli®er designs
that will be considered in Part II of the text.
6.3 THE COMMON-SOURCE AMPLIFIER

In this section, we consider the ®rst of the three basic circuitsÐthe common-
source ampli®er. We will analyze several basic common-source circuits, and
will determine small-signal voltage gain and input and output impedances.
6.3.1 A Basic Common-Source Configuration

For the circuit shown in Figure 6.13, assume that the transistor is biased in the
saturation region by resistors R1 and R2 , and that the signal frequency is
suf®ciently large for the coupling capacitor to act essentially as a short circuit.
The signal source is represented by a Thevenin equivalent circuit, in which the
signal voltage source vI is in series with an equivalent source resistance RSi . As
we will see, RSi should be much less than the ampli®er input resistance,
Ri R1 kR2 , in order to minimize loading effects.
Figure 6.14 shows the resulting small-signal equivalent circuit. The small-
signal variables, such as the input signal voltage Vi , are given in phasor form.
VDD
RD
R1
RSi CC1 vO
vi +
– R2
Figure 6.13 Common-source circuit with voltage divider biasing and coupling capacitor
Ri Ro
Rsi G D
Vo
+ +
Id
Vi + R1 R2 Vgs gmVgs ro RD Vds
–
– –
S
Figure 6.14 Small-signal equivalent circuit, assuming coupling capacitor acts as a short
circuit
Since the source is at ground potential, there is no body effect. The output
voltage is
Vo gm Vgs ro kRD 6:27
The input gate-to-source voltage is

Ri
Vgs Vi 6:28
Ri RSi
so the small-signal voltage gain is

V Ri
Av o gm ro kRD 6:29
Vi Ri RSi
We can also relate the ac drain current to the ac drain-to-source voltage, as

Vds Id RD .
Figure 6.15 shows the dc load line, the transistion point, and the Q-point,
which is in the saturation region. As previously stated, in order to provide the
maximum symmetrical output voltage swing and keep the transistor biased in
the saturation region, the Q-point must be near the middle of the saturation
region. At the same time, the input signal must be small enough for the ampli-
®er to remain linear.
iD
VDD
ID (max) =
RD
VDS (sat) = VGS – VTN
Transition point
Q-point
1
IDQ dc load line, slope = –
RD
VDSQ VDD vDS
Figure 6.15 DC load line and transition point separating saturation and nonsaturation
regions
The input and output resistances of the ampli®er can be determined from
Figure 6.14. The input resistance to the ampli®er is Ris R1 kR2 . Since the low-
frequency input resistance looking into the gate of the MOSFET is essentially
in®nite, the input resistance is only a function of the bias resistors. The output
resistance looking back into the output terminals is found by setting the inde-
pendent input source Vi equal to zero, which means that Vgs 0. The output
resistance is therefore Ro RD kro :
Example 6.3 Objective: Determine the small-signal voltage gain and input and
output resistances of a common-source ampli®er.
For the circuit shown in Figure 6.13, the parameters are: VDD 10 V,
R1 70:9 k
, R2 29:1 k
, and RD 5 k
. The transistor parameters are:
VTN 1:5 V, Kn 0:5 mA=V2 , and 0:01 V 1 . Assume RSi 4 k
.
Solution: DC Calculations: The dc or quiescent gate-to-source voltage is

R2 29:1
VGSQ VDD 10 2:91 V
R1 R2 70:9 29:1
The quiescent drain current is
IDQ Kn VGSQ VTN 2 0:52:91 1:52 1 mA
and the quiescent drain-to-source voltage is
VDSQ VDD IDQ RD 10 15 5 V
Since VDSQ > VGSQ VTN , the transistor is biased in the saturation region.
Small-signal Voltage Gain: The small-signal transconductance gm is then
gm 2Kn VGSQ VTN 20:52:91 1:5 1:41 mA=V
and the small-signal output resistance ro is
1 1
ro IDQ 0:011 100 k
The ampli®er input resistance is

Ri R1 kR2 70:9k29:1 20:6 k
From Figure 6.14 and Equation (6.29), the small-signal voltage gain is

Ri 20:6
Av gm ro kRD 1:41100k5
Ri RSi 20:6 4
or
Av 5:62
Input and Output Resistances: As already calculated, the ampli®er input resistance is
Ri R1 kR2 70:9k29:1 20:6 k
and the ampli®er output resistance is

Ro RD kro 5k100 4:76 k
Comment: The resulting Q-point is in the center of the load line but not in the center
of the saturation region. Therefore, this circuit does not achieve the maximum symme-
trical output voltage swing in this case.
Discussion: The small-signal input gate-to-source voltage is

Ri 20:6
Vgs Vi Vi 0:837 Vi
Ri RSi 20:6 4
Since RSi is not zero, the ampli®er input signal Vgs is approximately 84 percent of the
signal voltage. This is again called a loading effect. Even though the input resistance to
the gate of the transistor is essentially in®nite, the bias resistors greatly in¯uence the
ampli®er input resistance and loading effect.

6.7 Consider the circuit in Figure 6.1 with circuit parameters VDD 5 V, RD 5 k
,
VGSQ 2 V, and with transistor paramaeters Kn 0:25 mA=V2 , VTN 0:8 V, and
0. (a) Calculate the quiescent values IDQ and VDSQ . (b) Calculate the transconduc-
tance gm . (c) Determine the small-signal voltage gain Av vo =vi . (Ans. (a)
IDQ 0:36 mA, VDSQ 3:2 V; (b) gm 0:6 mA=V, ro 1; (c) Av 3:0)
6.8 For the circuit in Figure 6.1, the circuit and transistor parameters are given in
Exercise 6.2. If vi 0:1 sin !t V, determine iD and vDS . (Ans. iD 0:36 0:06 sin !t mA,
vDS 3:2 0:3 sin !t V)
Design Example 6.4 Objective: Design the bias of a MOSFET such that the
Q-point is in the middle of the saturation region.
Consider the circuit in Figure 6.16 with transistor parameters VTN 1 V,
Kn 1 mA=V2 , and 0:015 V 1 . Let Ri R1 kR2 100 k
. Design the circuit such
that IDQ 2 mA and the Q-point is in the middle of the saturation region.
VDD = 12 V
RD ID = 2 mA
R1
vO
CC
vi +
– R2
Figure 6.16 Common-source NMOS transistor circuit
Solution: The load line and the desired Q-point are given in Figure 6.17. If the Q-point
is to be in the middle of the saturation region, the current at the transition point must be
4 mA.
iD 1
Load line, slope = –
RD
VDS (sat) = VGS – VTN
4 mA
Q-point
2 mA VGSQ = 2.41 V
VDS t (sat) VDSQ = 7 V VDD = 12 V vDS
Figure 6.17 DC load line and transition point for NMOS circuit shown in Figure 6.16
We can now calculate VDS (sat) at the transition point. The subscript t indicates
transition point values. To determine VGSt , we use
IDt 4 Kn VGSt VTN 2 1VGSt 12
which yields
VGSt 3 V
Therefore
VDSt VGSt VTN 3 1 2V
If the Q-point is in the middle of the saturation region, then VDSQ 7 V, which
would yield a 10 V peak-to-peak symmetrical output voltage. From Figure 6.16, we can
write
VDSQ VDD IDQ RD
or
VDD VDSQ 12 7
RD 2:5 k
IDQ 2
We can determine the required quiescent gate-to-source voltage from the current
equation, as follows:
IDQ 2 Kn VGSQ VTN 2 1VGSQ 12
or
VGSQ 2:41 V
Then

R2 1 R1 R2
VGSQ 2:41 VDD VDD
R1 R2 R1 R1 R2
R 10012
i VDD
R1 R1
which yields
R1 498 k
and R2 125 k
We can then determine the small-signal equivalent circuit parameters from the Q-
point values. The transconductance is gm 2:82 mA/V, the transistor output resistance
is ro 33:3 k
, and the small-signal voltage gain, assuming an ideal signal source, is
Vo
Av gm ro kRD 2:8233:3k2:5 6:56
Vi
Comment: Establishing the Q-point in the middle of the saturation region allows the
maximum symmetrical swing in the output voltage, while keeping the transistor biased
in the saturation region.
Design Pointer: If the circuit were to contain by pass or load capacitors, then an ac
load line would be superimposed on the ®gure at the Q-point. Establishing the Q-point
in the middle of the saturation region, then, may not be optimal in terms of obtaining
the maximum symmetrical swing.
6.3.2 Common-Source Amplifier with Source Resistor

A source resistor RS tends to stabilize the Q-point against variations in tran-
sistor parameters (Figure 6.18). If, for example, the value of the conduction
parameter varies from one transistor to another, the Q-point will not vary as
much if a source resistor is included in the circuit. However, as shown in the
following example, a source resistor also reduces the signal gain. This same
effect was observed in BJT circuits when an emitter resistor was included.
The circuit in Figure 6.18 is an example of a situation in which the body
effect should be taken into account. The substrate (not shown) would normally
be connected to the 5 V supply, so that the body and substrate terminals are
not at the same potential. However, in the following example, we will neglect
this effect.
+5 V
RD = 7 kΩ
R1 = 165 kΩ
vO
CC
vi +
– R2 = 35 kΩ
RS = 0.5 kΩ
–5 V
Figure 6.18 Common-source circuit with source resistor and positive and negative supply
voltages
Example 6.5 Objective: Determine the small-signal voltage gain of a common-

source circuit containing a source resistor.
Consider the circuit in Figure 6.18. The transistor parameters are VTN 0:8 V,
Kn 1 mA=V2 , and 0:
Solution: From the dc analysis of the circuit, we ®nd that VGSQ 1:50 V,
IDQ 0:50 mA, and VDSQ 6:25 V. The small-signal transconductance is
gm 2Kn VGS VTN 211:50 0:8 1:4 mA=V
and the small-signal resistance is

1
ro IDQ 1
Figure 6.19 shows the resulting small-signal equivalent circuit.
Vo
+
Vi + R1 R2 Vgs gmVgs RD

–
–
RS
Figure 6.19 Small-signal equivalent circuit of NMOS common-source ampli®er with source
resistor
The output voltage is
Vo gm Vgs RD
Writing a KVL equation from the input around the gate±source loop, we ®nd
Vi Vgs gm Vgs RS Vgs 1 gm RS
or
Vi
Vgs
1 gm RS
The small-signal voltage gain is

Vo gm RD
Av
Vi 1 gm RS
We may note that if gm were large, then the small-signal voltage gain would be approxi-
mately
Av RD
RS
Substituting the appropriate parameters into the actual voltage gain expression, we ®nd
1:47
Av 5:76
1 1:40:5
Comment: A source resistor reduces the small-signal voltage gain. However, as dis-
cussed in the last chapter, the Q-point is more stabilized against variations in the
transistor parameters. We may note that the approximate voltage gain gives
Av RD =RS 14. Since the transconductance of MOSFETs is generally low, the
approximate gain expression is a poor one at best.
Discussion: We mentioned that including a source resistor tends to stabilize the cir-
cuit characteristics against any changes in transistor parameters. If, for example, the
conduction parameter Kn varies by 20 per cent, we ®nd the following results.
Kn (mA/V2 ) gm (mA/V) Av
0.8 1.17 5:17
1.0 1.40 5:76
1.2 1.62 6:27
The change in Kn produces a fairly large change in gm . The resulting change in the
voltage gain is approximately 9:5 per cent. This change is larger than might be
expected because the initial value of gM is smaller than that of the bipolar circuit.

6.9 For the circuit shown in Figure 6.20, the transistor parameters are Kp 1 mA/
V2 , VTP 1 V, and 0. The source-to-drain voltage is vSD 3 0:46 sin !t V, and
the quiescent drain current is IDQ 0:5 mA. Determine RD , VGG , vi , and the small-signal
voltage gain. (Ans. RD 4 k
, VGG 3:29 V, Av 5:64, vi 0:0816 sin !t V)
6.10 The common-source ampli®er in Figure 6.21 has transistor parameters
Kp 2 mA=V2 , VTP 2 V, and 0:01 V 1 . (a) Determine IDQ and VSDQ . (b)
Calculate the small-signal voltage gain. (Ans. (a) IDQ 4:56 mA, VSDQ 7:97 V; (b)
Av 6:04)
+9 V
RS = 1.2 kΩ
+5 V
CC1
CS
vi + vO vO
– + vi
– RG = 100 kΩ
+
VGG RD RD = 1 kΩ
–
–9 V
Figure 6.20 Figure for
Exercise 6.9 Figure 6.21 Figure for Exercise 6.10
6.3.3 Common-Source Circuit with Source Bypass Capacitor

A source bypass capacitor added to the common-source circuit with a source
resistor will minimize the loss in the small-signal voltage gain, while maintain-
ing the Q-point stability. The Q-point stability can be further increased by
replacing the source resistor with a constant-current source. The resulting

circuit is shown in Figure 6.22, assuming an ideal signal source. If the signal
frequency is suf®ciently large so that the bypass capacitor acts essentially as an
ac short-circuit, the source will be held at signal ground.
+5 V
RD = 7 kΩ
vO
vi +
– RG = 200 kΩ
CS
IQ = 0.5 mA
–5 V
Figure 6.22 NMOS common-source circuit with source bypass capacitor
Example 6.6 Objective: Determine the small-signal voltage gain of a circuit

biased with a constant-current source and incorporating a source bypass capacitor.
For the circuit shown in Figure 6.22, the transistor parameters are: VTN 0:8 V,
Kn 1 mA=V2 , and 0.
Solution: Since the dc gate current is zero, the dc voltage at the source terminal is
VS VGSQ , and the gate-to-source voltage is determined from
IDQ IQ Kn VGSQ VTN 2
or
0:5 1VGSQ 0:82
which yields
VGSQ VS 1:51 V
The quiescent drain-to-source voltage is
VDSQ VDD IDQ RD VS 5 0:57 1:51 3:01 V
The transistor is therefore biased in the saturation region.
The small-signal equivalent circuit is shown in Figure 6.23. The output voltage is
Vo
+
Vi + RG Vgs gmVgs RD = 7 kΩ
–
Figure 6.23 Small-signal equivalent circuit, assuming the source bypass capacitor acts as
a short circuit
Vo gm Vgs RD
Vo
Av gm RD 1:47 9:8
Vi
Comment: Comparing the small-signal voltage gain of 9.8 in this example to the 5.76
calculated in Example 6.5, we see that the magnitude of the gain increases when a source
bypass capacitor is included.

*D6.11 The common-source ampli®er in Figure 6.24 has transistor parameters
VTN 1:5 V, 12 n Cox 20 mA=V2 , and 0. Design the circuit such that
IDQ 0:5 mA and the small-signal voltage gain is Av 4:0. (Ans. For example: For
VGS 2:5 V, then W=L 25, RD 4:0 k
)
6.12 Consider the common-source ampli®er in Figure 6.25 with transistor para-
meters VTN 1:8 V, Kn 0:15 mA=V2 , and 0. (a) Calculate IDQ and VDSQ . (b)
Determine the small-signal voltage gain. (c) Discuss the purpose of RD and its effect
on the small-signal operation of the ampli®er. (Ans. (a) IDQ 1:05 mA, VDSQ 4:45 V;
(b) Av 2:65)
+5 V
VDD = 15 V
RD
vO RD = 10 kΩ
RG = 5 MΩ
vo
CC1 CC2
vi +
– RG = 50 kΩ RL = 5 kΩ
CS
IQ vi +
–
–5 V
Figure 6.24 Figure for Exercise 6.11 Figure 6.25 Figure for Exercise 6.12
*6.13 For the circuit in Figure 6.26, the n-channel depletion-mode transistor
parameters are: Kn 0:8 mA=V2 , VTN 2 V, and 0. (a) Calculate IDQ .
(b) Find RD such that VDSQ 6 V. (c) Determine the small-signal voltage gain. (Ans.
(a) IDQ 0:338 mA; (b) RD 7:83 k
; (c) Av 1:58)
6.14 The parameters of the transistor shown in Figure 6.27 are: VTP 0:8 V,
Kp 0:5 mA=V2 , and 0:02 V 1 . (a) Determine RS and RD such that
IDQ 0:8 mA and VSDQ 3 V. (b) Find the small-signal voltage gain. (Ans. (a)
RS 5:67 k
, RD 3:08 k
; (b) Av 3:73)
+5 V
VDD = 10 V
RS
RD
CC
vO CS
CC
vO
vi +
– RG = 1 MΩ
vi + RD
– RG = 200 kΩ
RS = 4 kΩ
–5 V
Figure 6.26 Figure for Exercise 6.13 Figure 6.27 Figure for Exercise 6.14
6.4 THE SOURCE-FOLLOWER AMPLIFIER

The second type of MOSFET ampli®er to be considered is the common-drain
circuit. An example of this circuit con®guration is shown in Figure 6.28. As
seen in the ®gure, the output signal is taken off the source with respect to
ground and the drain is connected directly to VDD . Since VDD becomes signal
ground in the ac equivalent circuit, we have the name common drain. The more
common name is source follower. The reason for this name will become appar-
ent as we proceed through the analysis.
VDD
R1
RSi CC
vO
vi +
– R2
RS
Figure 6.28 NMOS source-follower or common-drain ampli®er
6.4.1 Small-Signal Voltage Gain

The dc analysis of the circuit is exactly the same as we have already seen, so we
will concentrate on the small-signal analysis. The small-signal equivalent cir-
cuit, assuming the coupling capacitor acts as a short circuit, is shown in Figure
6.29(a). The drain is at signal ground, and the small-signal resistance ro of the
transistor is in parallel with the dependent current source. Figure 6.29(b) is the
same equivalent circuit, but with all signal grounds at a common point. We are
again neglecting the body effect. The output voltage is
RSi Vin G D
Ri
+
RS i Vin
Vgs gmVgs ro + Vgs – Vo
+ – Vo + R1R2 gmVgs ro
Vi – R1R2 Vi – RD
S
RS
(a) (b)
Figure 6.29 (a) Small-signal equivalent circuit of NMOS source-follower and (b) small-
signal equivalent circuit of NMOS source-follower with all signal grounds at a common point
Vo gm Vgs Rs kro 6:30

Writing a KCL equation from input to output results in the following:
Vin Vgs Vo Vgs gm Vgs Rs kro 6:31a
Therefore, the gate-to-source voltage is
2 3
1
Vin 6 gm 7
vgs 6
4
7 Vin
5 6:31b
1 gm Rs kro 1
Rs kro
gm
Equation (6.31(b)) is written in the form of a voltage-divider equation, in
which the gate-to-source of the NMOS device looks like a resistance with a
value of 1=gm . More accurately, the effective resistance looking into the source
terminal (ignoring ro ) is 1=gm . The voltage Vin is related to the source input
voltage Vi by

Ri
Vin Vi 6:32
Ri RSi
where Ri R1 kR2 is the input resistance to the ampli®er.
Substituting Equations (6.31(b)) and (6.32) into (6.30), we have the small-
signal voltage gain:

V gm RS kro Ri
Av o 6:33a
Vi 1 gm RS kro Ri RSi
or

Rs kro Ri
Av 6:33b
1 Ri RSi
Rs kro
gm
which again is written in the form of a voltage-divider equation. An inspection
of Equation 6.33(b) shows that the magnitude of the voltage gain is always less
than unity. This result is consistent with the results of the BJT emitter-follower
circuit.
Example 6.7 Objective: Calculate the small-signal voltage gain of the source-fol-
lower circuit in Figure 6.28.
Assume the circuit parameters are VDD 12 V, R1 162 k
, R2 463 k
, and
RS 0:75 k
, and the transistor parameters are VTN 1; 5 V, Kn 4 mA=V2 , and
0:01 V 1 . Also assume RSi 4 k
.
Solution: The dc analysis results are IDQ 7:97 mA and VGSQ 2:91 V. The small-
signal transconductance is therefore
gm 2Kn VGSQ VTN 242:91 1:5 11:3 mA=V
and the small-signal transistor resistance is

1 1
ro IDQ 0:017:97 12:5 k
The ampli®er input resistance is

Ri R1 kR2 162k463 120 k
The small-signal voltage gain then becomes

gm RS kro Ri 11:30:75k12:5 120
Av 0:860
1 gm RS kro Ri RSi 1 11:30:75k12:5 120 4
Comment: The magnitude of the small-signal voltage gain is less than 1. An examina-
tion of Equation (6.33(b)) shows that this is always true. Also, the voltage gain is
positive, which means that the output signal voltage is in phase with the input signal
voltage. Since the output signal is essentially equal to the input signal, the circuit is
called a source follower.
Discussion: The expression for the voltage gain of the source follower is essentially
identical to that of the bipolar emitter follower. Since the transconductance of the BJT
is, in ingeneral, larger than that of the MOSFET, the voltage gain of the emitter
follower will be closer to unity than that of the MOSFET source follower.
Although the voltage gain is slightly less than 1, the source-follower is an

extremely useful circuit because the output resistance is less than that of a
common-sosurce circuit. A small output resistance is desirable when the circuit
is to act as an ideal voltage source and drive a load circuit without suffering
any loading effects.

6.15 For an NMOS source-follower circuit, the parameters are gm 4 mA/V and
ro 50 k
. (a) Find the no load RS 1 small-signal voltage gain and the output
resistance. (b) Determine the small-signal voltage gain when a 4 k
load is connected to
the output. (Ans. (a) Av 0:995, Ro 0:25 k
; (b) Av 0:937)
D6.16 The source-follower circuit in Figure 6.28 has transistor parameters
VTN 0:8 V, Kn 1 mA=V2 , and 0:015 V 1 . Let VDD 10 V, RSi 200
, and
R1 R2 400 k
. Design the circuit such that IDQ 1:5 mA and VDSQ 5 V.
Determine the small-signal voltage gain and the output resistance. (Ans.
RS 3:33 k
, R1 119 k
, R2 281; k
, Av 0:884, and Ro 0:36 k
)
Design Example 6.8 Objective: Design a speci®c source follower with a

p-channel enhancement-mode MOSFET.
For the circuit in Figure 6.30, the transistor parameters are VTP 2 V,
kp0 40 mA=V2 , and 0. The circuit parameters are VDD 20 V and RSi 4 k
.
The circuit is to be designed such that VSDQ 10 V, IDQ 2:5 mA, and
Ri 50 k
, and the transistor width-to-length ratio is to be designed such that the
small-signal voltage gain is Av 0:90:
VDD
RS
Ri R1
vO
RSi CC1
vi +
– R2
Figure 6.30 PMOS source follower
Solution: From the dc analysis, we have

VDD VSDQ IDQ RS
or
20 10 2:5RS
The required source resistance value is therefore
RS 4 k
The small-signal voltage gain of this circuit is the same as that of a source-follower
using an NMOS device. From Equation (6.33(a)), we have

Vo gm RS Ri
Av
Vi 1 gm RS Ri RSi
or

gm 4 50
0:90
1 gm 4 50 4
which yields
gm 4
0:972
1 gm 4
Therefore, the required small-signal transconductance is
gm 8:68 mA=V
Since the transconductance can be written as
p
gm 2 Kp IDQ
we have
q
3
8:68 10 2 Kp 2:5 10 3
which yields
3
K p 7:53 10 A=V2
The conduction parameter, which is a function of the width-to-length ratio, is
!
3 W 1 0 W 40 10 6
Kp 7:53 10 k
L 2 p L 2
which means that the width-to-length ratio is

W
377
L
This is a relatively large p-channel transistor.
Completing the dc analysis, we have
IDQ Kp VSGQ VTP 2
or
2:5 7:53VSGQ 22
which yields a quiescent source-to-gate voltage of

VSGQ 2:58 V
The quiescent source-to-gate voltage can also be written as

R2
VSGQ VDD IDQ RS VDD
R1 R2
Since

R2 1 R1 R2 1
R
R1 R2 R1 R1 R2 R1 i
we have

1
2:58 20 2:54 5020
R1
the bias resistor R1 is then found to be
R1 135 k
Since
Ri R1 kr2 50 k
then
R2 79:4 k
Comment: In order to achieve the desired speci®cations, a relatively large transcon-

ductance is required, which means that a large transistor is needed. If the load effect
were reduced, that is, if RI were made larger, the required size of the transistor could be
reduced.
6.4.2 Input and Output Impedance

The input resistance Ri as de®ned in Figure 6.29(b), for example, is the
Thevenin equivalent resistance of the bias resistors. Even though the input
resistance to the gate of the MOSFET is essentially in®nite, the input bias
resistances do provide a loading effect. This same effect was seen in the com-
mon-source circuits.
To calculate the output resistance, we set all independent small-signal
sources equal to zero, apply a test voltage to the output terminals, and measure
a test current. Figure 6.31 shows the circuit we will use to determine the output
resistance of the source-follower shown in Figure 6.28. We set Vi 0 and apply
a test voltage Vx . Since there are no capacitances in the circuit, the output
impedance is simply an output resistance, which is de®ned as
Vx
Ro 6:34
Ix
RSi Ro
+ Vgs –
Ix
R1R2 gmVgs RS ro + Vx
–
Figure 6.31 Equivalent circuit of NMOS source-follower, for determining output resistance
Writing a KCL equation at the output source terminal produces
Vx Vx
Ix gm Vgs 6:35
R S ro
Since there is no current in the input portion of the circuit, we see that
Vgs Vx . Therefore, Equation (6.35) becomes

1 1
Ix Vx gm 6:36a
R S ro
or
Ix 1 1 1
gm 6:36b
Vx Ro RS ro
The output resistance is then
1
Ro kR kr 6:37
gm S o
From Figure 6.31, we see that the voltage Vgs is directly across the current
source gm Vgs . This means that the effective resistance of the device is 1=gm . The
output resistance given by Equation (6.37) can therefore be written directly.
This result also means that the resistance looking into the source terminal
(ignoring ro ) is 1=gm , as previously noted.
Example 6.9 Objective: Calculate the output resistance of a source-follower

circuit.
Consider the circuit shown in Figure 6.28 with circuit and transistor parameters
given in Example 6.7.
Solution: The results of Example 6.7 are: RS 0:75 k
, ro 12:5 k
, and
gm 11:3 mA=V. Using Figure 6.31 and Equation (6.37), we ®nd
1 1
Ro kR kr k0:75k12:5
gm S o 11:3
or
Ro 0:0787 k
78:7
Comment: The output resistance of a source-follower circuit is dominated by the

transconductance parameter. Also, because the output resistance is very low, the
source-follower tends to act like an ideal voltage source, which means that the output
can drive another circuit without signi®cant loading effects.

*6.17 Consider the circuit shown in Figure 6.30 with circuit parameters VDD 5 V,
RS 5 k
, R1 70:7 k
, R2 9:3 k
, and RSi 500
. The transistor parameters are:
VTP 0:8 V, Kp 0:4 mA=V2 , and 0. Calculate the small-signal voltage gain Av
vo =vi and the output resistance Ro seen looking back into the circuit. (Ans.
Av 0:817, Ro 0:915 k
)
D6.18 The transistor in the source-follower circuit shown in Figure 6.32 is biased
with a constant current source. The transistor parameters are: VTN 2 V,
kn0 40 mA=V2 , and 0:01 V 1 . The load resistor is RL 4 k
. (a) Design the tran-
sistor width-to-length ratio such that gm 2 mA/V when I 0:8 mA. What is the cor-
responding value for VGS ? (b) Determine the small-signal voltage gain and the output
resistance Ro . (Ans. (a) W=L 62:5, VGS 2:8 V; (b) Av 0:886, Ro 0:5 k
)
+9 V
Ro
CC
vi + RG = vo
–
100 kΩ
I RL
–9 V
Figure 6.31 Equivalent circuit of NMOS source-follower, for determining output resistance
*D6.19 The parameters of the transistor in the source-follower circuit shown in

Figure 6.33 are: VTP 2 V, Kp 2 mA=V2 , and 0:02 V 1 . Design the circuit
such that IDQW 3 mA. Determine the open-circuit RL 1 small-signal voltage
+5 V
RS
vo
CC1
CC2
RL
vi + RG =
–
500 kΩ
–5 V
Figure 6.33 Figure for Exercise 6.19
gain. What value of RL will result in a 10 percent reduction in the gain? (Ans.
RS 0:593 k
, Av 0:737, RL 1:35 k
)
6.5 THE COMMON-GATE CONFIGURATION

The third ampli®er con®guration is the common-gate circuit. To determine the
small-signal voltage and current gains, and the input and output impedances,
we will use the same small-signal equivalent circuit for the transistor that was
used previously. The dc analysis of the common-gate circuit is the same as that
of previous MOSFET circuits.
6.5.1 Small-Signal Voltage and Current Gains

In the common-gate con®guration, the input signal is applied to the source
terminal and the gate is at signal ground. The common-gate con®guration
shown in Figure 6.34 is biased with a constant-current source IQ . The gate
resistor RD prevents the buildup of static charge on the gate terminal, and the
capacitor CG ensures that the gate is at signal ground. The coupling capacitor
CC1 couples the signal to the source, and coupling capacitor CC2 couples the
output voltage to load resistance RL .
The small-signal equivalent circuit is shown in Figure 6.35. The small-
signal transistor resistance ro is assumed to be in®nite. The output voltage is
Ri
RSi CC1 CC2

vo
ii
vi + IQ
– RD RL
RG CG
V – V+
Figure 6.34 Common-gate circuit

Ri gmVgs Ro
RS i S
Vo
–
Ii
+ Vgs
Vi – RD Io RL
+
G
Figure 6.35 Small-signal equivalent circuit of common-gate ampli®er
Vo gm Vgs RD kRL 6:38
Writing the KVL equation around the input, we ®nd
Vi Ii RSi Vgs 6:39
where Ii gm Vgs . The gate-to-source voltage can then be written as

V
V gs 6:40
1 gm RSi
The small-signal voltage gain is found to be
Vo gm RD kRL
Av 6:41
Vi 1 gm RSi
Also, since the voltage gain is positive, the output and input signals are in
phase.
In many cases, the signal input to a common-gate circuit is a current.
Figure 6.36 shows the small-signal equivalent common-gate circuit with a
Norton equivalent circuit as the signal source. We can calculate a current
gain. The output current Io can be written

RD
Io gm Vgs 6:42
RD RL
At the input we have

Vgs
Ii gm Vgs 0 6:43
RSi
Figure 6.36 Small-signal equivalent circuit of common-gate ampli®er with a Norton

equivalent signal source
or

RSi
Vgs Ii 6:44
1 gm RSi
The small-signal current gain is then

I RD gm RSi
Ai o 6:45
Ii RD RL 1 gm RSi
We may note that if RD RL and gm RSi 1, then the current gain is essen-
tially unity as it is for an ideal BJT common-base circuit.
6.5.2 Input and Output Impedance

In contrast to the common-source and source-follower ampli®ers, the com-
mon-gate circuit has a low input resistance because of the transistor.
However, if the input signal is a current, a low input resistance is an advantage.
The input resistance is de®ned as
Vgs
Ri 6:46
Ii
Since Ii gm Vgs , the input resistance is
1
Ri 6:47
gm
This result has been obtained previously.
We can ®nd the output resistance by setting the input signal voltage equal
to zero. From Figure 6.35, we see tht Vgs gm Vgs RSi , which means that
Vgs 0. Consequently, gm Vgs 0. The output resistance, looking back from
the load resistance, is therefore
Ro RD 6:48
Example 6.10 Objective: For the common-gate circuit, determine the output vol-
tage for a given input current.
For the circuit shown in Figure 6.36, the circuit parameters are: IQ 1 mA,
V 5 V, V 5 V, RG 100 k
, RD 4 k
, and RL 10 k
. The transistor para-
meters are: VTN 1 V, Kn 1 mA=V2 , and 0. Assume the input current is
100 sin !t mA.
Solution: The quiescent gate-to-source voltage is determined from
IQ IDQ Kn VGSQ VTN 2
or
1 1VGSQ 12
which yields
VGSQ 2 V
The small-signal transconductance is
gm 2Kn VGSQ VTN 212 1 2 mA=V
From Equation (6.45), we can write the output current as

RD gm RSi
Io Ii
RD RL 1 gm RSi
The output voltage is Vo Io RK , so we ®nd

RL RD gm RSi
V o Ii
RD RL 1 gm RSi

104 250
0:1 sin !t
4 10 1 250
or
Vo 0:283 sin !t V
Comment: As with the BJT common-base circuit, the MOSFET common-gate ampli-
®er is useful if the input signal is a current

RD6.20 For the circuit shown in Figure 6.34, the circuit parameters are: V 5 V,
V 5 V, RG 100 k
, RL 4 k
, and IQ 0:5 mA. The transistor parameters are
VTN 1 V and 0. The circuit is driven by a signal current source Ii . Redesign RD
and gm such that the transfer function Vo =Ii is 2.4 k
and the output resistance is Ri
350
: Determine VGSQ and show that the transistor is biased in the saturation region.
(Ans. gm 2:86 mA/V, RD 6 k
, VGSQ 1:35 V)
6.21 Consider the circuit shown in Figure 6.37 with circuit parameters V 5 V,
V 5 V, RS 4 k
, RD 2 k
, RL 4 k
and RG 50 k
. The transistor para-
meters are: Kp 1 mA=V2 , VTP 0:8 V, and 0. Draw the small-signal equivalent
circuit, determine the small-signal voltage gain Av Vo =Vi , and ®nd the input resistance
Ri . (Ans. Av 2:41, Ri 0:485 k
)
Ri
CC1 CC2
vo
vi +
– RS RD RL
RG CG
V+ V–

6.6 THE THREE BASIC AMPLIFIER CONFIGURATIONS:

SUMMARY AND COMPARISON
Table 6.1 is a summary of the small-signal characteristics of the three ampli®er
con®gurations.
Table 6.1 Characteristics of the three MOSFET ampli®er con®gurations

Con®guration Voltage gain Current gain Input resistance Output resistance
Common source Av > 1 Ð RTH Moderate to high
Source follower Av 1 Ð RTH Low
Common gate Av > 1 Ai 1 Low Moderate to high
The common-source ampli®er voltage gain is generally greater than 1. The

voltage gain of the source-follower is slightly less than1, and that of the com-
mon-gate circuit is generally greater than 1.
The input resistance looking directly into the gate of the common-source
and source-follower circuits is essentially in®nite at low to moderate signal
frequencies. However, the input resistance of these discrete ampli®ers is the
Thevenin equivalent resistance RTH of the bias resistors. In contrast, the input
resistance to the common-gate circuit is generally in the range of only a few
hundred ohms.
The output resistance of the source follower is generally in the range of a
few hundred ohms or less. The output resistance of the common-source and
common-gate con®gurations is dominated by the resistance RD . In Chapters 10
and 11, we will see that the output resistance of these con®gurations is domi-
nated by the resistance ro when transistors are used as load devices in ICs.
The speci®c characteristics of these single-stage ampli®ers are used in the
design of multistage ampli®ers.
6.7 SINGLE-STAGE INTEGRATED CIRCUIT MOSFET

AMPLIFIERS
In the last chapter, we considered three all-MOSFET inverters and plotted the
voltage transfer characteristics. All three inverters use an n-channel enhance-
ment-mode driver transistor. The three types of load devices are an n-channel
enhancement-mode device, an n-channel depletion-mode device, and a p-chan-
nel enhancement-mode device. The MOS transistor used as a load device is
referred to as an active load. We mentioned that these three circuits can be used
as ampli®ers.
In this section, we revisit these three circuits and consider their ampli®er
characteristics. We will emphasize the small-signal equivalent circuits. This
section serves as an introduction to more advanced MOS integrated circuit
ampli®er designs considered in Part II of the text.
6.7.1 NMOS Amplifiers with Enhancement Load

The characteristics of an n-channel enhancement load device were presented in
the last chapter. Figure 6.38(a) shows an NMOS enhancement load transistor,
iD
VDS (sat) = VGS – VTNL
Transistor
characteristics
iD(max)
iD
+
vDS
–
VTNL vDD vDS

(a) (b)
Figure 6.38 (a) NMOS enhancement-mode transistor with gate and drain connected in a
load device con®guration and (b) current±voltage characteristics of NMOS enhancement load
transistor
and Figure 6.38(b) shows the current±voltage characteristics. The threshold

voltage is VTNL .
Figure 6.39(a) shows an NMOS ampli®er with enhancement load. The
driver transistor is MD and the load transistor is ML . The characteristics of
transistor MD and the load curve are shown in Figure 6.39(b). The load curve is
essentially the mirror image of the i±v characteristic of the load device. Since
the i v characteristics of the load device are nonlinear, the load curve is also
nonlinear. The load curve intersects the voltage axis at VDD VTNL , which is
the point where the current in the enhancement load device goes to zero. The
transistion point is also shown on the curve.
The voltage transfer characteristic is also useful in visualizing the opera-
tion of the ampli®er. This curve is shown in Figure 6.39(c). When the enhance-
ment-mode driver ®rst begins to conduct, it is biased in the saturation region.
For use as an ampli®er, the circuit Q-point should be in this region, as shown in
both Figures 6.39(b) and (c).
We can now apply the small-signal equivalent circuits to ®nd the voltage
gain. In the discussion of the source-follower, we found that the equivalent
resistance looking into the source terminal (with RS 1) was Ro 1=gm kro .
The small-signal equivalent circuit of the inverter is given in Figure 6.40, where
the subscripts D and L refer to the driver and load transistors, respectively. We
are again neglecting the body effect of the load transistor.
The small-signal voltage gain is then

Vo 1
Av gmD roD
g roL 6:49
Vi mL
Since, generally, 1=gmL roL and r=gmD roD , the voltage gain, to a good
approximation is given by
VDD
iD
iD
+ iD(max)
ML vDSL
+
–
vGSL
– vO Transition point
+ Q-point
MD vDSD
+
vi + – Load curve
– vGSD
–
+
VGS
VDD vDSD = vO
–
VTNL
(a) (b)
vO
MD MD in MD in
cut-off saturation nonsaturation
VDD – VTNL Cutoff point
Q-point
Transition point
0 VTND vGSD
(c)
Figure 6.39 (a) NMOS ampli®er with enhancement load device; (b) driver transistor
characteristics and enhancement load curve with transition point; and (c) voltage transfer
characteristics of NMOS ampli®er with enhancement load device
Figure 6.40 Small-signal equivalent circuit of NMOS inverter with enhancement load
device.
s s
gmD KnD W=LD
Av 6:50
gmL KnL W=LL
The voltage gain, then, is related to the size of the two transistors.
Design Example 6.11 Objective: Design the small-signal voltage gain of an

NMOS ampli®er with enhancement load, and establish the Q-point in the middle of
the saturation region.
Consider the circuit shown in Figure 6.39(a) with transistor parameters
VTND VTNL 1 V, kn0 30 mA=V2 , W=LL 1. The circuit parameter is VDD 5 V.
Design the circuit such that the voltage gain is jAv j 10.
Solution: From Equation (6.50), we have
s
W=LD
jAv j 10
W=LL
Therefore, the width-to-length ratio of the driver transistor must be

W W
102 1001 100
L D L L
The conduction parameters are then

W 1 0
KnD kn 10015 ) 1:5 mA=V2
L D 2
and

W 1 0
KnL kn 115 ) 0:015 mA=V2
L L 2
We can determine the transition point by setting
vO vGSD VTND
Therefore,
s
KnD
vGSD VTND VDD VTNL v VTND
KnL GSD
or
r
1:5
vGSD 1 5 1 v 1
0:015 GSD
which yields transition point values of
vGSD 1:36 V and vDSD 0:36 V

Considering the resulting voltage transfer characteristics shown in Figure 6.41, the
middle of the saturation region is halfway between the cutoff point
(vGSD VTND 1 V) and the transition point vGSD 1:36 V), or
VGSQ 1:18 V
vO (V)
5
Cut-off point
4
Q-point
VDSDQ = 2.18
2
1
Transition point
0.36
0 1.0 1.2 1.4 1.6 vGSD (V)

VGSQ = 1.18 V 1.36 V
Figure 6.41 Voltage transfer characteristics and Q-point of NMOS ampli®er with
enhancement load, for Example 6.11
Comment: These results show that a very large difference is required in the sizes of the
two transistors to produce a gain of 10. In fact, a gain of 10 is about the largest practical
gain that can be produced by an enhancement load device. A larger small-signal gain
can be obtained by using a depletion-mode MOSFET as a load device, as shown in the
next section.
Design Pointer: The body effect of the load transistor was neglected in this analysis.
The body effect will actally lower the small-signal voltage gain from that determined in
the example.

6.22 For the enhancement load ampli®er shown in ®gure 6.39(a), the parameters
are: VTND VTNL 0:8 V, kn0 40 mA=V2 , W=LD 80, W=LL 1, and VDD 5 V.
Determine the small-signal voltage gain. Determine VGS such that the Q-point is in the
middle of the saturation region. (Ans. Av 8:94, VGS 1:01 V)
D6.23 For the enhancement load ampli®er shown in Figure 6.39(a), the parameters
are: VTND VTNL 1 V, kn0 30 ma=V2 , W=LL 2, and VDD 10 V. Design the cir-
cuit such that the small-signal voltage gain is jAv j 6 and the Q-point is in the center of
the saturation region. (Ans. W=LD 72, VGS 1:645 V)
6.7.2 NMOS Amplifier with Depletion Load

Figure 6.42(a) shows the NMOS depletion-mode transistor connected as a load
device and Figure 6.42(b) shows the current±voltage characteristics. The tran-
sition point is also indicated. The threshold voltage VTNL of this device is
negative, which means that the vDS value at the transition point is positive.
Also, the slope of the curve in the saturation region is not zero; therefore, a
®nite resistance ro exists in this region.
iD
iD vDS (sat) = – VTNL

vGS = 0
iD(max)
1
+ Slope =
rO
vDS
Transition
– point
vDD vDS
(a) (b)
Figure 6.42 (a) NMOS depletion-mode transistor with gate and source connected in a load
device con®guration and (b) current±voltage characteristic of NMOS depletion load transistor
Figure 6.43(a) shows an NMOS depletion load ampli®er. The transistor

characteristics of MD and the load curve for the cicuit are shown in Figure
6.43(b). The load curve, again, is the mirror image of the i v characteristic of
the load device. Since the i v characteristics of the load device are nonlienar,
the load curve is also nonlinear. The transistion points for both MD and ML
are also indicated. Point A is the transition point for MD , and point B is the
transistion point for ML . The Q-point should be approximately midway
between the two transition points.
The dc voltage VGSDQ biases transistor MD in the saturation region at the
Q-point. The signal voltage vi superimposes a sinuosoidal gate-to-source vol-
tage on the dc value, and the bias point moves along the load curve about the
Q-point. Again, both MD and ML must be biased in their saturation regions at
all times.
The voltage transfer characteristics of this circuit is shown in Figure
6.43(c). Region III corresponds to the condition in which both transistors
are biased in the saturation region. The desired Q-point is indicated.
We can again apply the small-signal equivalent circuit to ®nd the small-
signal voltage gain. Since the gate-to-source voltage of the depletion-load
device is held at zero, the equivalent resistance looking into the source term-
inal is Ro ro . The small-signal equivalent circuit of the inverter is given in
Figure 6.44, where the subscripts D and L refer to the driver and load
transistors, respectively. We are again neglecting the body effect of the
load device.
VDD
iD
iD
+ VGSDQ
Load curve Q-point
ML vDSL
– A
vO
+ iD(max)
MD vDSD
–
vi +
–
+
VGSDQ B C
–
VDD vDSD
(a) (b)
vO
I II III IIIV
VDD
C
VDD – VTNL 
B
Q-point
0 VTND vGSD
(c)
Figure 6.43 (a) NMOS ampli®er with depletion load device; (b) driver transistor
characteristics and depletion load curve, with transition points; and (c) voltage transfer
characteristics
Figure 6.44 Small-signal equivalent circuit of NMOS inverter with depletion load device
Vo
Av gmD roD kroL 6:51
Vi
In this circuit, the voltage gain is directly proportional to the output resistances
of the two transistors.
Example 6.12 Objective: Determine the small-signal voltage gain of the NMOS
ampli®er with depletion load.
For the circuit shown in Figure 6.43(a), assume transistor parameters of
VTND 0:8 V, VTNL 1:5 V, KnD 1 mA=V2 , KnL 0:2 mA=V2 , and
1
D L 0:01 V . Assume the transistors are biased at IDQ 0:2 mA.
Solution: The transconductance of the driver is
p p
gmD 2 KnD IDQ 2 10:2 0:894 mA=V
Since D L , the output resistances are
1 1
roD roL 500 k
IDQ 0:010:2
Av gmD roD kroL 0:894500k500 224
Comment: The voltage gain of the NMOS ampli®er with depletion load is, in general,
signi®cantly larger than that with the enhancement load device. The body effect will
lower the ideal gain factor.
Discussion: One aspect of this circuit design that we have not emphasized is the dc
biasing. We mentioned that both transistors need to be biased in their saturation
regions. From Figure 6.43(a), this dc biasing is accomplished with the dc source
VGSDQ . However, because of the steep slope of the transfer characteristics (Figure
6.43(c)), applying the ``correct'' voltage becomes dif®cult. As we will see in the next
section, dc biasing is generally accomplished with current source biasing.

*6.24 For the depletion load ampli®er in Figure 6.43(a), the parameters are:
VTND 0:8 V, VTNL 1:2 V, KnD 250 mA=V2 , KnL 25 mA=V2 , D L
0:01 V 1 , and VDD 5 V. (a) Determine VGS such that the Q-point is in the middle of
the saturation region. (b) Calculate the quiescent drain current. (c) Determine the small-
signal voltage gain. (Ans. (a) VGS 1:18 V; (b) IDQ 37 mA; (c) Av 257)
6.7.3 NMOS Amplifier with PMOS Load

Common-Source Ampli®er
An ampli®er using an n-channel enhancement-mode driver and a p-channel
enhancement mode active load is shown in Figure 6.45(a) in a common-source
con®guration. The p-channel active load transistor M2 is biased from M3 and
IBias . This con®guration is similar to the MOSFET current source shown in
Figure 5.39 in Chapter 5. With both n- and p-channel transistors in the same
circuit, this circuit is now referred to as a CMOS ampli®er.
The i v characteristic curve for M2 is shown in Figure 6.45(b). The source-
to-gate voltage is a constant and is established by M3 . The driver transistor
characteristics and the load curve are shown in Figure 6.45(c). The transistion
points of both M1 and M2 are shown. Point A is the transistion point for M1
and point B is the transition point for M2 . The Q-point, to establish an ampli-
®er, should be approximately halfway between points A and B, so that both
transistors are biased in their saturation regions. The voltage transfer charac-
teristics are shown in Figure 6.45(d). Shown on the curve are the same transi-
tion points A and B and the desired Q-point.
We again apply the small-signal equivalent circuits to ®nd the small-signal
voltage gain. With vSG2 held constant, the equivalent resistance looking into the
Figure 6.45 (a) CMOS common-source ampli®er; (b) PMOS active load i v characteristic,
(c) driver transistor characteristics with load curve, (d) voltage transfer characteristics
drain of M2 is just Ro rop . The small-signal equivalent circuit of the inverter

is then as given in Figure 6.46. The subscripts n and p refer to the n-channel
and p-channel transistors, respectively. We may note that the body terminal of
M1 will be tied to ground, which is the same as the source of M1 , and the body
terminal of M2 will be tied to VDD , which is the same as the source of M2 .
Hence, there is no body effect in this circuit.
The small-signal voltage gain is
Vo
Av gmn ron krop
Vi
Again for this circuit, the small-signal voltage gain is directly proportional to
the output resistances of the two transistors.
Figure 6.46 Small-signal equivalent circuit of the CMOS common-source ampli®er
Example 6.13 Objective: Determine the small-signal voltage gain of the CMOS
ampli®er.
For the circuit shown in Figure 6.45(a), assume transistor parameters of
VTN 0:8 V, VTP 0:8 V, kn0 80 mA=V2 , kp0 40 mA=V2 , W=Ln 15,
W=Lp 30, and n p 0:01 V 1 . Also, assume IBias 0:2 mA.
Solution: The transconductance of the NMOS driver is
s

p kn0 W
gmn 2 Kn IDQ 2 I
2 L n Bias
s

0:08
2 150:2 0:693 mA=V
2
Since n p , the output resistances are
1 1
ron rop 500 k
IDQ 0:010:2
Av gm ron krop 0:693500k500 173
Comment: The voltage gain of the CMOS ampli®er is on the same order of magnitude
as the NMOS ampli®er with depletion load. However, the CMOS ampli®er does not
suffer from the body effect.
Discussion: In the circuit con®guration shown in Figure 6.45(a), we must again apply
a dc voltage to the gate of M1 to achieve the ``proper'' Q-point. We will show in later
chapters using more sophisticated circuits how the Q-point is more easily established
with current-source biasing. However, this circuit demonstrates the basic principles of
the CMOS common-source ampli®er.
CMOS Source-Follower and Common-Gate Ampli®ers

The same basic CMOS circuit con®guration can be used to form CMOS
source-follower and common-gate con®gurations. Figure 6.47(a) and (b)
show these circuits.
We see that for the source-follower circuit, the active load M2 is an n-
channel rather than a p-channel device. The input is applied to the gate of M1
and the output is at the source of M1 . For the common-gate ampli®er, the
active load M2 is again a p-channel device. The input is applied to the source
of M1 and the output is at the drain of M1 .
We may note that in both the source-follower and common-gate circuits,
the body effect will need to be taken into account. In both circuits, the body
terminal of the amplifying transistor M1 will be connected to the most negative
voltage, which is not the same as the source terminal. We will consider these
types of circuits in detail in later chapters.
Figure 6.47 (a) CMOS source-follower ampli®er; (b) CMOS common-gate ampli®er
6.8 MULTISTAGE AMPLIFIERS

In most applications, a single-transistor ampli®er will not be able to meet the
combined speci®cations of a given ampli®cation factor, input resistance, and
output resistance. For example, the requried voltage gain may exceed that
which can be obtained in a single-transistor circuit.
Transistor ampli®er circuits can be connected in series, or cascaded, as

shown in Figure 6.48. This may be done either to increase the overall small-
signal voltage gain, or provide an overall voltage gain greater than 1, with a
very low output resistance. The overall voltage gain may not simply be the
product of the individual ampli®cation factors. Loading effects, in general,
need to be taken into account.
There are many possible multistage con®gurations; we will examine a few
here, in order to understand the type of analysis required.
+ +
Stage 1 Stage 2
vi vo
AV 1 AV 2
– AV 1 –
Ri1 Ro1 Ri2 Ro2
Figure 6.48 Generalized two-stage ampli®er
6.8.1 DC Analysis
The circuit shown in Figure 6.49 is a cascade of a common-source ampli®er
followed by a source-follower ampli®er. As shown previously, the common-
source ampli®er provides a small-signal voltage gain and the source-follower
has a low output impedance.
V+=5V
RD1
Ri R1
RSi CC
M1 M2 C Ro
C2
vo
vi +
– R2
RS1 CS RS2 RL =
4 kΩ
V – = –5 V
Figure 6.49 Common-source ampli®er in cascade with source-follower
Design Example 6.14 Objective: Design the biasing of a multistage MOSFET

circuit to meet speci®c requirements.
Consider the circuit shown in Figure 6.49 with transistor parameters
Kn1 500 mA=V2 , Kn2 200 mA=V2 , VTN1 VTN2 1:2 V, and 1 2 0. Design
the circuit such that IDQ1 0:2 mA, IDQ2 0:5 mA, VDSQ1 VDSQ2 6 V, and
Ri 100 k
. Let RSi 4 k
:
Solution: For output transistor M2 , we have
VDSQ2 5 5 IDQ2 RS2
or
6 10 0:5RS2
which yields RS2 8 k

. Also,
IDQ2 Kn2 VGS2 VTN2 2
or
0:5 0:2VGS2 1:22
which yields
VGS2 2:78 V
Since VDSQ2 6 V, the source voltage of M2 is VS2 1 V. With VGS2 2:78 V,

the gate voltage on M2 must be
VG2 1 2:78 1:78 V
The resistor RD1 is then

5 1:78
RD1 16:1 k
0:2
For VDSQ1 6 V, the source voltage of M1 is
VS1 1:78 6 4:22 V
The resistor RS1 is then

4:22 5
RS1 3:9 k
0:2
For transistor M1 , we have
IDQ1 Kn1 VGS1 VTN1 2
or
0:2 0:50VGS1 1:22
which yields
VGS1 1:83 V
To ®nd R1 and R2 , we can write

R2
VGS1 10 IDQ1 RS1
R1 R2
Since

R2 1 R1 R2 1
R
R1 R2 R1 R1 R2 R1 i
then
1
1:83 10010 0:23:9
R1
which yields R1 383 k

. From R 100 k
, we ®nd that R2 135 k
.
Comment: Both transistors are biased in the saturation region, which is desired for
linear ampli®ers.
Figure 6.50 shows a cascode circuit with n-channel MOSFETs. Transistor

M1 is connected in a common source con®guration and M2 is connected in a
common-gate con®guration. The advantage of this type of circuit is a higher
frequency response, which is discussed in a later chapter.
V+=5V
RD
R1
vO
CG
M2
R2
CC
M1
vi + R3
–
RS CS
V – = –5 V
Figure 6.50 NMOS cascode circuit
Design Example 6.15 Objective: Design the biasing of the cascode circuit to
meet speci®c requirements.
For the circuit shown in Figure 6.50, the transistor parameters are: VTN1
VTN2 1:2 V, Kn1 Kn2 0:8 mA=V2 , and 1 2 0. Let R1 R2 R3 300 k
and RS 10 k
. Design the circuit such that IDQ 0:4 mA and
VDSQ1 VDSQ2 2:5 V.
Solution: The dc voltage at the source of M1 is
VS1 IDQ RS 5 0:410 5 1V

Since M1 and M2 are identical transistors, and since the same current exists in the two
transistors, the gate-to-source voltage is the same for both devices. We have
ID Kn VGS VTN 2
or
0:4 0:8VGS 1:22

which yields
VGS 1:91 V
Then,

R3
VG1 5 VGS VS1
R1 R2 R3
or

R3
5 1:91 1 0:91
300
which yields
R3 54:6 k
The voltage at the source of M2 is

VS2 VDSQ2 VS2 2:5 1 1:5 V
Then,

R2 R3
VG2 5 VGS VS2
R1 R2 R3
or

R2 R3
5 1:91 1:5 3:41 V
300
which yields
R2 R3 204:6 k
and
R2 150 k
Therefore
R1 95:4 k
The voltage at the drain of M2 is

VD2 VDSQ2 VS2 2:5 1:5 4 V
The drain resistor is therefore

5 VD2 5 4
RD 2:5 k
IDQ 0:4
Comment: Since VDS 2:5 V > VGS VTN 1:91 1:2 0:71 V, each transistor is
biased in the saturation region.
6.8.2 Small-Signal Analysis

The midband small-signal voltage gain of multistage ampli®ers is determined
by assuming that all external coupling capacitors act as short circuits and
inserting the small-signal equivalent circuits for the transistors.
Example 6.16 Objective: Determine the small-signal voltage gain of a multistage

cascade circuit.
Consider the circuit shown in Figure 6.49 with transistor and circuit parameters
given in Example 6.14.
Solution: The small-signal transconductance parameters are
gm1 2Kn1 VGS1 VTN1 20:501:83 1:2 0:63 mA=V
and
gm2 2Kn2 VGS2 VTN2 20:22:78 1:2 0:632 mA=V
The small-signal equivalent circuit is shown in Figure 6.51.
Ri
gm2Vgs2
RSi
+ – Vo
+ Vg s2
Vi + R1R2 Vg s1 RD1 RS2 RL
– gm1Vgs1
–
Figure 6.51 Small-signal equivalent circuit of NMOS cascade circuit
The output voltage is

Vo gm2 Vgs2 Rs2 kRL
Also,
Vgs2 Vo gm1 Vgs1 RD1
where

Ri
Vgs1 Vi
Ri RSi
Then

Ri
Vgs2 gm1 RD1 Vi Vo
Ri RSi
Therefore

Ri
Vo gm2 gm1 RD1 Vi Vo Rs2 kRL
Ri RSi

Vo gm1 Gm2 Rd1 Rs2 kRL Ri
Av
Vi 1 gm2 RS2 kRL Ri RSi
or

0:630:63216:18k4 100
Av 6:13
1 0:6328k4 100 4
Comment: Since the small-signal voltage gain of the source-follower is slightly less
than 1, the overall gain is due essentially to the common-source input stage. also, as
shown previously, the output resistance of the source-follower is small, which is desir-
able in many applications.
Example 6.17 Objective: Determine the small-signal voltage gain of a cascode

circuit.
For the circuit shown in Figure 6.50, the transistor and circuit parameters are as
given in Example 6.15. The input signal to the circuit is an ideal voltage source.
Solution: Since the transistors are identical, the small-signal transconductance para-
meters of the two transistors are equal. Therefore,
gm1 gm2 2Kn VGS VTN 20:81:91 1:2 1:14 mA=V
The small-signal equivalent circuit is shown in Figure 6.52. Transistor M1 supplies the
source current of M2 with the signal current gm1 Vi . Transistor M2 acts as a current-
follower and passes this current on to its drain terminal. The output voltage is
therefore
Vo gm1 Vgs1 RD
Since Vgs1 Vi , the small-signal voltage gain is
Vo
Av gm1 RD
Vi
or
Av 1:142:5 2:85
gm2Vgs2 = gm1Vgs1
Vo
+
+ R3 R2 Vgs1 gm1Vgs1 RD
Vi –
Figure 6.52 Small-signal equivalent circuit of NMOS cascode circuit
Comment: The small-signal voltage gain is essentially the same as that of a single
common-source ampli®er stage. The addition of a common-gate transistor will increase
the frequency bandwidth, as we will see in a later chapter.

6.25 For the cascade circuit shown in Figure 6.49, the transistor and circuit para-
meters are given in Example 6.15. Calculate the small-signal output resistance Ro . (The
small-signal equvialent circuit is shown in Figure 6.15.) (Ans. Ro 1:32 k
)
*D6.26 The supply voltages to the cascade circuit shown in Figure 6.49 are changed
to V 10 V and V 10 V. The transistor parameters are: Kn1 Kn2 1 mA=V2 ,
VTN1 VTN2 2 V, and 1 2 0:01 V 1 . (a) Let RL 4 k
, and design the circuit
such that IDQ1 IDQ2 2 mA, VDSQ1 VDSQ2 10 V, and Ris 200 k
. (b) Calculate
the small-signal voltage gain and the output resistance Ro . (Ans. (a) RS2 5 k
,
RD1 3:3 k
, RS1 1:71 k
, R1 586 k
, R2 304 k
; (b) Av 8:06, Ro
0:330 k
)
D6.27 The supply voltages to the cascode circuit shown in Figure 6.50 are changed
to V 10 V and V 10 V. The transistor parameters are: Kn1 Kn2 1:2 mA=V2 ,
VTN1 VTN2 2 V, and 1 2 0. (a) Let R1 R2 R3 500 k
, and Rs 10 k
.
Design the circuit such that IDQ 1 mA and VDSQ1 VDSQ2 3:5 V. (b) Determine the
small-signal voltage gain. (Ans. (a) R3 145:5 k
, R2 175 k
, R1 179:5 k
,
RD 3 k
; (b) Av 6:57)
6.9 BASIC JFET AMPLIFIERS

Like MOSFETs, JFETs can be used to amplify small time-varying signals.
Initially, we will develop the small-signal model and equivalent circuit of the
JFET. We will then use the model in the analysis of JFET ampli®ers.
6.9.1 Small-Signal Equivalent Circuit

VDD Figure 6.53 shows a JFET circuit with a time-varying signal applied to the gate.
The instantaneous gate-to-source voltage is
iD RD vGS VGS vi VGS vgs 6:53
vO where vgs is the small-signal gate-to-source voltage. Assuming the transistor is

+ biased in the saturation region, the instantaneous drain current is
iG
vDS
– vGS 2
+ iD IDSS 1 6:54
vi + vGS
–
VP
–
+ where IDSS is the saturation current and VP is the pinchoff voltage.
VGS
Substituting Equation (6.53) into (6.54), we obtain
–
2
VGS vgs
iD IDSS 1 6:55
Figure 6.53 JFET common- VP VP
source circuit with time-
varying signal source in series If we expand the squared term, we have
with gate dc source

VGS 2 VGS vgs 2
iD IDSS 1 2IDSS 1 IDSS vgs P 6:56
VP VP VP
The ®rst term in Equation (6.56) is the dc or quiescent drain current IDQ ,
the second term is the time-varying drain current component, which is linearly
related to the signal votlage vgs , and the third term is proportional to the square
of the signal voltage. As in the case of the MOSFET, the third term produces a
nonlinear distortion in the output current. To minimize this distortion, we will
usually impose the following condition:

vgs
2 1 VGS 6:57
V VP
P
Equation (6.57) represents the small-signal condition that must be satis®ed for
JFET ampli®ers to be linear.
Neglecting the term v2gs in Equation (6.56), we can write
iD IDQ id 6:58
where the time-varying signal current is

2IDSS VGS
id 1 v 6:59
VP VP gs
The constant relating the small-signal drain current and small-signal gate-to-
source voltage is the transconductance gm . We can write
id gm vgs 6:60
where

2IDSS VGS
gm 1 6:61
VP VP
Since VP is negative for n-channel JFETs, the transconductance is positive. A
relationship that applies to both n-channel and p-channel JFETs is

2IDSS VGS
gm 1 6:62
jVP j VP
We can also obtain the transconductance from

@iD
gm 6:63
@vGS vGS VGSQ
Since the transconductance is directly proportional to the saturation current

IDSS , the transconductance is also a function of the width-to-length ratio of the
transistor.
Since we are looking into a reverse-biased pn junction, we assume that the
input gate current ig is zero, which means that the small-signal input resistance
is in®nite. Equation (6.54) can be expanded to take into account the ®nite
output resistance of a JFET biased in the saturation region. The equation
becomes

vGS 2
iD IDSS 1 1 vDS 6:64
VP
The small-signal output resistance is
1
@iD
ro 6:65
@vDS
vGS const:
Using Equation (6.64), we obtain

" 2 # 1
VGS
ro IDSS 1 6:66a
VP
G D or
+
1 1
Vgs gmVgs ro ro IDQ 6:66b
IDQ
–
S The small-signal equivalent circuit of the n-channel JFET, shown in Figure
6.54, is exactly the same as that of the n-channel MOSFET. The small-signal
Figure 6.54 Small-signal
equivalent circuit of n-channel
equivalent circuit of the p-channel JFET is also the same as that of the p-
JFET channel MOSFET. However, the polarity of the controlling gate-to-source
voltage and the direction of the dependent current source are reversed from
those of the n-channel device.
6.9.2 Small-Signal Analysis

Since the small-signal equivalent circuit of the JFET is the same as that of the
MOSFET, the small-signal analyses of the two types of circuits are identical.
For illustration purposes, we will analyze two JFET circuits.
Example 6.18 Objective: Determine the small-signal voltage gain of JFET ampli-
®er.
Consider the circuit shown in Figure 6.55 with transistor parameters IDSS 12 mA,
VP 4 V, and 0:008 V 1 . Determine the small-signal voltage gain Av vo =vi .
VDD = 20 V
RD = 2.7 kΩ
R1 = 420 kΩ
vo
CC2
CC1 RL = 4 kΩ
vi +
– R2 = 180 kΩ RS = 2.7 kΩ CS
Figure 6.55 Common-source JFET circuit with source resistor and source bypass capacitor
Solution: The dc quiescent gate-to-source voltage is determined from

R2
VGSQ V IDQ RS
R1 R2 DD
where
2
VGSQ
IDQ IDSS 1
VP
Combining these two equations produces

2
180 VGSQ
VGSQ 20 122:7 1
180 420 4
which reduces to
2
2:025VGSQ 17:2VGSQ 26:4 0
The appropriate solution is
VGSQ 2:01 V
The quiescent drain current is

2 2
VGSQ 2:01
IDQ IDSS 1 12 1 2:97 mA
VP 4
The small-signal parameters are then

2I VGS 212 2:01
gm DSS 1 1 2:98 mA=V
VP VP 4 4
and
1 1
ro 42:1 k
IDQ 0:0082:97
The small-signal equivalent circuit is shown in Figure 6.56.
Vo
+
Vi + R1R2 Vgs gmVgs ro RD RL

–
–
Figure 6.56 Small-signal equivalent circuit of common-source JFET, assuming bypass

capacitor acts as a short circuit

Vo
Av gm ro kRD kRL
Vi
or
Av 2:9842:1k2:7k4 4:62
Comment: The voltage gain of JFET ampli®ers is the same order of magnitude as that
of MOSFET ampli®ers.
Design Example 6.19 Objective: Design a JFET source-follower circuit with a

speci®ed small-signal voltage gain.
For the source-follower circuit shown in Figure 6.57, the transistor parameters are:
IDSS 12 mA, VP 4 V, and 0:01 V 1 . Determine RS and IDQ such that the
small-signal voltage gain is at least Av vo =vi 0:90.
+10 V
CC1
CC2
vo
vi + RL = 10 kΩ
– RG = 50 kΩ RS
–10 V
Figure 6.57 JFET source-follower circuit
Solution: The small-signal equivalent circuit is shown in Figure 6.58. The output
voltage is
Vo gm Vgs RS kRL kro
Also
Vi Vgs Vo
or
Vgs Vi Vo
Therefore, the output voltage is
Vo gm Vi Vo RS kRL kro
The small-signal voltage gain becomes
Vo gm Rs kRL kro
Av
Vi 1 gm Rs kRL kro
As a ®rst approximation, assume ro is suf®ciently large for the effect of ro to be
neglected.
gmVgs ro
+ Vgs – Vo
Vi + RG
– RS RL
Figure 6.58 Small-signal equivalent circuit of JFET source-follower circuit

The transconductance is

2IDSS VGS 212 VGS
gm 1 1
VP VP 4 4
If we pick a nominal transconductance value of gm 2 mA/V, then VGS 2:67 V and

the quiescent drain current is
2 2
VGS 2:67
IDQ IDSS 1 12 1 1:33 mA
VP 4
The value of RS is then determined from
VGS 10 2:67 10

RS 9:53 k
IDQ 1:33
Also, the value of ro is
1 1
ro 75:2 k
IDQ 0:011:33
The small-signal voltage gain, including the effect of ro , is
gm RS kRL kro 29:53k10k75:2

Av 0:902
1 gm Rs kRL kro 1 29:53k10k75:2
Comment: This particular design meets the design criteria, but the solution is not
unique.
In the last example, we chose a value of transconductance and continued

through the design. A more detailed examination shows that both gm and RS
depend upon the drain current IDQ in such a way that the product gm RS is
approximately a constant. This means the small-signal voltage gain is insensi-
tive to the initial value of the transconductance.

6.28 Reconsider the JFET ampli®er shown in Figure 6.55 with transistor parameters
given in Example 6.19. Determine the small-signal voltage gain if a 20 k
resistor is in
series with the signal source vi . (Ans. Av 3:98
RD6.29 For the JFET ampli®er shown in Figure 6.55, the transistor parameters are:
IDSS 4 mA, VP 3 V, and 0:005 V 1 . Let RL 4 k
, RS 2:7 k
, and
R1 R2 500 k
. Redesign the circuit such that IDQ 1:2 mA and VDSQ 12 V.
Calculate the small-signal voltage gain. (Ans. RD 3:97 k
, R1 453 k
,
R2 47 k
, Av 2:87)
*6.30 For the circuit shown in Figure 6.59, the transistor parameters are:
IDSS 6 mA, jVP j 2 V, and 0. (a) Calculate the quiescent drain current and
VDD = 20 V
R1 = 70 kΩ RS1 = 4 kΩ
CC1
CS
Q1
Q2
CC2
vi + vo
– R2 = 430 kΩ
RD1 = 4 kΩ
RS 2 = 4 kΩ RL = 2 kΩ
drain-to-source voltage of each transistor. (b) Determine the overall small-signal voltage
gain Av vo =vi . (Ans. (a) IDQ1 1 mA, VSDQ1 12 V, IDQ2 1:27 mA, VDSQ2 14:9 V;
(b) Av 2:05)
6.31 Reconsider the source-follower circuit shown in Figure 6.57 with transistor
parameters IDSS 8 mA, VP 3:5 V, and 0:01 V 1 . (a) Design the circuit such
that IDQ 2 mA. (b) Calculate the small-signal voltage gain if RL approaches in®nity.
(c) Determine the value of RL at which the small-signal gain is reduced by 20 percent
from its value for (b). (Ans. (a) RS 5:88 k
, (b) Av 0:923, RL 1:64 k
)
6.10 SUMMARY
* The application of MOSFET transistors in linear ampli®er circuits was emphasized in
this chapter. A small-signal equivalent circuit for the transistor was developed, which
is used in the analysis and design of linear ampli®ers.
* Three basic circuit con®gurations were considered: the common source, source fol-
lower, and common gate. These three con®gurations form the basic building blocks
for complex integrated circuits. The small-signal voltage gains and output resistances
for these circuits were analyzed. The circuit characteristics of the three circuits were
compared in Table 6.1.
* The ac analysis of circuits with enhancement load devices, with depletion load
devices, and complementary (CMOS) devices were analyzed. These circuits are
examples of all MOSFET circuits and act as an introduction to more complex all
MOSFET integrated circuits considered later in the text.
* The small-signal equivalent circuit of a JFET was developed and used in the analysis
of several con®gurations of JFET ampli®ers.
CHECKPOINT
After studying this chapter, the reader should have the ability to:
\ Explain graphically the ampli®cation process in a simple MOSFET ampli®er circuit.
(Section 6.1)
\ Describe the small-signal equivalent circuit of the MOSFET and to determine the
values of the small-signal parameters. (Section 6.1)
\ Apply the small-signal equivalent circuit to various MOSFET ampli®er circuits to

obtain the time-varying circuit characteristics.
\ Characterize the small-signal voltage gain and output resistance of a common-source
ampli®er. (Section 6.3)
\ Characterize the small-signal voltage gain and output resistance of a source-follower
\ Characterize the small-signal voltage gain and output resistance of a common-gate
\ Describe the operation of an NMOS ampli®er with either an enhancement load, a
depletion load, or a PMOS load. (Section 6.7)
\ Apply the MOSFET small-signal equivalent circuit in the analysis of multistage
ampli®er circuits. (Section 6.8)
\ Describe the operation and analyze basic JFET ampli®er circuits. (Section 6.9)
REVIEW QUESTIONS
1. Discuss, using the concept of a load line superimposed on the transistor character-
istics, how a simple common-source circuit can amplify a time-varying signal.
2. How does a transistor width-to-length ratio affect the small-signal voltage gain of
a common-source ampli®er?
3. Discuss the physical meaning of the small-signal circuit parameter ro .
4. How does the body effect change the small-signal equivalent circuit of the
MOSFET?
5. Sketch a simple common-source ampli®er circuit and discuss the general ac circuit
characteristics (voltage gain and output resistance).
6. Discuss the general conditions under which a common-source ampli®er would be
used.
7. Why, in general, is the magnitude of the voltage gain of a common-source ampli-
®er smaller than that of a bipolar common-emitter ampli®er?
8. What are the changes in the ac characteristics of a common-source ampli®er
when a source resistor and a source bypass capacitor are incorporated in the
design?
9. Sketch a simple source-follower ampli®er circuit and discuss the general ac circuit
10. Discuss the general conditions under which a source-follower ampli®er would be
used.
11. Sketch a simple common-gate ampli®er circuit and discuss the general ac circuit
12. Discuss the general conditions under which a common-gate ampli®er would be
used.
13. Compare the ac circuit characteristics of the common-source, source-follower, and
common-gate circuits.
14. State the general advantage of using transistors in place of resistors in integrated
circuits.
15. State at least two reasons why a multistage ampli®er circuit would be required in a
design compared to using a single-stage circuit.
16. Give one reason why a JFET might be used as an input device in a circuit as
opposed to a MOSFET.
PROBLEMS
Section 6.1 The MOSFET Amplifier

6.1 An NMOS transistor has parameters VTN 0:8 V, kn0 40 mA=V2 , and 0. (a)
Determine the width-to-length ratio W=L such that gm 0:5 mA/V at ID 0:5 mA
when biased in the saturation region. (b) Calculate the required value of VGS .
6.2 A PMOS transistor has parameters VTP 1:2 V, kp0 20 mA=V, and 0. (a)
Determine the width-to-length ratio W=L such that gm 50 mA=V at ID 0:1 mA
when biased in the saturation region. (b) Calculate the required value of VSG .
6.3 An NMOS transistor is biased in the saturation region at a constant VGS . The
drain current is ID 3 mA at VDS 5 V and ID 34 mA at VDS 10 V. Determine
and ro .
6.4 The minimum value of small-signal resistance of a PMOS transistor is to be
ro 100 k
. If 0:012 V 1 , calculate the maximum allowed value of ID .
6.5 Calculate the small-signal voltage gain of the circuit shown in Figure 6.1, for
gm 1 mA/V, ro 50 k
, and RD 10 k
.
*D6.6 For the circuit shown in Figure 6.1, the transistor parameters are:
VTN 0:8 V, 0:015 V 1 , and kn0 60 mA=V2 . Let VDD 10 V. (a) Design the tran-
sistor width-to-length ratio W=L and the resistance RD such that IDQ 0:5 mA and
VDSQ 6 V. (b) Calculate gm and ro . (c) What is the small-signal voltage gain
Av vo =vi ?
*6.7 In our analyses, we assumed the small-signal condition given by Equation (6.4).
Now consider Equation (6.3b) and let vgs Vgs sin !t. Show that the ratio of the signal
at frequency 2! to the signal at frequency ! is given by Vgs =4VGS VTN . This ratio,
expressed in a percentage, is called the second-harmonic distortion. [Hint: Use the trigo-
nometric identity sin2 12 12 cos 2.]
6.8 Using the results of Problem 6.7, ®nd the peak amplitude Vgs that produces a
second-harmonic distortion of 1 percent if VGS 3 V and VTh 1 V.
Section 6.3 Common-Source Amplifier

6.9 Calculate the small-signal voltage gain of a common-source ampli®er, such as that
shown in Figure 6.13, assuming gm 1 mA/V, ro 50 k
, and RD 10 k
. Also
assume RSi 2 k
and R1 kR2 50 k
.
6.10 A common-source ampli®er, such as shown in Figure 6.13 in the text, has para-
meters ro 100 k
and RD 5 k
. Determine the transconductance of the transistor if
the small-signal voltage gain is Av 10. Assume RSi 0.
6.11 For the NMOS common-source ampli®er in Figure P6.11, the transistor para-
meters are: VTN 2 V, Kn 1 mA=V2 , and 0. The circuit parameters are:
VDD 12 V, RS 2 k
, RD 3 k, R1 300 k
, and R2 200 k
. Assume RSi
2 k
and assume a load resistance RL 3 k
is capacitively coupled to the output.
(a) Determine the quiescent values of ID and VDS . (b) Find the small-signal voltage
gain. (c) Determine the maximum symmetrical swing in the output voltage.
6.12 In the circuit in Figure P6.11, VDD 15 V, RD 2 k
, RL 5 k
, RS 0:5 k
,
and Rin 200 k
. (a) Find R1 and R2 such that IDQ 3 mA for VTN 2 V,
Kn 2 mA=V2 , and 0. (b) Determine the small-signal voltage gain.
6.13 Repeat Problem 6.11 if the source resistor is bypassed by a source capacitor CS .
VDD
RD
Rin R1 CC2
vo
CC1
RL
vi +
– R2
RS
Figure P6.11
*6.14 The transistor in the common-source ampli®er in Figure P6.14 has parameters
VTN 1 V, Kn 0:5 mA=V2 , and 0:01 V 1 . The circuit parameters are: V 5 V,
V 5 V, and RD RL 10 k
. (a) Determine IDQ to achieve the maximum sym-
metrical swing in the output voltage. (b) Find the small-signal voltage gain.
D6.15 For the common-source ampli®er in Figure P6.15, the transistor parameters
are: VTN 1 V, Kn 4 mA=V2 , and 0. The circuit parameters are VDD 10 V
and RL 2 k
. (a) Design the circuit such that IDQ 2 mA and VDSQ 6 V. (b)
Determine the small-signal voltage gain. (c) If vi Vi sin !t, determine the maximum
value of Vi such that vo is an undistorted sine wave.
V+
VDD
RD
CC2
vo RD
CC1
CC2
RL vo
CC1
vi + RG =
– 200 kΩ RL
vi +
IQ CS – RG = 1 MΩ
RS
V–
Figure P6.14 Figure P6.15
*6.16 The transistor in the common-source circuit in Figure P6.15 has the same para-
meters as given in Problem 6.15. The circuit parameters are VDD 5 V and
RD RL 2 k
. (a) Find RS and VDSQ 2:5 V. (b) Determine the small-signal voltage
gain.
*6.17 Consider the PMOS common-source circuit in Figure P6.17 with transistor
parameters VTP 2 V and 0, and circuit parameters RD RL 10 k
. (a)
Determine the values of Kp and RS such that VSDQ 6 V. (b) Determine the resulting
value of IDQ and the small-signal voltage gain. (c) Can the values of Kp and RS from
+5 V
RS
CC1 CS
CC2
vo
vi + RG =
– 100 kΩ
RD RL
–5 V
Figure P6.17
part (a) be changed to achieve a larger voltage gain, while still meeting the requirements
of part (a)?
D6.18 For the common-source circuit in Figure P6.17, the PMOS transistor para-
meters are: VTP 1:5 V, Kp 5 mA=V2 , and 0. The load resistor is RL 2 k
.
(a) Design the circuit such that IDQ 1 mA and VSDQ 5 V. (b) Determine the small-
signal voltage gain Av vo =vi . (c) What is the maximum symmetrical swing in the
output voltage?
*D6.19 Design the common-source circuit in Figure P6.19 using an n-channel
MOSFET with 0. The quiescent values are to be IDQ 6 mA, VGSQ 2:8 V, and
VDSQ 10 V. The transconductance is gm 2:2 mA/V. Let RL 1 k
, Av 1, and
Rin 100 k
. Find R1 ; R2 ; RS ; RD ; Kn , and VTN .
*6.20 For the common-source ampli®er in Figure P6.20, the transistor parameters
are: VTP 1:5 V, Kp 2 mA=V2 , and 0:01 V 1 . The circuit is to drive a load
resistance of RL 20 k
. To minimize loading effects, the drain resistance should
be RD 0:1RL . (a) Determine IQ such that the Q-point is in the center of the
saturation region. (b) Determine the open-circuit RL 1 small-signal voltage
gain. (c) By what percentage does the small-signal voltage gain decrease when RL
is connected?
VDD = 18 V +9 V
IQ
RD
Rin R1
vo CC1 CS
CC1
CC2 CC2
vo
vi +
RL – RG = 500 kΩ
vi +
– R2
RS RD RL
–9 V

D6.21 For the circuit shown in Figure P6.21, the transistor parameters are: VTP 2 V,
Kp 0:5 mA=V2 , and 0. (a) Design the circuit such that IDQ 2 mA and
VSDQ 6 V. (b) Determine the small-signal voltage gain Av vo =vi .
*D6.22 Design a common-source ampli®er, such as that in Figure P6.22, to achieve a
small-signal voltage gain of at least Av vo =vi 10 for RL 20 k
and
Rin 200 k
. Assume the Q-point is chosen at IDQ 1 mA and VDSQ 10 V. Let
VTN 2 V, and 0.
VDD = 20 V
+10 V
RS RD
Rin R1
vo
CC1
CC CS CC2
vo RL
vi + vi +
– RG = 200 kΩ – R2
RS CS
RD
–10 V
Section 6.4 Source-Follower Amplifier

6.23 For an enhancement-mode MOSFET source-follower, gm 4 mA=V and
ro 50 k
. Determine the no-load voltage gain and the output resistance. Calculate
the small-signal voltage gain when a load resistance RS 2:5 k
is connected.
6.24 The transistor in the source-follower circuit in Figure P6.24 has parameters
Kp 2 mA=V2 , VTP 2 V, and 0:02 V 1 . The circuit parameters are: RL
4 k
, RS 4 k
, R1 1:24 M
, and R2 396 k
. (a) Calculate IDQ and VSDQ . (b)
Determine the small-signal gains Av vo =vi and Ai io =ii , and the output resistance Ro .
VDD = 10 V
RS Ro
R1
vo
CC1
CC2
ii io RL
vi + R2
–
Figure P6.24
6.25 Consider the source-follower circuit in Figure P6.25 with transistor parameters
VTN 1:2 V, Kn 1 mA=V2 , and 0:01 V 1 . If IQ 1 mA, determine the small-
signal voltage gain Av vo =vi and the output resistance Ro .
+5 V
CC1
Ro
CC2
vi + RG = vo
–
500 kΩ
RL =
IQ
4 kΩ
–5 V
Figure P6.25
6.26 For the source-follower circuit shown in Figure P6.25, the transistor parameters
are: VTN 1 V, kn0 60 mA=V2 , and 0. The small-signal voltage gain is to be
Av vo =vi 0:95. (a) Determine the required width-to-length ratio W=L for
IQ 4 mA. (b) Determine the required IQ if W=L 60.
*D6.27 In the source-follower circuit in Figure P6.27 with a depletion NMOS transis-
tor, the device parameters are: VTN 2 V, Kn 5 mA=V2 , and 0:01 V 1 . Design
the circuit such that IDQ 5 mA. Find the small-signal voltage gain Av vo =vi and the
output resistance Ro .
+5 V
CC1
Ro
CC2
vi + RG = vo
– 200 kΩ
RL =
RS
2 kΩ
–5 V
Figure P6.27
6.28 Consider the circuit in Figure P6.27. Let RS 10 k

and 0. The open-circuit
voltage gain RL 1 is Av vo =vi 0:90. Determine gm and Ro . Determine the value
of the voltage gain if a load resistor RL 2 k
is connected.
D6.29 For the source-follower circuit in Figure P6.27, the transistor parameters are:
VTN 2 V, Kn 4 mA=V2 , and 0. Design the circuit such that Ro 200
.
Determine the resulting small-signal voltage gain.
6.30 The current source in the source-follower circuit in Figure P6.30 is IQ 5 mA
and the transistor parameters are: VTP 2 V, Kp 5 mA=V2 , and 0. (a)
Determine the output resistance Ro . (b) Determine the value of RL that reduces the
small-signal voltage gain to one-half the open-circuit RL 1 value.
V+=5V
IQ
Ro
vo
CC1
CC2
RL
vi + RG =
–
200 kΩ
V – = –5 V
Figure P6.30
6.31 Consider the source-follower circuit shown in Figure P6.31. The most negative
output signal voltage occurs when the transistor just cuts off. Show that this output
voltage vo min is given by
IDQ RS
vo min
R
1 S
RL
Show that the corresponding input voltage is given by

IDQ
vi min 1 gm RS kRL
gm
D6.32 The transistor in the circuit in Figure P6.32 has parameters VTN 1 V,
Kn 1 mA=V2 , and 0. The circuit parameters are VDD 5 V and Ri 300 k
.
(a) Design the circuit such that IDQ 1:7 mA and VDSQ 3 V. (b) Determine the
small-signal voltage gain Av vo =vi and the output resistance Ro .
VDD
VDD
Ri
R1
CC1
CC1
CC2 Ro
vi + vo vO
– RG +
vi R2
–
RS
RS RL
Section 6.5 Common-Gate Configuration

6.33 For the common-gate circuit in Figure P6.33, the NMOS transistor parameters
are: VTN 1 V, Kn 3 mA=V2 , and 0. (a) Determine IDQ and VDSQ . (b) Calculate
gm and ro . (c) Find the small-signal voltage gain Av vo =vi .
6.34 Consider the PMOS common-gate circuit in Figure P6.34. The transistor para-
meters are: VTP 1 V, Kp 0:5 mA=V2 , and 0. (a) Determine RS and RD such
that IDQ 0:75 mA and VSDQ 6 V. (b) Determine the input impedance Ri and the
Ro
Ri
CC1 CC2
vo
CC1 CC2
Ri =
vo RL =
100 kΩ RS RD i o
2 kΩ
RG =
vi + CG
– RS = 10 kΩ RD = 5 kΩ RL = 4 kΩ 50 kΩ
V + = +5 V V – = –5 V
V – = –5 V V + = +5 V
output impedance Ro . (c) Determine the load current io and the output voltage vo , if
ii 5 sin !t mA.
6.35 The parameters of the transistor in the circuit in Figure 6.34 in the text are:
VTN 2 V, Kn 4 mA=V2 , and 0. The circuit parameters are: V 10 V,
V 10 V, RG 100 k
, RL 2 k
, and IQ 5 mA. (a) Find RD such that
VDSQ 12 V. (b) Calculate gm and Ri . (c) Determine the small-signal voltage gain
Av vo =vi .
6.36 For the common-gate ampli®er in Figure 6.37 in the text, the PMOS transistor
parameters are: VTP 2 V, Kp 2 mA=V2 , and 0. The circuit parameters are:
V 10 V, V 10 V, RG 200 k
, and RL 10 k
. (a) Determine RS and RD
such that IDQ 3 mA and VSDQ 10 V. (b) Determine the small-signal voltage gain
Av vo =vi .
Section 6.7 Amplifiers with MOSFET Load Devices

D6.37 Consider the NMOS ampli®er with saturated load in Figure 6.39(a). The tran-
sistor parameters are: VTND VTNL 2 V, kn0 60 mA=V2 , 0, and W=LL 0:5.
Let VDD 10 V. (a) Design the circuit such that the small-signal voltage gain is jAv j 5
and the Q-point is in the center of the saturation region. (b) Determine IDQ and the dc
value of vo .
*6.38 For the NMOS ampli®er with depletion load in Figure 6.43(a), the transistor
parameters are: VTND 1:2 V, VTNL 2 V, KnD 0:5 mA=V2 , KnL 0:1 mA=V2 , and
D L 0:02 V 1 . Let VDD 10 V. (a) Determine VGS such that the Q-point is in the
middle of the saturation region. (b) Calculate IDQ and the dc value of vo . (c) Determine
VDD = 10 V the small-signal voltage gain.
6.39 Consider a saturated load device in which the gate and drain of an enhancement
mode MOSFET are connected together. The transistor drain current becomes zero
when VDS 1:5 V. When VDS 3 V, the drain current is 0.8 mA. Determine the
ML small-signal resistance at this operating point.
6.40 The parameters of the transistors in the circuit in Figure P6.40 are VTND 1 V,
vO
KnD 0:5 mA=V2 for transistor MD , and VTNL 1 V, KnL 30 mA=V2 for transistor
ML . Assume 0 for both transistors. (a) Calculate the quiescent drain current IDQ
MD
and the dc value of the output voltage. (b) Determine the small-signal voltage gain Av
vi + vo =vi about the Q-point.
–
6.41 A source-follower circuit with a saturated load is shown in Figure P6.41. The
transistor parameters are VTND 1 V, KnD 1 mA=V2 for MD , and VTNL 1 V, KnL
Figure P6.40 0:1 mA=V2 for ML . Assume 0 for both transistors. Let VDD 9 V. (a) Determine
VDD
MD
Ro
vi + CC
– vo
+
VGG +
– ML vDSL RL
–
Figure P6.41
VGG such that the quiescent value of vDSL is 4 V. (b) Show that the small-signal open-
p
circuit RL 1 voltage gain about this Q-point is given by Av 1=1 KnL =KnD .
(c) Calculate the small-signal voltage gain for RL 4 k
.
6.42 For the source-follower circuit with a saturated load, as shown in Figure P6.41,
assume the same transistor parameters as given in Problem 6.41. (a) Determine the small-
signal voltage gain if RL 10 k
. (b) Determine the small-signal output resistance Ro .
Section 6.8 Multistage Amplifiers

*D6.43 The transistor parameters in the circuit in Figure P6.43 are: Kn1 0:1 mA=V2 ,
Kp2 1:0 mA=V2 , VTN1 2 V, VTD2 2 V, and 1 2 0. The circuit parameters
are: VDD 10 V, RS1 4 k
, and Rin 200 k
. (a) Design the circuit such that
IDQ1 0:4 mA, IDQ2 2 mA, VDSQ1 4 V, and VSDQ2 5 V. (b) Calculate the small-
signal voltage gain Av vo =vi . (c) Determine the maximum symmetrical swing in the
output voltage.
VDD
RD1 RS2
R1
Rin
CS2
M1 M2
CC
vO
vi + R2
– CS1
RS1 RD2
Figure P6.43
D6.44 The transistor parameters in the circuit in Figure P6.43 are the same as those given
in Problem 6.43. The circuit parameters are: VDD 10 V, RS1 1 k
, Rin 200 k
,
RD2 2 k
, and RS2 0:5 k
. (a) Design the circuit such that the Q-point of M2 is in
the center of the saturation region and IDQ1 0:4 mA. (b) Determine the resulting values
of IDQ2 ; VSDQ2 ; and VDSQ1 . (c) Determine the resulting small-signal voltage gain.
D6.45 Consider the circuit in Figure P6.45 with transistor parameters Kn1
Kn2 200 mA=V2 , VTN1 VTN2 0:8 V, and 1 2 0. (a) Design the circuit such
that VDSQ2 7 V and Rin 400 k
. (b) Determine the resulting values of IDQ1 , IDQ2 ,
and VDSQ1 . (c) Calculate the resulting small-signal voltage gain Av vo =vi and the
output resistance Ro .
6.46 For the circuit in Figure P6.46, the transistor parameters are: Kn1
Kn2 4 mA=V2 , VTN1 VTN2 2 V, and 1 2 0. (a) Determine IDQ1 , IDQ2 ,
VDSQ1 , and VDSQ2 . (b) Determine gm1 and gm2 . (c) Determine the overall small-signal
voltage gain Av vo =vi .
VDD = 10 V
+10 V
Rin
R1
CC CC1
M1 M2 Ro
M1
CC2 CC3
vO
vi + RG = M2 vo
vi + – 400 kΩ
– R2 RS1 = RS2 =
RS1 = RS2 = RD = RL =
20 kΩ 6 kΩ
10 kΩ 10 kΩ 5 kΩ 2 kΩ
–10 V –10 V +10 V
D6.47 For the cascode circuit in Figure 6.50 in the text, the transistor parameters are:
VTN1 VTN2 1 V, Kn1 Kn2 2 mA=V2 , and 1 2 0. (a) Let RS 1:2 k
and
R1 R2 R3 500 k
. Design the circuit such that IDQ 3 mA and
VDSQ1 VDSQ2 2:5 V. (b) Determine the small-signal voltage gain Av vo =vi .
D6.48 The supply voltages to the cascode circuit in Figure 6.50 in the text are
changed to V 10 V and V 10 V. The transistor parameters are:
Kn1 Kn2 4 mA=V2 , VTN1 VTN2 1:5 V, and 1 2 0. (a) Let RS 2 k
,
and assume the current in the bias resistors is 0.1 mA. Design the circuit such that
IDQ 5 mA and VDSQ1 VDSQ2 3:5 V. (b) Determine the resulting small-signal vol-
tage gain.
Section 6.9 Basic JFET Amplifiers

6.49 Consider the JFET ampli®er in Figure 6.53 with transistor parameters
IDSS 6 mA, VP 3 V, and 0:01 V 1 . Let VDD 10 V. (a) Determine RD and
VGS such that IDQ 4 mA and VDSQ 6 V. (b) Determine gm and ro at the Q-point.
(c) Determine the small-signal voltage gain Av vo =vi where vo is the time-varying
portion of the output voltage vO .
6.50 For the JFET ampli®er in Figure P6.50, the transistor parameters are:
IDSS 2 mA, VP 2 V, and 0. Determine gm , Av vo =vi , and Ai io =ii .
D6.51 The parameters of the transistor in the JFET common-source ampli®er shown
in Figure P6.51 are: IDSS 8 mA, VP 4:2 V, and 0. Let VDD 20 V and
RL 16 k
. Design the circuit such that VS 2 V, R1 R2 100 k
, and the Q-
point is at IDQ IDSS =2 and VDSQ VDD =2.
VDD
VDD
RD = 8 kΩ
vo
CC CC2 RD
R1
Rin vo
ii RS1 = CC1 CC2
RL =
100 Ω io
4 kΩ
vi + RG =
– io RL
50 kΩ ii
RS2 = vi + R2 RS
CS –
250 Ω
*D6.52 Consider the source-follower JFET ampli®er in Figure P6.52 with transistor
parameters IDSS 10 mA, VP 5 V, and 0:01 V 1 . Let VDD 12 V and
RL 0:5 k
. (a) Design the circuit such that Rin 100 k
, and the Q-point is at IDQ
IDSS =2 and VDSQ VDD =2: (b) Determine the resulting small-signal voltage gain Av
vo =vI and the output resistance Ro .
6.53 For the p-channel JFET source-follower circuit in Figure P6.53, the transistor
parameters are: IDSS 2 mA, VP 1:75 V, and 0. (a) Determine IDQ and VSDQ .
(b) Determine the small-signal gains Av vo =vi and Ai io =ii . (c) Determine the max-
imum symmetrical swing in the output voltage.
D6.54 The p-channel JFET common-source ampli®er in Figure P6.54 has transistor
parameters IDSS 8 mA, VP 4 V, and 0. Design the circuit such that IDQ 4 mA,
VSDQ 7:5 V, Av vo =vi 3, and R1 R2 400 k
.
VDD VDD = 10 V
Rin
R1 R1 = 90 kΩ RS = 5 kΩ
CC1 Ro CC1
vo
vo CC2
ii CC2 ii
RL =
vi +
R2 io
– RS RL vi + 10 kΩ
io – R2 = 110 kΩ

VDD = 20 V
R1 RS
CC1
vO
vi +
– R2
RD
Figure P6.54
COMPUTER SIMULATION PROBLEMS

6.55 Consider the circuit in Figure 6.22 with transistor parameters given in Example
6.6. Using a computer analysis, investigate the effect of the channel-length modulation
parameter and the body-effect parameter on the small-signal voltage gain.
6.56 Using a computer analysis, investigate the effect of the transistor parameters
and on the small-signal voltage gain and output resistance of the source-follower
circuit in Figure 6.28. The circuit and transistor parameters are given in Example 6.7.
6.57 For the common-gate circuit in Figure 6.34 the circuit and transistor parameters
are as given in Example 6.10. Using a computer analysis, determine the small-signal
voltage gain, current gain, input resistance Ri , and output resistance (looking into the
drain of the transistor). As part of the analysis, investigate the effect of the transistor
parameters and on the circuit characteristics.
6.58 Perform a computer analysis of Exercise 6.22, including the body effect.
Determine the change in the small-signal voltage gain when the body effect is included.
If the dc output voltage is approximately 2.5 V, determine the required change in the dc
bias on the driver transistor when the body effect is included.
6.59 Repeat Problem 6.58 for Exercise 6.24.
DESIGN PROBLEMS
[Note: Each design should be correlated with a computer analysis.]
*D6.60 A discrete common-source circuit with the con®guration shown in Figure 6.16
is to be designed to provide a voltage gain of 20 and a symmetrical output voltage swing.
The power supply voltage is VDD 5 V, the output resistance of the signal source is
1 k
, and the transistor parameters are: VTN 0:8 V, kn0 40 mA=V2 , and 0:01 V 1 .
Plot W=L and RD versus quiescent drain current. Determine W=L and RD for IDQ
0:1 mA:
*D6.61 For a common-gate ampli®er in Figure 6.37 the available power supplies are
10 V, the output resistance of the signal source is 200
, and the input resistance of the
ampli®er is to be 200
. The transistor parameters are: kp0 30 mA=V2 , VTP 2 V,
and 0. The output load resistance is RL 5 k
. Design the circuit such that the
output voltage has a peak-to-peak symmetrical swing of at least 5 V.
*D6.62 A source-follower ampli®er with the general con®guration shown in Figure

6.32 is to be designed. The available power supplies are 12 V, and the transistor
parameters are: VTN 1:5 V, kn0 40 mA=V2 , and 0. The load resistance is
RL 100
. Design the circuit such that 200 mW of signal power is delivered to the
load. As part of the design, a constant-current source circuit is also to be designed.
*D6.63 For an NMOS ampli®er with a depletion load, such as shown in Figure
6.43(a), the available power supplies are 5 V, and the transistor parameters are:
VTN MD 1 V, VTN ML 2 V, kn0 40 mA=V2 , 0:01 V 1 , and 0:35 V1=2 .
Design the circuit such that the small-signal voltage gain is at least jAv j 200 when the
output is an open circuit. Use a constant-current source to establish the quiescent Q-
point, and couple the signal source vi directly to the gate of MD .
*D6.64 For the cascode circuit shown in Figure 6.50, the transistor parameters are:
VTN 1 V, kn0 40 mA=V2 , and 0. Design the circuit such that the minimum open-
circuit voltage gain is 10. Determine the maximum symmetrical swing in the output
voltage.

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C H A P T E R

6.1 THE MOSFET AMPLIFIER

6.1.1 Graphical Analysis, Load Lines, and Small-Signal

VDSQ VDD vDS

which can be written

VTh VGS vGS

As shown in Equation (6.8(a)), the transconductance is directly propor-

Example 6.1 Objective: Calculate the transconductance of an n-channel

Assuming the transistor is biased in the saturation region, the transconductance is

Comment: The transconductance of a bipolar transistor is gm  ICQ =VT , which is

The ac equivalent circuit in Figure 6.4 is developed by setting the dc

source is assumed to be constant, the sinusoidal current produces no sinusoidal

6.1.2 Small-Signal Equivalent Circuit

This small-signal equivalent circuit can also be expanded to take into

iD  Kn  vGS VTN 2 1  vDS  6:16

where  is the channel-length modulation parameter and is a positive quantity.

ro  Kn VGSQ VTN 2  1

This small-signal output resistance is also a function of the Q-point parameters.

The expanded small-signal equivalent cicuit of the n-channel MOSFET is

Vi + Vgs gmVgs ro RD Vds

Example 6.2 Objective: Determine the small-signal voltage gain of a MOSFET

IDQ  Kn VGSQ VTN 2  0:8 2:12 12  1:0 mA

and the output resistance is

From Figure 6.7, the output voltage is

Since Vgs  Vi , the small-signal voltage gain is

Comment: Because of the relatively low value of transconductance, MOSFET circuits

Problem Solving Method: MOSFET AC Analysis

Test Your Understanding

The previous discussion was for an n-channel MOSFET ampli®er. The

Vo  gm Vsg Ro kRD  6:19

Vsg gmVsg ro Vsd Vi + Vsg gmVsg ro RD

Figure 6.9 Small-signal Figure 6.10 Small-signal equivalent circuit

and the small-signal voltage gain is

We may again note that if the polarity of the small-signal gate-to-source

6.1.3 Modeling the Body Effect

iD  Kn vGS VTN 2 6:22

and the threshold voltage is given by

If an ac component exists in the source-to-body voltage, vSB , there will be

Using Equation (6.22), we ®nd

The back gate transconductance is then

gmb  gm    gm  6:26

Test Your Understanding

6.2 BASIC TRANSISTOR AMPLIFIER CONFIGURATIONS

6.3 THE COMMON-SOURCE AMPLIFIER

6.3.1 A Basic Common-Source Configuration

The input gate-to-source voltage is

so the small-signal voltage gain is

We can also relate the ac drain current to the ac drain-to-source voltage, as

VDS (sat) = VGS – VTN

VDSQ VDD vDS

The ampli®er input resistance is

and the ampli®er output resistance is

Discussion: The small-signal input gate-to-source voltage is

Test Your Understanding

Figure 6.16 Common-source NMOS transistor circuit

VDS (sat) = VGS – VTN

VDS t (sat) VDSQ = 7 V VDD = 12 V vDS

6.3.2 Common-Source Amplifier with Source Resistor

Example 6.5 Objective: Determine the small-signal voltage gain of a common-

Comment: The transconductance of a bipolar transistor is gm ICQ =VT , which is

iD Kn vGS VTN 2 1 vDS 6:16

where is the channel-length modulation parameter and is a positive quantity.

ro Kn VGSQ VTN 2 1

IDQ Kn VGSQ VTN 2 0:82:12 12 1:0 mA

Since Vgs Vi , the small-signal voltage gain is

Vo gm Vsg Ro kRD 6:19

iD Kn vGS VTN 2 6:22

gmb gm gm 6:26

Vi Vgs gm Vgs RS Vgs 1 gm RS

Since Vgs Vi , the small-signal voltage gain is

Vo gm Vgs Rs kro 6:30

Vo gm Vgs RD kRL 6:38

Vi Ii RSi Vgs 6:39

where Ii gm Vgs . The gate-to-source voltage can then be written as

gm 2Kn VGSQ VTN 212 1 2 mA=V

The output voltage is Vo Io RK , so we ®nd

vGSD 1:36 V and vDSD 0:36 V