18cs33 Ade m2 Notes

CANARA ENGINEERING COLLEGE
Benjanapadavu, Bantwal Taluk - 574219

Department of Computer Science & Engineering
VISION
To be recognized as a center of knowledge dissemination in Computer Science and Engineering
by imparting value-added education to transform budding minds into competent computer
professionals.
MISSION
M1. Provide a learning environment enriched with ethics that helps in enhancing problem
solving skills of students and, cater to the needs of the society and industry.
M2. Expose the students to cutting-edge technologies and state-of-the-art tools in the
many areas of Computer Science & Engineering.
M3. Create opportunities for all round development of students through co-curricular and
extra-curricular activities.
M4. Promote research, innovation and development activities among staff and students.
PROGRAMME EDUCATIONAL OBJECTIVES
A. Graduates will work productively as computer science engineers exhibiting ethical

qualities and leadership roles in multidisciplinary teams.
B. Graduates will adapt to the changing technologies, tools and societal requirements.
C. Graduates will design and deploy software that meets the needs of individuals and the
industries
D. Graduates will take up higher education and/or be associated with the field so that they
can keep themselves abreast of Research & Development
PROGRAMME OUTCOMES
Engineering graduates in Computer Science and Engineering will be able to:

1. Engineering knowledge: Apply the knowledge of mathematics, science, engineering
fundamentals and an engineering specialization to the solution of complex engineering
problems.
2. Problem analysis: Identify, formulate, review research literature and analyze complex
engineering problems reaching substantiated conclusions using first principles of
mathematics, natural sciences and engineering sciences.
3. Design/development of solutions: Design solutions for complex engineering problems
and design system components or processes that meet the specific needs with appropriate
consideration for the public health and safety, and the cultural, societal and
environmental considerations.
4. Conduct investigations of complex problems: Use research-based knowledge and
research methods, including design of experiments, analysis and interpretation of data
and synthesis of the information to provide valid conclusions.
5. Modern tool usage: Select/Create and apply appropriate techniques, resources and
modern engineering and IT tools, including prediction and modeling to complex
engineering activities, taking comprehensive cognizance of their limitations.
6. The engineer and society: Apply reasoning informed by the contextual knowledge to
assess societal, health, safety, legal and cultural issues and the consequent
responsibilities relevant to the professional engineering practice.
7. Environment and Sustainability: Understand the impact of the professional
engineering solutions in societal and environmental contexts and demonstrate the
knowledge of and need for sustainable development.
8. Ethics: Apply ethical principles and commit to professional ethics and responsibilities
and norms of the relevant scientific and/or engineering practices.
9. Individual and team work: Function effectively as an individual and as a member or
leader in diverse teams and in multidisciplinary settings.
10. Communication: Communicate effectively on complex engineering activities with the
engineering community and with the society-at-large, such as being able to comprehend
and write effective reports and design documentation, make effective presentations and
give and receive clear instructions.
11. Project management and finance: Demonstrate knowledge and understanding of the
engineering and management principles and apply these to one’s own work as a member
and leader in a team to manage projects and in multidisciplinary environments.
12. Life-long learning: Recognize the need for and above have the preparation and ability
to engage in independent and life-long learning in the broadcast context of technological
changes.
PROGRAMME SPECIFIC OUTCOMES

1. Computer System Components:Apply the principles of computer system architecture and
software to design, develop and deploy computer subsystem.
2. Data Driven and Internet Applications: Apply the knowledge of data storage, analytics
and network architecture in designing Internet based applications.
Analog & Digital Electronics
[As per Choice Based Credit System (CBCS) scheme]
(Effective from the academic year 2018 - 2019)
SEMESTER – III
Subject Code 18CS33 IA Marks 40
Number of Lecture Hours/Week 3:0:0 Exam Marks 60
Total Number of Lecture Hours 50 Exam Hours 03
CREDITS – 03
Module – 1 Teaching
Hours
Photodiodes, Light Emitting Diodes and Optocouplers, BJT Biasing :Fixed bias ,Collector 8 Hours
to base Bias , voltage divider bias, Operational Amplifier Application Circuits:
Multivibrators using IC-555, Peak Detector, Schmitt trigger, Active Filters, Non-Linear
Amplifier, Relaxation Oscillator, Current-to-Voltage and Voltage-to-Current Converter ,
Regulated Power Supply Parameters, adjustable voltage regulator ,D to A and A to D
converter.
Text Book 1 :Part A:Chapter 2(Section 2.9,2.10,2.11), Chapter 4(Section 4.2
,4.3,4.4),Chapter 7 (section (7.2,7.3.1,7.4,7.6 to 7.11), Chapter 8 (section (8.1,8.5),
Chapter 9 RBT: L1, L2
Module – 2
Karnaugh maps: minimum forms of switching functions, two and three variable Karnaugh 8 Hours
maps, four variable karnaugh maps, determination of minimum expressions using essential
prime implicants, Quine-McClusky Method: determination of prime implicants, The prime
implicant chart, petricks method, simplification of incompletely specified functions,
simplification using map-entered variables
Text book 1:Part B: Chapter 5 ( Sections 5.1 to 5.4) Chapter 6(Sections 6.1 to 6.5)
RBT: L1, L2
Module – 3
Combinational circuit design and simulation using gates: Review of Combinational circuit 8 Hours
design, design of circuits with limited Gate Fan-in ,Gate delays and Timing diagrams,
Hazards in combinational Logic, simulation and testing of logic circuits
Multiplexers, Decoders and Programmable Logic Devices: Multiplexers, three state
buffers, decoders and encoders, Programmable Logic devices, Programmable Logic
Arrays, Programmable Array Logic.
Text book 1:Part B: Chapter 8,Chapter 9 (Sections 9.1 to 9.6) RBT: L1, L2
Module – 4
Introduction to VHDL: VHDL description of combinational circuits, VHDL Models for 08 8 Hours
multiplexers, VHDL Modules. Latches and Flip-Flops: Set Reset Latch, Gated Latches,
Edge-Triggered D Flip Flop 3,SR Flip Flop, J K Flip Flop, T Flip Flop, Flip Flop with
additional inputs, Asynchronous Sequential Circuits
Text book 1:Part B: Chapter 10(Sections 10.1 to 10.3),Chapter 11 (Sections 11.1 to
11.9) RBT: L1, L2
Module – 5
Registers and Counters: Registers and Register Transfers, Parallel Adder with accumulator, 8 Hours
shift registers, design of Binary counters, counters for other sequences, counter design using
SR and J K Flip Flops, sequential parity checker, state tables and graphs
Text book 1:Part B: Chapter 12(Sections 12.1 to 12.5),Chapter 13(Sections 13.1,13.3
RBT: L1, L2
Course outcomes: The students should be able to:

• Design and analyze application of analog circuits using photo devices, timer IC, power supply
and regulator IC and op-amp.
• Explain the basic principles of A/D and D/A conversion circuits and develop the same. •
Simplify digital circuits using Karnaugh Map, and Quine-McClusky Methods
• Explain Gates and flip flops and make us in designing different data processing circuits,
registers and counters and compare the types.
• Develop simple HDL programs
• Question paper pattern:
• The question paper will have ten questions.
• Each full Question consisting of 20 marks
• There will be 2 full questions (with a maximum of four sub questions) from each module.
• Each full question will have sub questions covering all the topics under a module.
• The students will have to answer 5 full questions, selecting one full question from each module
TextBooks:
1. Charles H Roth and Larry L Kinney, Analog and Digital Electronics, Cengage Learning,2019
Reference Books:
1. Anil K Maini, Varsha Agarwal, Electronic Devices and Circuits, Wiley, 2012.
2. Donald P Leach, Albert Paul Malvino & Goutam Saha, Digital Principles and Applications, 8th
Edition, Tata McGraw Hill, 2015.
3. M. Morris Mani, Digital Design, 4th Edition, Pearson Prentice Hall, 2008.
4. David A. Bell, Electronic Devices and Circuits, 5th Edition, Oxford University Press, 2008
COURSE OBJECTIVES:
Explain the use of photoelectronics devices, 555 timer IC, Regulator ICs and uA741
1 opamp IC
2 Make use of simplifying techniques in the design of combinational circuits.
3 Illustrate combinational and sequential digital circuits

4 Demonstrate the use of flip flops and apply the same for registers
5 Design and test counters, Analog-to-Digital and Digital-to-Analog conversion
COURSE OUTCOMES (COs):

SL. DESCRIPTION
NO After Completing thus course, the students will be able to:
Design and analyse application of analog circuits using photo devices, timer IC,
CO:1
power supply and regulator IC and op-amp.
CO:2 Simplify digital circuits using Karnaugh Map, and Quine-McCluskey Methods
CO:3 Designing different data processing circuits
CO:4 Develop simple HDL programs and Explain Gates and flip flops
CO:5 Explain and develop Registers & Counters

Table of contents
Chapter Topic Page No.
2.0 Introduction 1
2.1 Minimum forms of switching functions 7
2.2 Two and three variable Karnaugh maps 8
2.3 Four variable Karnaugh maps 10
2.4 Determination of minimum expressions using essential prime 13

implicants
2.5 Quine-McClusky Method 19
2.6 Determination of prime implicants 20
2.7 The prime implicant chart 20
2.8 Petricks method 23
2.9 Simplification of incompletely specified functions 24
2.10 Simplification using map-entered variables 25
References 29
Question Bank 30
University Questions 32
18CS33 Analog & Digital Electronics
MODULE 2
2.0: Introduction
Analog electronics is an electronics system where signal change continuously. Analog signal is a signal whose
amplitude can take any value between given limits. A continuous signal. An analog circuits operates on
continuous signals.
Digital electronics is a field of electronics involving the study of digital signals and the engineering of devices
that use or produce them. Digital signal is a signal whose amplitude can have only given discrete values between
defined limits. A signal that changes amplitude in discrete steps. A digital circuits operates on discrete signals.
Clock is a periodic, rectangular waveform used as a basic timing signal. Duty cycle for a periodic digital signal,
the ratio of high level time to the period or the ratio of low level time to the period. A table that shows all of the
input output possibilities of a logic circuit is called truth table.
Fig: Clock Signal
A digital circuit having one or more input signals but only one output signal is called a gate. Logic circuit is a
digital circuit, a switching circuit, or any kind of two-state circuit that duplicates mental processes.
The most basic gates are -the NOT gate (inverter), the OR gate and the AND gate.
NOT gate: A gate with only one input Truth table Logic diagram
and a complemented output.
OR gate: A gate with two or more inputs.

The output is high when any input is high.
AND gate: A gate with 2 or more inputs.

The output is high only when all inputs
are high.
Prepared by Anupama V & Dhananjaya B, Dept. of CSE, CEC 1

Realize following Boolean functions using basic gate.

i) Y=AB+CD ii) Y= (A+B)(C+D)
Any logic function/ logic circuit can be implemented using only one kind of gate then such gates are called
universal logic gates. NOR gate and NAND gate are called universal logic gates.
NOR gate: A gate with two or more inputs. Truth table Logic diagram
The output is low when any input is high.
Universality of NOR gate:
NOT from NOR OR from NOR AND from NOR
NAND gate: A gate with two or more inputs.

The output is low when all input is high.
Universality of NAND gate:
NOT from NAND AND from NAND OR from NAND
Other important gates are XOR and XNOR gates.

Exclusive-OR gate: A gate with two or more

inputs and output of is HIGH only when the
number of HIGH inputs is odd.
Equivalence/exclusive-NOR gate: A gate

with two or more inputs and output of is HIGH
only when the number of HIGH inputs is even.
Realize Y = AB + C using only NOR and NAND type of gate.
Active-low refers to the concept in which a signal must be low to cause something to happen or to indicate that
something has happened. Assert means to activate. If an input line has a bubble on it, you assert the input by
making it low. If there is no bubble, you assert the input by making it high.
Laws of Boolean algebra

Minimum Forms of Switching Functions
In a positive logic system, binary 0 stands for low voltage and binary 1 for high voltage. In a negative logic
system, binary 0 stands for high voltage and binary 1 for low voltage. Assert means to activate. If an input line
has a bubble on it, you assert the input by making it low. If there is no bubble, you assert the input by making it
high. Active-low refers to the concept in which a signal must be low to cause something to happen or activate
the circuit. Active-high refers to the concept in which a signal must be high to cause something to happen or to
activate the circuit.
Combinational Circuits are circuits made up of different types of logic gates. The output of the combinational
circuit depends on the values at the input at any given time. The circuits do not make use of any memory or
storage device. A literal is a variable or its complement.
A minterm of n variables is a product of n literals in which each variable appears exactly once in either true or
complemented form, but not both. A maxterm of n variables is a sum of n literals in which each variable appears
exactly once in either true or complemented form, but not both.
Example: Minterms and Maxterms for Three Variables
Minterm expansion or a standard sum of products (SOP): A Boolean equation that is the logical sum of
logical products. This type of equation applies to an AND-OR circuit.
Maxterm expansion or standard product of sums (POS): A Boolean equation that is the logical product of
logical sums. This type of equation applies to an OR-AND circuit.
Steps to get SOP:

1) Locate each output 1 in truth table
2) Write the respective minterm

3) Apply OR operation to the minterms

Example:
Steps to get POS:

1) Locate each output 0 in truth table
2) Write the respective maxterm
3) Apply AND operation to the maxterms
Example:
Conversion between SOP and POS:

1) Identifying complementary locations,
2) Changing mintenn to maxtenn or reverse, and finally
3) Changing summation by product or reverse
Example: Y = F(A, B, C) = Π M(O, 3, 6)

= Σm(l, 2, 4, 5, 7)
Example: Y = F(A, B, C) = Σm(3, 5, 6, 7)
= ΠM(O, 1, 2, 4)
Example: Combinational Circuit with Truth Table is given write SOP and POS expressions.

An Incompletely specified function is a Boolean function that only define output values for a subset of its inputs
- i.e. a Boolean function who’s output is a don't care for at least one of its input combinations. The X’s in the
truth table indicate that we don’t care whether the value of 0 or 1 is assigned to F.
Example: Truth Table with Don’t-Cares
In SOP we use m to denote the required minterms and d to denote the don’t-care minterms.
F(A,B,C) = Σ m(0, 3, 7) + Σ d(1, 6)
In POS we use M to denote the required maxterms and D to denote the don’t-care maxterms.
F(A,B,C) = Π M(2, 4, 5) · Π D(1, 6)
Write minterm and maxterm expansions for the following truth table.

2.1 Minimum Forms of Switching Functions

A minimum sum of products expression for a function is defined as a sum of product terms which
(i) has a minimum number of terms and
(ii) of all those expressions which have the same minimum number of terms, has a minimum number of literals.
The minimum sum of products corresponds directly to a minimum two-level gate circuit which
(i) has a minimum number of gates and
(ii) a minimum number of gate inputs.
The minimum sum of products is not necessarily unique; that is, a given function may have two different
minimum sum of products forms, each with the same number of terms and the same number of literals.
Given a minterm expansion, the minimum sum-of products form can often be obtained by the following
procedure:
(i) Combine terms by using 𝑋𝑌′+ 𝑋Y =(𝑌′+𝑌)=𝑋. Do this repeatedly to eliminate as many literals as possible.
A given term may be used more than once because X+X=X.
(ii) Eliminate redundant terms by using the theorems of Boolean Algebra.

A minimum product of sums expression for a function is defined as a product of sum terms which
(i) has a minimum number of terms, and
(ii) of all those expressions which have the same number of terms, has a minimum number of literals.
Unlike the maxterm expansion, the minimum product of sums form of a function is not necessarily unique. Given
a maxterm expansion, the minimum product of sums can often be obtained by a procedure similar to that used in
the minimum sum of products case, except that the theorem (𝑋+𝑌′)(𝑋+𝑌)= 𝑋 is used to combine terms.
Simplification of Boolean function reduces the gate count required to implement the circuit, the circuit works
faster and circuit require less power consumption.
The various Boolean expression simplification techniques are

1) Algebraic techniques
2) Karnaugh Map/K-Map Method
3) Quine McCluskey Method
4) Entered Variable Map/ MEV/EMV Method
Switching/Boolean functions can generally be simplified by using the algebraic techniques. The disadvantages
of algebraic procedure usage are
(i) The procedures are difficult to apply in a systematic way,
(ii) It is difficult to tell when we have arrived at a minimum solution.
Karnaugh map/K map is a method simplifying and manipulating switching functions. K map method is faster
and easier to apply than other simplification methods.
2.2 Two and Three Variable Karnaugh Maps
Karnaugh map of a function specifies the value of the function for every combination of values of the independent
variables.

Two Variable K-Map
The number of cells in 2 variable K-map is four (22), since the number of variables is two. The following figure
shows 2 variable K-map and location of minterms on a 2 variable K-map.
Example: Convert following truth table into K map.

Y = F(A, B) = Σ m (2, 3)
Three Variable K-Map
The number of cells in 3 variable K-map is eight (23), since the number of variables is 3. The following figure
OR

Y = F(A, B, C) = Σ m (2,6,7)

2.3 Four-Variable Karnaugh Maps
The number of cells in 4 variable K-map is sixteen (24), since the number of variables is 4. The following figure

Y = F(A, B, C, D) = Σ m(1,6,7)
Pairs, Quads, and Octets
Two adjacent 1s in the K-map is called a pair and it eliminate the variable that changes form.
Sample of pair

A quad is a group of four ls that are horizontally or vertically adjacent and a quad eliminates two variables and
their complements.

An octet is a group of 8 ls that are horizontally or vertically adjacent and an octet eliminates three variables and
their complements.
Overlapping of groups: We are allowed to use the same 1 more than once.
Rolling of Map: Groups may wrap around the table. The leftmost cell in a row may be grouped with the rightmost
cell and the top cell in a column may be grouped with the bottom cell. Roll and overlap to get largest group.

Eliminating redundant group: A groups of 1s or 0s whose all members are overlapped by other groups is called
redundant group. After encircling all possible group, eliminate any redundant group if any. We don’t consider
this group while writing the simplified equations from the K-map.
2.4 Determination of Minimum Expressions using Essential Prime Implicants
Any single 1 or any group of 1’s which can be combined together on a map of the function F represents a product
term which is called an implicant of F. Several implicants of F may be possible. A product term implicant is
called a prime implicant if it cannot be combined with another term to eliminate a variable.
The following procedure can then be used to obtain a minimum sum of products from a Karnaugh map:
1) Choose a minterm (a 1) which has not yet been covered.

2) Find all 1’s and X’s adjacent to that minterm. (Check the n adjacent squares on an n-variable map.)
3) If a single term covers the minterm and all of the adjacent 1’s and X’s, then that term is an essential prime
implicant, so select that term. (don’t-care terms are treated like 1’s in steps 2 and 3 but not in step 1.)
4) Repeat steps 1, 2, and 3 until all essential prime implicants have been chosen.
5) Find a minimum set of prime implicants which cover the remaining 1’s on the map. (If there is more than
one such set, choose a set with a minimum number of literals.)
The following figure shows the flowchart for determining a minimum sum of products using a Karnaugh map
with an example.

Solve S(A,B,C)=Σm(1,3,5) using K map and implement using basic gates.
Solve S= F(A,B,C)=Σ m(0, 1, 3, 5, 6, 7, 11, 12, 14) using Kmap and implement uisng basic, nand only and norly
gates.

OR
Circuit diagram for
Solve S=F(A,B,C,D)=Σ m(0,1, 2, 4, 5,6, 8,9,10,12,13) using Kmap and implement uisng basic, nand only and norly
gates.
Solve S= F(A,B,C,D)=Σm(7,9,10,11,12,13,14,15) using K map to get minimum SOP expression.

Solve S=F(A,B,C,D)=Σm(1,2,3,6,8,9,10,12,13,14) using K map to get minimum SOP expression.
Solve S=F(A,B,C,D)=Σm(7)+d(10,11,12,13,14,15) using K map to get minimum SOP expression.
Solve S =F(A,B,C,D)=Σm(2,3,5,7,10,12)+d(11,15) using K map to get minimum SOP expression.

Solve S=F(A,B,C,D)=Σm(6,7,9,10,13)+d(1,4,5,11) using K map to get minimum SOP expression.
Solve S= F(A,B,C,D)=Σm(0,1,2,4,5,12,14)+d(8,10) using K map to get minimum SOP expression.
Solve S= F(A,B,C,D)=Σm(0,1,4,8,9,10)+d(2,11) using K map to get minimum SOP expression.
Solve S=F(A,B,C,D)=ΠM(0,1,3,4,7) using K map to get minimum POS expression.

Solve S=F(A,B,C,D)=ΠM(0,6,7,8,12,13,14,15) using K map to get minimum POS expression and implement uisng
basic, nand only and norly gates.
Solve F(A,B,C,D)=ΠM(0,3,4,7,810,12,14).ΠD(2,6) using K map to get minimum POS expression and implement
uisng basic, nand only and norly gates.

Solve S=F(A,B,C,D)=Σm(6,7,9,10,13)+ Σd(1,4,5,11) using K map to get minimum POS expression.
S= F(A,B,C,D)=ΠM(0,2,3,8,12,14,15).ΠD(1,4,5,11)
Limitations of K map:
Complexity of K-map simplification process increases with the increase in the number of variables
K map is manual technique and simplification process heavily depends on the human ability.
2.5 Quine-McCluskey Method
The Quine-McCluskey method provides a systematic simplification procedure which can be readily programmed
for a digital computer. The Quine-McCluskey method reduces the minterm expansion (standard sum-of-products
form) of a function to obtain a minimum sum of products.
Quine-McClusky method involves preparation of two tables; one determines prime implicants and the other
selects essential prime implicants to get minimal expression. Prime implicants are expressions with least number
of literals that represents all the terms given in a truth table. Prime implicants are examined to get essential prime
implicants for a particular expression that avoids any type of duplication.

2.6 Determination of Prime Implicants
In order to apply the Quine-McCluskey method to determine a minimum sum-of-products expression for a
function, the function must be given as a sum of minterms.
Step 1 − Arrange the given min terms in an ascending order and make the groups based on the number of ones
present in their binary representations. So, there will be at most ‘n+1’ groups if there are ‘n’ Boolean variables
in a Boolean function or ‘n’ bits in the binary equivalent of min terms.
Step 2 − Compare the min terms present in successive groups. If there is a change in only one-bit position, then
take the pair of those two min terms. Place this symbol ‘_’ in the differed bit position and keep the remaining bits
as it is.
Step 3 − Repeat step2 with newly formed terms till we get all prime implicants.
Given a function F of n variables, a product term P is an implicant of F if for every combination of values of the
n variables for which P = 1, F is also equal to 1.
A prime implicant of a function F is a product term implicant which is no longer an implicant if any literal is
deleted from it.
2.7 The Prime Implicant Chart:

The second part of the Quine-McCluskey method employs a prime implicant chart to select a minimum set of prime
implicants.
Step 4 − Formulate the prime implicant table/chart. It consists of set of rows and columns. Prime implicants can
be placed in row wise and min terms can be placed in column wise. Place ‘1’ in the cells corresponding to the
min terms that are covered in each prime implicant.
Step 5 − Find the essential prime implicants by observing each column. If the min term is covered only by one
prime implicant, then it is essential prime implicant. Those essential prime implicants will be part of the simplified
Boolean function.
Step 6 − Reduce the prime implicant table by removing the row of each essential prime implicant and the columns
corresponding to the min terms that are covered in that essential prime implicant. Repeat step 5 for Reduced
prime implicant table. Stop this process when all min terms of given Boolean function are over.

Find the minimum SOP for the function f (a, b, c, d) =∑m(0, 1, 2, 5, 6, 7, 8, 9, 10, 14) using Quine McCluskey
method.
Determination of prime implicants:
Prime implicant chart:
Determine the essential prime implicants using QM method for the function f(A, B, C,
D)=∑M(0,1,2,3,10,12,11,13,14,15)

Prime implicant charts:
Find the minimum SOP for the function f (A, B, C) =∑m(2, 6, 7) using Quine McCluskey method.

Prime implicant charts:
2.8 Petrick’s Method
Petrick’s method is a technique for determining all minimum sum-of-products solutions from a prime implicant
chart. The example discussed above has two minimum solutions. As the number of variables increases, the
number of prime implicants and the complexity of the prime implicant chart may increase significantly. In such
cases, a large amount of trial and error may be required to find the minimum solution(s).
Petrick’s method is a more systematic way of finding all minimum solutions from a prime implicant chart than
the method used previously. Before applying Petrick’s method, all essential prime implicants and the minterms
they cover should be removed from the chart.
Steps in Petrick’s method:

1. Reduce the prime implicant chart by eliminating the essential prime implicant rows and the corresponding
columns.
2. Label the rows of the reduced prime implicant chart P1, P2, P3, etc.
3. Form a logic function P which is true when all columns are covered. P consists of a product of sum terms,
each sum term having the form (Pi0 + Pi1 + ・・・ ), where Pi0, Pi1 . . . represent the rows which cover
column i.
4. Reduce P to a minimum sum of products by multiplying out and applying X + XY = X.
5. Each term in the result represents a solution, that is, a set of rows which covers all of the minterms in the
table. To determine the minimum solutions, find those terms which contain a minimum number of
variables. Each of these terms represents a solution with a minimum number of prime implicants.

6. For each of the terms found in step 5, count the number of literals in each prime implicant and find the
total number of literals. Choose the term or terms which correspond to the minimum total number of
literals, and write out the corresponding sums of prime implicants.
Find the minimum SOP form for the function f(a,b,c)=∑m(0,1,2,5,6,7) using pettricks method.
The two solutions with the minimum number of prime implicants are obtained by choosing rows P1, P4, and P5
or rows P2, P3, and P6.
F = a′b′ + bc′ + ac
OR
F = a′c′ + b′c + ab
2.9 Simplification of Incompletely Specified Functions:
Given an incompletely specified function, the proper assignment of values to the don’t-care terms is necessary in
order to obtain a minimum form for the function. Modified Quine-McCluskey method is used to obtain a
minimum solution when don’t-care terms are present. In modified Quine-McCluskey method the don’t-care terms
are treated like required minterms when finding the prime implicants and don’t-care columns are omitted when
forming the prime implicant chart. If extra prime implicants are generated because of the don’t-cares, the extra
prime implicants are eliminated in the prime implicant chart.
Find the minimum SOP for the function F(A, B, C, D) = Σ m(2, 3, 7, 9, 11, 13) + Σ d(1, 10, 15) using Quine
McCluskey method.

Prime implicant chart:
(The don’t-care columns are omitted when forming the prime implicant chart)
2.10 Simplification Using Map Entered Variables:
A technique called Map Entered Variable (MEV) or Entered Variable Map (EVM) is used to increase the effective
size of k-map. It allows a smaller map to handle large number of variables. This is done by writing output in
terms of input. It allows a smaller map to handle large number of variables. This is done by writing output in
terms of input.
Rules for entering values in a Map Entered Variable K map are:

Rule No. MEV f Map Entry Comments
0 0 If function equals 0 for both values of MEV, enter 0 in
1 0
1 0 appropriate cell of MEV Map.
2 0 1 1 If function equals 1 for both values of MEV, enter 1.

1 1
0 0
3 MEV If function equals MEV, enter MEV
1 1
0 1 ̅̅̅̅̅̅
4 ̅̅̅̅̅̅
MEV If the function is compliment of MEV, enter MEV
1 0
0 X
5 X If function equals X, enter X
1 X
0 0
6 0 f=0 for MEV=0 and f=X for MEV=1,enter 0
1 X
0 X
7 0 f=X for MEV=0 and f=0 for MEV=1,enter 0
1 0
0 1
8 1 f=1 for MEV=0 and f=X for MEV=1,enter 1
1 X
0 X
9 1 f=X for MEV=0 and f=1 for MEV=1,enter 1
1 1
Minimization procedure for MEV/EVM:
1) Write all the variables (original and complimented forms are treated as two different variables) in the map as
0, leave 0’s, minterms and don’t cares as it is and obtain the SOP expression.
2) Select one variable and make all occurrences of that variable as 1, write minterms (1’s) as don’t cares, leave
0’s and don’t cares as it is. Now, obtain the SOP expression by multiply the obtained SOP expression with
the concerned variable.
3) Repeat step 2 for all the variables in the k-map.
4) SOP of MEV/EVM is obtained by ORing all the obtained SOP expressions.
Example – A 3-variable function can be defined as a function of 2-variables if the output is written in terms of
third variable.
Consider a function F(A,B,C) = (0,1,2,5)

Solve S=F(A,B,C,D)=Σm(2,3,6,7,9,10,13,14) using MEV to get minimum SOP expression.
Solve S=F(A,B,C,D)=Σm(2,3,4,5,13,15) + Πd(8, 9, 10, 11) using MEV to get minimum SOP expression.


References
Books:
1. Charles H Roth and Larry L Kinney, Analog and Digital Electronics, Cengage Learning, 2019
2. Donald P Leach, Albert Paul Malvino & Goutam Saha, Digital Principles and Applications, 8th Edition,
Tata McGraw Hill, 2015.
Website Links:
1. https://www.geeksforgeeks.org/introduction-of-k-map-karnaugh-map/
2. https://www.tutorialspoint.com/digital_circuits/digital_circuits_k_map_method.htm
3. https://www.tutorialspoint.com/digital_circuits/digital_circuits_quine_mccluskey_tabular_method.htm
4. https://www.geeksforgeeks.org/variable-entrant-map-vem-in-digital-logic/
5. https://www.allaboutcircuits.com/technical-articles/everything-about-the-quine-mccluskey-method/
Video Links:
1. https://youtu.be/5c16CswEG2A
2. https://youtu.be/lo3pTQ09QGI
3. https://youtu.be/PInDAFIQQNI
4. https://youtu.be/224iz7EAEXA
5. https://youtu.be/-A2aoqWckvs
6. https://youtu.be/CoMQLMqVFTI
7. https://youtu.be/1tYF6SyKLjs
8. https://youtu.be/LgS8HaHEcWM



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CANARA ENGINEERING COLLEGE

Benjanapadavu, Bantwal Taluk - 574219

PROGRAMME EDUCATIONAL OBJECTIVES

A. Graduates will work productively as computer science engineers exhibiting ethical

Engineering graduates in Computer Science and Engineering will be able to:

PROGRAMME SPECIFIC OUTCOMES

Course outcomes: The students should be able to:

2 Make use of simplifying techniques in the design of combinational circuits.

3 Illustrate combinational and sequential digital circuits

COURSE OUTCOMES (COs):

CO:5 Explain and develop Registers & Counters

Chapter Topic Page No.

2.1 Minimum forms of switching functions 7

2.2 Two and three variable Karnaugh maps 8

2.3 Four variable Karnaugh maps 10

2.4 Determination of minimum expressions using essential prime 13

2.5 Quine-McClusky Method 19

2.6 Determination of prime implicants 20

2.7 The prime implicant chart 20

2.8 Petricks method 23

2.9 Simplification of incompletely specified functions 24

2.10 Simplification using map-entered variables 25

Fig: Clock Signal

OR gate: A gate with two or more inputs.

AND gate: A gate with 2 or more inputs.

Prepared by Anupama V & Dhananjaya B, Dept. of CSE, CEC 1

Realize following Boolean functions using basic gate.

Universality of NOR gate:

NOT from NOR OR from NOR AND from NOR

NAND gate: A gate with two or more inputs.

Universality of NAND gate:

NOT from NAND AND from NAND OR from NAND

Other important gates are XOR and XNOR gates.

Prepared by Anupama V & Dhananjaya B, Dept. of CSE, CEC 2

Exclusive-OR gate: A gate with two or more

Equivalence/exclusive-NOR gate: A gate

Realize Y = AB + C using only NOR and NAND type of gate.

Laws of Boolean algebra

Prepared by Anupama V & Dhananjaya B, Dept. of CSE, CEC 3

Minimum Forms of Switching Functions

Example: Minterms and Maxterms for Three Variables

Steps to get SOP:

Prepared by Anupama V & Dhananjaya B, Dept. of CSE, CEC 4

3) Apply OR operation to the minterms

Steps to get POS:

Conversion between SOP and POS:

Example: Y = F(A, B, C) = Π M(O, 3, 6)

Prepared by Anupama V & Dhananjaya B, Dept. of CSE, CEC 5

Example: Truth Table with Don’t-Cares

Prepared by Anupama V & Dhananjaya B, Dept. of CSE, CEC 6

2.1 Minimum Forms of Switching Functions

Prepared by Anupama V & Dhananjaya B, Dept. of CSE, CEC 7

The various Boolean expression simplification techniques are

2.2 Two and Three Variable Karnaugh Maps

Prepared by Anupama V & Dhananjaya B, Dept. of CSE, CEC 8

Two Variable K-Map

Example: Convert following truth table into K map.

Three Variable K-Map

Example: Convert following truth table into K map.

Prepared by Anupama V & Dhananjaya B, Dept. of CSE, CEC 9