Professional Documents
Culture Documents
Opa 277
Opa 277
1s/div
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
OPA277, OPA2277, OPA4277
SBOS079B – MARCH 1999 – REVISED JUNE 2015 www.ti.com
Table of Contents
1 Features .................................................................. 1 7.3 Feature Description................................................. 16
2 Applications ........................................................... 1 7.4 Device Functional Modes........................................ 19
3 Description ............................................................. 1 8 Application and Implementation ........................ 20
4 Revision History..................................................... 2 8.1 Application Information............................................ 20
8.2 Typical Applications ............................................... 20
5 Pin Configuration and Functions ......................... 3
6 Specifications......................................................... 6 9 Power Supply Recommendations...................... 22
6.1 Absolute Maximum Ratings ...................................... 6 10 Layout................................................................... 22
6.2 ESD Ratings ............................................................ 6 10.1 Layout Guidelines ................................................. 22
6.3 Recommended Operating Conditions....................... 6 10.2 Layout Example .................................................... 23
6.4 Thermal Information for OPA277 .............................. 6 10.3 DFN Package........................................................ 24
6.5 Thermal Information for OPA2277 ............................ 6 11 Device and Documentation Support ................. 25
6.6 Thermal Information for OPA4277 ............................ 7 11.1 Device Support .................................................... 25
6.7 Electrical Characteristics for OPAx277P, OPAx277U, 11.2 Documentation Support ....................................... 25
and OPAx277xA ........................................................ 7 11.3 Community Resources.......................................... 26
6.8 Electrical Characteristics for OPAx277AIDRM ......... 9 11.4 Trademarks ........................................................... 26
6.9 Typical Characteristics ............................................ 12 11.5 Electrostatic Discharge Caution ............................ 26
7 Detailed Description ............................................ 16 11.6 Glossary ................................................................ 26
7.1 Overview ................................................................. 16 12 Mechanical, Packaging, and Orderable
7.2 Functional Block Diagram ....................................... 16 Information ........................................................... 26
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
• Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................. 1
Pin 1
+In 3 6 Output −In 2 Indicator 7 V+
V– 4 5 NC(1)
+In 3 6 Output
V− 4 5 NC
Thermal Pad
on Bottom
(Connect to V−)
+In A 3 6 −In B
V− 4 5 +In B
Thermal Pad
on Bottom
(Connect to V−)
Out A 1 14 Out D
–In A 2 13 –In D
A D
+In A 3 12 +In D
V+ 4 11 V–
+In B 5 10 +In C
B C
–In B 6 9 –In C
Out B 7 8 Out C
6 Specifications
6.1 Absolute Maximum Ratings
(1)
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
Supply voltage, Vs = (V+) – (V–) 36 V
Input voltage (V–) –0.7 (V+) +0.7 V
Output short-circuit (2) Continuous
Operating temperature –55 125 °C
Junction temperature 150 °C
Lead temperature 300 °C
Storage temperature, Tstg –55 125 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Short-circuit to ground, one amplifier per package.
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6 Submit Documentation Feedback Copyright © 1999–2015, Texas Instruments Incorporated
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
(1) VS = ±15 V
(2) Specifications are the same as OPA277P, U.
(2)
f = 10 kHz 8 See
(2)
in Current Noise Density, f = 1 kHz 0.2 See pA/√Hz
INPUT VOLTAGE RANGE
(2) (2)
VCM Common-Mode Voltage Range (V–)+2 (V+)–2 See See V
VCM = (V–) +2 V (2)
130 140 115 See
to (V+) –2 V
CMRR Common-Mode Rejection dB
TA = –40°C to
128 115
85°C
INPUT IMPEDANCE
(2)
Differential 100 || 3 See MΩ || pF
VCM = (V–) +2 V (2)
Common-Mode 250 || 3 See GΩ || pF
to (V+) –2 V
OPEN-LOOP GAIN
VO = (V–)+0.5 V
to (2)
140 See
(V+)–1.2 V,
RL = 10 kΩ
AOL Open-Loop Voltage Gain dB
VO = (V–)+1.5 V
to (2) (2)
126 134 See See
(V+)–1.5 V,
RL = 2 kΩ
VO = (V–)+1.5 V
to
(V+)–1.5 V, (2)
RL = 2 kΩ 126 See dB
TA = –40°C to
85°C
FREQUENCY RESPONSE
(2)
GBW Gain-Bandwidth Product 1 See MHz
(2)
SR Slew Rate 0.8 See V/µs
(2)
0.1% VS = ±15 V, 14 See
Settling Time G = 1, (2)
µs
0.01% 10-V Step 16 See
(2)
Overload Recovery Time VIN × G = VS 3 See µs
1 kHz, G = 1, (2)
THD+N Total Harmonic Distortion + Noise 0.002% See
VO = 3.5 Vrms
(1) VS = ±15 V
(2) Specifications are the same as OPA277P, U.
(2)
f = 10 kHz See
(2)
in Current Noise Density, f = 1 kHz See pA/√Hz
INPUT VOLTAGE RANGE
(2) (2)
VCM Common-Mode Voltage Range See See V
VCM = (V–) +2 V to (2)
115 See
CMRR Common-Mode Rejection (V+) –2 V dB
TA = –40°C to 85°C 115
INPUT IMPEDANCE
(2)
Differential See MΩ || pF
VCM = (V–) +2 V to (2)
Common-Mode See GΩ || pF
(V+) –2 V
OPEN-LOOP GAIN
VO = (V–)+0.5 V to
(2)
(V+)–1.2 V, See
RL = 10 kΩ
AOL Open-Loop Voltage Gain dB
VO = (V–)+1.5 V to
(2) (2)
(V+)–1.5 V, See See
RL = 2 kΩ
VO = (V–)+1.5 V to
(V+)–1.5 V, (2)
RL = 2 kΩ See dB
TA = –40°C to 85°C
FREQUENCY RESPONSE
(2)
GBW Gain-Bandwidth Product See MHz
(2)
SR Slew Rate See V/µs
(2)
0.1% VS = ±15 V, See
Settling Time G = 1, (2)
µs
0.01% 10-V Step See
(2)
Overload Recovery Time VIN × G = VS See µs
1 kHz, G = 1, (2)
THD+N Total Harmonic Distortion + Noise See
VO = 3.5 Vrms
OUTPUT
(2) (2)
RL = 10 kΩ See See
(2) (2)
TA = –40°C to +85°C See See
VO Voltage Output (2) (2)
V
RL = 2 kΩ See See
(2) (2)
TA = –40°C to +85°C See See
(2)
ISC Short-Circuit Current See mA
CLOAD Capacitive Load Drive
(2)
ZO Open-loop output impedance f = 1 MHz See Ω
140 140
G CL = 0
120 0 120
CL = 1500pF +PSR
100 –30 –PSR
100
Phase (°)
AOL (dB)
φ 80
60 –90 CMR
60
40 –120
40
20 –150
0 –180 20
–20 0
0.1 1 10 100 1k 10k 100k 1M 10M 0.1 1 10 100 1k 10k 100k 1M
Frequency (Hz) Frequency (Hz)
Figure 1. Open-Loop Gain and Phase vs Frequency Figure 2. Power Supply and Common-Mode Rejection vs
Frequency
INPUT NOISE AND CURRENT NOISE
SPECTRAL DENSITY vs FREQUENCY
1000
Noise signal is bandwidth limited to
lie between 0.1Hz and 10Hz.
Current Noise
Voltage Noise (nV/√Hz)
Current Noise (fA/√Hz)
50nV/div
100
10 Voltage Noise
1
0.1 1 10 100 1k 1s/div
Frequency (Hz)
Figure 3. Input Noise and Current Noise Spectral Density Figure 4. Input Noise Voltage vs Time
vs Frequency
140 1
VOUT = 3.5Vrms
120
Channel Separation (dB)
THD+Noise (%)
0.1
100
Dual and quad devices. G = 1, G = 10, RL = 2kΩ, 10kΩ
all channels. Quad measured
80 channel A to D or B to C —other
0.01
combinations yield similar or
improved rejection.
60 G = 1, RL = 2kΩ, 10kΩ
40 0.001
10 100 1k 10k 100k 1M 10 100 1k 10k 100k
Figure 5. Channel Separation vs Frequency Figure 6. Total Harmonic Distortion + Noise vs Frequency
2 5
0 0
– 50– 45– 40– 35– 30– 25– 20– 15– 10– 5 0 5 10 15 20 25 30 35 40 45 50 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
Offset Voltage (µV) Offset Voltage (µV/°C)
Figure 7. Offset Voltage Production Distribution Figure 8. Offset Voltage Drift Production Distribution
3 160
2 150
Offset Voltage Change (µV)
CMR
AOL, CMR, PSR (dB)
1 140 AOL
0 130
PSR
–1 120
–2 110
–3 100
0 15 30 45 60 75 90 105 120 –75 –50 –25 0 25 50 75 100 125
Time from Power Supply Turn-On (s) Temperature ( °C)
Figure 9. Warm-Up Offset Voltage Drift Figure 10. AOL, CMR, PSR vs Temperature
5 1000 100
4 950 90
900 80
2 850 70
±I Q
1 800 60
0 750 50
–ISC
–1 700 40
650 +ISC 30
–2
Curves represent typical 600 20
–3
production units.
550 10
–4
500 0
–5
–75 –50 –25 0 25 50 75 100 125 –75 –50 –25 0 25 50 75 100 125
Temperature (°C)
Temperature ( °C)
Figure 11. Input Bias Current vs Temperature Figure 12. Quiescent Current and Short-Circuit Current vs
Temperature
∆IB (nA)
0.0 0.0
VCM = 0V
–0.5 –0.5
VS = ±15V
–1.0 –1.0
–1.5 –1.5
–2.0 –2.0
0 5 10 15 20 25 30 35 40 –15 –10 –5 0 5 10 15
Supply Voltage (V) Common-Mode Voltage (V)
Figure 13. Change in Input Bias Current vs Figure 14. Change in Input Bias Current vs
Power Supply Voltage Common-Mode Voltage
1000 100
10V step
per amplifier
CL = 1500pF
900
Quiescent Current (µA)
50
Settling Time (µs)
0.01%
800
0.1%
700
20
600
500 10
0 ±5 ±10 ±15 ±20 ±1 ±10 ±100
Supply Voltage (V) Gain (V/V)
Figure 15. Quiescent Current vs Supply Voltage Figure 16. Settling Time vs Closed-Loop Gain
30 (V+)
VS = ±15V (V+) – 1
25 –55°C
(V+) – 2
Output Voltage Swing (V)
Output Voltage (V PP)
(V+) – 3
20 125°C
(V+) – 4
(V+) – 5 25°C
15
(V–) + 5
125°C 25°C
10 (V–) + 4
VS = ±5V (V–) + 3
5 (V–) + 2
–55°C
(V–) + 1
0 (V–)
1k 10k 100k 1M 0 ±5 ±10 ±15 ±20 ±25 ±30
Frequency (Hz) Output Current (mA)
Figure 17. Maximum Output Voltage vs Frequency Figure 18. Output Voltage Swing vs Output Current
40
Overshoot (%)
Gain = +1
2V/div
30
20
Gain = ±10
10
0
10 100 1k 10k 100k
Load Capacitance (pF) 10µs/div
Figure 19. Small-Signal Overshoot vs Load Capacitance Figure 20. Large-Signal Step Response
G = 1, CL = 1500 pF, VS = ±15 V
20mV/div
20mV/div
1µs/div 1µs/div
Figure 21. Small-Signal Step Response Figure 22. Small-Signal Step Response
G= +1, CL = 0, VS = ±15 V G= 1, CL = 1500 pF, VS = ±15 V
100
70
50
30
Impedance (:)
20
10
7
5
3
2
1
1k 10k 100k 1M
Frequency (Hz)
7 Detailed Description
7.1 Overview
The OPAx277 series precision operational amplifiers replace the industry standard OP-177. They offer improved
noise, wider output voltage swing, and are twice as fast with half the quiescent current. Features include ultralow
offset voltage and drift, low bias current, high common-mode rejection, and high power supply rejection. Single,
dual, and quad versions have identical specifications, for maximum design flexibility.
Input Offset
Adjust
(OPA277 only)
+IN +
Output
-IN ±
Input Offset
Adjust Compensation
(OPA277 only)
V+
Trim Range: Exceeds
Offset Voltage Specification
0.1µF
20kΩ
7
2 1
8
OPA277 6
3
V–
1 k ±
R1 R1
Op Amp OPA277
RB = R2 || R1
No bias current
cancellation resistor
(see text)
(a) (b)
Conventional op amp with external bias OPA277 with no external bias current
current cancellation resistor. cancellation resistor.
80
EMIRR IN+ (db)
60
40
20
0
10 100 1k 10k
Frequency (MHz)
If available, any dual and quad operational amplifier device versions have nearly similar EMIRR IN+
performance. The OPA277 unity-gain bandwidth is 1 MHz. EMIRR performance below this frequency denotes
interfering signals that fall within the operational amplifier bandwidth.
+VS
±
50
Low-Pass Filter
+
RF source
-VS
DC Bias: 0 V Sample /
Modulation: None (CW) Averaging Digital Multimeter
Frequency Sweep: 201 pt. Log Not shown: 0.1 µF and 10 µF
supply decoupling
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
2.25 k
1 nF
2.25 k
1.13 k
Input ±
Output
4 nF +
20
Gain (db)
-20
-40
-60
100 1k 10k 100k 1M
Frequency (Hz)
V+
1/2 R2
VOUT = (V1 – V2)(1 + )
OPA2277 R1
R2
V–
R–∆R R+∆R V+
V2 R1
V1 Load
Cell
1/2
R+∆R R–∆R
OPA2277
V–
R2 R1
IREG ∼ 1mA
5V
12
V+ VLIN 1
1/2 13 IR1 14
+
IR2 11
OPA2277 VIN 10
Type J VREG
V+
RF 4
10kΩ RG
RG 9
R XTR105 B
RF 1250Ω
412Ω
10kΩ
3 E
RG
8
IO
–
1/2 2 VIN 7
1kΩ
OPA2277 IRET
IO = 4mA + (V IN – VIN) 40
+ –
50Ω V– 6 RG
25Ω
RCM = 1250Ω
2RF
(G = 1 + = 50)
R
0.01µF
Figure 32. Thermocouple Low-Offset, Low-Drift Loop Measurement With Diode Cold Junction
Compensation
CAUTION
Supply voltages larger than 36 V can permanently damage the device; see the
Absolute Maximum Ratings.
Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high-
impedance power supplies. For more detailed information on bypass capacitor placement, refer to the Layout
Guidelines.
10 Layout
VIN +
RG VOUT
RF
(Schematic Representation)
Place components
Run the input traces close to device and to
as far away from each other to reduce
the supply lines parasitic errors VS+
as possible RF
NOTE
These files require that either the TINA software (from DesignSoft™) or TINA-TI software
be installed. Download the free TINA-TI software from the TINA-TI folder.
11.4 Trademarks
TINA-TI, E2E are trademarks of Texas Instruments.
TINA, DesignSoft are trademarks of DesignSoft, Inc.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
www.ti.com 7-Oct-2021
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)
OPA2277AIDRMT ACTIVE VSON DRM 8 250 RoHS & Green NIPDAU Level-1-260C-UNLIM BHZ
OPA2277AIDRMTG4 ACTIVE VSON DRM 8 250 RoHS & Green NIPDAU Level-1-260C-UNLIM BHZ
OPA2277P ACTIVE PDIP P 8 50 RoHS & Green Call TI N / A for Pkg Type OPA2277P
OPA2277PA ACTIVE PDIP P 8 50 RoHS & Green Call TI N / A for Pkg Type OPA2277P
A
OPA2277PAG4 ACTIVE PDIP P 8 50 RoHS & Green Call TI N / A for Pkg Type OPA2277P
A
OPA2277U ACTIVE SOIC D 8 75 RoHS & Green Call TI Level-3-260C-168 HR OPA
2277U
OPA2277U/2K5 ACTIVE SOIC D 8 2500 RoHS & Green Call TI Level-3-260C-168 HR -40 to 85 OPA
2277U
OPA2277U/2K5G4 ACTIVE SOIC D 8 2500 RoHS & Green Call TI Level-3-260C-168 HR -40 to 85 OPA
2277U
OPA2277UA ACTIVE SOIC D 8 75 RoHS & Green Call TI Level-3-260C-168 HR -40 to 85 OPA
2277U
A
OPA2277UA/2K5 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 OPA
2277U
A
OPA2277UA/2K5E4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 OPA
2277U
A
OPA2277UAE4 ACTIVE SOIC D 8 75 RoHS & Green Call TI Level-3-260C-168 HR -40 to 85 OPA
2277U
A
OPA2277UAG4 ACTIVE SOIC D 8 75 RoHS & Green Call TI Level-3-260C-168 HR -40 to 85 OPA
2277U
A
OPA2277UG4 ACTIVE SOIC D 8 75 RoHS & Green Call TI Level-3-260C-168 HR -40 to 85 OPA
2277U
OPA277AIDRMR ACTIVE VSON DRM 8 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM NSS
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 7-Oct-2021
Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)
OPA277AIDRMT ACTIVE VSON DRM 8 250 RoHS & Green NIPDAU Level-1-260C-UNLIM NSS
OPA277P ACTIVE PDIP P 8 50 RoHS & Green Call TI N / A for Pkg Type OPA277P
OPA277PA ACTIVE PDIP P 8 50 RoHS & Green Call TI N / A for Pkg Type OPA277P
A
OPA277PAG4 ACTIVE PDIP P 8 50 RoHS & Green Call TI N / A for Pkg Type OPA277P
A
OPA277U ACTIVE SOIC D 8 75 RoHS & Green Call TI Level-3-260C-168 HR OPA
277U
OPA277U/2K5 ACTIVE SOIC D 8 2500 RoHS & Green Call TI Level-3-260C-168 HR OPA
277U
OPA277U/2K5G4 ACTIVE SOIC D 8 2500 RoHS & Green Call TI Level-3-260C-168 HR OPA
277U
OPA277UA ACTIVE SOIC D 8 75 RoHS & Green Call TI Level-3-260C-168 HR -40 to 85 OPA
277U
A
OPA277UA/2K5 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 OPA
277U
A
OPA277UA/2K5E4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 OPA
277U
A
OPA277UAE4 ACTIVE SOIC D 8 75 RoHS & Green Call TI Level-3-260C-168 HR -40 to 85 OPA
277U
A
OPA277UAG4 ACTIVE SOIC D 8 75 RoHS & Green Call TI Level-3-260C-168 HR -40 to 85 OPA
277U
A
OPA277UG4 ACTIVE SOIC D 8 75 RoHS & Green Call TI Level-3-260C-168 HR OPA
277U
OPA4277PA ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type OPA4277PA
OPA4277UA ACTIVE SOIC D 14 50 RoHS & Green NIPDAU-DCC Level-3-260C-168 HR -40 to 85 OPA4277UA
OPA4277UA/2K5 ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU-DCC Level-3-260C-168 HR -40 to 85 OPA4277UA
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com 7-Oct-2021
Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)
OPA4277UA/2K5E4 ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU-DCC Level-3-260C-168 HR -40 to 85 OPA4277UA
OPA4277UAE4 ACTIVE SOIC D 14 50 RoHS & Green NIPDAU-DCC Level-3-260C-168 HR -40 to 85 OPA4277UA
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 3
PACKAGE OPTION ADDENDUM
www.ti.com 7-Oct-2021
Addendum-Page 4
PACKAGE MATERIALS INFORMATION
www.ti.com 3-Jun-2022
B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers
Sprocket Holes
Q1 Q2 Q1 Q2
Pocket Quadrants
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 3-Jun-2022
Width (mm)
H
W
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 3-Jun-2022
TUBE
T - Tube
height L - Tube length
W - Tube
width
Pack Materials-Page 3
PACKAGE OUTLINE
D0008A SCALE 2.800
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A PIN 1 ID AREA
6X .050
[1.27]
8
1
.189-.197 2X
[4.81-5.00] .150
NOTE 3 [3.81]
4X (0 -15 )
4
5
8X .012-.020
B .150-.157 [0.31-0.51]
.069 MAX
[3.81-3.98] .010 [0.25] C A B [1.75]
NOTE 4
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
0 -8 [0.11-0.25]
.016-.050
[0.41-1.27] DETAIL A
(.041) TYPICAL
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
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EXAMPLE BOARD LAYOUT
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM SEE
DETAILS
1
8
8X (.024)
[0.6] SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
EXPOSED
METAL EXPOSED
METAL
.0028 MAX .0028 MIN
[0.07] [0.07]
ALL AROUND ALL AROUND
4214825/C 02/2019
NOTES: (continued)
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EXAMPLE STENCIL DESIGN
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55] SYMM
1
8
8X (.024)
[0.6] SYMM
(R.002 ) TYP
5 [0.05]
4
6X (.050 )
[1.27]
(.213)
[5.4]
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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