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OPA454 High-Voltage (100-V), High-Current (50-Ma) Operational Amplifiers, G 1 Stable
OPA454 High-Voltage (100-V), High-Current (50-Ma) Operational Amplifiers, G 1 Stable
OPA454
SBOS391B – DECEMBER 2007 – REVISED MARCH 2016
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
OPA454
SBOS391B – DECEMBER 2007 – REVISED MARCH 2016 www.ti.com
Table of Contents
1 Features .................................................................. 1 10 Application and Implementation........................ 22
2 Applications ........................................................... 1 10.1 Applications Information........................................ 22
3 Description ............................................................. 1 10.2 Typical Application ................................................ 24
4 Revision History..................................................... 2 10.3 System Examples ................................................. 27
5 Device Comparison Table..................................... 3 11 Power Supply Recommendations ..................... 33
6 Pin Configuration and Functions ......................... 3 12 Layout................................................................... 33
12.1 Layout Guidelines ................................................. 33
7 Specifications......................................................... 4
12.2 Layout Example .................................................... 35
7.1 Absolute Maximum Ratings ...................................... 4
12.3 Thermal Protection................................................ 36
7.2 ESD Ratings ............................................................ 4
12.4 Power Dissipation ................................................. 36
7.3 Recommended Operating Conditions....................... 4
12.5 Heatsinking ........................................................... 37
7.4 Thermal Information .................................................. 4
7.5 Electrical Characteristics: VS = ±50 V....................... 5 13 Device and Documentation Support ................. 38
7.6 Typical Characteristics .............................................. 7 13.1 Device Support .................................................... 38
13.2 Documentation Support ....................................... 38
8 Parameter Measurement Information ................ 16
13.3 Community Resources.......................................... 39
9 Detailed Description ............................................ 17
13.4 Trademarks ........................................................... 39
9.1 Overview ................................................................. 17
13.5 Electrostatic Discharge Caution ............................ 39
9.2 Functional Block Diagram ....................................... 17
13.6 Glossary ................................................................ 39
9.3 Feature Description................................................. 18
9.4 Device Functional Modes........................................ 21 14 Mechanical, Packaging, and Orderable
Information ........................................................... 39
4 Revision History
Changes from Revision A (December 2008) to Revision B Page
• Added Pin Functions table, ESD Ratings table, Recommended Operating Conditions table, Thermal Information
table, Feature Description section, Device Functional Modes section, Application and Implementation section,
Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 1
• Changed OPA454 Related Products table to Device Comparison table ............................................................................... 3
• Deleted Ordering Information table ........................................................................................................................................ 3
• Corrected symbol error in Absolute Maximum Ratings table; changed operating temperature specification from TJ to
TA ........................................................................................................................................................................................... 4
• Changed Figure 29 title from THD+N vs Temperature to THD+N vs Frequency ................................................................ 10
• Changed Figure 30 title from THD+N vs Temperature to THD+N vs Frequency ................................................................ 10
PRODUCT DESCRIPTION
(1)
OPA445 80 V, 15 mA
OPA452 80 V, 50 mA
OPA547 60 V, 750 mA
OPA548 60 V, 3 A
OPA549 60 V, 9 A
OPA551 60 V, 200 mA
OPA567 5 V, 2 A
OPA569 5 V, 2.4 A
(1) The OPA445 is pin-compatible with the OPA454, except in applications using the offset trim, and NC
pins other than open.
DDA PACKAGE
8-Pin SO PowerPAD
Top View
V- 4 5 Status Flag
(1) PowerPAD is internally connected to V–. Soldering the PowerPAD to the printed-circuit board (PCB) is always
required, even with applications that have low power dissipation.
Pin Functions
PIN
I/O DESCRIPTION
NAME NO.
E/D (Enable/Disable) 8 I Enable/Disable
E/D Com 1 I Enable/Disable common
–IN 2 I Inverting input
+IN 3 I Noninverting input
OUT 6 O Output
The Status Flag is an open-drain active-low output referenced to E/D Com. This
Status Flag 5 O
pin goes active for either an overcurrent or overtemperature condition.
V– 4 — Negative (lowest) power supply
V+ 7 — Positive (highest) power supply
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
Supply voltage, VS = (V+) – (V–) 120 V
(2)
Voltage Signal input pin (V–) – 0.3 (V+) + 0.3 V
E/D to E/D Com 5.5 V
Signal input pin (2) ±10 mA
Current
Output short circuit (3) Continuous
Operating, TA –55 125 °C
Temperature Junction, TJ 150 °C
Storage, Tstg –55 125 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Input terminals are diode-clamped to the power-supply rails. Input signals that can swing more than 0.3 V beyond the supply rails must
be current-limited to 10 mA or less.
(3) Short-circuit to ground.
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
(1) TP is the temperature of the leadframe die pad (exposed thermal pad) of the PowerPAD package.
(2) Typical range is (V–) + 1.5 V to (V+) – 1.5 V.
(3) Measured using low-frequency (<10 Hz) ±49-V square wave. See typical characteristic curve, Current Limit vs Temperature (Figure 23).
(4) See Typical Characteristics curves.
(5) See typical characteristic curve, Maximum Output Voltage vs Frequency (Figure 11).
(6) See the Feature Description section, Settling Time.
(7) Supplies reduced to allow closer swing to rails due to test equipment limitations. See typical characteristic curves Total Harmonic
Distortion + Noise vs Frequency (Figure 29 and Figure 30) for additional power levels.
(8) See typical characteristic curve, Output Voltage Swing vs Output Current (Figure 10).
(9) Measured using Figure 56.
(10) See Typical Characteristics curves for current limit behavior.
(11) See typical characteristic curve, IENABLE vs VENABLE (Figure 45).
(12) High enables the outputs.
180 70
CL = 30pF VCM = -45V
160
Open-Loop Gain, Phase (dB, °)
VCM = 0V
65
140 VCM = +45V
120
Figure 1. Open-Loop Gain and Phase vs Frequency Figure 2. Phase Margin vs Temperature
3.8 1M
3.2 10k
VCM = 0V
3.0
1k
2.8
VCM = 45V
2.6 100
VCM = -45V
2.4
10
2.2
CL = 30pF, 100pF, and 200pF
2.0 1
-75 -50 -25 0 25 50 75 100 125 1 10 100 1k 10k 100k 1M 10M
Exposed Thermal Pad Temperature (°C) Frequency (Hz)
130 130
VS = ±50V
120
120
110
110 RLOAD = 48kW
AOL (dB)
AOL (dB)
80
VCM = -45V 60
100kHz, CMRR
60
40
40 1.3MHz, CMRR
VCM = +45V
20 20 VCM = +45V
VCM = -45V
0 0
1 10 100 1k 10k 100k 1M 10M -75 -50 -25 0 25 50 75 100 125
Frequency (Hz) Exposed Thermal Pad Temperature (°C)
Figure 7. Common-Mode Rejection Ratio vs Frequency Figure 8. Power-Supply and Common-Mode Rejection Ratio
vs Temperature
140 50
-55°C
120 49
100 48
PSRR (dB)
VOUT (V)
80 47
+125°C +85°C +25°C
60 -47
40 -48
20 -49
-55°C
0 -50
1 10 100 1k 10k 100k 1M 0 10 20 30 40 50
Frequency (Hz) IOUT (mA)
Figure 9. Power-Supply Rejection Ratio vs Frequency Figure 10. Output Voltage Swing vs Output Current
(Measured When Status Flag Transitions From
Low To High)
120 Average = 111mV
VOUT = ±49V
Standard Deviation = 142mV
100 RL = 4.8kW
IOUT = ±10mA
Output Voltage (VPP)
80
Population
60
40
20
0
0 50 100 150 200 250 300 -4000 -3000 -2000 -1000 0 1000 2000 3000 4000
Frequency (kHz) Offset Voltage (mV)
Figure 11. Maximum Output Voltage vs Frequency Figure 12. DDA Package Offset Voltage
Production Distribution
Population
Population
-0.8
-0.4
-2.0
0.8
1.2
1.6
2.0
-1.6
-1.2
0.4
0 1 2 3 4 5 6 7 8 9 10
Offset Voltage Drift (mV/°C) Output Voltage Shift (mV/°C)
Figure 13. Offset Voltage Drift Production Distribution Figure 14. Solder-Attached, VOS TC Shift
Average = 48mV/°C 200
Standard
150
Deviation = 28mV/°C
Offset Voltage (mV) 100
VS = ±50V
Population
50
PowerPAD Attached
0 9in ´ 12in 0.062
Layer Metal PCB FR10
-50
-100
-150
-200
-400
-200
-1000
400
600
800
1000
-800
-600
200
100s/div
Figure 15. DDA Package, Solder-Attached, VOS Shift Figure 16. Offset Voltage Warmup
(60 Devices)
3.25
3.20
3.15
Population
IQ (mA)
3.10
3.05
3.00
2.95
2.90
3.1
3.3
3.5
3.2
2.5
2.8
3.4
3.8
3.9
3.0
3.6
3.7
2.6
2.7
2.9
Figure 17. Quiescent Current Production Distribution Figure 18. Quiescent Current vs Supply Voltage
3.0
2.8 140
2.6
2.4 120
2.2
2.0 100
-75 -50 -25 0 25 50 75 100 125 -75 -50 -25 0 25 50 75 100 125
Exposed Thermal Pad Temperature (°C) Exposed Thermal Pad Temperature (°C)
Figure 19. Quiescent Current vs Temperature Figure 20. Shutdown Current vs Temperature
100 20
15
10
10
5
IB (pA)
IB (pA)
-5
1 Common-Mode Voltage Range
-10
-15
0.1 -20
-75 -50 -25 0 25 50 75 100 125 -50 -40 -30 -20 -10 0 10 20 30 40 50
Exposed Thermal Pad Temperature (°C) VCM (V)
Figure 21. Input Bias Current vs Temperature Figure 22. Input Bias Current vs Common-Mode Voltage
200 8
7
180 RP = 20kW, IP = 5mA
6
Sourcing
5
VFLAG to V-
ILIMIT (mA)
160
4
RP = 50kW, IP = 2mA
140 3
RP = 100kW, IP = 100mA
2
120 RP = 200kW, IP = 50mA
1
Sinking
100 0
-75 -50 -25 0 25 50 75 100 125 -75 -50 -25 0 25 50 75 100 125
Exposed Thermal Pad Temperature (°C) Exposed Thermal Pad Temperature (°C)
See Figure 72 in the System Examples section.
Figure 23. Current Limit vs Temperature Figure 24. Status Flag Voltage vs Temperature
(E/D Com Connected To V–)
1.5 14
13
1.0 12
Figure 25. Maximum Power Dissipation vs Figure 26. Slew Rate vs Temperature
Temperature With Minimum Attach Area
1000
Voltage Noise (nV/ÖHz)
100
5mV/div
10
1
10 100 1k 10k 100k 20s/div
Frequency (Hz)
Figure 27. Input Voltage Noise Spectral Density Figure 28. 0.01-Hz to 10-Hz Input Voltage Noise
0.040 0.0030
G = +10 G = +1
RI = 4.75kW RI = 4.75kW
0.035 VPK = 38.6V 0.0025 VPK = 38.6V VS = +41.6, -40.6
0.030 0.0020
THD + N (%)
THD + N (%)
0.025 0.0015
VS = +40.6,
VS = -55, +55 -39.6
0.020 0.0010
VS = -49, +50
0.015 0.0005
0.010 0
10 100 1k 10k 100k 10 100 1k 10k 100k
Frequency (Hz) Frequency (Hz)
Figure 29. Total Harmonic Distortion + Noise vs Frequency Figure 30. Total Harmonic Distortion + Noise vs Frequency
G = +1 G = +1
TC = +60°C TC = +105°C
CLOAD = 50pF CLOAD = 50pF
500mV/div
500mV/div
VCM = +30V VCM = +30V
RF = 10kW RF = 10kW
VOUT VOUT
Figure 31. Large-Signal Step Response Figure 32. Large-Signal Step Response
TC = +125°C
TC = +25°C
VOUT (400mV/div)
VIN (200mV/div)
50mV TC = -55°C
G = +2
TC = +100°C G = +1
CLOAD = 100pF CLOAD = 100pF
VIN
VCM = +40V VCM = 0V
VOUT RF = 10kW RF = 0W
Figure 33. Large-Signal Step Response Figure 34. Small-Signal Step Response
2.0 180
G = +1 RF = 0W
1.5 160 RF = 10kW
G = +2 TC = -55°C
140
1.0 TC = +25°C
120
Peaking (%)
0.5 TC = +85°C
VOUT (V)
100
TC = +125°C
0
80
-0.5 60
-1.0 40
RF = 10kW
-1.5 20
CLOAD = 100pF, 125°C
VCM = +40V 0
-2.0 0 100 200 300 400 500
1ms/div CLOAD (pF)
See Application section, Unity-Gain Noninverting Configuration.
G = +1 VCM = 0 V
Gain (dB)
15
TC = +125°C 2
10
0
5
-2
RF = 10kW, CF = 50pF
0 -4
RF = 0W
CL = 50pF
-5 -6
0 100 200 300 400 500 10k 100k 1M 10M
CLOAD (pF) Frequency (Hz)
G = +2 RF = 10 kΩ VCM = 0 V See Application section Unity-Gain Noninverting Configuration.
4 5 0.02
Gain (dB)
VIN (V)
CL = 50pF V2 (Noninverting)
2 0 0
-5 -0.02
0
-10 -0.04
-2 CF = 0pF VIN
CF = 2.5pF -15 -0.06
-4
CF = 5pF
-20 -0.08
-6 Time (1ms/div)
10k 100k 1M 10M
See the Settling Time section. The grid for voltage at V1 and V2 is
Frequency (Hz) scaled 20 mV or 0.1% per division.
See Application section Unity-Gain Noninverting Configuration. 20-V Step Gain = 1 RF = 10 kΩ
Figure 39. Gain of +2 vs Frequency Figure 40. Settling Time, Positive Step
20 0.08
15 0.06
VIN
Voltage at V1 and V2 (V)
10 0.04
20V/div OUT
5 0.02
VIN (V)
0 0
V2 (Noninverting) 50V/div Status Flag
-5 -0.02
-10 -0.04
V1 (Inverting) Enable
-15 -0.06
5V/div
-20 -0.08
Time (1ms/div) Time (1ms/div)
See the Settling Time section. The grid for voltage at V1 and V2 is
scaled 20 mV or 0.1% per division.
20-V Step Gain = 1 RF = 10 kΩ
Figure 41. Settling Time, Negative Step Figure 42. Enable Response Time
20V/div
OUT
20V/div OUT
5V/div
0.95
0
-40°C Threshold (V) 0.90
IENABLE (mA)
-10 0.85
+25°C
+85°C 0.80
-20
0.75
-30 0.70
0 1 2 3 4 5 -75 -50 -25 0 25 50 75 100 125
VENABLE (V) Temperature (°C)
40 100 40 50
IOUT
VFLAG (V)
VFLAG (V)
IOUT (mA)
IOUT (mA)
30 50 30 0
20 0 20 -50
IOUT
10 -50 10 -100
0 -100 0 -150
RP = 100kW RP = 100kW
-10 -150 -10 -200
10ms/div 10ms/div
The OPA454 was connected to sufficient heatsinking to prevent The OPA454 was connected to sufficient heatsinking to prevent
thermal shutdown. thermal shutdown.
TP = 125°C TP = 25°C
Figure 47. ILIMIT Showing Flag Delay () Figure 48. ILIMIT Showing Flag Delay
40 50 2ms Pulse
IOUT (mA)
Relay
VOUT (V)
30 0
0.8
20 -50 0.6
10 -100 0.4
0.2
0 -150
RP = 100kW 0
-10 -200
10ms/div -0.2
10ms/div
The OPA454 was connected to sufficient heatsinking to prevent
thermal shutdown.
TP = –55°C
Figure 49. ILIMIT Showing Flag Delay Figure 50. Apply Load (25-mA Sink Response)
0.2 0.2
0 0
-0.2 -0.2
-0.4 -0.4
VOUT (V)
VOUT (V)
-0.6 -0.6
-0.8 -0.8
0.988VPP +50V 0.988VPP +50V
-1.0 0.01Hz -1.0 0.01Hz
+125°C +125°C
- -
OPA454 OPA454
-1.2 +85°C + 2Hz -1.2 + 2Hz +85°C
2ms Pulse 2ms Pulse
Figure 51. Remove Load (25-mA Sink Response) Figure 52. Apply Load (25-mA Source Response)
1.6
+125°C RL = 1.8kW V+
1.4 +85°C
+25°C VOUT
1.2
-55°C
1.0 0.988VPP +50V
0.01Hz
- Flag
VOUT (V)
20V/div
OPA454
0.8 + 2Hz
2ms Pulse 0
0.6 -50V Mercury
Wetted
Relay
0.4
Delay in V- is due to
0.2 V-
test equipment.
0 Power supplies may be
applied in any sequence.
-0.2
10ms/div 20ms/div
Figure 53. Remove Load (25-mA Source Response) Figure 54. Power On
VOUT
Flag
20V/div
0
V-
20ms/div
VOUT
RL
50kW
100VPP
E/D Com
10kHz
-50V
9 Detailed Description
9.1 Overview
The OPA454 is a low-cost operational amplifier (op amp) with high voltage (100 V) and a relatively high current
drive of 50 mA. This device is unity-gain stable and features a gain-bandwidth product of 2.5 MHz. The high-
voltage OPA454 offers excellent accuracy, wide output swing, and has no phase inversion problems that are
typically found in similar op amps. The device can be used in virtually any ±5-V to ±50-V op amp configuration,
and is especially useful for supply voltages greater than 36 V.
V+
V IN
Biasing
V+IN Current Limiting
Enable/Disable
Status
Voltage (V)
49.0 VOUT
-48.0
RS = 50kW
48.5 -48.5
-49.0
48.0
VIN
-49.5
VOUT f = 1kHz
47.5
RS = 0W -50.0
V-
47.0 -50.5
0 20 40 60 80 100 0 20 40 60 80 100
Time (ms) Time (ms)
Figure 57. Output Voltage with Input Voltage Figure 58. Output Voltage with Input Voltage
up to V+ Down to V–
-46.0
TA = +25°C
-46.5
-47.0
-47.5
Voltage (V)
VOUT
-48.0
RS = 50kW
-48.5
-49.0
VIN VOUT
-49.5 R S = 0W
f = 1kHz
-50.0
V-
-50.5
0 20 40 60 80 100
Time (ms)
RF
10kW
V+ = +50V
RS OPA454 VOUT
RL
4.8kW
VIN V- = -50V
RL = 1880W, 1mV/div
|(VIN+) - (VIN-)|
Inverting Response
Measured Here, V1
R2
R1 10kW
R4 Combination of Both
R3 10kW Inverting and R7 R8
Noninverting Responses, V2
R5 R6
-IN 10kW 10kW -IN
VOUT VOUT
OPA454 OPA454
+IN +IN
A1 A2
VIN
IP
RP
DVDD
(Digital Supply)
V+
-IN E/D 5V Logic
OPA454 VOUT
+IN E/D Com
V-
V-
(Negative Op Amp Supply)
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
V+
V+ 2nd Stage, +50V
1st Stage, +5V
VOUT 2nd Stage
VOUT 1st Stage
OPA454
OPA735 A2, 2nd Stage RLOAD
A1, 1st Stage 10kW
V-
VG = ±1V VOUT 1st Stage ±4.9V, Max 2nd Stage, -50V
V-
1st Stage, -5V VOUT 2nd Stage ±46V (92VPP), Max
VINPUT = ±1VPP
Figure 64. Two-Stage, High-Voltage Op Amp Circuit with Very Low Input Offset Temperature Drift
(1)
MASTER RS
10W
A1 OPA454
VIN
(1)
RS
10W
A2 OPA454
SLAVE RL
(1) RS resistors minimize the circulating current that always flows between the two devices because of VOS errors.
R1 R2
+50V
NPN
TIP29C, MJL21194,
MJE15003, MJL3281
CF
R4
R3
(1) 0.2W
-IN V+
(2)
VOUT 20W
(3)
OPA454 VO = VOUT - ILRL
+IN
VIN
V- R5
RL IL
0.2W
PNP
TIP30C, MJL21193,
MJE15004, MJL1302A
-50V
(1) Provides current limit for OPA454 and allows the amplifier to drive the load when the output is between +0.7 V and –0.7 V.
(2) Op amp VOUT swings from +47 V to –48 V.
(3) VO swings from +44.1 V to –45.1 V at IL = 1 A.
Figure 66. External Output Transistors Boost Output Current Greater Than 1 A
-100
R7
100k R6 C4
1M 10n
Status R11
Z2 Flg 100k
1N5229B E/D _
V-
-100
Vo2
E/D Com V+ +
U2 OPA454
R1 -100
10k
R12
R2 +V1 100k
190k
-V1
R4 R5
1M 100k
Status Z1
Flg E/D 1N5229B
_
V-
-V1
R3 + VLoad
+ V+ E/D Com
+ 3.75k
U3 OPA454 -
VG1
4.75 Vpk -V1
+V1
R13
+100 10k
R9
100k R8
1M
Z3 Status R14
1N5229B Flg 100k
E/D _
V-
Vo1
E/D Com V+ +
U1 OPA454
where
• R1 = 10 kΩ
• R2 = 190 kΩ
• AV = 20 V/V (1)
Applying this gain and a VPK of ±97.5 V, the maximum input voltage that may be applied without causing the
output to clip is ±4.75 V.
U1 and U2 are connected as unity-gain buffers. The purpose of this configuration is to track the U3 output
voltage, and then adjust the voltage levels at the U3 V+ and V– pins so that 100 V is maintained across them.
This input is accomplished by the U1 and U2 input connection to the U3 output voltage through the 100-kΩ
voltage dividers formed by R11, R12, and R14, R15. For example, as the output of U3 moves more positive, the
voltage on the U1 noninverting input moves up more closely to the +100-V supply level. Even though U2
provides the U1 V– supply, its output moves more positive as well. The result is that all the devices move
together in unison up and down, while maintaining the 100-V difference between the V+ and V– pins for U3.
Figure 68 shows how the U3 op amp output voltage VLOAD moves upward, becoming more positive, as the input
voltage VG1 increases from –4.75 V to 4.75 V. Figure 68 also shows VO1 and VO2, the U1 and U2 (respectively)
output voltages. The 100-V difference between the supply pins is evident in the graph. Notice how the U3 V+ pin
(VO1) allows 100 V greater than its V– pin (VO2).
100
80 VO1
60
Output Voltage (V)
40
100 V
20
VLOAD
0
-20
100 V
-40
VO2
-60
-80
-100
-5 -4 -3 -2 -1 0 1 2 3 4 5
VG1 Input Voltage (V)
75
V01
50
VLOAD
25
Voltage (V) 0
-25
V02
-50
-75
-100
Time (20ms/div)
Figure 69. Output Voltage Boost Develops 195-VPP VLOAD Across 3.75-kΩ Load Resistance
The output voltage booster may be used in an inverting configuration also. This use is easily accomplished by
applying the input signal to the input resistor R1 as seen in Figure 70. The noninverting input is grounded and the
ratio of feedback resistor R2 to R1 is set to 20:1 to satisfy the inverting gain equation given in Equation 2.
-V -R
AV = OUT = 2
VIN R1
where
• R1 = 10 kΩ
• R2 = 200 kΩ
• AV = –20 V/V (2)
R1 To Vo2 R2 To U2
10k 200k +IN
+V1
VG1 + 4.75 Vpk
-V1
R5
R4 100k
1M R12
100k
Status Z1
_ Flg E/D 1N5229B
V-
-V1
R3 + VLoad
+ V+ E/D Com 3.75k
U3 OPA454 -
R14
+V1 -V1 100k
To U1
To Vo1 +IN
50
Voltage (V) 0
-50 VG1
VLOAD
VO1
VO2
-100
0 25 50 75 100
Time (ms)
Figure 71. Voltage Levels in OPA454 Inverting Boost Amplifier Circuit from TINA-TI Simulation
(1) R2
R1 RP R2 G = 1+
R1
Status
V+
-IN Flag
VOUT
OPA454 VOUT
+IN E/D
VIN
E/D Com RL
V-
0.1mF
V- V-
(1) Pullup resistor with at least 10 μA (choose RP = 1 MΩ with V+ = 50 V for IP = 50 μA).
45.3kW
0-2mA V+
DAC8811 -IN
or
DAC7811 OPA454
+IN VOUT = 0V to +91V
Protects DAC
During Slewing V- RL
0.1mF
-5V
R4
10kW
+50V +50V
Up To
-IN V+ 195V V+ -IN
VOUT VOUT
MASTER OPA454 OPA454 SLAVE
VIN +IN A1 A2 +IN
(1)
±4V V- Piezo V-
Crystal
-50V -50V
(1) For transducers with large capacitance, stabilization may become an issue. Be certain that the Master amplifier is stable before stabilizing
the Slave amplifier.
Figure 74. Bridge Circuit Doubles Voltage for Exciting Piezo Crystals
OPA454 VOUT = V2 - V1
R3 R4
25kW 25kW
V2
25kW 25kW
V1
OPA454
A1
25kW 25kW R
V2 OPA454
A2
Load IO
IO = (V2 - V1)/R
A red light emitting diode (LED) was used to generate Figure 77.
6V 14
12
VOUT
10
VOUT (1V/div)
VLED (V)
6
4
VLED
0V 2
-2V -2
5ms/div
Gain of the avalanche photodiode (APD) is adjusted by changing the voltage across the APD. Gain starts to
increase when reverse voltage is increased beyond 130 V for this APD diode. See Figure 78.
R7 R1
10kW 90kW
+100V
+100V
R2 R4
V+
V+ 1kW 100kW
OPA454
OPA454 A2
A1 V- +100V
V- VOUT = 100 ´ RSENSE ´ ID
V+
APD
Figure 78. APD Gain Adjustment Using the OPA454, High-Voltage Op Amp
OPA454
A1
R4 R5
V-
R2 V+
R2
V-
R6 R7
V+
OPA454
A2
V2 VOUT = (1 + 2R2/R1) (V2 - V1)
VCM V-
(1) The linear input range is limited by the output swing on the input amplifiers, A1 and A2.
Figure 80 uses three OPA454s to measure current in a high-side shunt application. VSUPPLY must be greater than
VCM. VCM must be between (V–) + 2.5 V and (V+) – 2.5 V. Adhering to these restrictions keeps V1 and V2 within
the voltage range required for linear operation of the OPA454. For example, if V+ = 50 V and V– = 50 V, then
V1 = +47.5 V (maximum) and V2 = –47.5 V (minimum). The maximum supply voltage equals ±50 V, or 100 V
total.
RSHUNT
V+
Plus V1 Load
VSUPPLY or
Minus
OPA454
(1)
A1
R4 R5
V-
R2 V+
OPA454 VOUT
R1 (2)
A3
R2
V-
R6 R7
V+
OPA454
(1)
A2
V2 VOUT = (1 + 2R2/R1) (V2 - V1)
V-
(1) To increase the linear input voltage range, configure A1 and A2 as unity-gain followers.
(2) The linear input range is limited by the output swing on the input amplifiers, A1 and A2.
+120V +120V
100kW 100kW
V+ V+
OPA454 OPA454
A1 A4
V- V-
10kW 190kW 200kW 10kW
100kW 100kW
V+ RLOAD V+
(+97V, -98V) 7.5kW (-98V, +97V)
OPA454 OPA454
A3 A6
VLOAD
V- (±195V, 390VPP) V-
10kW 10kW
VIN
100kW 100kW
V+ V+
OPA454 OPA454
A2 A5
V- V-
100kW 100kW
-100V -100V
-100V -100V
Figure 81. Output Voltage Boost with ±195 V (390 VPP) Across Bridge-Tied Load
(Six Op Amps, see Figure 82 and Figure 83)
200 200 6
VLOAD
150 150
VIN VOUT 4
100 100
2
50 50
VOUT (V)
VOUT (V)
VIN (V)
0 0 0
-50 -50
-2
-100 -100
-4
-150 -150
-200 -200 -6
Time (20ms/div) Time (10ms/div)
Figure 82. 390 VPP Across 7.5-kΩ Load SR of 34 V/ms, which is significantly higher than the specified 13
20 kHz, Uses Six OPA454s, 100-V Supplies V/ms due to tracking of the power-supply voltage
Figure 83. 7.5-kΩ Load, G = +20, Six OPA454s, 100-V
Supplies
12 Layout
NOTE
Because the SO-8 PowerPAD is pin-compatible with standard SO-8 packages, the
OPA454 is a drop-in replacement for operational amplifiers in existing sockets. Soldering
the PowerPAD to the PCB is always required, even with applications that have low power
dissipation. Soldering the device to the PCB provides the necessary thermal and
mechanical connection between the leadframe die pad and the PCB.
E/D
Feedback Resistor
Gain Resistor
Bypass
Capacitor
E/D Com
IN typically V E/D Com E/D
or GND V+
IN V+
VOUT
+IN OUT
+IN
V Status
GND
Bypass
Capacitor
V GND
VFLAG (V)
VOUT (V)
-40 60 1MW
VFLAG
-60 40 -IN V+ Flag
VOUT
-80 20 VOUT
VFLAG +IN OPA454
E/D Com
-100 0
V- 625W
-120 -20
0 200 400 600 800 1000 -50V
(ms)
R1 R2
100kW 10kW
V1
+50V
-IN V+
VOUT
OPA454
+IN
V- R5
R3 R4
100kW 100W
-50V 9.9kW
V2
IL RL
IL = [(V2 - V1)/R5] (R2/R1)
= (V2 - V1)/1kW
Compliance Voltage Range = +47V, -48V
12.5 Heatsinking
Power dissipated in the OPA454 causes the junction temperature to rise. For reliable operation, junction
temperature must be limited to 125°C, maximum. Maintaining a lower junction temperature always results in
higher reliability. Some applications require a heatsink to assure that the maximum operating junction
temperature is not exceeded. Junction temperature can be determined according to Equation 3:
TJ = TA + PDqJA (3)
Package thermal resistance, θJA, is affected by mounting techniques and environments. Poor air circulation and
use of sockets can significantly increase thermal resistance to the ambient environment. Many op amps placed
closely together also increase the surrounding temperature. Best thermal performance is achieved by soldering
the op amp onto a circuit board with wide printed circuit traces to allow greater conduction through the op amp
leads. Increasing circuit board copper area to approximately 0.5 in2 decreases thermal resistance; however,
minimal improvement occurs beyond 0.5 in2, as shown in Figure 88.
For additional information on determining heatsink requirements, consult Application Bulletin SBOA021 (available
for download at www.ti.com).
60
Thermal Resistance, qJA (°C/W)
50
40
30
20
10
0
0 0.5 1.0 1.5 2.0 2.5 3.0
2
Copper Area (inches ), 2 oz
NOTE
These files require that either the TINA software (from DesignSoft™) or TINA-TI software
be installed. Download the free TINA-TI software from the TINA-TI folder.
13.4 Trademarks
PowerPAD, TINA-TI, E2E are trademarks of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
TINA, DesignSoft are trademarks of DesignSoft, Inc.
All other trademarks are the property of their respective owners.
13.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
www.ti.com 6-Feb-2020
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)
OPA454AIDDA ACTIVE SO PowerPAD DDA 8 75 Green (RoHS NIPDAU Level-2-260C-1 YEAR -55 to 125 OPA454
& no Sb/Br)
OPA454AIDDAG4 ACTIVE SO PowerPAD DDA 8 75 Green (RoHS NIPDAU Level-2-260C-1 YEAR -55 to 125 OPA454
& no Sb/Br)
OPA454AIDDAR ACTIVE SO PowerPAD DDA 8 2500 Green (RoHS NIPDAU Level-2-260C-1 YEAR -55 to 125 OPA454
& no Sb/Br)
OPA454AIDDARG4 ACTIVE SO PowerPAD DDA 8 2500 Green (RoHS NIPDAU Level-2-260C-1 YEAR -55 to 125 OPA454
& no Sb/Br)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 6-Feb-2020
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 3-Aug-2017
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 3-Aug-2017
Pack Materials-Page 2
GENERIC PACKAGE VIEW
DDA 8 PowerPAD TM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4202561/G
PACKAGE OUTLINE
DDA0008J SCALE 2.400
PowerPAD TM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE
C
6.2
TYP SEATING PLANE
5.8
A PIN 1 ID
AREA 0.1 C
6X 1.27
8
1
5.0 2X
4.8 3.81
NOTE 3
4
5
0.51
8X
4.0 0.31
B 1.7 MAX
3.8 0.1 C A B
NOTE 4
0.25
TYP
0.10
SEE DETAIL A
4 5
EXPOSED
THERMAL PAD
3.1 0.25
2.5 GAGE PLANE
0.15
0 -8 1.27 0.00
1 8
0.40
DETAIL A
2.6 TYPICAL
2.0
4221637/B 03/2016
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MS-012, variation BA.
www.ti.com
EXAMPLE BOARD LAYOUT
DDA0008J PowerPAD TM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE
(2.95)
NOTE 9
SOLDER MASK
(2.6) DEFINED PAD
SOLDER MASK
OPENING
8X (1.55) SEE DETAILS
1
8
8X (0.6)
(3.1)
SYMM SOLDER MASK
(1.3) OPENING
TYP (4.9)
NOTE 9
6X (1.27)
5
4
( 0.2) TYP
VIA SYMM METAL COVERED
BY SOLDER MASK
(1.3) TYP
(5.4)
4221637/B 03/2016
NOTES: (continued)
www.ti.com
EXAMPLE STENCIL DESIGN
DDA0008J PowerPAD TM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE
(2.6)
BASED ON
0.125 THICK
STENCIL
8X (1.55)
1
8
8X (0.6)
(3.1)
SYMM
BASED ON
0.127 THICK
STENCIL
6X (1.27)
5
4
4221637/B 03/2016
NOTES: (continued)
10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
11. Board assembly site may have different recommendations for stencil design.
www.ti.com
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