OPA454 High-Voltage (100-V), High-Current (50-Ma) Operational Amplifiers, G 1 Stable

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OPA454
SBOS391B – DECEMBER 2007 – REVISED MARCH 2016
OPA454 High-Voltage (100-V), High-Current (50-mA)

Operational Amplifiers, G = 1 Stable
1 Features 3 Description
1• Wide Power-Supply Range: The OPA454 device is a low-cost operational
±5 V (10 V) to ±50 V (100 V) amplifier with high voltage (100 V) and relatively high
current drive (50 mA). It is unity-gain stable and has a
• High-Output Load Drive: IO > ±50 mA gain-bandwidth product of 2.5 MHz.
• Wide Output Voltage Swing: 1 V to Rails
The OPA454 is internally protected against
• Independent Output Disable or Shutdown overtemperature conditions and current overloads. It
• Wide Temperature Range: –40°C to +85°C is fully specified to perform over a wide power-supply
• 8-Pin SO Package range of ±5 V to ±50 V or on a single supply of 10 V
to 100 V. The status flag is an open-drain output that
allows it to be easily referenced to standard low-
2 Applications voltage logic circuitry. This high-voltage operational
• Test Equipment amplifier provides excellent accuracy, wide output
• Avalanche Photodiode: swing, and is free from phase inversion problems that
High-V Current Sense are often found in similar amplifiers.
• Piezoelectric Cells The output can be independently disabled using the
• Transducer Drivers Enable or Disable Pin that has its own common
return pin to allow easy interface to low-voltage logic
• Servo Drivers circuitry. This disable is accomplished without
• Audio Amplifiers disturbing the input signal path, not only saving power
• High-Voltage Compliance Current Sources but also protecting the load.
• General High-Voltage Regulators and Power Featured in a small exposed metal pad package, the
OPA454 is easy to heatsink over the extended
Simplified Pin Description industrial temperature range, –40°C to +85°C.
Status
Flag Device Information(1)
V+ PART NUMBER PACKAGE BODY SIZE (NOM)
Enable/Disable (E/D) OPA454 SO PowerPAD™ (8) 4.89 mm × 3.90 mm
-IN (1) For all available packages, see the orderable addendum at
OPA454 VO the end of the data sheet.
+IN
Enable/Disable Common
(E/D Com)
V-
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
OPA454
SBOS391B – DECEMBER 2007 – REVISED MARCH 2016 www.ti.com
Table of Contents
1 Features .................................................................. 1 10 Application and Implementation........................ 22
2 Applications ........................................................... 1 10.1 Applications Information........................................ 22
3 Description ............................................................. 1 10.2 Typical Application ................................................ 24
4 Revision History..................................................... 2 10.3 System Examples ................................................. 27
5 Device Comparison Table..................................... 3 11 Power Supply Recommendations ..................... 33
6 Pin Configuration and Functions ......................... 3 12 Layout................................................................... 33
12.1 Layout Guidelines ................................................. 33
7 Specifications......................................................... 4
12.2 Layout Example .................................................... 35
7.1 Absolute Maximum Ratings ...................................... 4
12.3 Thermal Protection................................................ 36
7.2 ESD Ratings ............................................................ 4
12.4 Power Dissipation ................................................. 36
7.3 Recommended Operating Conditions....................... 4
12.5 Heatsinking ........................................................... 37
7.4 Thermal Information .................................................. 4
7.5 Electrical Characteristics: VS = ±50 V....................... 5 13 Device and Documentation Support ................. 38
7.6 Typical Characteristics .............................................. 7 13.1 Device Support .................................................... 38
13.2 Documentation Support ....................................... 38
8 Parameter Measurement Information ................ 16
13.3 Community Resources.......................................... 39
9 Detailed Description ............................................ 17
13.4 Trademarks ........................................................... 39
9.1 Overview ................................................................. 17
13.5 Electrostatic Discharge Caution ............................ 39
9.2 Functional Block Diagram ....................................... 17
13.6 Glossary ................................................................ 39
9.3 Feature Description................................................. 18
9.4 Device Functional Modes........................................ 21 14 Mechanical, Packaging, and Orderable
Information ........................................................... 39
4 Revision History
Changes from Revision A (December 2008) to Revision B Page
• Added Pin Functions table, ESD Ratings table, Recommended Operating Conditions table, Thermal Information
table, Feature Description section, Device Functional Modes section, Application and Implementation section,
Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 1
• Changed OPA454 Related Products table to Device Comparison table ............................................................................... 3
• Deleted Ordering Information table ........................................................................................................................................ 3
• Corrected symbol error in Absolute Maximum Ratings table; changed operating temperature specification from TJ to
TA ........................................................................................................................................................................................... 4
• Changed Figure 29 title from THD+N vs Temperature to THD+N vs Frequency ................................................................ 10
• Changed Figure 30 title from THD+N vs Temperature to THD+N vs Frequency ................................................................ 10
Changes from Original (December 2007) to Revision A Page
• Deleted DDA Package from title of Figure 13 ........................................................................................................................ 9

• Deleted DDA Package from title of Figure 14 ........................................................................................................................ 9
• Corrected mislabeled y-axis in Figure 42 ............................................................................................................................. 12
• Changed statement about thermal shutdown cycling qualification studies from 400 hours to 1000 hours in Current
Limit section.......................................................................................................................................................................... 21
• Deleted Top-Side PowerPAD Package section.................................................................................................................... 33
• Added alternate units (.013 in, or 0.3302 mm) for measurement of recommended through-hole diameter to
PowerPAD Layout Guidelines description............................................................................................................................ 34
2 Submit Documentation Feedback Copyright © 2007–2016, Texas Instruments Incorporated
Product Folder Links: OPA454

OPA454
www.ti.com SBOS391B – DECEMBER 2007 – REVISED MARCH 2016
5 Device Comparison Table
PRODUCT DESCRIPTION
(1)
OPA445 80 V, 15 mA
OPA452 80 V, 50 mA
OPA547 60 V, 750 mA
OPA548 60 V, 3 A
OPA549 60 V, 9 A
OPA551 60 V, 200 mA
OPA567 5 V, 2 A
OPA569 5 V, 2.4 A
(1) The OPA445 is pin-compatible with the OPA454, except in applications using the offset trim, and NC
pins other than open.
6 Pin Configuration and Functions
DDA PACKAGE
8-Pin SO PowerPAD
Top View
E/D Com (Enable/Disable Common) 1 8 E/D (Enable/Disable)

(1)
PowerPAD
-IN 2 Heat Sink 7 V+
(Located on
+IN 3 bottom side) 6 OUT
V- 4 5 Status Flag
(1) PowerPAD is internally connected to V–. Soldering the PowerPAD to the printed-circuit board (PCB) is always
required, even with applications that have low power dissipation.
Pin Functions
PIN
I/O DESCRIPTION
NAME NO.
E/D (Enable/Disable) 8 I Enable/Disable
E/D Com 1 I Enable/Disable common
–IN 2 I Inverting input
+IN 3 I Noninverting input
OUT 6 O Output
The Status Flag is an open-drain active-low output referenced to E/D Com. This
Status Flag 5 O
pin goes active for either an overcurrent or overtemperature condition.
V– 4 — Negative (lowest) power supply
V+ 7 — Positive (highest) power supply
Copyright © 2007–2016, Texas Instruments Incorporated Submit Documentation Feedback 3

OPA454
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
Supply voltage, VS = (V+) – (V–) 120 V
(2)
Voltage Signal input pin (V–) – 0.3 (V+) + 0.3 V
E/D to E/D Com 5.5 V
Signal input pin (2) ±10 mA
Current
Output short circuit (3) Continuous
Operating, TA –55 125 °C
Temperature Junction, TJ 150 °C
Storage, Tstg –55 125 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Input terminals are diode-clamped to the power-supply rails. Input signals that can swing more than 0.3 V beyond the supply rails must
be current-limited to 10 mA or less.
(3) Short-circuit to ground.
7.2 ESD Ratings

VALUE UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±4000
V(ESD) Electrostatic discharge Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±500 V
Machine model (MM) ±150
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
Supply voltage, VS = (V+) – (V–) 10 (±5) 100 (±50) V
TA Operating temperature –55 125 °C
7.4 Thermal Information

OPA454
THERMAL METRIC (1) DDA (SO) UNIT
8 PINS
RθJA Junction-to-ambient thermal resistance 40.6 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 46 °C/W
RθJB Junction-to-board thermal resistance 20.7 °C/W
ψJT Junction-to-top characterization parameter 5.6 °C/W
ψJB Junction-to-board characterization parameter 20.6 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 2.5 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.

OPA454
7.5 Electrical Characteristics: VS = ±50 V

At TP (1) = 25°C, RL = 4.8 kΩ to mid-supply, VCM = VOUT = mid-supply, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OFFSET VOLTAGE
VOS Input offset voltage IO = 0 mA ±0.2 ±4 mV
dVOS/dT Input offset voltage vs temperature At TA = –40°C to +85°C ±1.6 ±10 µV/°C
PSRR Input offset voltage vs power supply VS = ±4 V to ±60 V, VCM = 0 V 25 100 µV/V
INPUT BIAS CURRENT
At TP = 25°C ±1.4 ±100 pA
IB Input bias current
At TA = –40°C to +85°C See Typical Characteristics
IOS Input offset current ±0.2 ±100 pA
NOISE
f = 10 Hz 300 nV/√Hz
en Input voltage noise density
f = 10 kHz 35 nV/√Hz
Input voltage noise f = 0.01 Hz to 10 Hz 15 µVPP
in Current noise density f = 1 kHz 40 fA/√Hz
INPUT VOLTAGE RANGE
(2)
VCM Common-mode voltage range Linear operation (V–) + 2.5 See Note (V+) – 2.5 V
VS = ±50 V, –25 V ≤ VCM ≤ 25 V 100 146 dB
VS = ±50 V, –45 V ≤ VCM ≤ 45 V 100 147 dB
CMRR Common-mode rejection At TA = –40°C to +85°C,

80 88 dB
VS = ±50 V, –25 V ≤ VCM ≤ 25 V
At TA = –40°C to +85°C,
72 82 dB
VS = ±50 V, –45 V ≤ VCM ≤ 45 V
INPUT IMPEDANCE
Differential 1013 || 10 Ω || pF
Common-mode 13 Ω || pF
10 || 9
OPEN-LOOP GAIN
(V–) + 1 V < VO < (V+) – 1 V, 100 130 dB

RL = 49 kΩ, IO = ±1 mA At TA = –40°C to +85°C 112 dB
Open-loop (V–) + 1 V < VO < (V+) – 2 V, 100 115 dB

AOL
voltage gain (3) RL = 4.8 kΩ, IO = ±10 mA At TA = –40°C to +85°C 106 dB
(V–) + 2 V < VO < (V+) – 3 V, 80 102 dB

RL = 1880 Ω, IO = ±25 mA At TA = –40°C to +85°C 84 dB
FREQUENCY RESPONSE (4)
GBW Gain-bandwidth product Small-signal 2.5 MHz
G = ±1, VO = 80-V step,
SR Slew rate 13 V/µs
RL = 3.27 kΩ
(5)
Full-power bandwidth 35 kHz
To ±0.1%, G = ±1, VO = 20-V step 3 µs
tS Settling time (6) To ±0.01%, G = ±5 or ±10,
10 µs
VO = 80-V step
VS = +40.6 V/–39.6 V, G = ±1,
THD+N Total harmonic distortion + noise (7) 0.0008%
f = 1 kHz, VO = 77.2 VPP
(1) TP is the temperature of the leadframe die pad (exposed thermal pad) of the PowerPAD package.
(2) Typical range is (V–) + 1.5 V to (V+) – 1.5 V.
(3) Measured using low-frequency (<10 Hz) ±49-V square wave. See typical characteristic curve, Current Limit vs Temperature (Figure 23).
(4) See Typical Characteristics curves.
(5) See typical characteristic curve, Maximum Output Voltage vs Frequency (Figure 11).
(6) See the Feature Description section, Settling Time.
(7) Supplies reduced to allow closer swing to rails due to test equipment limitations. See typical characteristic curves Total Harmonic
Distortion + Noise vs Frequency (Figure 29 and Figure 30) for additional power levels.

OPA454
Electrical Characteristics: VS = ±50 V (continued)

At TP(1) = 25°C, RL = 4.8 kΩ to mid-supply, VCM = VOUT = mid-supply, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OUTPUT
RL = 49 kΩ, AOL ≥ 100 dB,
(V–) + 1 (V+) – 1 V
IO = 1 mA
RL = 4.8 kΩ, AOL ≥ 100 dB,
VO Voltage output swing from rail (8) (V–) + 1 (V+) – 2 V
IO = 10 mA
RL = 1880 Ω, AOL ≥ 80 dB,
(V–) + 2 (V+) – 3 V
IO = 26 mA
Continuous current output, DC Depends on circuit conditions See Figure 5
+120/–150 mA
IO Maximum peak current output, current limit (3)
At TA = –40°C to +85°C +140/–170 mA
CLOAD Capacitive load drive (4) 200 pF
RO Open-loop output impedance See Figure 4 Ω
Output Output capacitance 18 pF

disabled Feedthrough capacitance (9) 150 fF
STATUS FLAG PIN (Referenced to E/D Com)
Enable → Disable 6 µs
Disable → Enable 4 µs
Status Flag delay
Overcurrent delay (10) 15 µs
Overcurrent recovery delay (10) 10 µs
Alarm (Status Flag high) 150 °C
Junction
TJ Return to normal operation
temperature 130 °C
(Status Flag low)
Normal operation E/D Com + 2 V
Output voltage (4) RL = 100 Ω during thermal
(V+) – 2.5 V
overdrive, alarm
E/D (ENABLE/DISABLE) PIN
E/D pin, referenced to E/D Com pin (11) (12)
E/D Com +
High (output enabled) Pin open or forced high E/D Com + 5 V
VSD 2.5
Low (output disabled) Pin forced low E/D Com E/D Com + 0.65 V
Output disable time 4 µs
Output enable time 3 µs
E/D COM PIN
Voltage range (V–) (V+) – 5 V
POWER SUPPLY
VS Specified range ±50 V
Operating voltage range ±5 ±50 V
IQ Quiescent current IO = 0 mA 3.2 4 mA
Quiescent current in Shutdown mode IO = 0 mA, VE/D = 0.65 V 150 210 µA
TEMPERATURE RANGE
Specified range –40 85 °C
TA
Operating range –55 125 °C
(8) See typical characteristic curve, Output Voltage Swing vs Output Current (Figure 10).
(9) Measured using Figure 56.
(10) See Typical Characteristics curves for current limit behavior.
(11) See typical characteristic curve, IENABLE vs VENABLE (Figure 45).
(12) High enables the outputs.

OPA454
7.6 Typical Characteristics

At TP = 25°C, VS = ±50 V, and RL = 4.8 kΩ connected to GND, unless otherwise noted.
180 70
CL = 30pF VCM = -45V
160
Open-Loop Gain, Phase (dB, °)
VCM = 0V
65
140 VCM = +45V
120
Phase Margin (°)

60
100
Phase
80 55
60
50
40 CL = 100pF
Gain CL = 200pF
RLOAD = 4.87kW
20
CLOAD = 50pF 45
0 VCM = 0V
-20 40
0.1 1 10 100 1k 10k 100k 1M 10M -75 -50 -25 0 25 50 75 100 125
Frequency (Hz) Exposed Thermal Pad Temperature (°C)
Figure 1. Open-Loop Gain and Phase vs Frequency Figure 2. Phase Margin vs Temperature
3.8 1M
Open-Loop Output Impedance (W)

3.6
100k
3.4
Bandwidth (MHz)
3.2 10k
VCM = 0V
3.0
1k
2.8
VCM = 45V
2.6 100
VCM = -45V
2.4
10
2.2
CL = 30pF, 100pF, and 200pF
2.0 1
-75 -50 -25 0 25 50 75 100 125 1 10 100 1k 10k 100k 1M 10M
Exposed Thermal Pad Temperature (°C) Frequency (Hz)
Figure 3. Unity-Gain Bandwidth vs Temperature Figure 4. Open-Loop Output Impedance vs Frequency

140 140
130 130
VS = ±50V
120
120
110
110 RLOAD = 48kW
AOL (dB)
AOL (dB)
VS = ±15V 100 VOUT = ±49V (dc)

100 IOUT = ±1mA
90
RL = 4.8kW
90
80 VOUT = +48V, -49V (dc)
VS = ±4V
IOUT = +9.9mA to -10mA
80 70
RL = 1.88kW RL = 900W
70 VOUT = +47V, -48V (dc) VOUT = +45V, -47V (dc)
60
IOUT = ±25mA IOUT = 50mA to -52mA
60 50
0 5 10 15 20 25 -75 -50 -25 0 25 50 75 100 125
Peak IL (mA) Exposed Thermal Pad Temperature (°C)
Figure 5. Open-Loop Gain vs Peak-Load Current Figure 6. Open-Loop Gain vs Temperature

OPA454
Typical Characteristics (continued)

140 120
PSRR
120 100
1kHz, CMRR
PSRR and CMRR (dB)

100 10kHz, CMRR
80
CMRR (dB)
80
VCM = -45V 60
100kHz, CMRR
60
40
40 1.3MHz, CMRR
VCM = +45V
20 20 VCM = +45V
VCM = -45V
0 0
1 10 100 1k 10k 100k 1M 10M -75 -50 -25 0 25 50 75 100 125
Frequency (Hz) Exposed Thermal Pad Temperature (°C)
Figure 7. Common-Mode Rejection Ratio vs Frequency Figure 8. Power-Supply and Common-Mode Rejection Ratio
vs Temperature
140 50
-55°C
120 49
100 48
PSRR (dB)
VOUT (V)
80 47
+125°C +85°C +25°C
60 -47
40 -48
20 -49
-55°C
0 -50
1 10 100 1k 10k 100k 1M 0 10 20 30 40 50
Frequency (Hz) IOUT (mA)
Figure 9. Power-Supply Rejection Ratio vs Frequency Figure 10. Output Voltage Swing vs Output Current
(Measured When Status Flag Transitions From
Low To High)
120 Average = 111mV
VOUT = ±49V
Standard Deviation = 142mV
100 RL = 4.8kW
IOUT = ±10mA
Output Voltage (VPP)
80
Population
60
40
20
0
0 50 100 150 200 250 300 -4000 -3000 -2000 -1000 0 1000 2000 3000 4000
Frequency (kHz) Offset Voltage (mV)
Figure 11. Maximum Output Voltage vs Frequency Figure 12. DDA Package Offset Voltage
Production Distribution

OPA454

Average = 1.57mV/°C Average = 0.34mV/°C
Standard Deviation = 0.84mV/°C Standard Deviation = 0.44mV/°C
Population
Population
-0.8
-0.4
-2.0
0.8
1.2
1.6
2.0
-1.6
-1.2
0.4
0 1 2 3 4 5 6 7 8 9 10
Offset Voltage Drift (mV/°C) Output Voltage Shift (mV/°C)
Figure 13. Offset Voltage Drift Production Distribution Figure 14. Solder-Attached, VOS TC Shift
Average = 48mV/°C 200
Standard
150
Deviation = 28mV/°C
Offset Voltage (mV) 100
VS = ±50V
Population
50
PowerPAD Attached
0 9in ´ 12in 0.062
Layer Metal PCB FR10
-50
-100
-150
-200
-400
-200
-1000
400
600
800
1000
-800
-600
200
100s/div
Offset Voltage Shift (mV)
Figure 15. DDA Package, Solder-Attached, VOS Shift Figure 16. Offset Voltage Warmup
(60 Devices)
3.25
3.20
3.15
Population
IQ (mA)
3.10
3.05
3.00
2.95
2.90
3.1
3.3
3.5
3.2
2.5
2.8
3.4
3.8
3.9
3.0
3.6
3.7
2.6
2.7
2.9
0 10 20 30 40 50 60 70 80 90 100 110 120

Quiescent Current (mA) Total Supply Voltage (V)
Figure 17. Quiescent Current Production Distribution Figure 18. Quiescent Current vs Supply Voltage

OPA454

4.0 200
3.8 5 Typical Units Shown
3.6 180
Shutdown Current (mA)

3.4
3.2 160
IQ (mA)
3.0
2.8 140
2.6
2.4 120
2.2
2.0 100
-75 -50 -25 0 25 50 75 100 125 -75 -50 -25 0 25 50 75 100 125
Exposed Thermal Pad Temperature (°C) Exposed Thermal Pad Temperature (°C)
Figure 19. Quiescent Current vs Temperature Figure 20. Shutdown Current vs Temperature
100 20
15
10
10
5
IB (pA)
IB (pA)
-5
1 Common-Mode Voltage Range
-10
-15
0.1 -20
-75 -50 -25 0 25 50 75 100 125 -50 -40 -30 -20 -10 0 10 20 30 40 50
Exposed Thermal Pad Temperature (°C) VCM (V)
Figure 21. Input Bias Current vs Temperature Figure 22. Input Bias Current vs Common-Mode Voltage
200 8
7
180 RP = 20kW, IP = 5mA
6
Sourcing
5
VFLAG to V-
ILIMIT (mA)
160
4
RP = 50kW, IP = 2mA
140 3
RP = 100kW, IP = 100mA
2
120 RP = 200kW, IP = 50mA
1
Sinking
100 0
-75 -50 -25 0 25 50 75 100 125 -75 -50 -25 0 25 50 75 100 125
See Figure 72 in the System Examples section.
Figure 23. Current Limit vs Temperature Figure 24. Status Flag Voltage vs Temperature
(E/D Com Connected To V–)

OPA454

2.0 16
SO-8 PowerPAD:
TJ(max) = +125°C 15
1.5 14
Slew Rate (V/ms)

Dissipation (W)
13
1.0 12
TJ (+125°C max) = TA + [(|VS| - |VO|) IO ´ qJA] 11

qJA = +52°C/W, SO-8 PowerPAD G = +1
0.5 10
(1in ´ 0.5in [25.4mm x 12.7mm] VS = ±45V
Heat-Spreader, 1oz Copper) 9 VIN = 80V Step
TJ = +25°C + (1.93W ´ 52°C/W) = +125°C RLOAD = 4.8kW
0 8
-50 -25 0 25 50 75 100 125 -75 -50 -25 0 25 50 75 100 125
Figure 25. Maximum Power Dissipation vs Figure 26. Slew Rate vs Temperature
Temperature With Minimum Attach Area
1000
Voltage Noise (nV/ÖHz)
100
5mV/div
10
1
10 100 1k 10k 100k 20s/div
Frequency (Hz)
Figure 27. Input Voltage Noise Spectral Density Figure 28. 0.01-Hz to 10-Hz Input Voltage Noise
0.040 0.0030
G = +10 G = +1
RI = 4.75kW RI = 4.75kW
0.035 VPK = 38.6V 0.0025 VPK = 38.6V VS = +41.6, -40.6
0.030 0.0020
THD + N (%)
THD + N (%)
0.025 0.0015
VS = +40.6,
VS = -55, +55 -39.6
0.020 0.0010
VS = -49, +50
0.015 0.0005
0.010 0
10 100 1k 10k 100k 10 100 1k 10k 100k
Frequency (Hz) Frequency (Hz)
Figure 29. Total Harmonic Distortion + Noise vs Frequency Figure 30. Total Harmonic Distortion + Noise vs Frequency

OPA454

VIN VIN
G = +1 G = +1
TC = +60°C TC = +105°C
CLOAD = 50pF CLOAD = 50pF
500mV/div
500mV/div
VCM = +30V VCM = +30V
RF = 10kW RF = 10kW
VOUT VOUT
Time (1ms/div) Time (1ms/div)
Figure 31. Large-Signal Step Response Figure 32. Large-Signal Step Response
TC = +125°C
TC = +25°C
VOUT (400mV/div)
VIN (200mV/div)
50mV TC = -55°C
G = +2
TC = +100°C G = +1
CLOAD = 100pF CLOAD = 100pF
VIN
VCM = +40V VCM = 0V
VOUT RF = 10kW RF = 0W
Time (2.5ms/div) Time (500ns/div)
Figure 33. Large-Signal Step Response Figure 34. Small-Signal Step Response
2.0 180
G = +1 RF = 0W
1.5 160 RF = 10kW
G = +2 TC = -55°C
140
1.0 TC = +25°C
120
Peaking (%)
0.5 TC = +85°C
VOUT (V)
100
TC = +125°C
0
80
-0.5 60
-1.0 40
RF = 10kW
-1.5 20
CLOAD = 100pF, 125°C
VCM = +40V 0
-2.0 0 100 200 300 400 500
1ms/div CLOAD (pF)
See Application section, Unity-Gain Noninverting Configuration.
G = +1 VCM = 0 V
Figure 35. Step Response Figure 36. Gain Peaking vs CLOAD

OPA454

30 10
CF = 0pF TC = -55°C TA = +25°C CL = 200pF
CF = 2.5pF 8
25
CF = 5pF TC = +25°C
6
20 CL = 100pF
TC = +85°C 4
Peaking (%)
Gain (dB)
15
TC = +125°C 2
10
0
5
-2
RF = 10kW, CF = 50pF
0 -4
RF = 0W
CL = 50pF
-5 -6
0 100 200 300 400 500 10k 100k 1M 10M
CLOAD (pF) Frequency (Hz)
G = +2 RF = 10 kΩ VCM = 0 V See Application section Unity-Gain Noninverting Configuration.
Figure 37. Gain Peaking vs CLOAD Figure 38. Gain of +1 vs Frequency

10 20 0.08
TA = +25°C CL = 500pF
8 15 0.06
V1 (Inverting)
Voltage at V1 and V2 (V)

6 10 0.04
4 5 0.02
Gain (dB)
VIN (V)
CL = 50pF V2 (Noninverting)
2 0 0
-5 -0.02
0
-10 -0.04
-2 CF = 0pF VIN
CF = 2.5pF -15 -0.06
-4
CF = 5pF
-20 -0.08
-6 Time (1ms/div)
10k 100k 1M 10M
See the Settling Time section. The grid for voltage at V1 and V2 is
Frequency (Hz) scaled 20 mV or 0.1% per division.
See Application section Unity-Gain Noninverting Configuration. 20-V Step Gain = 1 RF = 10 kΩ
Figure 39. Gain of +2 vs Frequency Figure 40. Settling Time, Positive Step
20 0.08
15 0.06
VIN
Voltage at V1 and V2 (V)
10 0.04
20V/div OUT
5 0.02
VIN (V)
0 0
V2 (Noninverting) 50V/div Status Flag
-5 -0.02
-10 -0.04
V1 (Inverting) Enable
-15 -0.06
5V/div
-20 -0.08
See the Settling Time section. The grid for voltage at V1 and V2 is
scaled 20 mV or 0.1% per division.
20-V Step Gain = 1 RF = 10 kΩ
Figure 41. Settling Time, Negative Step Figure 42. Enable Response Time

OPA454

20V/div
OUT
20V/div OUT
50V/div Status Flag 50V/div Status Flag
Enable 5V/div Enable
5V/div
Figure 43. Disable Response Time Figure 44. Enable Response

10 1.00
0.95
0
-40°C Threshold (V) 0.90
IENABLE (mA)
-10 0.85
+25°C
+85°C 0.80
-20
0.75
-30 0.70
0 1 2 3 4 5 -75 -50 -25 0 25 50 75 100 125
VENABLE (V) Temperature (°C)
Figure 45. IENABLE vs VENABLE Figure 46. Enable/Disable Threshold vs Temperature

60 200 60 150
VFLAG VFLAG
50 150 50 100
40 100 40 50
IOUT
VFLAG (V)
VFLAG (V)
IOUT (mA)
IOUT (mA)
30 50 30 0
20 0 20 -50
IOUT
10 -50 10 -100
0 -100 0 -150
RP = 100kW RP = 100kW
-10 -150 -10 -200
10ms/div 10ms/div
The OPA454 was connected to sufficient heatsinking to prevent The OPA454 was connected to sufficient heatsinking to prevent
thermal shutdown. thermal shutdown.
TP = 125°C TP = 25°C
Figure 47. ILIMIT Showing Flag Delay () Figure 48. ILIMIT Showing Flag Delay

OPA454

60 150 1.6
VFLAG +125°C
1.4 +85°C 0.988VPP +50V
50 100 0.01Hz
-
+25°C OPA454
1.2
-55°C 2Hz
+
40 50 2ms Pulse
IOUT 1.0 -50V Mercury

Wetted
VFLAG (V)
IOUT (mA)
Relay
VOUT (V)
30 0
0.8
20 -50 0.6
10 -100 0.4
0.2
0 -150
RP = 100kW 0
-10 -200
10ms/div -0.2
10ms/div
The OPA454 was connected to sufficient heatsinking to prevent
thermal shutdown.
TP = –55°C
Figure 49. ILIMIT Showing Flag Delay Figure 50. Apply Load (25-mA Sink Response)
0.2 0.2
0 0
-0.2 -0.2
-0.4 -0.4
VOUT (V)
VOUT (V)
-0.6 -0.6
-0.8 -0.8
0.988VPP +50V 0.988VPP +50V
-1.0 0.01Hz -1.0 0.01Hz
+125°C +125°C
- -
OPA454 OPA454
-1.2 +85°C + 2Hz -1.2 + 2Hz +85°C
2ms Pulse 2ms Pulse
+25°C -50V Mercury -50V Mercury +25°C

-1.4 Wetted -1.4 Wetted
-55°C Relay Relay -55°C
-1.6 -1.6
10ms/div 10ms/div
Figure 51. Remove Load (25-mA Sink Response) Figure 52. Apply Load (25-mA Source Response)
1.6
+125°C RL = 1.8kW V+
1.4 +85°C
+25°C VOUT
1.2
-55°C
1.0 0.988VPP +50V
0.01Hz
- Flag
VOUT (V)
20V/div
OPA454
0.8 + 2Hz
2ms Pulse 0
0.6 -50V Mercury
Wetted
Relay
0.4
Delay in V- is due to
0.2 V-
test equipment.
0 Power supplies may be
applied in any sequence.
-0.2
10ms/div 20ms/div
Figure 53. Remove Load (25-mA Source Response) Figure 54. Power On

OPA454

V+ RL = 1.8kW
VOUT
Flag
20V/div
0
V-
20ms/div
Figure 55. Power Off
8 Parameter Measurement Information

+50V
E/D
VOUT
RL
50kW
100VPP
E/D Com
10kHz
-50V
Figure 56. Feedthrough Capacitance Circuit

OPA454
9 Detailed Description
9.1 Overview
The OPA454 is a low-cost operational amplifier (op amp) with high voltage (100 V) and a relatively high current
drive of 50 mA. This device is unity-gain stable and features a gain-bandwidth product of 2.5 MHz. The high-
voltage OPA454 offers excellent accuracy, wide output swing, and has no phase inversion problems that are
typically found in similar op amps. The device can be used in virtually any ±5-V to ±50-V op amp configuration,
and is especially useful for supply voltages greater than 36 V.
9.2 Functional Block Diagram
V+
V IN
Differential Voltage High Current

VO
Amplifier Amplifier Output Stage
Biasing
V+IN Current Limiting
Enable/Disable
Status
E/D E/D STATUS

COM

OPA454
9.3 Feature Description

The OPA454 includes safety features on both the device input and output. On the input, protection is provided for
a variety of fault conditions. On the output, current limiting and thermal protection are provided. Performance
advantages include a ±50-mA output current capability along with the ability to swing to within 1 V of the supply
rails. The Enable/Disable function provides the ability to turn off the output stage and reduce power consumption
when not being used. The Status Flag indicates fault conditions and can be used in conjunction with the
Enable/Disable function to implement fault control loops.
9.3.1 Input Protection

The OPA454 has increased protection against damage caused by excessive voltage between op amp input pins
or input pin voltages that exceed the power supplies; external series resistance is not needed for protection.
Internal series JFETs limit input overload current to a non-destructive 4 mA, even with an input differential
voltage as large as 120 V. Additionally, the OPA454 has dielectric isolation between devices and the substrate.
Therefore, the amplifier is free from the limitations of junction isolation common to many IC fabrication processes.
9.3.2 Input Range

The OPA454 is specified to give linear operation with input swing to within 2.5 V of either supply. Generally, a
gain of +1 is the most demanding configuration. Figure 57 and Figure 58 show output behavior as the input
swings to within 0 V of the rail, using the circuit shown in Figure 60. Figure 59 shows the behavior with an input
signal that swings beyond the specified input range to within 1 V of the rail, also using the circuit in Figure 60.
Notice that the beginning of the phase reversal effect may be reduced by inserting series resistance (RS) in the
connection to the positive input. VOUT does not swing all the way to the opposite rail.
50.5 -46.0
V+ TA = +25°C TA = +25°C
50.0 -46.5
VOUT
VIN VOUT -47.0
49.5 R S = 0W
f = 1kHz RS = 50kW -47.5
Voltage (V)
Voltage (V)
49.0 VOUT
-48.0
RS = 50kW
48.5 -48.5
-49.0
48.0
VIN
-49.5
VOUT f = 1kHz
47.5
RS = 0W -50.0
V-
47.0 -50.5
0 20 40 60 80 100 0 20 40 60 80 100
Time (ms) Time (ms)
Figure 57. Output Voltage with Input Voltage Figure 58. Output Voltage with Input Voltage
up to V+ Down to V–
-46.0
TA = +25°C
-46.5
-47.0
-47.5
Voltage (V)
VOUT
-48.0
RS = 50kW
-48.5
-49.0
VIN VOUT
-49.5 R S = 0W
f = 1kHz
-50.0
V-
-50.5
0 20 40 60 80 100
Time (ms)
Figure 59. Output Voltage with Input Voltage Down to (V–) + 1 V

OPA454
RF
10kW
V+ = +50V
RS OPA454 VOUT
RL
4.8kW
VIN V- = -50V
Figure 60. Input Range Test Circuit
9.3.3 Output Range

The OPA454 is specified to swing to within 1 V of either supply rail with a 49-kΩ load while maintaining excellent
linearity. Swing to the rail decreases with increasing output current. The OPA454 can swing to within 2 V of the
negative rail and 3 V of the positive rail with a 1.88-kΩ load. The typical characteristic curve, Output Voltage
Swing vs Output Current (Figure 10), shows this behavior in detail.
9.3.4 Open-Loop Gain Linearity

Figure 61 shows the nonlinear relationship of AOL and output voltage. As Figure 61 shows, open-loop gain is
lower with positive output voltage levels compared to negative voltage levels. Specifications in Electrical
Characteristics: VS = ±50 V are based upon the average gain measured at both output extremes.
AOL is a Function of VOUT and ILOAD

TP = +25°C
RL = 1880W, 1mV/div
|(VIN+) - (VIN-)|
RL = 900W, 2mV/div 74dB 89dB
RL = 4.87kW, 200mV/div 106dB
-50 -40 -30 -20 -10 0 10 20 30 40 50

Output Voltage (V)
Figure 61. Differential Input Voltage (+IN to –IN) vs Output Voltage

OPA454
9.3.5 Settling Time

The circuit in Figure 62 is used to measure the settling time response. The left half of the circuit is a standard,
false-summing junction test circuit used for settling time and open-loop gain measurement. R1 and R2 provide the
gain and allow for measurement without connecting a scope probe directly to the summing junction, which can
disturb proper op amp function by causing oscillation.
The right half of the circuit looks at the combination of both inverting and noninverting responses. R5 and R6
remove the large step response. The remaining voltage at V2 shows the small-signal settling time that is centered
on zero. This test circuit can be used for incoming inspection, real-time measurement, or in designing
compensation circuits in system applications.
Table 1 lists the settling time measurement circuit configuration shown in Figure 62 with different gain settings.
Table 1. Settling Time Measurement Circuit Configuration Using Different Gain

Settings for Figure 62
GAIN
COMPONENT
1 5 10
R1 (Ω) 10 k 2k 1k
R3 (Ω) 10 k 2k 1k
R7 (Ω) 10 k 4k 9k
R8 (Ω) ∞ 1k 1k
VIN (VPP) 20 16 8
Inverting Response
Measured Here, V1
R2
R1 10kW
R4 Combination of Both
R3 10kW Inverting and R7 R8
Noninverting Responses, V2
R5 R6
-IN 10kW 10kW -IN
VOUT VOUT
OPA454 OPA454
+IN +IN
A1 A2
VIN
Figure 62. Settling Time Test Measurement Circuit

OPA454
9.3.6 ENABLE and E/D Com

If left disconnected, E/D Com is pulled near V– (negative supply) by an internal 10-μA current source. When left
floating, ENABLE is held approximately 2 V above E/D Com by an internal 1-μA source. Even though active
operation of the OPA454 results when the ENABLE and E/D Com pins are not connected, a moderately fast,
negative-going signal capacitively coupled to the ENABLE pin can overpower the 1-μA pullup current and cause
device shutdown. This behavior can appear as an oscillation and is encountered first near extreme cold
temperatures. If the enable function is not used, a conservative approach is to connect ENABLE through a 30-pF
capacitor to a low impedance source. Another alternative is the connection of an external current source from V+
(positive supply) sufficient to hold the enable level above the shutdown threshold. Figure 63 shows a circuit that
connects ENABLE and E/D Com. Choosing RP to be 1 MΩ with a +50-V positive power supply voltage results in
IP = 50 μA.
V+
(Positive Op Amp Supply)
IP
RP
DVDD
(Digital Supply)
V+
-IN E/D 5V Logic
OPA454 VOUT
+IN E/D Com
V-
V-
(Negative Op Amp Supply)
Figure 63. ENABLE and E/D Com
9.3.7 Current Limit

Figure 23 and Figure 47 to Figure 49 show the current limit behavior of the OPA454. Current limiting is
accomplished by internally limiting the drive to the output transistors. The output can supply the limited current
continuously, unless the die temperature rises to 150°C, which initiates thermal shutdown. With adequate
heatsinking, and use of the lowest possible supply voltage, the OPA454 can remain in current limit continuously
without entering thermal shutdown. Although qualification studies have shown minimal parametric shifts induced
by 1000 hours of thermal shutdown cycling, this mode of operation must be avoided to maximize reliability. It is
always best to provide proper heatsinking (either by a physical plate or by airflow) to remain considerably below
the thermal shutdown threshold. For longest operational life of the device, keep the junction temperature below
125°C.
9.4 Device Functional Modes

A unique mode of the OPA454 is the output disable capability. This function conserves power during idle periods
(quiescent current drops to approximately 150 µA). This disable is accomplished without disturbing the input
signal path, not only saving power but also protecting the load. This feature makes disable useful for
implementing external fault shutdown loops.

OPA454
10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Applications Information

The OPA454 is a high-voltage, high-current operational amplifier capable of operating with supply voltages as
high as ±50 V, or as low as ±10 V. Its design and processing allows it to be used in applications where most
operational amplifiers cannot be used because of high-voltage power supply conditions, or as a result of the
need for very high-output voltage swing. The output is capable of swinging within a volt, to a few volts, of the
supply rails depending on the output current, which can be as much as ±50 mA. In addition, the OPA454
features input overvoltage protection, built-in output current limiting, thermal protection, and an output
enable/disable function.
10.1.1 Lowering Offset Voltage and Drift

The OPA454 can be used with an OPA735 zero-drift series op amp to create a high-voltage op amp circuit that
has very low input offset temperature drift. This circuit is shown in Figure 64.
Low Offset, 5mV, Drift, High-Voltage Op Amp
0.05mV/°C, Self-Zeroing Op Amp Gain 2nd = 9.45V/V
Gain 1st = 4.9V/V
R1, 2nd R2, 2nd
R1, 1st R2, 1st 10kW 84.5kW
10kW 39.1kW
V+
V+ 2nd Stage, +50V
1st Stage, +5V
VOUT 2nd Stage
VOUT 1st Stage
OPA454
OPA735 A2, 2nd Stage RLOAD
A1, 1st Stage 10kW
V-
VG = ±1V VOUT 1st Stage ±4.9V, Max 2nd Stage, -50V
V-
1st Stage, -5V VOUT 2nd Stage ±46V (92VPP), Max
VINPUT = ±1VPP
Figure 64. Two-Stage, High-Voltage Op Amp Circuit with Very Low Input Offset Temperature Drift

OPA454
Applications Information (continued)

10.1.2 Increasing Output Current
The OPA454 drives an output current of a few milliamps to greater than 50 mA while maintaining good op amp
performance. See Figure 6 for open-loop gain versus temperature at various output current levels.
In applications where the 25-mA output current is not sufficient to drive the required load, the output current can
be increased by connecting two or more OPA454s in parallel, as Figure 65 shows. Amplifier A1 is the master
amplifier and may be configured in virtually any op amp circuit. Amplifier A2, the slave, is configured as a unity-
gain buffer. Alternatively, external output transistors can be used to boost output current. The circuit in Figure 66
is capable of supplying output currents up to 1 A, with the transistors shown.
R1 R2
(1)
MASTER RS
10W
A1 OPA454
VIN
(1)
RS
10W
A2 OPA454
SLAVE RL
(1) RS resistors minimize the circulating current that always flows between the two devices because of VOS errors.
Figure 65. Parallel Amplifiers Increase Output Current Capability
R1 R2
+50V
NPN
TIP29C, MJL21194,
MJE15003, MJL3281
CF
R4
R3
(1) 0.2W
-IN V+
(2)
VOUT 20W
(3)
OPA454 VO = VOUT - ILRL
+IN
VIN
V- R5
RL IL
0.2W
PNP
TIP30C, MJL21193,
MJE15004, MJL1302A
-50V
(1) Provides current limit for OPA454 and allows the amplifier to drive the load when the output is between +0.7 V and –0.7 V.
(2) Op amp VOUT swings from +47 V to –48 V.
(3) VO swings from +44.1 V to –45.1 V at IL = 1 A.
Figure 66. External Output Transistors Boost Output Current Greater Than 1 A

OPA454
Applications Information (continued)

10.1.3 Unity-Gain Noninverting Configuration
When in the noninverting unity-gain configuration, the OPA454 has more gain peaking with increasing positive
common-mode voltage and increasing temperature. It has less gain peaking with more negative common-mode
voltage. As with all op amps, gain peaking increases with increasing capacitive load. A resistor and small
capacitor placed in the feedback path can reduce gain peaking and increase stability.
10.2 Typical Application

Figure 67 shows the OPA454 in a typical noninverting application with output voltage boost.
R10
10k
-100
R7
100k R6 C4
1M 10n
Status R11
Z2 Flg 100k
1N5229B E/D _
V-
-100
Vo2
E/D Com V+ +
U2 OPA454
R1 -100
10k
R12
R2 +V1 100k
190k
-V1
R4 R5
1M 100k
Status Z1
Flg E/D 1N5229B
_
V-
-V1
R3 + VLoad
+ V+ E/D Com
+ 3.75k
U3 OPA454 -
VG1
4.75 Vpk -V1
+V1
R13
+100 10k
R9
100k R8
1M
Z3 Status R14
1N5229B Flg 100k
E/D _
V-
Vo1
E/D Com V+ +
U1 OPA454
V2 100 V1 100 C5 R15

10n 100k
-100 +100
+100
Figure 67. OPA454 Noninverting, AV = 20 V/V, Output Voltage Boost
10.2.1 Design Requirements

Figure 67 shows an output voltage boost circuit where three OPA454 op amps connected as shown can produce
an output voltage swing as high as 195 VPP. The resulting output swing range is twice that attainable with a
single OPA454 device operating from ±50-V supplies, and is useful in applications where an even higher output
swing is required. A ±100-VDC power supply is required for this configuration.
Three of the design goals for this circuit are:
• A noninverting gain of 20 V/V (26 dB)
• A peak output voltage approaching 97.5 V, while delivering a peak output current of approximately 24 mA
• Correct biasing of the Enable/Disable (E/D), E/D Com, and Status flag pins

OPA454
Typical Application (continued)

10.2.2 Detailed Design Procedure
U3 (an OPA454) is the only amplifier of the three devices in the application that is responsible for signal
amplification. The other two op amps, U1 and U2, provide the positive and negative supply sources (respectively)
for U3. The voltage gain of U3 is that of a traditional noninverting op amp amplifier. A simple relation involving U3
feedback (R2) and input (R1) resistors sets the closed-loop gain, AV. Equation 1 shows this calculation.
V (R + R2) R2
AV = OUT = 1 =1+
VIN R1 R1
where
• R1 = 10 kΩ
• R2 = 190 kΩ
• AV = 20 V/V (1)
Applying this gain and a VPK of ±97.5 V, the maximum input voltage that may be applied without causing the
output to clip is ±4.75 V.
U1 and U2 are connected as unity-gain buffers. The purpose of this configuration is to track the U3 output
voltage, and then adjust the voltage levels at the U3 V+ and V– pins so that 100 V is maintained across them.
This input is accomplished by the U1 and U2 input connection to the U3 output voltage through the 100-kΩ
voltage dividers formed by R11, R12, and R14, R15. For example, as the output of U3 moves more positive, the
voltage on the U1 noninverting input moves up more closely to the +100-V supply level. Even though U2
provides the U1 V– supply, its output moves more positive as well. The result is that all the devices move
together in unison up and down, while maintaining the 100-V difference between the V+ and V– pins for U3.
Figure 68 shows how the U3 op amp output voltage VLOAD moves upward, becoming more positive, as the input
voltage VG1 increases from –4.75 V to 4.75 V. Figure 68 also shows VO1 and VO2, the U1 and U2 (respectively)
output voltages. The 100-V difference between the supply pins is evident in the graph. Notice how the U3 V+ pin
(VO1) allows 100 V greater than its V– pin (VO2).
100
80 VO1
60
Output Voltage (V)
40
100 V
20
VLOAD
0
-20
100 V
-40
VO2
-60
-80
-100
-5 -4 -3 -2 -1 0 1 2 3 4 5
VG1 Input Voltage (V)
Figure 68. OPA454 Output Voltage Levels vs VS1 Input Voltage

OPA454

Figure 69 shows the VLOAD output, a 195-VPP, 20-kHz sine wave, as developed across the 3.75-kΩ load resistor.
The peak current provided by the OPA454 U3 output is 26 mA. U1 and U2 alternately source and sink the output
current, in addition to the operating current required by U3.
100
75
V01
50
VLOAD
25
Voltage (V) 0
-25
V02
-50
-75
-100
Time (20ms/div)
Figure 69. Output Voltage Boost Develops 195-VPP VLOAD Across 3.75-kΩ Load Resistance
The output voltage booster may be used in an inverting configuration also. This use is easily accomplished by
applying the input signal to the input resistor R1 as seen in Figure 70. The noninverting input is grounded and the
ratio of feedback resistor R2 to R1 is set to 20:1 to satisfy the inverting gain equation given in Equation 2.
-V -R
AV = OUT = 2
VIN R1
where
• R1 = 10 kΩ
• R2 = 200 kΩ
• AV = –20 V/V (2)
R1 To Vo2 R2 To U2
10k 200k +IN
+V1
VG1 + 4.75 Vpk
-V1
R5
R4 100k
1M R12
100k
Status Z1
_ Flg E/D 1N5229B
V-
-V1
R3 + VLoad
+ V+ E/D Com 3.75k
U3 OPA454 -
R14
+V1 -V1 100k
To U1
To Vo1 +IN
Figure 70. OPA454 Output Boost Circuit Applied as an Inverting Amplifier

OPA454

10.2.3 Application Curve
Figure 71 shows an example of the inverting output boost amplifier output waveforms obtained from a TINA-TI
simulation.
T
100
50
Voltage (V) 0
-50 VG1
VLOAD
VO1
VO2
-100
0 25 50 75 100
Time (ms)
Figure 71. Voltage Levels in OPA454 Inverting Boost Amplifier Circuit from TINA-TI Simulation
10.3 System Examples

10.3.1 Basic Noninverting Amplifier
Figure 72 shows the OPA454 connected as a basic noninverting amplifier. The OPA454 can be used in virtually
any ±5-V to ±50-V op amp configuration. It is especially useful for supply voltages greater than 36 V.
Power-supply terminals must be bypassed with 0.1-μF (or greater) capacitors, located near the power-supply
pins. Be sure that the capacitors are appropriately rated for the power-supply voltage used.
V+
0.1mF IP
V+
(1) R2
R1 RP R2 G = 1+
R1
Status
V+
-IN Flag
VOUT
OPA454 VOUT
+IN E/D
VIN
E/D Com RL
V-
0.1mF
V- V-
(1) Pullup resistor with at least 10 μA (choose RP = 1 MΩ with V+ = 50 V for IP = 50 μA).
Figure 72. Basic Noninverting Amplifier Configuration

OPA454
System Examples (continued)

10.3.2 Programmable Voltage Source
Figure 73 illustrates the OPA454 in a programmable voltage source.
+95V
0.1mF
45.3kW
0-2mA V+
DAC8811 -IN
or
DAC7811 OPA454
+IN VOUT = 0V to +91V
Protects DAC
During Slewing V- RL
0.1mF
-5V
Figure 73. Programmable Voltage Source
10.3.3 Bridge Circuit

Figure 74 shows the OPA454 in a bridge circuit.
R1 R2 R3
1kW 9kW 10kW
R4
10kW
+50V +50V
Up To
-IN V+ 195V V+ -IN
VOUT VOUT
MASTER OPA454 OPA454 SLAVE
VIN +IN A1 A2 +IN
(1)
±4V V- Piezo V-
Crystal
-50V -50V
(1) For transducers with large capacitance, stabilization may become an issue. Be certain that the Master amplifier is stable before stabilizing
the Slave amplifier.
Figure 74. Bridge Circuit Doubles Voltage for Exciting Piezo Crystals
10.3.4 High-Compliance Voltage Current Sources

This section describes four different applications using high-compliance voltage current sources with differential
inputs. Figure 75 shows a high-voltage difference amplifier circuit. Figure 76 and Figure 78 illustrate the different
applications.
R1 R2
25kW 25kW
V1
OPA454 VOUT = V2 - V1
R3 R4
25kW 25kW
V2
Figure 75. High-Voltage Difference Amplifier

OPA454
25kW 25kW
V1
OPA454
A1
25kW 25kW R
V2 OPA454
A2
Load IO
IO = (V2 - V1)/R
Figure 76. Differential Input Voltage-to-Current Converter for Low IOUT
A red light emitting diode (LED) was used to generate Figure 77.
6V 14
12
VOUT
10
VOUT (1V/div)
VLED (V)
6
4
VLED
0V 2
-2V -2
5ms/div
Figure 77. Avalanche Photodiode Circuit
Gain of the avalanche photodiode (APD) is adjusted by changing the voltage across the APD. Gain starts to
increase when reverse voltage is increased beyond 130 V for this APD diode. See Figure 78.

OPA454
R7 R1
10kW 90kW
+100V
+100V
R2 R4
V+
V+ 1kW 100kW
OPA454
OPA454 A2
A1 V- +100V
V- VOUT = 100 ´ RSENSE ´ ID
V+
OPA454 VOUT +100V

+ A4
Gain Adjust Voltage RSENSE
V1 2.5V to 9.5V V-
100W +100V R8
R3 198kW
V+
1kW
OPA454 R9
A3
4.9kW
V- R5
100kW
LM4041D
Adjusted for 2.0V 100W
APD
LED VLED R10

3.1kW
-200V
Advanced Photonix, Inc.
SD 036-70-62-531
Example Circuit For Reverse Biasing APD Digi-Key
(130V to 280V, max) SD 036-70-62-531
Figure 78. APD Gain Adjustment Using the OPA454, High-Voltage Op Amp

OPA454

10.3.5 High-Voltage Instrumentation Amplifier
Figure 79 uses three OPA454s to create a high-voltage instrumentation amplifier. VCM ± VSIG must be between
(V–) + 2.5 V and (V+) – 2.5 V. The maximum supply voltage equals ±50 V or 100 V total.
V+
V1
OPA454
A1
R4 R5
V-
R2 V+
VSIG OPA454 VOUT

R1 (1)
A3
R2
V-
R6 R7
V+
OPA454
A2
V2 VOUT = (1 + 2R2/R1) (V2 - V1)
VCM V-
(1) The linear input range is limited by the output swing on the input amplifiers, A1 and A2.
Figure 79. High-Voltage Instrumentation Amplifier
Figure 80 uses three OPA454s to measure current in a high-side shunt application. VSUPPLY must be greater than
VCM. VCM must be between (V–) + 2.5 V and (V+) – 2.5 V. Adhering to these restrictions keeps V1 and V2 within
the voltage range required for linear operation of the OPA454. For example, if V+ = 50 V and V– = 50 V, then
V1 = +47.5 V (maximum) and V2 = –47.5 V (minimum). The maximum supply voltage equals ±50 V, or 100 V
total.
RSHUNT
V+
Plus V1 Load
VSUPPLY or
Minus
OPA454
(1)
A1
R4 R5
V-
R2 V+
OPA454 VOUT
R1 (2)
A3
R2
V-
R6 R7
V+
OPA454
(1)
A2
V2 VOUT = (1 + 2R2/R1) (V2 - V1)
V-
(1) To increase the linear input voltage range, configure A1 and A2 as unity-gain followers.
(2) The linear input range is limited by the output swing on the input amplifiers, A1 and A2.
Figure 80. High-Voltage Instrumentation Amplifier for Measuring High-Side Shunt

OPA454

Figure 81 shows an example circuit that uses the OPA454 in an output voltage boost configuration with six op
amp output stages.
+100V +100V
10kW 10kW
+120V +120V
100kW 100kW
V+ V+
OPA454 OPA454
A1 A4
V- V-
10kW 190kW 200kW 10kW
100kW 100kW
V+ RLOAD V+
(+97V, -98V) 7.5kW (-98V, +97V)
OPA454 OPA454
A3 A6
VLOAD
V- (±195V, 390VPP) V-
10kW 10kW
VIN
100kW 100kW
V+ V+
OPA454 OPA454
A2 A5
V- V-
100kW 100kW
-100V -100V
-100V -100V
Figure 81. Output Voltage Boost with ±195 V (390 VPP) Across Bridge-Tied Load
(Six Op Amps, see Figure 82 and Figure 83)
200 200 6
VLOAD
150 150
VIN VOUT 4
100 100
2
50 50
VOUT (V)
VOUT (V)
VIN (V)
0 0 0
-50 -50
-2
-100 -100
-4
-150 -150
-200 -200 -6
Figure 82. 390 VPP Across 7.5-kΩ Load SR of 34 V/ms, which is significantly higher than the specified 13
20 kHz, Uses Six OPA454s, 100-V Supplies V/ms due to tracking of the power-supply voltage
Figure 83. 7.5-kΩ Load, G = +20, Six OPA454s, 100-V
Supplies

OPA454
11 Power Supply Recommendations

The OPA454 may be operated from power supplies up to ±50 V or a total of 100 V with excellent performance.
Most behavior remains unchanged throughout the full operating voltage range. Parameters that vary significantly
with operating voltage are shown in Typical Characteristics.
Some applications do not require equal positive and negative output voltage swing. Power-supply voltages do
not need to be equal. The OPA454 can operate with as little as 10 V between the supplies and with up to 100 V
between the supplies. For example, the positive supply could be set to 90 V with the negative supply at –10 V, or
vice-versa (as long as the total is less than or equal to 100 V).
12 Layout
12.1 Layout Guidelines

12.1.1 Thermally-Enhanced PowerPAD Package
The OPA454 comes in an 8-pin SO with PowerPAD version that provides an extremely low thermal resistance
(θJC) path between the die and the exterior of the package. This package features an exposed thermal pad. This
thermal pad has direct thermal contact with the die; thus, excellent thermal performance is achieved by providing
a good thermal path away from the thermal pad.
The OPA454 SO-8 PowerPAD is a standard-size SO-8 package constructed using a downset leadframe upon
which the die is mounted, as Figure 84 shows. This arrangement results in the lead frame being exposed as a
thermal pad on the underside of the package. The thermal pad on the bottom of the IC can then be soldered
directly to the PCB, using the PCB as a heatsink. In addition, plated-through holes (vias) provide a low thermal
resistance heat flow path to the back side of the PCB. This architecture enhances the OPA454 power dissipation
capability significantly, eliminates the use of bulky heatsinks and slugs traditionally used in thermal packages,
and allows the OPA454 to be easily mounted using standard PCB assembly techniques.
NOTE
Because the SO-8 PowerPAD is pin-compatible with standard SO-8 packages, the
OPA454 is a drop-in replacement for operational amplifiers in existing sockets. Soldering
the PowerPAD to the PCB is always required, even with applications that have low power
dissipation. Soldering the device to the PCB provides the necessary thermal and
mechanical connection between the leadframe die pad and the PCB.
Leadframe (Copper Alloy)

IC (Silicon) Die Attach (Epoxy)
Leadframe Die Pad

Mold Compound (Plastic) Exposed at Base of the Package
(Copper Alloy)
Figure 84. Cross-Section View of a PowerPAD Package

OPA454
Layout Guidelines (continued)

12.1.2 PowerPAD Layout Guidelines
The PowerPAD package allows for both assembly and thermal management in one manufacturing operation.
During the surface-mount solder operation (when the leads are being soldered), the thermal pad must be
soldered to a copper area underneath the package. Through the use of thermal paths within this copper area,
heat can be conducted away from the package into either a ground plane or other heat-dissipating device.
Soldering the PowerPAD to the PCB is always required, even with applications that have low power dissipation.
Follow these steps to attach the device to the PCB:
1. The PowerPAD must be connected to the most negative supply voltage on the device, V–.
2. Prepare the PCB with a top-side etch pattern. There must be etching for the leads as well as etch for the
thermal pad.
3. Use of thermal vias improves heat dissipation, but are not required. The thermal pad can connect to the PCB
using an area equal to the pad size with no vias, but externally connected to V–.
4. Place recommended holes in the area of the thermal pad. Recommended thermal land size and thermal via
patterns for the SO-8 DDA package are shown in the thermal land pattern mechanical drawing appended at
the end of this document. These holes must be 13 mils (.013 in, or 0.3302 mm) in diameter. Keep them
small, so that solder wicking through the holes is not a problem during reflow. The minimum recommended
number of holes for the SO-8 PowerPAD package is five.
5. Additional vias may be placed anywhere along the thermal plane outside of the thermal pad area. These vias
help dissipate the heat generated by the OPA454 IC. These additional vias may be larger than the 13-mil
diameter vias directly under the thermal pad. They can be larger because they are not in the thermal pad
area to be soldered; thus, wicking is not a problem.
6. Connect all holes to the internal power plane of the correct voltage potential (V–).
7. When connecting these holes to the plane, do not use the typical web or spoke via connection methodology.
Web connections have a high thermal resistance connection that is useful for slowing the heat transfer during
soldering operations, making the soldering of vias that have plane connections easier. In this application,
however, low thermal resistance is desired for the most efficient heat transfer. Therefore, the holes under the
OPA454 PowerPAD package must make the connections to the internal plane with a complete connection
around the entire circumference of the plated-through hole.
8. The top-side solder mask must leave the terminals of the package and the thermal pad area exposed. The
bottom-side solder mask must cover the holes of the thermal pad area. This masking prevents solder from
being pulled away from the thermal pad area during the reflow process.
9. Apply solder paste to the exposed thermal pad area and all of the IC terminals.
10. With these preparatory steps in place, the PowerPAD IC is simply placed in position and run through the
solder reflow operation as any standard surface-mount component. This preparation results in a properly
installed part.
For detailed information on the PowerPAD package, including thermal modeling considerations and repair
procedures, see technical brief SLMA002 PowerPAD Thermally-Enhanced Package, available for download at
www.ti.com.

OPA454
12.2 Layout Example
E/D
Feedback Resistor
Gain Resistor
Bypass
Capacitor
E/D Com
IN typically V E/D Com E/D
or GND V+
IN V+
VOUT
+IN OUT
+IN
V Status
GND
Bypass
Capacitor
V GND
Figure 85. OPA454 Layout Example

OPA454
12.3 Thermal Protection

Figure 86 shows the thermal shutdown behavior of a socketed OPA454 that internally dissipates 1 W.
Unsoldered and in a socket, θJA of the DDA package is typically 128°C/W. With the socket at 25°C, the output
stage temperature rises to the shutdown temperature of 150°C, which triggers automatic thermal shutdown of the
device. The device remains in thermal shutdown (output is in a high-impedance state) until it cools to 130°C
where it again is powered. This thermal protection hysteresis feature typically prevents the amplifier from leaving
the safe operating area, even with a direct short from the output to ground or either supply. The rail-to-rail supply
voltage at which catastrophic breakdown occurs is typically 135 V at 25°C. However, the absolute maximum
specification is 120 V, and the OPA454 must not be allowed to exceed 120 V under any condition. Failure as a
result of breakdown, caused by spiking currents into inductive loads (particularly with elevated supply voltage), is
not prevented by the thermal protection architecture.
40 140
10kW 100kW
20 120
VOUT
+2.5V +50V
0 100
10Hz Square Wave
-20 80 RP
VFLAG (V)
VOUT (V)
-40 60 1MW
VFLAG
-60 40 -IN V+ Flag
VOUT
-80 20 VOUT
VFLAG +IN OPA454
E/D Com
-100 0
V- 625W
-120 -20
0 200 400 600 800 1000 -50V
(ms)
Figure 86. Thermal Shutdown
12.4 Power Dissipation

Power dissipation depends on power supply, signal, and load conditions. For DC signals, power dissipation is
equal to the product of the output current times the voltage across the conducting output transistor, PD = IL (VS –
VO). Power dissipation can be minimized by using the lowest possible power-supply voltage necessary to assure
the required output voltage swing.
For resistive loads, the maximum power dissipation occurs at a DC output voltage of one-half the power-supply
voltage. Dissipation with AC signals is lower because the root-mean square (RMS) value determines heating.
Application bulletin SBOA022 explains how to calculate or measure dissipation with unusual loads or signals. For
constant current source circuits, maximum power dissipation occurs at the minimum output voltage, as Figure 87
shows.
The OPA454 can supply output currents of 25 mA and larger. Supplying this amount of current presents no
problem for some op amps operating from ±15-V supplies. However, with high supply voltages, internal power
dissipation of the op amp can be quite high. Operation from a single power supply (or unbalanced power
supplies) can produce even greater power dissipation because a large voltage is impressed across the
conducting output transistor. Applications with high power dissipation may require a heatsink or a heat spreader.

OPA454
Power Dissipation (continued)
R1 R2
100kW 10kW
V1
+50V
-IN V+
VOUT
OPA454
+IN
V- R5
R3 R4
100kW 100W
-50V 9.9kW
V2
IL RL
IL = [(V2 - V1)/R5] (R2/R1)
= (V2 - V1)/1kW
Compliance Voltage Range = +47V, -48V
NOTE: R1 = R3 and R2 = R4 + R5.
Figure 87. Precision Voltage-to-Current Converter With Differential Inputs
12.5 Heatsinking
Power dissipated in the OPA454 causes the junction temperature to rise. For reliable operation, junction
temperature must be limited to 125°C, maximum. Maintaining a lower junction temperature always results in
higher reliability. Some applications require a heatsink to assure that the maximum operating junction
temperature is not exceeded. Junction temperature can be determined according to Equation 3:
TJ = TA + PDqJA (3)
Package thermal resistance, θJA, is affected by mounting techniques and environments. Poor air circulation and
use of sockets can significantly increase thermal resistance to the ambient environment. Many op amps placed
closely together also increase the surrounding temperature. Best thermal performance is achieved by soldering
the op amp onto a circuit board with wide printed circuit traces to allow greater conduction through the op amp
leads. Increasing circuit board copper area to approximately 0.5 in2 decreases thermal resistance; however,
minimal improvement occurs beyond 0.5 in2, as shown in Figure 88.
For additional information on determining heatsink requirements, consult Application Bulletin SBOA021 (available
for download at www.ti.com).
60
Thermal Resistance, qJA (°C/W)
50
40
30
20
10
0
0 0.5 1.0 1.5 2.0 2.5 3.0
2
Copper Area (inches ), 2 oz
Figure 88. Thermal Resistance vs Circuit Board Copper Area

OPA454
13 Device and Documentation Support
13.1 Device Support

13.1.1 Development Support
13.1.1.1 TINA-TI™ (Free Software Download)

TINA™ is a simple, powerful, and easy-to-use circuit simulation program based on a SPICE engine. TINA-TI™ is
a free, fully-functional version of the TINA software, preloaded with a library of macro models in addition to a
range of both passive and active models. TINA-TI provides all the conventional dc, transient, and frequency
domain analysis of SPICE, as well as additional design capabilities.
Available as a free download from the Analog eLab Design Center, TINA-TI offers extensive post-processing
capability that allows users to format results in a variety of ways. Virtual instruments offer the ability to select
input waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic quick-start tool.
NOTE
These files require that either the TINA software (from DesignSoft™) or TINA-TI software
be installed. Download the free TINA-TI software from the TINA-TI folder.
13.1.1.2 TI Precision Designs

TI Precision Designs are analog solutions created by TI’s precision analog applications experts and offer the
theory of operation, component selection, simulation, complete PCB schematic and layout, bill of materials, and
measured performance of many useful circuits. TI Precision Designs are available online at
http://www.ti.com/ww/en/analog/precision-designs/.
13.1.1.3 WEBENCH® Filter Designer

WEBENCH® Filter Designer is a simple, powerful, and easy-to-use active filter design program. The WEBENCH
Filter Designer lets you create optimized filter designs using a selection of TI operational amplifiers and passive
components from TI's vendor partners.
Available as a web-based tool from the WEBENCH® Design Center, WEBENCH® Filter Designer allows you to
design, optimize, and simulate complete multistage active filter solutions within minutes.
13.2 Documentation Support

13.2.1 Related Documentation
The following documents are relevant to using the OPA454, and recommended for reference. All are available for
download at www.ti.com unless otherwise noted.
• Application bulletin AB-038: Heat Sinking—TO-3 Thermal Model, SBOA021
• Application bulletin AB-039: Power Amplifier Stress and Power Handling Limitations, SBOA022
• Application bulletin AB-045: Op Amp Performance Analysis, SBOA054
• Application bulletin AB-067: Single-Supply Operation of Operational Amplifiers, SBOA059
• Application bulletin AB-105: Tuning in Amplifiers, SBOA067.
• Technical brief: PowerPAD Thermally-Enhanced Package, SLMA002.

OPA454
13.3 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
13.4 Trademarks
PowerPAD, TINA-TI, E2E are trademarks of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
TINA, DesignSoft are trademarks of DesignSoft, Inc.
All other trademarks are the property of their respective owners.
13.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

PACKAGE OPTION ADDENDUM
www.ti.com 6-Feb-2020
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)
OPA454AIDDA ACTIVE SO PowerPAD DDA 8 75 Green (RoHS NIPDAU Level-2-260C-1 YEAR -55 to 125 OPA454
& no Sb/Br)
OPA454AIDDAG4 ACTIVE SO PowerPAD DDA 8 75 Green (RoHS NIPDAU Level-2-260C-1 YEAR -55 to 125 OPA454
& no Sb/Br)
OPA454AIDDAR ACTIVE SO PowerPAD DDA 8 2500 Green (RoHS NIPDAU Level-2-260C-1 YEAR -55 to 125 OPA454
& no Sb/Br)
OPA454AIDDARG4 ACTIVE SO PowerPAD DDA 8 2500 Green (RoHS NIPDAU Level-2-260C-1 YEAR -55 to 125 OPA454
& no Sb/Br)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 6-Feb-2020
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 3-Aug-2017
TAPE AND REEL INFORMATION
*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
OPA454AIDDAR SO DDA 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
Power
PAD
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 3-Aug-2017
*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
OPA454AIDDAR SO PowerPAD DDA 8 2500 367.0 367.0 35.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
DDA 8 PowerPAD TM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4202561/G
PACKAGE OUTLINE
DDA0008J SCALE 2.400
PowerPAD TM SOIC - 1.7 mm max height
C
6.2
TYP SEATING PLANE
5.8
A PIN 1 ID
AREA 0.1 C
6X 1.27
8
1
5.0 2X
4.8 3.81
NOTE 3
4
5
0.51
8X
4.0 0.31
B 1.7 MAX
3.8 0.1 C A B
NOTE 4
0.25
TYP
0.10
SEE DETAIL A
4 5
EXPOSED
THERMAL PAD
3.1 0.25
2.5 GAGE PLANE
0.15
0 -8 1.27 0.00
1 8
0.40
DETAIL A
2.6 TYPICAL
2.0
4221637/B 03/2016
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MS-012, variation BA.
www.ti.com
EXAMPLE BOARD LAYOUT
DDA0008J PowerPAD TM SOIC - 1.7 mm max height
(2.95)
NOTE 9
SOLDER MASK
(2.6) DEFINED PAD
SOLDER MASK
OPENING
8X (1.55) SEE DETAILS
1
8
8X (0.6)
(3.1)
SYMM SOLDER MASK
(1.3) OPENING
TYP (4.9)
NOTE 9
6X (1.27)
5
4
( 0.2) TYP
VIA SYMM METAL COVERED
BY SOLDER MASK
(1.3) TYP
(5.4)
LAND PATTERN EXAMPLE

SCALE:10X
0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND
SOLDER MASK METAL SOLDER MASK METAL UNDER

OPENING OPENING SOLDER MASK
NON SOLDER MASK SOLDER MASK

DEFINED DEFINED
SOLDER MASK DETAILS
4221637/B 03/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.
www.ti.com
EXAMPLE STENCIL DESIGN
DDA0008J PowerPAD TM SOIC - 1.7 mm max height
(2.6)
BASED ON
0.125 THICK
STENCIL
8X (1.55)
1
8
8X (0.6)
(3.1)
SYMM
BASED ON
0.127 THICK
STENCIL
6X (1.27)
5
4
METAL COVERED SEE TABLE FOR

SYMM DIFFERENT OPENINGS
BY SOLDER MASK
FOR OTHER STENCIL
THICKNESSES
(5.4)
SOLDER PASTE EXAMPLE

EXPOSED PAD
100% PRINTED SOLDER COVERAGE BY AREA
SCALE:10X
STENCIL SOLDER STENCIL

THICKNESS OPENING
0.1 2.91 X 3.47
0.125 2.6 X 3.1 (SHOWN)
0.150 2.37 X 2.83
0.175 2.20 X 2.62
4221637/B 03/2016
NOTES: (continued)
10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
11. Board assembly site may have different recommendations for stencil design.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third
party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims,
damages, costs, losses, and liabilities arising out of your use of these resources.
TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on
ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable
warranties or warranty disclaimers for TI products.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2020, Texas Instruments Incorporated

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E/D Com (Enable/Disable Common) 1 8 E/D (Enable/Disable)

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7.2 ESD Ratings

7.3 Recommended Operating Conditions

7.4 Thermal Information

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7.5 Electrical Characteristics: VS = ±50 V

CMRR Common-mode rejection At TA = –40°C to +85°C,

(V–) + 1 V < VO < (V+) – 1 V, 100 130 dB

Open-loop (V–) + 1 V < VO < (V+) – 2 V, 100 115 dB

(V–) + 2 V < VO < (V+) – 3 V, 80 102 dB

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Electrical Characteristics: VS = ±50 V (continued)

Output Output capacitance 18 pF

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7.6 Typical Characteristics

Phase Margin (°)

Open-Loop Output Impedance (W)

Figure 3. Unity-Gain Bandwidth vs Temperature Figure 4. Open-Loop Output Impedance vs Frequency

VS = ±15V 100 VOUT = ±49V (dc)

Figure 5. Open-Loop Gain vs Peak-Load Current Figure 6. Open-Loop Gain vs Temperature

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Typical Characteristics (continued)

PSRR and CMRR (dB)

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Typical Characteristics (continued)

Offset Voltage Shift (mV)

0 10 20 30 40 50 60 70 80 90 100 110 120

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Typical Characteristics (continued)

Shutdown Current (mA)

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Typical Characteristics (continued)

Slew Rate (V/ms)

TJ (+125°C max) = TA + [(|VS| - |VO|) IO ´ qJA] 11

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Typical Characteristics (continued)

Time (1ms/div) Time (1ms/div)

Time (2.5ms/div) Time (500ns/div)

Figure 35. Step Response Figure 36. Gain Peaking vs CLOAD

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Typical Characteristics (continued)

Figure 37. Gain Peaking vs CLOAD Figure 38. Gain of +1 vs Frequency

Voltage at V1 and V2 (V)

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Typical Characteristics (continued)

50V/div Status Flag 50V/div Status Flag

Enable 5V/div Enable

Time (1ms/div) Time (1ms/div)