OPA857 Ultralow-Noise, Wideband, Selectable-Feedback Resistance Transimpedance Amplifier
OPA857 Ultralow-Noise, Wideband, Selectable-Feedback Resistance Transimpedance Amplifier
OPA857
SBOS630D – DECEMBER 2013 – REVISED AUGUST 2016
TIA
RF2
RF1
25 W OUT
IN
25 W OUTN
TEST CLAMP
Test_SD
1:1 Clamping REF
Circuit
2 kW
Test_IN
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
OPA857
SBOS630D – DECEMBER 2013 – REVISED AUGUST 2016 www.ti.com
Table of Contents
1 Features .................................................................. 1 8 Application and Implementation ........................ 18
2 Applications ........................................................... 1 8.1 Application Information............................................ 18
3 Description ............................................................. 1 8.2 Typical Application ................................................. 18
4 Revision History..................................................... 2 9 Power-Supply Recommendations...................... 23
5 Pin Configuration and Functions ......................... 4 10 Layout................................................................... 23
6 Specifications......................................................... 5 10.1 Layout Guidelines ................................................. 23
6.1 Absolute Maximum Ratings ..................................... 5 10.2 Layout Example .................................................... 24
6.2 ESD Ratings.............................................................. 5 11 Device and Documentation Support ................. 25
6.3 Recommended Operating Conditions....................... 5 11.1 Device Support...................................................... 25
6.4 Thermal Information .................................................. 5 11.2 Documentation Support ........................................ 25
6.5 Electrical Characteristics........................................... 6 11.3 Receiving Notification of Documentation Updates 25
6.6 Typical Characteristics .............................................. 8 11.4 Community Resources.......................................... 25
7 Detailed Description ............................................ 14 11.5 Trademarks ........................................................... 25
7.1 Overview ................................................................. 14 11.6 Electrostatic Discharge Caution ............................ 26
7.2 Functional Block Diagram ....................................... 14 11.7 Glossary ................................................................ 26
7.3 Feature Description................................................. 15 12 Mechanical, Packaging, and Orderable
7.4 Device Functional Modes........................................ 17 Information ........................................................... 26
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
• Changed document format to meet new data sheet standards; added Handling Ratings and Device and
Documentation Support sections, and moved existing sections ............................................................................................ 1
• Changed OUTN to OUT in Output Voltage Swing parameter test conditions ....................................................................... 6
• Changed Functional Block Diagram .................................................................................................................................... 14
RGT Package
16-Pin VQFN
Top View
Test_SD
Test_IN
NC
IN
16
15
14
13
GND 1 12 GND
CTRL 2 11 +VS
Thermal
GND 3 Pad 10 +VS
GND 4 9 +VS
5
8
OUTN
GND
GND
OUT
Not to scale
Pin Functions
PIN
I/O DESCRIPTION
NAME NO.
Control pin for transimpedance gain.
CTRL 2 I
GND, logic 0 = 5-kΩ internal resistance; +VS, logic 1 = 20-kΩ internal resistance.
GND 1, 3, 4, 6, 7, 12 I Ground
IN 15 I Input
NC 16 — Not connected
OUT 8 O Signal output
OUTN 5 O Common-mode voltage output reference
Test_IN 14 I Test mode input. Connect to +VS during normal operation.
Test_SD 13 I Test mode enable. Connect to GND for normal operation, and connect to +VS to enable test mode.
+VS 9, 10, 11 I Supply voltage
6 Specifications
6.1 Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
Supply voltage, VS– to VS+ 3.8
Voltage Input and output voltage, VIN, VOUT pins (VS–) – 0.7 (VS+) + 0.7 V
Differential input voltage 1
Output current 50
Current mA
Input current, VIN pin 10
Continuous power dissipation See Thermal Information table
Maximum junction, TJ 150
Maximum junction, TJ (continuous operation, long-term reliability) 140
Temperature °C
Operating free-air, TA –40 85
Storage, Tstg –65 150
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report (SPRA953).
3 3
2 0
Normalized Gain (dB:)
0 -6
-1 -9
-2 -12
100 :
500 : -40qC
-3 1 k: -15 25qC
5 k: 85qC
-4 -18
1M 10M 100M 1M 10M 100M 500M
Frequency (Hz) D001
Frequency (Hz) D002
TZ Gain = 20 kΩ TZ Gain = 20 kΩ
2 0
Normalized Gain (dB:)
Normalized Gain (dB:)
1 -3
0 -6
-1 -9
-2 -12
100 :
500 : -40qC
-3 1 k: -15 25qC
5 k: 85qC
-4 -18
1M 10M 100M 1M 10M 100M 500M
Frequency (Hz) D003
Frequency (Hz) D004
TZ Gain = 5 kΩ TZ Gain = 5 kΩ
0 0
Output Voltage (V)
-0.25 -0.25
-0.5 -0.5
-0.75 -0.75
-1 -1
-1.25 -1.25
Time (50 ns/div) Time (50 ns/div)
D005 D006
TZ Gain = 20 kΩ TZ Gain = 5 kΩ
25 25
20 20
15 15
Figure 7. RMS Input-Referred Current Noise Figure 8. RMS Input-Referred Current Noise
vs Temperature vs Supply Voltage
100 100
Input-Referred Current Noise (nARMS)
60 60
40 40
20 20
2 2
Normalized Gain (dB:)
1 1
0 0
-1 -1
-2 Parasitic -2 Parasitic
1.5 pF 1.5 pF
4.7 pF 4.7 pF
-3 10 pF -3 10 pF
22 pF 22 pF
-4 -4
1M 10M 100M 1M 10M 100M
Frequency (Hz) D011
Frequency (Hz) D012
TZ Gain = 20 kΩ TZ Gain = 5 kΩ
Figure 11. Gain Frequency Response vs Figure 12. Gain Frequency Response vs
Input Capacitance Input Capacitance
1.6 1.6
1.2 1.2
Output Voltage (V)
0.4 0.4
0 0
TZ Gain = 20 kΩ TZ Gain = 5 kΩ
PSRR (dB)
±40 ±40
±50 ±50
±60 ±60
-40ƒC -40ƒC
±70 ±70
+0ƒC +0ƒC
±80 +25ƒC ±80 +25ƒC
±90 +70ƒC ±90 +70ƒC
+105ƒC +105ƒC
±100 ±100
0.001 0.01 0.1 1 10 100 1000 0.001 0.01 0.1 1 10 100 1000
Frequency (MHz) C014 Frequency (MHz) C015
Figure 15. Power-Supply Rejection Ratio Figure 16. Power-Supply Rejection Ratio
vs Frequency vs Frequency
25 -50
Source HD2
Sink -55 HD3
20
Harmonic Distortion (dBc)
-60
Output Current (mA)
15 -65
-70
10
-75
5 -80
-85
0
-50 -25 0 25 50 75 100 125 -90
Temperature (ƒC) C016
1M 10M 100M
Frequency (Hz) D018
-65 -65
-70 -70
-75 -75
-80 -80
-85 -85
-90 -90
1M 10M 100M 0 0.25 0.5 0.75 1 1.25
Frequency (Hz) D019 Output Voltage (V) D020
Figure 19. Harmonic Distortion vs Frequency Figure 20. Harmonic Distortion vs Output Voltage
-50 -50
HD2 HD2
-55 HD3 -55 HD3
Harmonic Distortion (dBc)
-65 -65
-70 -70
-75 -75
-80 -80
-85 -85
-90 -90
0 0.25 0.5 0.75 1 1.25 0 1000 2000 3000 4000 5000 6000
Output Voltage (V) D021 Output Load (:) D022
Figure 21. Harmonic Distortion vs Output Voltage Figure 22. Harmonic Distortion vs RLOAD
-50 -50
HD2 HD2
-55 HD3 -55 HD3
Harmonic Distortion (dBc)
-60 -60
-65 -65
-70 -70
-75 -75
-80 -80
-85 -85
-90 -90
0 1000 2000 3000 4000 5000 6000 2.5 2.7 2.9 3.1 3.3 3.5 3.7
Output Load (:) D023 Supply Voltage (V) D024
Figure 23. Harmonic Distortion vs RLOAD Figure 24. Harmonic Distortion vs Supply Voltage
-60 10 pF
22 pF
10
-65
-70
-75
1
-80
-85
-90 0.1
2.5 2.7 2.9 3.1 3.3 3.5 3.7 1M 10M 100M 1G
Supply Voltage (V) D025 Frequency (Hz) D026
Figure 25. Harmonic Distortion vs Supply Voltage Figure 26. Input-Referred Current Noise Density vs
Frequency
100 2500
No Cap
Input Referred Current Noise (pA/—Hz)
1.5 pF
4.7 pF 2000
10 pF
22 pF
10
1500
Count
1000
1
500
0.1 0
22.2
22.5
22.8
23.1
23.4
23.8
24.1
24.4
24.7
25.0
25.3
25.7
26.0
26.3
26.6
26.9
<21.9
>27.2
1M 10M 100M 1G
Frequency (Hz) D027
Quiescent Current (mA) C027
TZ Gain = 20 kΩ TZ Gain = 20 kΩ
23.5
2000
Quiescent Current (mA)
23.4
1500
23.3
Count
1000 23.2
23.1
500
23
5 kΩ
20 kΩ
0 22.9
22.0
22.3
22.7
23.0
23.4
23.7
24.0
24.4
24.7
25.1
25.4
25.7
26.1
26.4
26.8
27.1
<21.7
>27.4
TZ Gain = 5 kΩ
24
2500
Quiescent Current (mA)
22
2000
20
Count
18 1500
16
1000
14
500
12 5 kΩ
20 kΩ
10 0
>5
0.3
0.9
1.5
2.1
2.7
3.3
3.9
4.5
<-5
-4.5
-3.9
-3.3
-2.7
-2.1
-1.5
-0.9
-0.3
2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
Supply Voltage (V) C030 Output Offset Voltage (mV)
C031
TZ Gain = 5 kΩ
Figure 31. Quiescent Current vs Supply Voltage Figure 32. Differential VOSO Histogram
3500 0.6
5 kΩ
20 kΩ
3000 Output Offset Voltage (mV) 0.4
Same Characteristic Unit
2500
0.2
2000
Count
0
1500
–0.2
1000
500 –0.4
0 –0.6
>6
0.4
1.1
1.8
2.5
3.2
4.0
4.7
5.4
<-6
-5.4
-4.7
-4.0
-3.2
-2.5
-1.8
-1.1
-0.4
C032
TZ Gain = 20 kΩ
Figure 33. Differential VOSO Histogram Figure 34. Output Offset Voltage vs Temperature
4500
1.89 Characteristic unit
4000
1.87
Reference Voltage (mV)
3500
3000 1.85
2500
Count
1.83
2000
1.81
1500
1.79
1000
500 1.77
0 1.75
>1.9
<1.76
1.767
1.775
1.784
1.792
1.801
1.809
1.817
1.826
1.834
1.843
1.851
1.859
1.868
1.876
1.885
1.893
Figure 35. Reference Voltage (VOUTN) Distribution Histogram Figure 36. Reference Voltage (VOUTN) vs Temperature
7 Detailed Description
7.1 Overview
The OPA857 provides a unique combination of low-noise, high-bandwidth, and high-transimpedance gain. The
amplifier is optimized to achieve greater than 100-MHz bandwidth on either the 5-kΩ or 20-kΩ transimpedance
gain for the lowest possible RMS noise on the output for a targeted low input capacitance of
1.5 pF. Note that this 1.5-pF capacitance includes the board parasitic; thus, great attention must be placed on
minimizing stray capacitance in the layout. This value is selected because the device is expected to be driven by
a photodiode with biasing high enough to include the photodiode capacitance contribution between
approximately 0.5 pF and 0.7 pF, leaving between 0.8 pF to 1 pF for the external parasitic.
The OPA857 is a dedicated transimpedance amplifier with a pseudo-differential output. A block diagram is
provided in the Functional Block Diagram section.
There are four distinct blocks in this diagram: a transimpedance amplifier (TIA), a reference voltage (REF), a test
structure (TEST), and an internal clamping circuit (CLAMP).
The TIA block of the Functional Block Diagram includes two selectable gain configurations: RF1 and RF2. For a
500-Ω load, including the GND alternatives resulting from the internal 25-Ω series resistor on each output, the
resulting gain is 4.5 kΩ or 18.2 kΩ. The TIA block is designed to provide excellent bandwidth (> 100 MHz) in both
gain configurations with the lowest possible RMS noise over the entire bandwidth. This level of performance is
achieved by minimizing the noise gain peaking at higher frequencies. The noise gain peaking resulting from
feedback and source capacitance is the main noise contributor in high-speed transimpedance amplifiers.
The reference voltage block of the Functional Block Diagram has several purposes: this block provides an
adequate dc reference voltage to the input, and provides a dc reference at the output (thus allowing the dc-
coupled solution to interface to a fully-differential signal chain). The CMRR provided by the fully-differential signal
chain reduces any feedthrough from the OPA857 power supply, thereby increasing the PSRR of the amplifier.
The test structure block is available on the pinout, but the main purpose of this structure is to allow the device
characterization to proceed as smoothly as possible.
The internal clamping circuit block and ESD diodes on the IN pin are used for internal protection and to make
sure that the amplifier can recover quickly after saturation.
These blocks are each described in further detail in the Feature Description section.
TIA
RF2
RF1
25 W OUT
IN
25 W OUTN
TEST CLAMP
Test_SD
1:1 Clamping REF
Circuit
2 kW
Test_IN
Test_SD
IN
Test_IN 2 kW
+VS
When using a photodiode, make sure that this source is turned off completely. This test structure is not intended
to be used as a output dc-control voltage.
+VCC
External Internal
Pin Circuitry
−VCC
These diodes provide moderate protection to input overdrive voltages above the supplies as well. The protection
diodes can typically support 30-mA continuous current. Use additional external low-capacitance protection where
higher currents are possible.
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Set an adequate dc voltage at the input to make sure that the output is operating within normal operation. At
minimum, the output of the TIA block must be set to 5/9th of the supply voltage in preparation for a pulse
configuration. For sine-wave operation, as required when measuring a frequency response, set the dc voltage on
the OUT pin to allow the full sine-wave amplitude and avoid clipping. In such a case, the OUT pin voltage is set
lower than 5/9th of the supply voltage.
Note that the 2-kΩ internal resistance used for the V-to-I conversion is not trimmed and can vary ±15% with
process. Therefore, the source must be capable of sourcing both dc and ac voltages to make sure that the output
voltage swing is compliant with the class-A output stage of the TIA block. Any change in the test circuit
configuration (such as gain change) requires a new calibration of the internal V-to-I converter.
Again if a photodiode is used, the internal V-to-I converter must be shut off completely. Failure to do so results in
degraded performance and higher than normal quiescent current.
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
2k
OPA857
374 50 1k
± ±
+ + VREF ADC34J45
Bias 374 50 1k
Reference
2k
1 400P
125 mV 125 mV
250 mV 250 mV
350P
500 mV 500 mV
950 mV 1V
100m
300P
250P
10m
200P
150P
1m
100P
50P
100P
10P -50P
0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 2.75 3 3.25 3.5 3.75 4 0 1 2 3 4 5 6 7 8 9 10
Time (Ps) Time (Ps) D005
D004
TZ Gain = 20 kΩ TZ Gain = 20 kΩ
Figure 40. Pulse Response vs Output Voltage Figure 41. Long-Term Settling Response vs Output
Voltage
1 400P
125 mV 125 mV
250 mV 250 mV
350P
500 mV 500 mV
950 mV 1V
100m
300P
250P
Output Voltage (V)
Output Voltage (V)
10m
200P
150P
1m
100P
50P
100P
0P
10P -50P
0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 2.75 3 3.25 3.5 3.75 4 0 1 2 3 4 5 6 7 8 9 10
Time (Ps) Time (Ps) D007
D006
TZ Gain = 5 kΩ TZ Gain = 5 kΩ
Figure 42. Pulse Response vs Output Voltage Figure 43. Long-Term Settling Response vs Output
Voltage
External RF
TIA
RF2
VBIAS
RF1
± 25
IN + OUT
25
OUTN
CLAMP
Test_SD
REF
Clamping
TEST
Cicuit
1:1
2k
Test_In
4 2
RF(Internal) = 20 k:, RF || CF(External) = 6.8 k: || 0.1 pF
3 1.5 RF(Internal) = 5 k:, RF || CF(External) = 6.8 k: || 0.1 pF
2 1
1 0.5
Output (dB)
Output (dB)
0 0
-1 -0.5
-2 -1
Figure 45. Frequency Response With External Feedback Figure 46. Frequency Response With External Feedback
4
RF(Internal) = 20 k:, RF || CF(External) = 6.8 k: || 0.1 pF
3 RF(Internal) = 5 k:, RF || CF(External) = 6.8 k: || 0.1 pF
1
Output (dB)
-1
-2
-3
-4
1M 10M 100M 1G
Frequency (Hz) D007
RF = 6.8 kΩ, CF = 0.1 pF
9 Power-Supply Recommendations
Use a linear power supply with good PSRR. For a good, high-frequency, power-supply bypass, use a ceramic
capacitor connected as close as possible to the +VS pin.
10 Layout
10-nF
Bypass Capacitor
100-nF
Bypass Capacitor
C2 and C3
as Close as Possible
< 0.25"
to +Vs and GND Pins
Test_SD OUT
Test_IN GND
IN GND
NC OUTN
Open Planes to
Minimize Parasitic CTRL
Input Capacitance
The EVM can be requested at the Texas Instruments web site (www.ti.com) through the OPA857 product folder.
11.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
www.ti.com 10-Dec-2020
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)
OPA857IRGTR ACTIVE VQFN RGT 16 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 OPA857
OPA857IRGTT ACTIVE VQFN RGT 16 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 OPA857
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 11-Aug-2017
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 11-Aug-2017
Pack Materials-Page 2
PACKAGE OUTLINE
RGT0016A SCALE 3.600
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
3.1 B
A
2.9
1 MAX C
SEATING PLANE
0.05 0.08
0.00
1.45 0.1
(0.2) TYP
5 8
EXPOSED
THERMAL PAD
12X 0.5 4
9
4X SYMM
17
1.5
1
12
0.30
16X
0.18
16 13 0.1 C A B
PIN 1 ID SYMM
(OPTIONAL) 0.05
0.5
16X
0.3
4219032/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
4. Reference JEDEC registration MO-220
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EXAMPLE BOARD LAYOUT
RGT0016A VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
( 1.45)
SYMM
16 13
16X (0.6)
1
12
16X (0.24)
17 SYMM
(0.475) (2.8)
TYP
12X (0.5)
9
4
( 0.2) TYP
VIA
5 8
(R0.05) (0.475) TYP
ALL PAD CORNERS
(2.8)
SOLDER MASK
METAL OPENING
EXPOSED METAL
EXPOSED METAL
SOLDER MASK METAL UNDER
OPENING SOLDER MASK
NOTES: (continued)
5. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
6. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
RGT0016A VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
( 1.34)
16 13
16X (0.6)
1
12
16X (0.24)
17 SYMM
(2.8)
12X (0.5)
9
4
METAL
ALL AROUND
5 8
SYMM
(R0.05) TYP
(2.8)
4219032/A 02/2017
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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