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OPA357, OPA2357
SBOS235F – MARCH 2002 – REVISED APRIL 2018

OPAx357 250-MHz, Rail-to-Rail I/O, CMOS Operational Amplifier With Shutdown

1 Features 3 Description
•
1 Unity-Gain Bandwidth: 250 MHz The OPA357 series of high-speed, voltage-feedback
CMOS operational amplifiers is designed for video
• Wide Bandwidth: 100-MHz GBW and other applications requiring wide bandwidth.
• High Slew Rate: 150 V/µs These devices are unity-gain stable and can drive
• Low Noise: 6.5 nV/√Hz large output currents. Differential gain is 0.02% and
• Rail-to-Rail I/O differential phase is 0.09°. Quiescent current is only
4.9 mA per channel.
• High Output Current: > 100 mA
The OPA357 series of op amps is optimized for
• Excellent Video Performance:
operation on single or dual supplies as low as 2.5 V
– Differential Gain: 0.02%, Differential Phase: (±1.25 V) and up to 5.5 V (±2.75 V). Common-mode
0.09° input range extends beyond the supplies. The output
– 0.1-dB Gain Flatness: 40 MHz swing is within 100 mV of the rails, supporting wide
dynamic range.
• Low Input Bias Current: 3 pA
• Quiescent Current: 4.9 mA The single version (OPA357) comes in the miniature
SOT23-6 package. The dual version (OPA2357) is
• Thermal Shutdown
offered in the VSSOP-10 package.
• Supply Range: 2.5 V to 5.5 V
The dual version features completely independent
• Shutdown IQ < 6 µA circuitry for lowest crosstalk and freedom from
• MicroSIZE Package interaction. Both versions are specified over the
• Create a Custom Design Using the OPA357 With extended –40°C to +125°C temperature range.
the WEBENCH® Power Designer
Device Information(1)
2 Applications PART NUMBER PACKAGE BODY SIZE (NOM)
OPA357 SOT23 (6) 2.90 mm × 1.60 mm
• Video Processing
OPA2357 VSSOP (10) 3.00 mm × 3.00 mm
• Ultrasound
(1) For all available packages, see the orderable addendum at
• Optical Networking, Tunable Lasers the end of the data sheet.
• Photodiode Transimpedance Amplifiers
• Active Filters
• High-Speed Integrators
• Analog-to-Digital (A/D) Converter Input Buffers
• Digital-to-Analog (D/A) Converter Output
Amplifiers
• Barcode Scanners
• Communications
Simplified Schematic
V+

-VIN

OPA357 VOUT
+VIN

V- Enable

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features .................................................................. 1 8 Application and Implementation ........................ 20
2 Applications ........................................................... 1 8.1 Application Information............................................ 20
3 Description ............................................................. 1 8.2 Typical Applications ............................................... 20
4 Revision History..................................................... 2 9 Power Supply Recommendations...................... 26
5 Pin Configuration and Functions ......................... 3 9.1 Power Dissipation ................................................... 26
6 Specifications......................................................... 4 10 Layout................................................................... 26
6.1 Absolute Maximum Ratings ...................................... 4 10.1 Layout Guidelines ................................................. 26
6.2 ESD Ratings.............................................................. 4 10.2 Layout Example .................................................... 26
6.3 Recommended Operating Conditions....................... 4 11 Device and Documentation Support ................. 27
6.4 Thermal Information .................................................. 4 11.1 Device Support...................................................... 27
6.5 Electrical Characteristics: VS = +2.7-V to +5.5-V 11.2 Documentation Support ........................................ 27
Single-Supply ............................................................. 5 11.3 Related Links ........................................................ 27
6.6 Typical Characteristics .............................................. 7 11.4 Receiving Notification of Documentation Updates 27
7 Detailed Description ............................................ 13 11.5 Community Resources.......................................... 28
7.1 Overview ................................................................. 13 11.6 Trademarks ........................................................... 28
7.2 Functional Block Diagram ....................................... 13 11.7 Electrostatic Discharge Caution ............................ 28
7.3 Feature Description................................................. 14 11.8 Glossary ................................................................ 28
7.4 Device Functional Modes........................................ 19 12 Mechanical, Packaging, and Orderable
Information ........................................................... 28

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision E (May 2009) to Revision F Page

• Added Device Information table, Pin Functions table, ESD Ratings table, Recommended Operating Conditions
table, Thermal Information table, Overview section, Functional Block Diagram section, Feature Description section,
Device Functional Modes section, Application and Implementation section, Power Supply Recommendations
section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable
Information section ................................................................................................................................................................ 1
• Changed MSOP to VSSOP throughout document ................................................................................................................ 1
• Deleted DDA package (SO-8 PowerPAD) from document ................................................................................................... 1
• Changed MSOP to VSSOP throughout document ................................................................................................................ 1
• Added WEBENCH Features bullet ........................................................................................................................................ 1
• Deleted OADI from DBV pin drawing ..................................................................................................................................... 3
• Deleted Package/Ordering Information table ......................................................................................................................... 4
• Deleted footnote from Signal input pins parameter in Absolute Maximum Ratings table ...................................................... 4
• Changed Temperature Range section of Electrical Characteristics table: changed θJA to RθJA and deleted Specified
range, Operating range, and Storage range parameters ....................................................................................................... 6
• Added OPAx357 Comparison section and moved OPAx357 Related Products table to this section from page 1 ............. 14
• Deleted first paragraph of Power Dissipation section........................................................................................................... 26
• Changed PCB Layout title to Layout Guidelines .................................................................................................................. 26
• Deleted PowerPAD Thermall Enhanced Package and PowerPAD Assembly Process sections......................................... 26
• Added Custom Design With WEBENCH® Tools section ..................................................................................................... 27

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5 Pin Configuration and Functions

OPA357: DBV Package OPA2357: DGS Package

6-Pin SOT-23 10-Pin VSSOP
Top View Top View

Out 1 6 V+ Out A 1 10 V+

V- 2 5 Enable -In A 2 9 Out B

A
+In 3 4 -In +In A 3 8 -In B
B
V- 4 7 +In B

Enable A 5 6 Enable B

(1) Pin 1 of the SOT23-6 is determined by orienting the package marking as indicated in the diagram.

Pin Functions
PIN
DBV DGS I/O DESCRIPTION
NAME
(SOT-23) (VSSOP)
Amplifier power down.
Enable 5 — —
Low = disabled, high = normal operation (pin must be driven).
Amplifier power down, channel A.
Enable A — 5 —
Low = disabled, high = normal operation (pin must be driven).
Amplifier power down, channel B.
Enable B — 6 —
Low = disabled, high = normal operation (pin must be driven).
–In 4 — I Inverting input pin
–In A — 2 I Inverting input pin, channel A
–In B — 8 I Inverting input pin, channel B
+In 3 — I Noninverting input pin
+In A — 3 I Noninverting input pin, channel A
+In B — 7 I Noninverting input pin, channel B
Out 1 — O Output pin
Out A — 1 O Output pin, channel A
Out B — 9 O Output pin, channel B
V– 2 4 — Negative power supply
V+ 6 10 — Positive power supply

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6 Specifications
6.1 Absolute Maximum Ratings (1)
MIN MAX UNIT
Supply voltage, V+ to V− 7.5 V
Voltage (V–) – 0.5 (V+) + 0.5 V
Signal input pins
Current 10 mA
Enable input (V–) – 0.5 (V+) + 0.5 V
(2)
Output short-circuit Continuous
Operating temperature –55 150 °C
Junction temperature 150 °C
Storage temperature, Tstg –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Short-circuit to ground, one amplifier per package.

6.2 ESD Ratings

VALUE UNIT
(1)
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 ±2000
V(ESD) Electrostatic discharge V
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±250

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VS Total supply voltage 5.5 V
TA Ambient temperature –40 25 125 °C

6.4 Thermal Information

OPA357 OPA2357
THERMAL METRIC (1) DBV (SOT-23) DGS (VSSOP) UNIT
6 PINS 10 PINS
RθJA Junction-to-ambient thermal resistance 166.4 171.3 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 104.6 58.2 °C/W
RθJB Junction-to-board thermal resistance 38.9 93.1 °C/W
ψJT Junction-to-top characterization parameter 23.6 6.8 °C/W
ψJB Junction-to-board characterization parameter 38.7 91.4 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance — — °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.

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6.5 Electrical Characteristics: VS = +2.7-V to +5.5-V Single-Supply

at TA = 25°C, RF = 0 Ω, RL = 1 kΩ, and connected to VS / 2 (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OFFSET VOLTAGE
VS = +5 V ±2 ±8
VOS Input offset voltage Specified temperature range, mV
±10
TA = –40°C to +125°C
Specified temperature range,
dVOS/dT VOS vs temperature ±4 µV/°C
TA = –40°C to +125°C
VS = +2.7 V to +5.5 V,
±200 ±800
VCM = (VS / 2) – 0.55 V
PSRR Power-supply rejection ratio µV/V
Specified temperature range,
±900
TA = –40°C to +125°C
INPUT BIAS CURRENT
IB Input bias current 3 ±50 pA
IOS Input offset current ±1 ±50 pA
NOISE
en Input voltage noise density f = 1 MHz 6.5 nV/√Hz
in Current noise density f = 1 MHz 50 fA/√Hz
INPUT VOLTAGE RANGE
VCM Common-mode voltage range (V–) – 0.1 (V+) + 0.1 V
VS = +5.5 V, –0.1 V < VCM < +3.5 V 66 80
Specified temperature range,
64
TA = –40°C to +125°C
CMRR Common-mode rejection ratio dB
VS = +5.5 V, –0.1 V < VCM < +5.6 V 56 68
Specified temperature range,
55
TA = –40°C to +125°C
INPUT IMPEDANCE
Differential 1013 || 2 Ω || pF
Common-mode 1013 || 2 Ω || pF
OPEN-LOOP GAIN
VS = +5 V, +0.3 V < VO < +4.7 V 94 110
AOL Open-loop gain Specified temperature range, dB
TA = –40°C to +125°C, VS = +5 V, 90
+0.4 V < VO < +4.6 V
FREQUENCY RESPONSE
G = +1, VO = 100 mVPP, RF = 25 Ω 250
f−3dB Small-signal bandwidth MHz
G = +2, VO = 100 mVPP 90
GBP Gain-bandwidth product G = +10 100 MHz
f0.1dB Bandwidth for 0.1-dB gain flatness G = +2, VO = 100 mVPP 40 MHz
VS = +5 V, G = +1, 4-V step 150
SR Slew rate VS = +5 V, G = +1, 2-V step 130 V/µs
VS = +3 V, G = +1, 2-V step 110
G = +1, VO = 100 mVPP, 10% to
2
Rise-and-fall time 90% ns
G = +1, VO = 2 VPP, 10% to 90% 11
Settling time, 0.1% VS = +5 V, G = +1, 2-V output step 30 ns
Settling time, 0.01% 60 ns
Overload recovery time VIN × gain = VS 5 ns
G = +1, f = 1 MHz, VO = 2 VPP,
HD2 2nd-order harmonic distortion –75 dBc
RL = 200 Ω, VCM = 1.5 V
G = +1, f = 1 MHz, VO = 2 VPP,
HD3 3rd-order harmonic distortion –83 dBc
RL = 200 Ω, VCM = 1.5 V

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Electrical Characteristics: VS = +2.7-V to +5.5-V Single-Supply (continued)

at TA = 25°C, RF = 0 Ω, RL = 1 kΩ, and connected to VS / 2 (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
FREQUENCY RESPONSE (continued)
Differential gain error NTSC, RL = 150 Ω 0.02%
Differential phase error NTSC, RL = 150 Ω 0.09 Degrees
Channel-to-channel crosstalk,
f = 5 MHz –100 dB
OPA2357
OUTPUT
VS = +5 V, RL = 1 kΩ, AOL > 94 dB 0.1 0.3
Voltage output swing from rail Specified temperature range, V
TA = –40°C to +125°C, VS = +5 V, 0.4
RL = 1 kΩ, AOL > 90 dB
VS = +5 V, single 100
IO Output current (1) (2) mA
VS = +3 V, dual 50
Closed-loop output impedance 0.05 Ω
RO Open-loop output resistance 35 Ω
POWER SUPPLY
VS Specified voltage range 2.7 5.5 V
Operating voltage range 2.5 to 5.5 V
VS = +5 V, enabled, IO = 0 V 4.9 6
IQ Quiescent current (per amplifier) Specified temperature range, mA
7.5
TA = –40°C to +125°C
ENABLE, SHUTDOWN FUNCTION
Disabled (logic−low threshold) 0.8 V
Enabled (logic−high threshold) 2 V
Logic input current Logic low 200 nA
Turn-on time 100 ns
Turn-off time 30 ns
Off isolation G = +1, 5 MHz, RL = 10 Ω 74 dB
Quiescent current (per amplifier) 3.4 6 µA
THERMAL SHUTDOWN
Shutdown 160
TJ Junction temperature °C
Reset from shutdown 140
TEMPERATURE RANGE
SOT23-6 150
RθJA Thermal resistance °C/W
VSSOP-10 150

(1) See Figure 21 and Figure 23.

(2) Specified by design.

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6.6 Typical Characteristics

at TA = 25°C, VS = 5 V, G = +1, RF = 0 Ω, RL = 1 kΩ, and connected to VS / 2 (unless otherwise noted)

3 3
VO = 0.1 VPP G = +1, VO = 0.1 VPP, RF = 604 W
RF = 25 W
0 0

Normalized Gain (dB)

Normalized Gain (dB)

G = +2, RF = 604 W
-3 -3
G = +5, RF = 604 W G = -1
-6 -6
G = +10, RF = 604 W G = -5 G = -2
-9 -9
G = -10
-12 -12

-15 -15
100k 1M 10M 100M 1G 100k 1M 10M 100M 1G
Frequency (Hz) Frequency (Hz)

Figure 1. Noninverting Small-Signal Frequency Response Figure 2. Inverting Small-Signal Frequency Response

Output Voltage (500 mV/div)

Output Voltage (40 mV/div)

Time (20 ns/div) Time (20 ns/div)

Figure 3. Noninverting Small-Signal Step Response Figure 4. Noninverting Large-Signal Step Response
0.5
VO = 0.1 VPP
0.4
Output Voltage (400 mV/div)

Enabled 0.3
Normalized Gain (dB)

G = +1,
Disable Voltage (V)

4.5 0.2
RF = 25 W
3.5 0.1
2.5 0
1.5 -0.1
Disabled 0.5 -0.2
G = +2,
VOUT, -0.3
RF = 604 W
fIN = 5 MHz -0.4
-0.5
Time (200 ns/div) 100k 1M 10M 100M 1G
Frequency (Hz)

Figure 5. Large-Signal Disable, Enable Response Figure 6. 0.1-dB Gain Flatness

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Typical Characteristics (continued)

at TA = 25°C, VS = 5 V, G = +1, RF = 0 Ω, RL = 1 kΩ, and connected to VS / 2 (unless otherwise noted)
-50 -50
G = -1 VO = 2 VPP
f = 1 MHz f = 1 MHz
-60 RL = 200 W
Harmonic Distortion (dBc)

-60 RL = 200 W

Harmonic Distortion (dBc)

-70 -70
2nd-Harmonic
2nd-Harmonic
-80 -80

-90 -90

3rd-Harmonic 3rd-Harmonic
-100 -100
0 1 2 3 4 1 10
Output Voltage (VPP) Gain (V/V)

Figure 7. Harmonic Distortion vs Output Voltage Figure 8. Harmonic Distortion vs Noninverting Gain
-50 -50
VO = 2 VPP G = +1
f = 1 MHz VO = 2 VPP
RL = 200 W -60 RL = 200 W
Harmonic Distortion (dBc)
-60
Harmonic Distortion (dBc)

VCM = 1.5 V

-70 -70
2nd-Harmonic 2nd-Harmonic

-80 -80
3rd-Harmonic
3rd-Harmonic
-90 -90

-100 -100
1 10 100k 1M 10M
Gain (V/V) Frequency (Hz)

Figure 9. Harmonic Distortion vs Inverting Gain Figure 10. Harmonic Distortion vs Frequency
-50 10k
G = +1
VO = 2 VPP
-60 f = 1 MHz
Harmonic Distortion (dBc)

Voltage Noise (nV/ÖHz),

Current Noise (fA/ÖHz)

VCM = 1.5 V 1k
Current Noise
-70 Voltage Noise
2nd-Harmonic
100
-80

3rd-Harmonic 10
-90

-100 1
100 1k 10 100 1k 10k 100k 1M 10M 100M
RL (W) Frequency (Hz)

Figure 11. Harmonic Distortion vs Load Resistance Figure 12. Input Voltage and Current Noise Spectral Density
vs Frequency

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Typical Characteristics (continued)

at TA = 25°C, VS = 5 V, G = +1, RF = 0 Ω, RL = 1 kΩ, and connected to VS / 2 (unless otherwise noted)
3 9
G = +1
RL = 10 kW 6 VO = 0.1 VPP
0 CL = 100 pF
RS = 0 W
G = +1 3

Normalized Gain (dB)

Normalized Gain (dB)

RF = 0 W
-3
VO = 0.1 VPP 0
CL = 0 pF RL = 1 kW
-6 -3
RL = 100 W CL = 47 pF
-6
-9
RL = 50 W -9
-12 CL = 5.6 pF
-12

-15 -15
100k 1M 10M 100M 1G 100k 1M 10M 100M 1G
Frequency (Hz) Frequency (Hz)

Figure 13. Frequency Response for Various RL Figure 14. Frequency Response for Various CL
160 3
G = +1 CL = 5.6 pF, RS = 0 W
For 0.1-dB VO = 0.1 VPP
140
Flatness 0
120 Normalized Gain (dB) CL = 47 pF, RS = 140 W
-3
100
RS (W)

CL = 100 pF, RS = 120 W

80 -6

60
VIN RS -9 VIN RS
VO VO
40 OPA357 OPA357

CL 1 kW CL 1 kW
-12
20

0 -15
1 10 100 1k 100k 1M 10M 100M 1G
Capacitive Load (pF) Frequency (Hz)

Figure 15. Recommended RS vs Capacitive Load Figure 16. Frequency Response vs Capacitive Load
100 180
160
CMRR
Open-Loop Phase (Degrees)

80 140
Open-Loop Gain (dB)

120
CMRR, PSRR (dB)

PSRR+ Phase
100
60
80
PSRR-
60
40
40
Gain
20
20 0
-20
0 -40
10k 100k 1M 10M 100M 1G 10 100 1k 10k 100k 1M 10M 100M 1G
Frequency (Hz) Frequency (Hz)

Figure 17. Common-Mode Rejection Ratio and Power- Figure 18. Open-Loop Gain and Phase
Supply Rejection Ratio vs Frequency

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Typical Characteristics (continued)

at TA = 25°C, VS = 5 V, G = +1, RF = 0 Ω, RL = 1 kΩ, and connected to VS / 2 (unless otherwise noted)
0.8 10k

0.7

Input Bias Current (pA)

0.6 1k
dG/dP (%/Degrees)

0.5
dP
0.4 100

0.3

0.2 10

0.1
dG
0 1
1 2 3 4 -55 -35 -15 5 25 45 65 85 105 125 135
Number of 150-W Loads Temperature (°C)

Figure 19. Composite Video differential Gain and Phase Figure 20. Input Bias Current vs Temperature
3 7

6
VS = 5 V
Supply Current (mA)
5
Output Voltage (V)

2
4
+125°C +25°C -55°C VS = 2.5 V
3
1
2

0 0
0 20 40 60 80 100 120 -55 -35 -15 5 25 45 65 85 105 125 135
Output Current (mA) Temperature (°C)
VS = 3 V

Figure 21. Output Voltage Swing vs Output Current Figure 22. Supply Current vs Temperature
5 4.5
VS = 5.5 V
4.0
4 3.5
Shutdown Current (mA)
Output Voltage (V)

3.0
3 VS = 5 V
2.5
+125°C +25°C -55°C
2.0
2
1.5

1 1.0
VS = 3 V VS = 2.5 V
0.5
0 0
0 25 50 75 100 125 150 175 200 -55 -35 -15 5 25 45 65 85 105 125 135
Output Current (mA) Temperature (°C)
VS = 5 V

Figure 23. Output Voltage Swing vs Output Current Figure 24. Shutdown Current vs Temperature

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Typical Characteristics (continued)

at TA = 25°C, VS = 5 V, G = +1, RF = 0 Ω, RL = 1 kΩ, and connected to VS / 2 (unless otherwise noted)
0 100
VDISABLE = 0
RL = 10 W
-20

Output Impedance (W)

10
Feedthrough (dB)

-40

-60 1
Forward
Reverse
-80
0.1 OPA357
-100
ZO
-120 0.01
100k 1M 10M 100M 1G 100k 1M 10M 100M 1G
Frequency (Hz) Frequency (Hz)

Figure 25. Disable Feedthrough vs Frequency Figure 26. Closed-Loop Output Impedance vs Frequency
6 0.5
VS = 5.5 V 0.4
5 VO = 2 VPP
Maximum Output 0.3
Output Voltage (VPP)

Voltage Without 0.2

Output Error (%)
4
Slew-Rate
0.1
Induced Distortion
3 0
VS = 2.7 V
-0.1
2
-0.2
-0.3
1
-0.4
0 -0.5
1 10 100 0 10 20 30 40 50 60 70 80 90 100
Frequency (MHz) Time (ns)

Figure 27. Maximum Output Voltage vs Frequency Figure 28. Output Settling Time to 0.1%
120

RL = 1 kW
110
Open-Loop Gain (dB)

Population

100

90

80

70
-55 -35 -15 5 25 45 65 85 105 125 135 -8 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7 8
Temperature (°C) Offset Voltage (mV)

Figure 29. Open-Loop Gain vs Temperature Figure 30. Offset Voltage Production Distribution

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Typical Characteristics (continued)

at TA = 25°C, VS = 5 V, G = +1, RF = 0 Ω, RL = 1 kΩ, and connected to VS / 2 (unless otherwise noted)
100 0

Crosstalk, Input-Referred (dB)

-20
90
CMRR, PSRR (dB)

Common-Mode Rejection Ratio -40

80
-60
Power-Supply Rejection Ratio
70 OPA2357
-80

60
-100

50 -120
-55 -35 -15 5 25 45 65 85 105 125 135 100k 1M 10M 100M 1G
Temperature (°C) Frequency (Hz)

Figure 31. Common-Mode Rejection Ratio and Power- Figure 32. Channel-to-Channel Crosstalk
Supply Rejection Ratio vs Temperature

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7 Detailed Description

7.1 Overview
The OPA357 is a CMOS, rail-to-rail I/O, high-speed, voltage-feedback operational amplifier designed for video,
high-speed, and other applications. The device is available as a single or dual op amp.
The amplifier features a 100-MHz gain bandwidth, and 150-V/µs slew rate, but is unity-gain stable and can be
operated as a +1-V/V voltage follower.

7.2 Functional Block Diagram

V+

Reference
Current

VIN+ VIN-

VBIAS1 Class AB
Control VO
Circuitry
VBIAS2

V-
(Ground)

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7.3 Feature Description

7.3.1 OPAx357 Comparison
Table 1 lists several members of the device family that includes the OPAx357.

Table 1. OPAx357 Related Products

PART NUMBER FEATURED
OPAx354 Non-shutdown version of OPA357 family
OPAx355 200-MHz GBW, rail-to-rail output, CMOS, shutdown
OPAx356 200-MHz GBW, rail-to-rail output, CMOS
OPAx350, OPAx353 38-MHz GBW, rail-to-rail input/output, CMOS
OPAx631 75-MHz BW G = 2, rail-to-rail output
OPAx634 150-MHz BW G = 2, rail-to-rail output
THS412x 100-MHz BW, differential input/output, 3.3-V supply

7.3.2 Operating Voltage

The OPA357 is specified over a power-supply range of +2.7 V to +5.5 V (±1.35 V to ±2.75 V). However, the
supply voltage can range from +2.5 V to +5.5 V (±1.25 V to ±2.75 V). Supply voltages higher than 7.5 V
(absolute maximum) can permanently damage the amplifier.
Parameters that vary over supply voltage or temperature are shown in the Typical Characteristics section.

7.3.3 Enable Function

The OPA357 enable function is implemented using a Schmitt trigger. The amplifier is enabled by applying a TTL
high voltage level (referenced to V−) to the Enable pin. Conversely, a TTL low voltage level (referenced to V−)
disables the amplifier, reducing its supply current from 4.9 mA to only 3.4 µA per amplifier. Independent Enable
pins are available for each channel (dual version), providing maximum design flexibility. For portable battery-
operated applications, this feature can be used to greatly reduce the average current and thereby extend battery
life.
The Enable input can be modeled as a CMOS input gate with a 100-kΩ pull-up resistor to V+. Connect this pin to
a valid high or low voltage or driven, not left open circuit.
The enable time is 100 ns and the disable time is only 30 ns. This time allows the OPA357 to be operated as a
gated amplifier, or to have its output multiplexed onto a common output bus. When disabled, the output assumes
a high-impedance state.

7.3.4 Rail-to-Rail Input

The specified input common-mode voltage range of the OPA357 extends 100 mV beyond the supply rails. This
range is achieved with a complementary input stage—an N-channel input differential pair in parallel with a P-
channel differential pair; see the Functional Block Diagram section. The N-channel pair is active for input
voltages close to the positive rail, typically (V+) − 1.2 V to 100 mV above the positive supply, whereas the P-
channel pair is on for inputs from 100 mV below the negative supply to approximately (V+) − 1.2 V. There is a
small transition region, typically (V+) − 1.5 V to (V+) − 0.9 V, in which both pairs are on. This 600-mV transition
region can vary ±500 mV with process variation. Thus, the transition region (both input stages on) can range
from (V+) − 2.0 V to (V+) − 1.5 V on the low end, up to (V+) − 0.9 V to (V+) − 0.4 V on the high end.
A double-folded cascode adds the signal from the two input pairs and presents a differential signal to the class
AB output stage.

7.3.5 Rail-to-Rail Output

A class AB output stage with common-source transistors is used to achieve rail-to-rail output. For high-
impedance loads (> 200 Ω), the output voltage swing is typically 100 mV from the supply rails. With 10-Ω loads,
a useful output swing can be achieved while maintaining high open-loop gain; see Figure 21 and Figure 23.

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7.3.6 Output Drive

The OPA357 output stage can supply a continuous output current of ±100 mA and still provide approximately
2.7 V of output swing on a 5-V supply, as shown in Figure 33. For maximum reliability, TI recommends running a
continuous DC current in excess of ±100 mA; see Figure 21 and Figure 23. For supplying continuous output
currents greater than ±100 mA, the OPA357 can be operated in parallel as shown in Figure 34.
The OPA357 provides peak currents up to 200 mA, which corresponds to the typical short-circuit current.
Therefore, an on-chip thermal shutdown circuit is provided to protect the OPA357 from dangerously high junction
temperatures. At 160°C, the protection circuit shuts down the amplifier. Normal operation resumes when the
junction temperature cools to below 140°C.

R2
1 kW +
V1
C1 - 5V
50 pF

1 mF
R1
10 kW V+

OPA357

R3 V-
VIN 10 kW RSHUNT
+
R4
- 1 kW
1-V In = 100-mA
Out, as Shown Laser Diode

Figure 33. Laser Diode Driver

R2
10 kW

C1
200 pF

+5 V
1 mF
R1
100 kW
R5 = 1 W
OPA2357

R3
100 kW
+

-
RSHUNT
2-V In = 200-mA R6 = 1 W
1W
Out, as Shown OPA2357

R4
10 kW

Laser Diode

Figure 34. Parallel Operation

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7.3.7 Video
The OPA357 output stage is capable of driving standard back-terminated 75-Ω video cables, as shown in
Figure 35. By back-terminating a transmission line, the cable does not exhibit a capacitive load to its driver. A
properly back-terminated 75-Ω cable does not appear as capacitance; this cable presents only a 150-Ω resistive
load to the OPA357 output.
+5 V

Video
In 75 W
Video
75 W OPA357
Output

+2.5 V To enable,
connect to V+
or drive with logic.
604 W 604 W
+2.5 V

Figure 35. Single-Supply Video Line Driver

The OPA357 can be used as an amplifier for RGB graphic signals, which have a voltage of zero at the video
black level, by offsetting and AC-coupling the signal, as shown in Figure 36.
604 W

+3 V

+
1 mF 10 nF

V+
604 W
1/2 75 W
R1 Red
(1)
Red OPA2357
75 W
R2

V+

(1) R1
Green
1/2 75 W
Green
R2 604 W OPA2357
75 W

604W

604 W

+3 V

+
1 mF 10 nF
V+
604 W
75 W
R1 Blue
(1) OPA357
Blue
75 W
R2

(1) The source video signal offset is 300 mV above ground to accommodate the op amp swing-to-ground capability.

Figure 36. RGB Cable Driver

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7.3.8 Wideband Video Multiplexing

One common application for video speed amplifiers that include an Enable pin is to wire multiple amplifier
outputs together, then select which one of several possible video inputs to source onto a single line. This simple
wired-OR video multiplexer can be easily implemented using the OPA357, as shown in Figure 37.
+2.5 V

+
1 mF 10 nF

49.9 W
A
Signal 1 OPA357

+
1 mF 10 nF

-2.5 V
1 kW
49.9 W
VOUT

1 kW
49.9 W
+2.5 V

+
1 mF 10 nF

49.9 W
B
Signal 2 OPA357

+
1 mF 10 nF

-2.5 V
1 kW

1 kW

HCO4
BON
Select
AON

Figure 37. Multiplexed Output

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7.3.9 Driving Analog-to-Digital Converters

The OPA357 series op amps offer 60 ns of settling time to 0.01%, making the series a good choice for driving
high- and medium-speed sampling A/D converters and reference circuits. The OPA357 series provides an
effective means of buffering the A/D converter input capacitance and resulting charge injection while providing
signal gain.
Figure 38 shows the OPA357 driving an A/D converter. With the OPA357 in an inverting configuration, a
capacitor across the feedback resistor can be used to filter high-frequency noise in the signal, as shown in
Figure 38.
+5 V

330 pF

5 kW 5 kW
VIN
V+ VREF

5 kW ADS7818, ADS7861,
+In
OPA357 or ADS7864
+2.5 V 12-Bit A/D Converter
0.1 mF -In
GND

NOTE: A/D converter input = 0 V to VREF.

NOTE: VIN = 0 V to –5 V for a 0-V to 5-V output.

Figure 38. The OPA357 in Inverting Configuration Driving an A/D Converter

7.3.10 Capacitive Load and Stability

The OPA357 series of op amps can drive a wide range of capacitive loads. However, all op amps under certain
conditions may become unstable. Op amp configuration, gain, and load value are just a few factors to consider
when determining stability. An op amp in unity-gain configuration is most susceptible to the effects of capacitive
loading. The capacitive load reacts with the op amp output resistance, along with any additional load resistance,
to create a pole in the small-signal response that degrades the phase margin; see Figure 14 for details.
The OPA357 topology enhances its ability to drive capacitive loads. In unity gain, these op amps perform well
with large capacitive loads. See Figure 15 for details.
One method of improving capacitive load drive in the unity-gain configuration is to insert a 10-Ω to 20-Ω resistor
in series with the output, as shown in Figure 39. This method significantly reduces ringing with large capacitive
loads; see Figure 14. However, if there is a resistive load in parallel with the capacitive load, RS creates a voltage
divider. This process introduces a DC error at the output and slightly reduces output swing. This error can be
insignificant. For instance, with RL = 10 kΩ and RS = 20 Ω, there is only about a 0.2% error at the output.

V+

RS
OPA357 VOUT
VIN
RL CL

To enable,
connect to V+
or drive with logic.

Figure 39. Series Resistor in Unity-Gain Configuration Improves Capacitive Load Drive

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7.3.11 Wideband Transimpedance Amplifier

Wide bandwidth, low input bias current, and low input voltage and current noise make the OPA357 an ideal
wideband photodiode transimpedance amplifier for low-voltage single-supply applications. Low-voltage noise is
important because photodiode capacitance causes the effective noise gain of the circuit to increase at high
frequency.
The key elements to a transimpedance design, as shown in Figure 40, are the expected diode capacitance
(including the parasitic input common-mode and differential-mode input capacitance (2 + 2)pF for the OPA357),
the desired transimpedance gain (RF), and the gain bandwidth product (GBP) for the OPA357 (100 MHz). With
these three variables set, the feedback capacitor value (CF) can be set to control the frequency response.
CF
<1 pF
(prevents gain peaking)

RF
10 MW

+V

l
CD OPA357 VOUT

To enable,
connect to V+
or drive with logic.

Figure 40. Transimpedance Amplifier

To achieve a maximally flat 2nd-order Butterworth frequency response, set the feedback pole to:
1 GBP
2SR F C F 4SR F C D (1)
Typical surface-mount resistors have a parasitic capacitance of approximately 0.2 pF that must be deducted from
the calculated feedback capacitance value.
Bandwidth is calculated by:
GBP
f 3dB Hz
2SR F C D (2)
For even higher transimpedance bandwidth, the high-speed CMOS OPA355 (200-MHz GBW) or the OPA655
(400-MHz GBW) can be used.

7.4 Device Functional Modes

The OPAx357 family of devices is powered on when the supply is connected. The devices can be operated as
single-supply operational amplifiers or dual-supply amplifiers depending on the application. The devices can also
be used with asymmetrical supplies as long as the differential voltage (V– to V+) is at least 1.8 V and no greater
than 5.5 V (for example, when V– is set to –3.5 V and V+ is set to 1.5 V).

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8 Application and Implementation

NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

8.1 Application Information

The OPAx357 family of devices is a CMOS, rail-to-rail I/O, high-speed, voltage-feedback operational amplifier
designed for video, high-speed, and other applications. The OPAx357 family of devices is available as a single or
dual op-amp.
The amplifier features a 100-MHz gain bandwidth, and 150-V/μs slew rate, but the device is unity-gain stable and
operates as a 1-V/V voltage follower.

8.2 Typical Applications

8.2.1 Transimpedance Amplifier
Wide gain bandwidth, low input bias current, low input voltage, and current noise make the OPAx357 family of
devices an ideal wideband photodiode transimpedance amplifier. Low-voltage noise is important because
photodiode capacitance causes the effective noise gain of the circuit to increase at high frequency. The key
elements to a transimpedance design, as shown in Figure 41, are the expected diode capacitance, (which
include the parasitic input common-mode and differential-mode input capacitance) the desired transimpedance
gain, and the gain-bandwidth (GBW) for the OPAx357 family of devices (20 MHz). With these three variables set,
the feedback capacitor value is set to control the frequency response. Feedback capacitance includes the stray
capacitance, which is 0.2 pF for a typical surface-mount resistor.

Figure 41. Dual-Supply Transimpedance Amplifier

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Typical Applications (continued)

8.2.1.1 Design Requirements
For this design example, use the parameters listed in Table 2 as the input parameters.

Table 2. Design Parameters

PARAMETER EXAMPLE VALUE
Supply voltage, V(V+) 2.5 V
Supply voltage, V(V-) –2.5 V

C(F) is optional to prevent gain peaking. C(F) includes the stray capacitance of R(F).

8.2.1.2 Detailed Design Procedure

8.2.1.2.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the OPA357 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.

8.2.1.2.2 OPAx357 Design Procedure

To achieve a maximally-flat, second-order Butterworth frequency response, set the feedback pole using
Equation 3.

(3)
Calculate the bandwidth using Equation 4.

(4)
For other transimpedance bandwidths, consider the high-speed CMOS OPA380 (90-MHz GBW), OPA354
(100-MHz GBW), OPA300 (180-MHz GBW), OPA355 (200-MHz GBW), or OPA656 and OPA657 (400-MHz
GBW).

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For single-supply applications, the +INx input can be biased with a positive DC voltage to allow the output to
reach true zero when the photodiode is not exposed to any light, and respond without the added delay that
results from coming out of the negative rail; Figure 42 shows this configuration. This bias voltage appears across
the photodiode, providing a reverse bias for faster operation.
0.5 pF

100 k

±
OPAx357 VOUT
+

SFH213 13.7 k

1 F 280 5V

Figure 42. Single-Supply Transimpedance Amplifier

For additional information, see the Compensate Transimpedance Amplifiers Intuitively application bulletin.

8.2.1.2.2.1 Optimizing the Transimpedance Circuit

To achieve the best performance, components must be selected according to the following guidelines:
1. For lowest noise, select R(F) to create the total required gain. Using a lower value for R(F) and adding gain
after the transimpedance amplifier generally produces poorer noise performance. The noise produced by R(F)
increases with the square-root of R(F), whereas the signal increases linearly. Therefore, signal-to-noise ratio
improves when all the required gain is placed in the transimpedance stage.
2. Minimize photodiode capacitance and stray capacitance at the summing junction (inverting input). This
capacitance causes the voltage noise of the op amp to amplify (increasing amplification at high frequency).
Using a low-noise voltage source to reverse-bias a photodiode reduce the capacitance. Smaller photodiodes
have lower capacitance. Use optics to concentrate light on a small photodiode.
3. Noise increases with increased bandwidth. Limit the circuit bandwidth to only the required bandwidth. Use a
capacitor across the R(F) to limit bandwidth, even if a capacitor not required for stability.
4. Circuit board leakage degrades the performance of an otherwise well-designed amplifier. Clean the circuit
board carefully. A circuit board guard trace that encircles the summing junction and is driven at the same
voltage helps control leakage.

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8.2.1.3 Application Curve

Figure 43. AC Transfer Function

8.2.2 High-Impedance Sensor Interface

Many sensors have high source impedances that can range up to 10 MΩ, or even higher. The output signal of
sensors often must be amplified or otherwise conditioned by an amplifier. The input bias current of this amplifier
can load the sensor output and cause a voltage drop across the source resistance, as shown in Figure 44, where
(V(+INx) = VS – I(BIAS) × R(S)). The last term, I(BIAS) × R(S), shows the voltage drop across R(S). To prevent errors
introduced to the system as a result of this voltage, use an op amp with low input bias current and high-
impedance sensors. This low current keeps the error contribution by I(BIAS) × R(S) less than the input voltage
noise of the amplifier, so that the amplifier does not become the dominant noise factor. The OPAx357 family of
devices series of op amps feature low input bias current (typically 200 fA), and are therefore designed for such
applications.
R(S)
100 kΩ IIB
V(+INx)
V(V+)

Device VO

V(V–) R(F)

R(G)

Figure 44. Noise as a Result of I(BIAS)

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8.2.3 Driving ADCs

The OPAx357 op amps are designed for driving sampling analog-to-digital (A/D) converters with sampling
speeds up to 1 MSPS. The zero-crossover distortion input stage topology allows the OPAx357 family of devices
to drive A/D converters without degradation of differential linearity and THD.
The OPAx357 family of devices can be used to buffer the A/D converter switched input capacitance and resulting
charge injection while providing signal gain. Figure 45 shows the OPAx357 family of devices configured to drive
the ADS8326.

5V

C1
100 nF 5V
(1)
R1
V(V+) 100 Ω
+INx
OPAx357
ADS8326
C3
(1) 16-Bit
V(V–)
1 nF –INx 250kSPS
VI
0 to 4.096 V
REF IN
(2) 5V
Optional
R2
50 kΩ SD1
BAS40
–5 V REF3240
C2 4.096 V
C4
100 nF 100 nF

(1) Suggested value; may require adjustment based on specific application.

(2) Single-supply applications lose a small number of A/D converter codes near ground as a result of op amp output swing limitation. If a
negative power supply is available, this simple circuit creates a –0.3-V supply to allow output swing to true ground potential.

Figure 45. Driving the ADS8326

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8.2.4 Active Filter

The OPAx357 family of devices is designed for active filter applications that require a wide bandwidth, fast slew
rate, low-noise, single-supply operational amplifier. Figure 46 shows a 500-kHz, second-order, low-pass filter
using the multiple-feedback (MFB) topology. The components are selected to provide a maximally-flat
Butterworth response. Beyond the cutoff frequency, roll-off is –40 dB/dec. The Butterworth response is designed
for applications requiring predictable gain characteristics, such as the antialiasing filter used in front of an A/D
converter.
One point to note when considering the MFB filter is that the output is inverted relative to the input. If this
inversion is not required, or not desired, a noninverting output can be achieved through one of the following
options:
1. Adding an inverting amplifier
2. Adding an additional second-order MFB stage
3. Using a noninverting filter topology, such as the Sallen-Key (see Figure 47).
MFB and Sallen-Key, low-pass and high-pass filter synthesis is accomplished using TI’s FilterPro™ program.
This software is available as a free download on www.ti.com.
R3
549 Ω

C2
150 pF

V(V+)
R1 R2
549 Ω 1.24 kΩ
VI
Device VO
C1
1 nF

V(V–)

Figure 46. Second-Order, Butterworth, 500-kHz, Low-Pass Filter

220 pF

V(V+)
1.8 kΩ 19.5 kΩ 150 kΩ
VI = 1 VRMS

3.3 nF 47 pF Device VO

V(V–)

Figure 47. OPAx357 Configured as a Three-Pole, 20-kHz, Sallen-Key Filter

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9 Power Supply Recommendations

9.1 Power Dissipation

For resistive loads, the maximum power dissipation occurs at a DC output voltage of one-half the power-supply
voltage. Dissipation with AC signals is lower. The Power Amplifier Stress and Power Handling Limitations
application note explains how to calculate or measure power dissipation with unusual signals and loads, and can
be found at www.ti.com. Any tendency to activate the thermal protection circuit indicates excessive power
dissipation or an inadequate heat sink. For reliable operation, limit junction temperature to 150°C, maximum. To
estimate the margin of safety in a complete design, increase the ambient temperature until the thermal protection
is triggered at 160°C. The thermal protection should trigger more than 35°C above the maximum expected
ambient condition of your application.

10 Layout

10.1 Layout Guidelines

Use good high-frequency printed circuit board (PCB) layout techniques for the OPA357. Generous use of ground
planes, short and direct signal traces, and a suitable bypass capacitor located at the V+ pin assures clean, stable
operation. Large areas of copper also provide a means of dissipating heat that is generated in normal operation.
Sockets are definitely not recommended for use with any high-speed amplifier.
A 10-nF ceramic bypass capacitor is the minimum recommended value; adding a 1-μF or larger tantalum
capacitor in parallel can be beneficial when driving a low-resistance load. Providing adequate bypass
capacitance is essential to achieving very low harmonic and intermodulation distortion.

10.2 Layout Example

Ground and power plane exist on
inner layers

Ground and power plane removed

Place output resistors close from inner layers
to output pins to minimize 1 6
parasitic capacitance Place bypass capacitors
close to power pins
Place bypass capacitors
close to power pins 2 5 Power control (disable) pin
+

Must be driven

Place input resistor close to pin 4

Noninverting input 3 4 to minimize stray capacitance
terminated in 50 Ÿ

Place feedback resistor on the bottom

of PCB between pins 4 and 6

Remove GND and Power plane

under pins 1 and 4 to minimize
stray PCB capacitance

Figure 48. Example Layout

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11 Device and Documentation Support

11.1 Device Support

11.1.1 Development Support

11.1.1.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the OPA357 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.

11.2 Documentation Support

11.2.1 Related Documentation
For related documentation see the following:
• OPAx380 Precision, High-Speed Transimpedance Amplifier
• OPAx354 250-MHz, Rail-to-Rail I/O, CMOS Operational Amplifiers
• OPAx300 Low-Noise, High-Speed, 16-Bit Accurate, CMOS Operational Amplifier
• OPAx355 200MHz, CMOS Operational Amplifier with Shutdown
• OPA656 Wideband, Unity-Gain Stable, FET-Input Operational Amplifier
• OPA657 1.6-GHz, Low-Noise, FET-Input Operational Amplifier
• ADS8326 16-Bit, High-Speed, 2.7V to 5.5V microPower Sampling Analog-to-Digital Converter
• FilterPro™
• Compensate Transimpedance Amplifiers Intuitively
• Power Amplifier Stress and Power Handling Limitations

11.3 Related Links

The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to order now.

Table 3. Related Links

TECHNICAL TOOLS & SUPPORT &
PARTS PRODUCT FOLDER ORDER NOW
DOCUMENTS SOFTWARE COMMUNITY
OPA357 Click here Click here Click here Click here Click here
OPA2357 Click here Click here Click here Click here Click here

11.4 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.

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11.5 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.

11.6 Trademarks
FilterPro, E2E are trademarks of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.7 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

11.8 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

28 Submit Documentation Feedback Copyright © 2002–2018, Texas Instruments Incorporated

Product Folder Links: OPA357 OPA2357

 PACKAGE OPTION ADDENDUM

www.ti.com 15-Jun-2024

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

OPA2357AIDGSR ACTIVE VSSOP DGS 10 2500 RoHS & Green NIPDAUAG Level-2-260C-1 YEAR -40 to 125 BBG Samples

OPA2357AIDGST ACTIVE VSSOP DGS 10 250 RoHS & Green NIPDAUAG Level-2-260C-1 YEAR -40 to 125 BBG Samples

OPA357AIDBVR ACTIVE SOT-23 DBV 6 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 OADI Samples

OPA357AIDBVT ACTIVE SOT-23 DBV 6 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 OADI Samples

OPA357AIDBVTG4 ACTIVE SOT-23 DBV 6 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 OADI Samples

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 15-Jun-2024

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 15-Jun-2024

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
OPA2357AIDGSR VSSOP DGS 10 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
OPA2357AIDGST VSSOP DGS 10 250 180.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
OPA357AIDBVR SOT-23 DBV 6 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
OPA357AIDBVT SOT-23 DBV 6 250 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
OPA357AIDBVT SOT-23 DBV 6 250 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 15-Jun-2024

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
OPA2357AIDGSR VSSOP DGS 10 2500 356.0 356.0 35.0
OPA2357AIDGST VSSOP DGS 10 250 210.0 185.0 35.0
OPA357AIDBVR SOT-23 DBV 6 3000 445.0 220.0 345.0
OPA357AIDBVT SOT-23 DBV 6 250 213.0 191.0 35.0
OPA357AIDBVT SOT-23 DBV 6 250 445.0 220.0 345.0

Pack Materials-Page 2
 PACKAGE OUTLINE
DGS0010A SCALE 3.200
VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE

C
5.05
TYP SEATING PLANE
4.75

A PIN 1 ID 0.1 C
AREA

8X 0.5
10
1

3.1
2.9 2X
NOTE 3 2

5
6
0.27
10X
0.17
3.1 0.1 C A B 1.1 MAX
B
2.9
NOTE 4

0.23
TYP
SEE DETAIL A 0.13

0.25
GAGE PLANE

0.7 0.15
0 -8 0.05
0.4

DETAIL A
TYPICAL

4221984/A 05/2015

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-187, variation BA.

www.ti.com
 EXAMPLE BOARD LAYOUT
DGS0010A VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE

10X (1.45)
10X (0.3) SYMM (R0.05)
1 TYP
10

SYMM

8X (0.5) 5 6

(4.4)

LAND PATTERN EXAMPLE

SCALE:10X

SOLDER MASK METAL UNDER SOLDER MASK

METAL OPENING
OPENING SOLDER MASK

0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

NOT TO SCALE

4221984/A 05/2015
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
DGS0010A VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE

10X (1.45)
SYMM (R0.05) TYP
10X (0.3)
1
10

SYMM
8X (0.5)

5 6

(4.4)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:10X

4221984/A 05/2015
NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
 PACKAGE OUTLINE
DBV0006A SCALE 4.000
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

3.0 C
2.6
1.75 0.1 C
B A
1.45
PIN 1
INDEX AREA

1
6

2X 0.95
3.05
2.75
1.9 5
2

4
3
0.50
6X
0.25
0.15
0.2 C A B (1.1) TYP
0.00
1.45
0.90

0.25
GAGE PLANE 0.22
TYP
0.08

8
TYP 0.6
0 TYP SEATING PLANE
0.3

ALTERNATIVE PACKAGE SINGULATION VIEW

4214840/F 05/2024

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Body dimensions do not include mold flash or protrusion. Mold flash and protrusion shall not exceed 0.25 per side.
4. Leads 1,2,3 may be wider than leads 4,5,6 for package orientation.
5. Refernce JEDEC MO-178.

www.ti.com
 EXAMPLE BOARD LAYOUT
DBV0006A SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

PKG
6X (1.1)
1

6X (0.6)
6

SYMM
2 5
2X (0.95)

3 4

(R0.05) TYP (2.6)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:15X

SOLDER MASK
SOLDER MASK METAL METAL UNDER OPENING
OPENING SOLDER MASK

EXPOSED METAL EXPOSED METAL

0.07 MAX 0.07 MIN

ARROUND ARROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)

SOLDER MASK DETAILS

4214840/F 05/2024

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
DBV0006A SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

PKG
6X (1.1)
1

6X (0.6)
6

SYMM
2 5
2X(0.95)

3 4

(R0.05) TYP
(2.6)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:15X

4214840/F 05/2024

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
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