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Opa 357
Opa 357
OPA357, OPA2357
SBOS235F – MARCH 2002 – REVISED APRIL 2018
-VIN
OPA357 VOUT
+VIN
V- Enable
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
OPA357, OPA2357
SBOS235F – MARCH 2002 – REVISED APRIL 2018 www.ti.com
Table of Contents
1 Features .................................................................. 1 8 Application and Implementation ........................ 20
2 Applications ........................................................... 1 8.1 Application Information............................................ 20
3 Description ............................................................. 1 8.2 Typical Applications ............................................... 20
4 Revision History..................................................... 2 9 Power Supply Recommendations...................... 26
5 Pin Configuration and Functions ......................... 3 9.1 Power Dissipation ................................................... 26
6 Specifications......................................................... 4 10 Layout................................................................... 26
6.1 Absolute Maximum Ratings ...................................... 4 10.1 Layout Guidelines ................................................. 26
6.2 ESD Ratings.............................................................. 4 10.2 Layout Example .................................................... 26
6.3 Recommended Operating Conditions....................... 4 11 Device and Documentation Support ................. 27
6.4 Thermal Information .................................................. 4 11.1 Device Support...................................................... 27
6.5 Electrical Characteristics: VS = +2.7-V to +5.5-V 11.2 Documentation Support ........................................ 27
Single-Supply ............................................................. 5 11.3 Related Links ........................................................ 27
6.6 Typical Characteristics .............................................. 7 11.4 Receiving Notification of Documentation Updates 27
7 Detailed Description ............................................ 13 11.5 Community Resources.......................................... 28
7.1 Overview ................................................................. 13 11.6 Trademarks ........................................................... 28
7.2 Functional Block Diagram ....................................... 13 11.7 Electrostatic Discharge Caution ............................ 28
7.3 Feature Description................................................. 14 11.8 Glossary ................................................................ 28
7.4 Device Functional Modes........................................ 19 12 Mechanical, Packaging, and Orderable
Information ........................................................... 28
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
• Added Device Information table, Pin Functions table, ESD Ratings table, Recommended Operating Conditions
table, Thermal Information table, Overview section, Functional Block Diagram section, Feature Description section,
Device Functional Modes section, Application and Implementation section, Power Supply Recommendations
section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable
Information section ................................................................................................................................................................ 1
• Changed MSOP to VSSOP throughout document ................................................................................................................ 1
• Deleted DDA package (SO-8 PowerPAD) from document ................................................................................................... 1
• Changed MSOP to VSSOP throughout document ................................................................................................................ 1
• Added WEBENCH Features bullet ........................................................................................................................................ 1
• Deleted OADI from DBV pin drawing ..................................................................................................................................... 3
• Deleted Package/Ordering Information table ......................................................................................................................... 4
• Deleted footnote from Signal input pins parameter in Absolute Maximum Ratings table ...................................................... 4
• Changed Temperature Range section of Electrical Characteristics table: changed θJA to RθJA and deleted Specified
range, Operating range, and Storage range parameters ....................................................................................................... 6
• Added OPAx357 Comparison section and moved OPAx357 Related Products table to this section from page 1 ............. 14
• Deleted first paragraph of Power Dissipation section........................................................................................................... 26
• Changed PCB Layout title to Layout Guidelines .................................................................................................................. 26
• Deleted PowerPAD Thermall Enhanced Package and PowerPAD Assembly Process sections......................................... 26
• Added Custom Design With WEBENCH® Tools section ..................................................................................................... 27
Out 1 6 V+ Out A 1 10 V+
Enable A 5 6 Enable B
(1) Pin 1 of the SOT23-6 is determined by orienting the package marking as indicated in the diagram.
Pin Functions
PIN
DBV DGS I/O DESCRIPTION
NAME
(SOT-23) (VSSOP)
Amplifier power down.
Enable 5 — —
Low = disabled, high = normal operation (pin must be driven).
Amplifier power down, channel A.
Enable A — 5 —
Low = disabled, high = normal operation (pin must be driven).
Amplifier power down, channel B.
Enable B — 6 —
Low = disabled, high = normal operation (pin must be driven).
–In 4 — I Inverting input pin
–In A — 2 I Inverting input pin, channel A
–In B — 8 I Inverting input pin, channel B
+In 3 — I Noninverting input pin
+In A — 3 I Noninverting input pin, channel A
+In B — 7 I Noninverting input pin, channel B
Out 1 — O Output pin
Out A — 1 O Output pin, channel A
Out B — 9 O Output pin, channel B
V– 2 4 — Negative power supply
V+ 6 10 — Positive power supply
6 Specifications
6.1 Absolute Maximum Ratings (1)
MIN MAX UNIT
Supply voltage, V+ to V− 7.5 V
Voltage (V–) – 0.5 (V+) + 0.5 V
Signal input pins
Current 10 mA
Enable input (V–) – 0.5 (V+) + 0.5 V
(2)
Output short-circuit Continuous
Operating temperature –55 150 °C
Junction temperature 150 °C
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Short-circuit to ground, one amplifier per package.
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
3 3
VO = 0.1 VPP G = +1, VO = 0.1 VPP, RF = 604 W
RF = 25 W
0 0
G = +2, RF = 604 W
-3 -3
G = +5, RF = 604 W G = -1
-6 -6
G = +10, RF = 604 W G = -5 G = -2
-9 -9
G = -10
-12 -12
-15 -15
100k 1M 10M 100M 1G 100k 1M 10M 100M 1G
Frequency (Hz) Frequency (Hz)
Figure 1. Noninverting Small-Signal Frequency Response Figure 2. Inverting Small-Signal Frequency Response
Figure 3. Noninverting Small-Signal Step Response Figure 4. Noninverting Large-Signal Step Response
0.5
VO = 0.1 VPP
0.4
Output Voltage (400 mV/div)
Enabled 0.3
Normalized Gain (dB)
G = +1,
Disable Voltage (V)
4.5 0.2
RF = 25 W
3.5 0.1
2.5 0
1.5 -0.1
Disabled 0.5 -0.2
G = +2,
VOUT, -0.3
RF = 604 W
fIN = 5 MHz -0.4
-0.5
Time (200 ns/div) 100k 1M 10M 100M 1G
Frequency (Hz)
-60 RL = 200 W
-90 -90
3rd-Harmonic 3rd-Harmonic
-100 -100
0 1 2 3 4 1 10
Output Voltage (VPP) Gain (V/V)
Figure 7. Harmonic Distortion vs Output Voltage Figure 8. Harmonic Distortion vs Noninverting Gain
-50 -50
VO = 2 VPP G = +1
f = 1 MHz VO = 2 VPP
RL = 200 W -60 RL = 200 W
Harmonic Distortion (dBc)
-60
Harmonic Distortion (dBc)
VCM = 1.5 V
-70 -70
2nd-Harmonic 2nd-Harmonic
-80 -80
3rd-Harmonic
3rd-Harmonic
-90 -90
-100 -100
1 10 100k 1M 10M
Gain (V/V) Frequency (Hz)
Figure 9. Harmonic Distortion vs Inverting Gain Figure 10. Harmonic Distortion vs Frequency
-50 10k
G = +1
VO = 2 VPP
-60 f = 1 MHz
Harmonic Distortion (dBc)
VCM = 1.5 V 1k
Current Noise
-70 Voltage Noise
2nd-Harmonic
100
-80
3rd-Harmonic 10
-90
-100 1
100 1k 10 100 1k 10k 100k 1M 10M 100M
RL (W) Frequency (Hz)
Figure 11. Harmonic Distortion vs Load Resistance Figure 12. Input Voltage and Current Noise Spectral Density
vs Frequency
RF = 0 W
-3
VO = 0.1 VPP 0
CL = 0 pF RL = 1 kW
-6 -3
RL = 100 W CL = 47 pF
-6
-9
RL = 50 W -9
-12 CL = 5.6 pF
-12
-15 -15
100k 1M 10M 100M 1G 100k 1M 10M 100M 1G
Frequency (Hz) Frequency (Hz)
Figure 13. Frequency Response for Various RL Figure 14. Frequency Response for Various CL
160 3
G = +1 CL = 5.6 pF, RS = 0 W
For 0.1-dB VO = 0.1 VPP
140
Flatness 0
120 Normalized Gain (dB) CL = 47 pF, RS = 140 W
-3
100
RS (W)
60
VIN RS -9 VIN RS
VO VO
40 OPA357 OPA357
CL 1 kW CL 1 kW
-12
20
0 -15
1 10 100 1k 100k 1M 10M 100M 1G
Capacitive Load (pF) Frequency (Hz)
Figure 15. Recommended RS vs Capacitive Load Figure 16. Frequency Response vs Capacitive Load
100 180
160
CMRR
Open-Loop Phase (Degrees)
80 140
Open-Loop Gain (dB)
120
CMRR, PSRR (dB)
PSRR+ Phase
100
60
80
PSRR-
60
40
40
Gain
20
20 0
-20
0 -40
10k 100k 1M 10M 100M 1G 10 100 1k 10k 100k 1M 10M 100M 1G
Frequency (Hz) Frequency (Hz)
Figure 17. Common-Mode Rejection Ratio and Power- Figure 18. Open-Loop Gain and Phase
Supply Rejection Ratio vs Frequency
0.7
0.5
dP
0.4 100
0.3
0.2 10
0.1
dG
0 1
1 2 3 4 -55 -35 -15 5 25 45 65 85 105 125 135
Number of 150-W Loads Temperature (°C)
Figure 19. Composite Video differential Gain and Phase Figure 20. Input Bias Current vs Temperature
3 7
6
VS = 5 V
Supply Current (mA)
5
Output Voltage (V)
2
4
+125°C +25°C -55°C VS = 2.5 V
3
1
2
0 0
0 20 40 60 80 100 120 -55 -35 -15 5 25 45 65 85 105 125 135
Output Current (mA) Temperature (°C)
VS = 3 V
Figure 21. Output Voltage Swing vs Output Current Figure 22. Supply Current vs Temperature
5 4.5
VS = 5.5 V
4.0
4 3.5
Shutdown Current (mA)
Output Voltage (V)
3.0
3 VS = 5 V
2.5
+125°C +25°C -55°C
2.0
2
1.5
1 1.0
VS = 3 V VS = 2.5 V
0.5
0 0
0 25 50 75 100 125 150 175 200 -55 -35 -15 5 25 45 65 85 105 125 135
Output Current (mA) Temperature (°C)
VS = 5 V
Figure 23. Output Voltage Swing vs Output Current Figure 24. Shutdown Current vs Temperature
-40
-60 1
Forward
Reverse
-80
0.1 OPA357
-100
ZO
-120 0.01
100k 1M 10M 100M 1G 100k 1M 10M 100M 1G
Frequency (Hz) Frequency (Hz)
Figure 25. Disable Feedthrough vs Frequency Figure 26. Closed-Loop Output Impedance vs Frequency
6 0.5
VS = 5.5 V 0.4
5 VO = 2 VPP
Maximum Output 0.3
Output Voltage (VPP)
Figure 27. Maximum Output Voltage vs Frequency Figure 28. Output Settling Time to 0.1%
120
RL = 1 kW
110
Open-Loop Gain (dB)
Population
100
90
80
70
-55 -35 -15 5 25 45 65 85 105 125 135 -8 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7 8
Temperature (°C) Offset Voltage (mV)
Figure 29. Open-Loop Gain vs Temperature Figure 30. Offset Voltage Production Distribution
60
-100
50 -120
-55 -35 -15 5 25 45 65 85 105 125 135 100k 1M 10M 100M 1G
Temperature (°C) Frequency (Hz)
Figure 31. Common-Mode Rejection Ratio and Power- Figure 32. Channel-to-Channel Crosstalk
Supply Rejection Ratio vs Temperature
7 Detailed Description
7.1 Overview
The OPA357 is a CMOS, rail-to-rail I/O, high-speed, voltage-feedback operational amplifier designed for video,
high-speed, and other applications. The device is available as a single or dual op amp.
The amplifier features a 100-MHz gain bandwidth, and 150-V/µs slew rate, but is unity-gain stable and can be
operated as a +1-V/V voltage follower.
V+
Reference
Current
VIN+ VIN-
VBIAS1 Class AB
Control VO
Circuitry
VBIAS2
V-
(Ground)
R2
1 kW +
V1
C1 - 5V
50 pF
1 mF
R1
10 kW V+
OPA357
R3 V-
VIN 10 kW RSHUNT
+
R4
- 1 kW
1-V In = 100-mA
Out, as Shown Laser Diode
R2
10 kW
C1
200 pF
+5 V
1 mF
R1
100 kW
R5 = 1 W
OPA2357
R3
100 kW
+
-
RSHUNT
2-V In = 200-mA R6 = 1 W
1W
Out, as Shown OPA2357
R4
10 kW
Laser Diode
7.3.7 Video
The OPA357 output stage is capable of driving standard back-terminated 75-Ω video cables, as shown in
Figure 35. By back-terminating a transmission line, the cable does not exhibit a capacitive load to its driver. A
properly back-terminated 75-Ω cable does not appear as capacitance; this cable presents only a 150-Ω resistive
load to the OPA357 output.
+5 V
Video
In 75 W
Video
75 W OPA357
Output
+2.5 V To enable,
connect to V+
or drive with logic.
604 W 604 W
+2.5 V
The OPA357 can be used as an amplifier for RGB graphic signals, which have a voltage of zero at the video
black level, by offsetting and AC-coupling the signal, as shown in Figure 36.
604 W
+3 V
+
1 mF 10 nF
V+
604 W
1/2 75 W
R1 Red
(1)
Red OPA2357
75 W
R2
V+
(1) R1
Green
1/2 75 W
Green
R2 604 W OPA2357
75 W
604W
604 W
+3 V
+
1 mF 10 nF
V+
604 W
75 W
R1 Blue
(1) OPA357
Blue
75 W
R2
(1) The source video signal offset is 300 mV above ground to accommodate the op amp swing-to-ground capability.
+
1 mF 10 nF
49.9 W
A
Signal 1 OPA357
+
1 mF 10 nF
-2.5 V
1 kW
49.9 W
VOUT
1 kW
49.9 W
+2.5 V
+
1 mF 10 nF
49.9 W
B
Signal 2 OPA357
+
1 mF 10 nF
-2.5 V
1 kW
1 kW
HCO4
BON
Select
AON
330 pF
5 kW 5 kW
VIN
V+ VREF
5 kW ADS7818, ADS7861,
+In
OPA357 or ADS7864
+2.5 V 12-Bit A/D Converter
0.1 mF -In
GND
V+
RS
OPA357 VOUT
VIN
RL CL
To enable,
connect to V+
or drive with logic.
Figure 39. Series Resistor in Unity-Gain Configuration Improves Capacitive Load Drive
RF
10 MW
+V
l
CD OPA357 VOUT
To enable,
connect to V+
or drive with logic.
To achieve a maximally flat 2nd-order Butterworth frequency response, set the feedback pole to:
1 GBP
2SR F C F 4SR F C D (1)
Typical surface-mount resistors have a parasitic capacitance of approximately 0.2 pF that must be deducted from
the calculated feedback capacitance value.
Bandwidth is calculated by:
GBP
f 3dB Hz
2SR F C D (2)
For even higher transimpedance bandwidth, the high-speed CMOS OPA355 (200-MHz GBW) or the OPA655
(400-MHz GBW) can be used.
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
C(F) is optional to prevent gain peaking. C(F) includes the stray capacitance of R(F).
(3)
Calculate the bandwidth using Equation 4.
(4)
For other transimpedance bandwidths, consider the high-speed CMOS OPA380 (90-MHz GBW), OPA354
(100-MHz GBW), OPA300 (180-MHz GBW), OPA355 (200-MHz GBW), or OPA656 and OPA657 (400-MHz
GBW).
For single-supply applications, the +INx input can be biased with a positive DC voltage to allow the output to
reach true zero when the photodiode is not exposed to any light, and respond without the added delay that
results from coming out of the negative rail; Figure 42 shows this configuration. This bias voltage appears across
the photodiode, providing a reverse bias for faster operation.
0.5 pF
100 k
±
OPAx357 VOUT
+
SFH213 13.7 k
1 F 280 5V
For additional information, see the Compensate Transimpedance Amplifiers Intuitively application bulletin.
Device VO
V(V–) R(F)
R(G)
5V
C1
100 nF 5V
(1)
R1
V(V+) 100 Ω
+INx
OPAx357
ADS8326
C3
(1) 16-Bit
V(V–)
1 nF –INx 250kSPS
VI
0 to 4.096 V
REF IN
(2) 5V
Optional
R2
50 kΩ SD1
BAS40
–5 V REF3240
C2 4.096 V
C4
100 nF 100 nF
C2
150 pF
V(V+)
R1 R2
549 Ω 1.24 kΩ
VI
Device VO
C1
1 nF
V(V–)
220 pF
V(V+)
1.8 kΩ 19.5 kΩ 150 kΩ
VI = 1 VRMS
3.3 nF 47 pF Device VO
V(V–)
10 Layout
Must be driven
11.6 Trademarks
FilterPro, E2E are trademarks of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.7 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.8 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
www.ti.com 15-Jun-2024
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)
OPA2357AIDGSR ACTIVE VSSOP DGS 10 2500 RoHS & Green NIPDAUAG Level-2-260C-1 YEAR -40 to 125 BBG Samples
OPA2357AIDGST ACTIVE VSSOP DGS 10 250 RoHS & Green NIPDAUAG Level-2-260C-1 YEAR -40 to 125 BBG Samples
OPA357AIDBVR ACTIVE SOT-23 DBV 6 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 OADI Samples
OPA357AIDBVT ACTIVE SOT-23 DBV 6 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 OADI Samples
OPA357AIDBVTG4 ACTIVE SOT-23 DBV 6 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 OADI Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 15-Jun-2024
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 15-Jun-2024
B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers
Sprocket Holes
Q1 Q2 Q1 Q2
Pocket Quadrants
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 15-Jun-2024
Width (mm)
H
W
Pack Materials-Page 2
PACKAGE OUTLINE
DGS0010A SCALE 3.200
VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
C
5.05
TYP SEATING PLANE
4.75
A PIN 1 ID 0.1 C
AREA
8X 0.5
10
1
3.1
2.9 2X
NOTE 3 2
5
6
0.27
10X
0.17
3.1 0.1 C A B 1.1 MAX
B
2.9
NOTE 4
0.23
TYP
SEE DETAIL A 0.13
0.25
GAGE PLANE
0.7 0.15
0 -8 0.05
0.4
DETAIL A
TYPICAL
4221984/A 05/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-187, variation BA.
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EXAMPLE BOARD LAYOUT
DGS0010A VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
10X (1.45)
10X (0.3) SYMM (R0.05)
1 TYP
10
SYMM
8X (0.5) 5 6
(4.4)
4221984/A 05/2015
NOTES: (continued)
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EXAMPLE STENCIL DESIGN
DGS0010A VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
10X (1.45)
SYMM (R0.05) TYP
10X (0.3)
1
10
SYMM
8X (0.5)
5 6
(4.4)
4221984/A 05/2015
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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PACKAGE OUTLINE
DBV0006A SCALE 4.000
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
3.0 C
2.6
1.75 0.1 C
B A
1.45
PIN 1
INDEX AREA
1
6
2X 0.95
3.05
2.75
1.9 5
2
4
3
0.50
6X
0.25
0.15
0.2 C A B (1.1) TYP
0.00
1.45
0.90
0.25
GAGE PLANE 0.22
TYP
0.08
8
TYP 0.6
0 TYP SEATING PLANE
0.3
4214840/F 05/2024
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Body dimensions do not include mold flash or protrusion. Mold flash and protrusion shall not exceed 0.25 per side.
4. Leads 1,2,3 may be wider than leads 4,5,6 for package orientation.
5. Refernce JEDEC MO-178.
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EXAMPLE BOARD LAYOUT
DBV0006A SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
6X (1.1)
1
6X (0.6)
6
SYMM
2 5
2X (0.95)
3 4
SOLDER MASK
SOLDER MASK METAL METAL UNDER OPENING
OPENING SOLDER MASK
4214840/F 05/2024
NOTES: (continued)
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0006A SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
6X (1.1)
1
6X (0.6)
6
SYMM
2 5
2X(0.95)
3 4
(R0.05) TYP
(2.6)
4214840/F 05/2024
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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